Memory module, electronic device and signal transmission method

Abstract

A memory module, an electronic device and a signal transmission method. The memory module is a dual in-line memory module, a circuit board of the memory module is provided with a fool-proof bayonet and a locking bayonet, and a plurality of memory chips are respectively arranged on two side surfaces of the circuit board, wherein the plurality of memory chips are connected to a processing chip by means of a parallel bus, and the processing chip is connected to a gold finger interface by means of a serial bus. In such an arrangement, the memory module can realize a serial interconnection relationship by means of a connector, the data transmission rate can be reliably improved, crosstalk and simultaneous switching noise caused by high-speed transmission based on the parallel bus are avoided, and the SI is effectively improved, the actual occupied area is small, and high-density layout is facilitated. On the whole, technical support is provided for high-density layout and high-performance operation of an architecture. In addition, the physical space occupied by the memory module is approximately the same as that occupied by a traditional memory bank, so that the structural standardization design of a mainboard is facilitated.

Description

Memory module, electronic device and signal transmission method

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on July 27, 2023, with application number 202310937615.6 and invention name “A memory module, electronic device and signal transmission method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of computer hardware, and in particular to a memory module, an electronic device, and a signal transmission method. Background Art

[0003] Dual in-line memory module (DIMM) connectors are used in double data rate (DDR) parallel bus systems. DIMM connectors are used to install and connect memory modules, connecting the central processing unit (CPU) to the synchronous dynamic random access memory (SDRAM) chips on the internal modules. This connection forms an efficient, low-cost memory system between the CPU and the storage medium, enabling fast read and write access operations.

[0004] With the development of data-intensive applications such as high-performance computing and artificial intelligence, the demand for memory system bandwidth and capacity continues to increase, driving the continuous improvement of DDR parallel bus speed and SDRAM chip capacity in memory modules. Currently, the DDR parallel bus has gradually transitioned from the fourth generation of DDR (DDR4) to the fifth generation of DDR (DDR5), with the single-line rate increasing from 2.133Gbps to 3.2Gbps, and then to 4.8Gbps to 8.4Gbps. Due to issues such as crosstalk and simultaneous switching noise (SSN), further increasing the single-line rate will affect signal integrity (SI).

[0005] To address memory system bandwidth and capacity issues, the industry has proposed serial memory solutions to achieve memory expansion. Memory expansion modules can be connected to the motherboard in different ways. One typical approach is to use a vertical plug-in GENZ (Generation Z, a high-speed protocol) connector. However, the GENZ connector is relatively large and, due to internal device space limitations, the board width of the memory expansion module cannot meet the layout requirements of larger expansion chips. Another typical approach is to use a flat plug-in GENZ splint connector. The memory expansion module is arranged parallel to the motherboard, occupying a large space on the motherboard surface and hindering the implementation of a high-density architecture.

[0006] Summary of the Invention

[0007] The embodiments of the present application provide a memory module, an electronic device, and a signal transmission method, which, on the basis of effectively improving the signal transmission rate, provide technical support for improving SI while taking into account the design requirements of high-density architecture layout.

[0008] The first aspect of the embodiment of the present application provides a memory module, which includes a circuit board, a processing chip and multiple memory chips arranged on the circuit board, and a gold finger interface located at the edge of the circuit board; wherein the circuit board is provided with an anti-fool-proofing latch and a locking latch, and the multiple memory chips are arranged on both sides of the board of the circuit board; wherein the multiple memory chips are connected to the processing chip via a parallel bus, and the processing chip is connected to the gold finger interface via a serial bus. With such a configuration, the memory module can achieve a serial interconnection relationship through the connector. On the one hand, the serial bus can reliably increase the data transmission rate, and can to a certain extent avoid the crosstalk and synchronous switching noise generated by high-speed transmission based on the parallel bus, meet the reliability and stability requirements of signal transmission, and effectively improve SI. On the other hand, based on the relatively small height size of the DIMM connector, for the same assembly space, the circuit board provided by this solution can have a relatively large board width, which can realize the layout of larger devices; and the memory module adopts a vertical plug-in connection method, and the actual board area is small. Overall, it provides technical support for the high-density layout and high-performance operation of the architecture.

[0009] In addition, the physical space occupied by the memory module in the electronic device is roughly the same as the physical space occupied by a traditional memory stick, which is conducive to the structural standardization design of the electronic device motherboard and can further improve the structural compatibility of the memory module and the motherboard.

[0010] Exemplarily, the memory module may be a memory expansion card, and the processing chip may be a memory expansion chip used to manage and control multiple memory chips to ensure compatibility and collaboration with the computer system. For example, the computer system may determine data storage location based on access frequency. For example, frequently accessed data may be stored in the storage space provided by the system memory module, while relatively less frequently accessed data may be stored in the storage space provided by the memory chip of the memory expansion card, thereby improving the performance and processing power of the computer system.

[0011] Based on the first aspect, the present application also provides a first implementation method of the first aspect: the gold finger interface includes a first power pin area, a second power pin area, a management control signal pin area, and a serial bus pin area, which are respectively arranged on two sides of the circuit board; wherein the first power pin area is used to provide a first voltage power supply, and the second power pin area is used to provide a second voltage power supply, and the voltage of the second voltage power supply is lower than that of the first voltage power supply; each side of the circuit board includes two serial bus pin areas, and in the arrangement direction of the gold finger interface, the first power pin area is located at one end of the circuit board, one serial bus pin area is arranged adjacent to the first power pin area, and the other serial bus pin area is located at the other end of the circuit board, and the management control signal pin area and the second power pin area are located between the two serial bus pin areas. In this way, the electromagnetic crosstalk that may be generated by the first power pin area with a higher output voltage on other pin areas can be reduced. In addition, the management control signal pin area and the second power pin area can be flexibly arranged between the two serial bus pin areas as needed to provide partial power and control signal channels for devices on the circuit board. It has good adaptability.

[0012] Exemplarily, the power provided by the first power pin area is 5V, 6V or 12V, which is converted into a low-voltage power supply (such as 1.2V or 1V, etc.) through the secondary power supply on the circuit board to power devices such as processing chips and memory chips on the circuit board.

[0013] In actual applications, for scenarios where there are many devices arranged on a circuit board and the overall load is large, the second power pin area can provide partial power supply according to the actual operating status.

[0014] Based on the first implementation of the first aspect, the embodiment of the present application also provides a second implementation of the first aspect: an empty pin is arranged between the first power pin area and the adjacent serial bus pin area, where the "empty pin" refers to a pin on which no signal is defined; based on the setting of the empty pin, the noise in the first power pin area can be effectively prevented from interfering with the differential signal.

[0015] For example, the number of the empty pins can be one, or a plurality of other numbers. In practical applications, reasonable configuration can be performed while effectively preventing the possible impact of 12V noise.

[0016] Based on the first implementation of the first aspect, or the second implementation of the first aspect, the embodiment of the present application also provides a third implementation of the first aspect: the gold finger interface also includes a differential clock pin to ensure data synchronization in high-speed serial transmission, and the differential clock pin is located between the empty pin and the serial bus pin area arranged adjacent to the first power pin area.

[0017] Based on the first embodiment of the first aspect, or the second embodiment of the first aspect, or the third embodiment of the first aspect, the embodiment of the present application further provides a fourth embodiment of the first aspect: wherein the portion of the gold finger interface located on one side of the circuit board is a first-side gold finger, and the portion of the gold finger interface located on the other side of the circuit board is a second-side gold finger; the serial bus pin area includes differential pair pins arranged at intervals, the differential pair pins including two differential signal pins for transmitting differential signals, and a ground pin is provided between two adjacent pairs of differential pair pins. In this way, crosstalk that may occur between adjacent differential pairs can be avoided.

[0018] Based on the fourth implementation of the first aspect, the present application also provides a fifth implementation of the first aspect: the serial bus pin area includes eight pairs of differential pins spaced apart from each other, with the differential pins of the first-side gold fingers interleaved with the differential pins of the second-side gold fingers. In other words, the first-side gold fingers and the second-side gold fingers each include two pairs of eight serial signal pins, thereby providing x16 high-speed transmission bandwidth.

[0019] Based on the fourth embodiment of the first aspect, or the fifth embodiment of the first aspect, the embodiment of the present application further provides a sixth embodiment of the first aspect: four ground pins are set between adjacent differential pair pins, and along the arrangement direction of the gold finger interface, the four ground pins on one of the first-side gold fingers and the second-side gold fingers are arranged continuously with a pair of differential pair pins on the other side as the center. The four GND pins arranged at intervals have good anti-interference capabilities when the single-line rate further evolves and improves; at the same time, on the basis of reducing the signal crosstalk between the two adjacent pairs of differential pair pins on the same surface, the signal crosstalk between the differential pin pairs on the two surfaces can be further reasonably controlled.

[0020] Based on the sixth embodiment of the first aspect, the embodiment of the present application also provides a seventh embodiment of the first aspect: the four ground pins on one side of the gold finger on the first side are connected via a first conductor sheet, and the four ground pins on one side of the gold finger on the second side are connected via a second conductor sheet; the first conductor sheet is electrically connected to the four third pads, and the second conductor sheet is electrically connected to the four fourth pads, wherein the third pads on one side of the gold finger on the first side correspond one-to-one to the fourth pads on the side of the gold finger on the second side, and the corresponding third pads and fourth pads on both sides are formed by a via. In this way, based on the arrangement of the first conductor sheet and the second conductor sheet, and the POFV process to realize the via formation, the ground pins can be connected to a common ground, which helps to maintain the consistency and stability of high-speed signal transmission and can further effectively suppress noise and interference.

[0021] Based on the fourth implementation of the first aspect or the fifth implementation of the first aspect, the embodiment of the present application further provides an eighth implementation of the first aspect: two ground pins are provided between adjacent differential pair pins, the differential pair pins on the first side of the gold finger are arranged correspondingly to the two ground pins on the second side of the gold finger, and the differential pair pins on the second side of the gold finger are arranged correspondingly to the two ground pins on the first side of the gold finger. In this way, the differential signal definition of the serial bus pin area is relatively compact, and the number of pins used to define the management control signal pin area and the second power supply (low-voltage power supply) pin area is relatively large.

[0022] In actual applications, the two ground pins on one side of the gold finger on the first side are connected via a first conductor plate, and the two ground pins on the other side of the gold finger on the second side are connected via a second conductor plate. The first conductor plate is electrically connected to the three third pads, and the second conductor plate is electrically connected to the three fourth pads. The two third pads on either side of the first conductor plate correspond one-to-one with the four pads on either side of the second conductor plate, and the corresponding third and fourth pads on either side are formed through a via. Similarly, the ground pins on both sides of the gold finger on the first and second sides are connected to a common ground, which helps maintain the consistency and stability of high-speed signal transmission and further effectively suppresses noise and interference.

[0023] Based on the fourth implementation of the first aspect, or the fifth implementation of the first aspect, the embodiment of the present application further provides a ninth implementation of the first aspect: a ground pin is set between adjacent differential pair pins.

[0024] In actual use, the ground pin on the first-side gold finger is connected to the first conductor plate, which is electrically connected to the two third pads. The ground pin on the second-side gold finger is connected to the second conductor plate, which is electrically connected to the two fourth pads. The third pads on the first-side gold finger correspond one-to-one with the fourth pads on the second-side gold finger, and the corresponding third and fourth pads on both sides are formed through a via. This arrangement allows the ground pins on both sides of the first and second-side gold fingers to be connected to a common ground, helping to maintain the consistency and stability of high-speed signal transmission and further effectively suppressing noise and interference.

[0025] A second aspect of an embodiment of the present application provides an electronic device, which includes a housing and a motherboard and a memory module arranged in the housing; a DIMM connector is provided on the motherboard; the memory module is plugged into the DIMM connector on the motherboard, and the memory module is the memory module described above.

[0026] In practical applications, the electronic device may be a server, a computer, or a high-performance computing cluster. In addition, the electronic device may also be a switch or a router.

[0027] The third aspect of an embodiment of the present application provides a signal transmission method, which is applied to a memory module. Specifically, the memory module is a dual in-line memory module, including a circuit board, a processing chip and multiple memory chips arranged on the circuit board, and a gold finger interface located at the edge of the circuit board, and the circuit board is provided with an anti-foolproofing latch and a locking latch; wherein, the multiple memory chips are connected to the processing chip through a parallel bus, and the processing chip is connected to the gold finger interface through a serial bus; the signal transmission method includes the following steps: transmitting data signals, control signals and power signals through the gold finger interface of the memory module.

[0028] Based on the third aspect, the embodiment of the present application also provides a first implementation method of the third aspect: the gold finger interface includes a first power pin area, a second power pin area, a serial bus pin area and a management control signal pin area, and are respectively arranged on both sides of the circuit board; the first power pin area is used to provide a first voltage power supply, and the second power pin area is used to provide a second voltage power supply, and the voltage of the second voltage power supply is lower than the voltage of the first voltage power supply; both sides of the circuit board include two serial bus pin areas, in the arrangement direction of the gold finger interface, the first power pin area is located at one end of the circuit board, one serial bus pin area is arranged adjacent to the first power pin area, and the other serial bus pin area is located at the other end of the circuit board, and the management control signal pin area and the second power pin area are located between the two serial bus pin areas; at the same time, data signals, control signals and power signals are transmitted through the gold finger interface, including: transmitting data signals through the serial bus pin area, transmitting control signals through the management control signal pin area, transmitting the first power signal in the power signal through the first power pin area, and transmitting the second power signal in the power signal through the second power pin area. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0030] FIG2 is a schematic diagram of a memory module structure provided in an embodiment of the present application;

[0031] FIG3 is a schematic diagram of a gold finger interface arrangement of a memory module provided in an embodiment of the present application;

[0032] FIG4 is a partial enlarged schematic diagram of the serial bus pin area of ​​the gold finger interface shown in FIG3 ;

[0033] FIG5 is a schematic diagram showing the position relationship between the pins and pads on both sides of the serial bus pin area shown in FIG3;

[0034] FIG6 is a schematic diagram of another arrangement of gold finger interfaces of a memory module provided in an embodiment of the present application;

[0035] FIG7 is a partial enlarged schematic diagram of the serial bus pin area of ​​the gold finger interface shown in FIG6 ;

[0036] FIG8 is a schematic diagram showing the position relationship between the pins and pads on both sides of the serial bus pin area shown in FIG6;

[0037] FIG9 is a schematic diagram of a layout of a gold finger interface of another memory module provided in an embodiment of the present application;

[0038] FIG10 is a partial enlarged schematic diagram of the serial bus pin area of ​​the gold finger interface shown in FIG9 ;

[0039] FIG11 is a schematic diagram showing the position relationship between the pins and pads on both sides of the serial bus pin area shown in FIG9 . DETAILED DESCRIPTION

[0040] The embodiment of the present application provides a memory module that can provide technical support for improving the high-density layout of the architecture on the basis of obtaining a higher data transmission rate.

[0041] For the convenience of description, the terms involved in this application are first explained as follows.

[0042] DIMM connector: A connector used to install and connect memory modules, using parallel high-speed transmission technology to provide the memory capacity and performance required by the system. DIMM connectors can support different standard protocols, such as, but not limited to, 288-pin connectors that support DDR4 SDRAM (4th generation double data rate synchronous dynamic random access memory) or DDR5 SDRAM (5th generation double data rate synchronous dynamic random access memory) standard protocols.

[0043] Memory Expansion Module: A hardware device used to increase the memory capacity of a computer system. Memory expansion modules are typically plug-in boards that provide additional physical memory to expand the system's available memory capacity.

[0044] A memory expansion chip is an integrated circuit processing chip used to expand a computer system's memory capacity. Typically integrated into a memory expansion module or other expansion device, a memory expansion chip manages and controls the additional physical memory to ensure compatibility and interoperability with the computer system. Memory expansion chips that implement memory expansion based on a serial memory solution transmit data and control signals via a serial bus, achieving higher data transfer rates.

[0045] For the connection between the memory expansion board and the motherboard, a typical method is to use the GENZ connector for vertical connection. The GENZ connector is relatively high and is limited by the internal space of the device. The board width of the memory expansion module cannot meet the layout requirements of larger-sized expansion chips. Another typical method is to use the GENZ splint connector for flat connection. The memory expansion module is arranged parallel to the motherboard, which occupies a large space on the motherboard surface and is not conducive to the high-density implementation of the architecture.

[0046] Based on this, an embodiment of the present application provides a memory module, which includes a circuit board and a processing chip and multiple memory chips arranged on the circuit board; the edge of the circuit board has a gold finger interface that is compatible with the DIMM connector, wherein the circuit board is provided with an anti-fool-proofing latch and a locking latch, and the multiple memory chips are arranged on the two side surfaces of the circuit board; wherein the multiple memory chips are connected to the processing chip via a parallel bus, and the processing chip is connected to the gold finger interface via a serial bus. The "gold finger layout" here refers to the ability to achieve electrical connection between the gold fingers and the pins on the side of the DIMM connector, and can include the position and spacing of the gold fingers, and can also include the size and number of the gold fingers, etc.

[0047] With this configuration, the memory module can achieve serial interconnection through the connector. On the one hand, the serial bus can reliably increase the data transmission rate, and to a certain extent, it can avoid the crosstalk and synchronous switching noise generated by high-speed transmission based on the parallel bus, which can meet the reliability and stability requirements of signal transmission and effectively improve SI. On the other hand, due to the relatively small height of the DIMM connector, for the same assembly space, the circuit board provided by this solution has a relatively large board width, which can realize the layout of larger and more devices. In addition, the memory module adopts a vertical plug-in connection method, and the actual board area is relatively small. Overall, it provides technical support for the high-density layout and high-performance operation of the architecture.

[0048] In addition, the physical space occupied by the memory module in the electronic device is roughly the same as the physical space occupied by a traditional memory stick, which is conducive to the structural standardization design of the electronic device motherboard and can further improve the structural compatibility of the memory module and the motherboard.

[0049] Please refer to Figure 1, which is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Memory module 300 can be applied to the electronic device shown in Figure 1. In a specific implementation, the electronic device can be a server, a computer, or a high-performance computing cluster. The above technical advantages are particularly significant for high-power, highly integrated, and ultra-large-scale data center servers. In addition, the electronic device can also be a switch or router, etc., which is not limited in the embodiments of the present application.

[0050] As shown in Figure 1, the electronic device includes a housing 100 and a motherboard 200 and a memory module 300 arranged in the housing 100. The motherboard 200 is provided with a CPU 210 and a DIMM connector 220; the circuit board of the memory module 300 is provided with a processing chip 310, and the gold finger interface (not shown in the figure) at the bottom edge of the circuit board is plugged into the DIMM connector 220 on the motherboard 200, that is, the memory module 300 is vertically connected relative to the board surface of the motherboard 200, so that the memory module 300 is electrically connected to the motherboard 200 to realize signal transmission.

[0051] Please also refer to Figure 2, which is a schematic diagram of a memory module structure provided in an embodiment of the present application. In particular, the connection between the processing chip 310 and the gold finger interface 320 on the circuit board of the memory module 300, and between the gold finger interface 320 and the DIMM connector 220, are both connected via a serial protocol standard.

[0052] The plate-like body of memory module 300 is provided with a foolproof tab 301 and a locking tab 302 that mate with DIMM connector 220. This leverages the foolproof structure and locking catch structure (not shown) on the side of DIMM connector 220 to securely assemble memory module 300. This assembly structure based on DIMM connector 220 meets the reliability and stability requirements of memory module 300 assembly, providing technical support for high-speed serial transmission performance without increasing design and implementation costs.

[0053] In a specific implementation, the memory module 300 can be a memory expansion card, and the processing chip 310 is correspondingly a memory expansion chip. Each memory chip 330 is connected to the processing chip 310 via a parallel bus, and is thus managed and controlled by the processing chip 310. FIG. 2 exemplifies six memory chips 330, and the specific number can be determined based on the overall design of the memory expansion card.

[0054] In other specific implementations, the memory module 300 may also be an artificial intelligence training card, an artificial intelligence reasoning card, a graphics processing card, or any other memory module that requires a high-speed transmission interface. This embodiment of the present application is not limited thereto.

[0055] It is understood that the size and spacing of the gold fingers on the gold finger interface 320 of the memory module 300 correspond to the slot pins of the DIMM connector 220. The number of gold fingers provided at the bottom edge of the memory module 300 can be determined based on the actual performance requirements of the memory module. For example, for a 288-pin DIMM connector 220, 288 gold fingers can be provided on the circuit board and all enabled. Alternatively, 288 gold fingers can be provided on the circuit board and some enabled based on performance requirements.

[0056] Of course, the number of golden fingers can be set according to actual activation needs, for example but not limited to 210 golden fingers or 260 golden fingers, etc., as long as serial interconnection can be established by setting corresponding golden fingers. This embodiment of the present application is not limited.

[0057] As shown in Figure 2, the gold finger interface 320 at the bottom edge of the circuit board of the memory module 300 includes a serial bus pin area 321, a first power pin area 322, a management control signal pin area 323, and a second power pin area 324. These areas are located on both sides of the circuit board edge. For ease of description, the portion of the gold finger interface 320 located on one side of the circuit board is defined as the first gold finger, while the portion located on the other side of the circuit board is defined as the second gold finger.

[0058] Serial bus pin area 321 is used to transmit high-speed interconnect signals, such as, but not limited to, data signals, to enable data storage and retrieval. In a specific implementation, serial bus pin area 321 can transmit multiple sets of high-speed interconnect signals. Management control signal pin area 323 is used to transmit low-speed signals, such as, but not limited to, I2C signals, enable signals, or GPIO signals.

[0059] The first power pin region 322 provides a first voltage power source for transmitting a first power signal, such as, but not limited to, 12V. This voltage is converted to a low voltage power source (e.g., 1.2V or 1V) by a secondary power source on the memory module 300, and then powers components such as the memory expansion chip and memory chips on the memory module 300. The second power pin region 324 provides a second voltage power source for transmitting a second power signal, such as, but not limited to, 1.2V, 3.3V, or 5V, and then powers components such as the memory expansion chip and memory chips on the memory module 300.

[0060] It can be understood that if there are many devices arranged on the memory module 300, the overall load is large, and the power supply capacity of the first power pin area 322 cannot meet the working needs of all devices, the second power pin area 324 can provide partial power supply according to the actual operating status; in the specific implementation, power management and control can be performed through the power circuit of the memory expansion chip and the memory module, which will not be repeated here.

[0061] Here, the power supply capability of the first power pin area 322 satisfies the working requirements of various components on the memory module 300 ; the second power pin area 324 can be used as power redundancy to ensure reliable and stable operation of the memory module.

[0062] As shown in FIG. 2 , in the arrangement direction X of the gold finger interface 320 , the first power pin area 322 is located at one end of the circuit board. That is, the 12V pin is set at the side of the circuit board. In this way, the electromagnetic crosstalk that may be generated by the first power pin area 322 outputting a higher voltage to other pin areas can be reduced.

[0063] In this embodiment, the gold finger interface 320 includes two serial bus pin areas 321. In the arrangement direction X of the gold finger interface 320, one serial bus pin area 321 is arranged adjacent to the first power pin area 322, while the other serial bus pin area 321 is located at the other end of the circuit board. The management control signal pin area 323 and the second power pin area 324 are centrally located between the two serial bus pin areas 321 to prevent crosstalk on the pins in the serial bus pin areas 321. Corresponding to the socket pin configuration of the DIMM connector 220, the management control signal pin area 323 and the second power pin area 324 are approximately located in the long pin area of ​​the circuit board, while the first power pin area 322 and the serial bus pin area 321 are located in the short pin area.

[0064] In other specific implementations, the number of serial bus pin areas 321 can be determined according to the high-speed transmission performance requirements of the memory module.

[0065] While properly controlling crosstalk between pins, the regional layout of each of the aforementioned pin areas must also take into account the layout of components on the memory module 300. For example, for a memory expansion card, if the memory expansion chip is placed in the center of the circuit board and the memory chips are arranged on either side of the memory expansion chip, the management control signal pin area 323 and the second power pin area 324 can be placed between the two serial bus pin areas 321 to optimize the internal circuit board wiring. Furthermore, the gold finger interface 320 also includes a differential clock pin, which can be placed adjacent to one of the two serial bus pin areas 321.

[0066] The management control signal pin area 323 and the second power pin area 324 may include two management control signal pin areas 323. As shown in FIG2 , the two management control signal pin areas 323 are arranged on either side of the second power pin area 324. In other specific implementations, multiple second power pin areas 324 may be included, each configured with a different supply voltage. Furthermore, in the arrangement direction of the gold finger interface, the two management control signal pin areas 323 may be staggered between the second power pin areas 324.

[0067] It is understood that the management control signal pin area 323 and the second power pin area 324 disposed between the two serial bus pin areas 321 can be defined based on the low-voltage power supply voltage and the number of low-speed signals, respectively, to provide partial power to the components on the circuit board and control signal channels for the memory modules. The specific arrangement can be flexibly arranged based on the overall product design and is not limited in this embodiment.

[0068] To better understand the technical solutions and effects of this application, without loss of generality, specific embodiments will be described in detail below with reference to the accompanying drawings. Please refer to Figure 3, which is a schematic diagram of the layout of a gold finger interface 320a of a memory module provided in an embodiment of this application. As shown in the figure, the 144 pins of the first-side gold fingers 320A and the 144 pins of the second-side gold fingers 320B are arranged sequentially on the respective sides of the circuit board, with each pin on the T side corresponding to the pin on the B side.

[0069] In this embodiment, the first side gold finger 320A and the second side gold finger 320B each include a first power pin area 322 with a supply voltage of 12V, two serial bus pin areas 321a, two management control signal pin areas 323a and three second power pin areas 324a.

[0070] The pins on the left side of the surface are defined as the first power pin area 322 for 12V power supply, which is located in the same position as the 12V power supply pins of a standard DDR5 memory module. The pin area adjacent to the first power pin area 322 is defined as a serial bus pin area 321a, that is, this serial bus pin area 321a is arranged adjacent to the first power pin area 322. The pin area on the right side of the surface is defined as another serial bus pin area 321a. The pin area between the two serial bus pin areas 321a is defined as two management control signal pin areas 323a and three second power pin areas 324a, respectively. The pin areas are, in order, the first second power pin area 324a, the first management control signal pin area 323a, the second second power pin area 324a, the third second power pin area 324a, and the second management control signal pin area 323a.

[0071] In a specific implementation, the three second power pin areas 324a can provide different power supply voltages, such as but not limited to providing 1.2V, 3.3V or 5V power supply voltages respectively, to meet the functional requirements of different devices on the memory module.

[0072] The first-side gold finger 320A and the second-side gold finger 320B each have two lanes of eight serial signal pins, providing x16 high-speed transmission bandwidth. The serial bus pin area 321a includes eight differential pairs of pins, with two differential signal pins forming a differential pair for transmitting differential signals. Four ground pins (GND) are defined between adjacent differential pairs of pins. Please also refer to Figure 4, which illustrates the layout of the serial bus pin area 321a of the gold finger interface 320a shown in Figure 3. The serial bus pin area 321a shown in the figure is the serial bus pin area located on the left end of Figure 3, and the pin layout is clearly illustrated through a partial magnification. It will be understood that the pin layout of the two serial bus pin areas 321a is the same, so the serial bus pin area located on the right end of Figure 3 is not magnified for illustration.

[0073] In this embodiment, the serial bus pin area 321a of the first-side gold fingers 320A and second-side gold fingers 320B has four GND pins 3212 spaced between adjacent differential pin pairs 3211 to reduce signal crosstalk during high-speed serial transmission. These four spaced GND pins provide excellent anti-interference capabilities as the single-pair rate further evolves.

[0074] As shown in Figure 4 , the differential pair pins 3211 of the first-side gold fingers 320A are arranged alternately with the differential pair pins 3211 of the second-side gold fingers 320B. Specifically, along the layout direction of the gold finger interface, the four GND pins 3212 on one of the first-side gold fingers 320A and the second-side gold fingers 320B are arranged continuously with the pair of differential pair pins 3211 on the other side as the center. In other words, two pins of the differential pair pins 3211 on one side of the board are arranged corresponding to the middle two of the four consecutive GND pins 3212 on the other side of the board. This reduces signal crosstalk between two adjacent pairs of differential pins 3211 on the same side, and further effectively controls signal crosstalk between the differential pin pairs on the two sides.

[0075] In other specific implementations, for the serial bus pin area 321a of the first-side gold finger 320A and the second-side gold finger 320B, the four GND pins 3212 on one are not limited to being arranged continuously with a pair of differential pair pins 3211 on the other as the center. For example, but not limited to, the two pins of the differential pair pins 3211 on one side of the board are arranged corresponding to the two GND pins located on the side (left or right) of the four GND pins 3212 on the other side of the board, which can also reduce the signal crosstalk between the differential pin pairs on the two sides.

[0076] As shown in Figures 3 and 4 , the memory module's gold finger interface 320a described in this embodiment includes a pair of differential clock pins 325 located between the serial bus pin area 321a on the left side of the first-side gold finger 320A and the 12V first power pin area 322. Of course, the differential clock pins 325 can also be located adjacent to other serial bus pin areas 321a, including adjacent to any serial bus pin area 321a on the second-side gold finger 320B. This embodiment of the present application is not limited thereto.

[0077] Optionally, to further reduce noise interference in the first power pin area 322, two dummy pins 326 are provided between the first power pin area 322 and the differential clock pins 325 of the first-side gold finger 320A. "Dummy pins" here refer to pins that are not assigned any signals. Two dummy pins 326 are also provided between the first power pin area 322 and the serial bus pin area 321a of the second-side gold finger 320B. The provision of dummy pins effectively prevents 12V noise from interfering with the differential signal.

[0078] In other specific implementations, the number of the above-mentioned empty pins 326 can be one, or multiple, of other numbers. It should be understood that too many empty pins will affect the number of available pins. In comparison, setting two empty pins between the 12V power pin and the differential signal effectively prevents the impact of 12V noise while allowing for a reasonable allocation of the number of available pins.

[0079] Optionally, to support the signal transmission rate under this serial standard protocol, in a specific implementation, the electrical connection between each pin of the gold finger interface and the corresponding conductor layer within the circuit board can be achieved through the POFV (plated over filled via) process. The POFV process is a special plugging process for VIP (Vias In Pad). It uses materials such as resin to plug the through-hole, and then copper is electroplated to form the pad. This can improve the PCB layout density and electrical performance. Please refer to Figure 5, which shows the schematic diagram of the position relationship of the pins and pads on both sides of the serial bus pin area shown in Figure 3. Figure 5 (a) shows the position relationship of the pins and pads of the gold finger 320A on the first side, and Figure 5 (b) shows the position relationship of the pins and pads of the gold finger 320B on the second side.

[0080] In the arrangement direction of the gold finger interface, the first solder pad 3211A electrically connected to the differential pair pin 3211 on one side of the first-side gold finger 320A, and the second solder pad 3211B electrically connected to the differential pair pin 3211 on one side of the second-side gold finger 320B are arranged at intervals, and corresponding electrical connections are respectively achieved through conductors in the circuit board (not shown in the figure); and in the extension direction of the gold finger, the first solder pad 3211A and the second solder pad 3211B of each differential pair pin 3211 are staggered with the solder pad of the GND pin 3212. Specifically, relative to the solder pad electrically connected to the GND pin 3212, the first solder pad 3211A and the second solder pad 3211B are arranged on the circuit board away from the gold finger.

[0081] As shown in Figure 5(a), the four GND pins 3212 between the two pairs of differential pins 3211 on the first side of the gold finger 320A are connected via a first conductor plate 3213A to achieve the same ground potential. As shown in Figure 5(b), the four GND pins 3212 between the two pairs of differential pins 3211 on the second side of the gold finger 320B are connected via a second conductor plate 3213B to achieve the same ground potential. This common ground connection between the pins on each side helps maintain the consistency and stability of high-speed signal transmission and further effectively suppresses noise and interference.

[0082] Furthermore, the first conductor plate 3213A on the first-side gold finger 320A is electrically connected to the four third pads 3212A, and the second conductor plate 3213B on the second-side gold finger 320B is electrically connected to the four fourth pads 3212B. The third pads 3212A and fourth pads 3212B are spaced apart in the arrangement direction of the gold finger interface. As shown by the dotted lines in FIG5 , the third pads 3212A on the first-side gold finger 320A correspond one-to-one with the fourth pads 3212B on the second-side gold finger 320B. The corresponding third pads 3212A and fourth pads 3212B on both sides are formed through a via. Furthermore, the GND pins on both sides of the board have the same ground potential.

[0083] In the implementation scheme described in FIG3 , four ground pins are defined between two adjacent differential pairs of pins in the serial bus pin area. In other specific implementations, other numbers of ground pins may be defined based on overall design requirements, such as, but not limited to, defining two ground pins or one ground pin between two adjacent differential pairs of pins.

[0084] Please refer to Figures 6 and 7 , where Figure 6 is a schematic diagram of the layout of the gold finger interface of another memory module provided in an embodiment of the present application, and Figure 7 is a partially enlarged schematic diagram of the serial bus pin area of ​​the gold finger interface shown in Figure 6 . To clearly illustrate the differences and connections between this embodiment and the gold finger interface layout described in Figure 3 , components or structures with the same functions are indicated with the same reference numerals in the figures.

[0085] The gold finger interface 320b provided in this embodiment includes both the first gold finger 320A and the second gold finger 320B, which include a first power pin area 322 with a 12V supply voltage, two serial bus pin areas 321b, two management control signal pin areas 323b, and three second power pin areas 324b. In terms of overall layout, as shown in Figure 6, the two management control signal pin areas 323b and the three second power pin areas 324b are also defined between the two serial bus pin areas 321b, in the order of the first management control signal pin area 323b, the first second power pin area 324b, the second second power pin area 324b, the third second power pin area 324b, and the second management control signal pin area 323b. One serial bus pin area 321b is defined in the pin area adjacent to the first power pin area 322, while the other serial bus pin area 321b is defined in the pin area to the right.

[0086] Two ground pins (GND) are defined between adjacent differential pin pairs in the serial bus pin area 321b. Referring also to Figure 7, two consecutive GND pins 3212 are located between adjacent differential pin pairs 3211 on the first-side gold finger 320A and the second-side gold finger 320B. Furthermore, the differential pin pairs 3211 on the first-side gold finger 320A are interleaved with the differential pin pairs 3211 on the second-side gold finger 320B. In other words, the GND pins 3212 on the second-side gold finger 320B are defined as the pins corresponding to the differential pin pairs 3211 on the first-side gold finger 320A, and the differential pins 3211 on the second-side gold finger 320B are defined as the pins corresponding to the GND pins 3212 on the first-side gold finger 320A. This reduces signal crosstalk between the differential pin pairs on the two sides. Compared with the implementation scheme described in Figure 3, the differential signal definition of the serial bus pin area 321b in this implementation scheme is more compact, and the number of pins used to define the management control signal pin area 323b and the second power supply (low voltage power supply) pin area 324b is relatively large.

[0087] Please refer to Figure 8, which shows a schematic diagram of the position relationship between the pins and pads on both sides of the serial bus pin area shown in Figure 6, wherein Figure 8 (a) shows the position relationship between the pins and pads of the first-side gold finger 320A, and Figure 8 (b) shows the position relationship between the pins and pads of the second-side gold finger 320B.

[0088] Within the circuit board, first pads 3211A electrically connected to differential pair pins 3211 on the first-side gold finger 320A and second pads 3211B electrically connected to differential pair pins 3211 on the second-side gold finger 320B are staggered, and are electrically connected to each other via conductors within the circuit board (not shown). Similarly, first pads 3211A and second pads 3211B of each differential pair pin 3211 are staggered relative to the pads of GND pin 3212.

[0089] As shown in FIG8(a), the two GND pins 3212 between the two pairs of differential pins 3211 on one side of the first-side gold finger 320A are connected via a first conductor plate 3213A1 to obtain the same ground potential. As shown in FIG8(b), the two GND pins 3212 between the two pairs of differential pins 3211 on one side of the second-side gold finger 320B are connected via a second conductor plate 3213B1 to obtain the same ground potential.

[0090] Furthermore, a first conductor patch 3213A1 on one side of the first-side gold finger 320A is electrically connected to three third pads 3212A, and a second conductor patch 3213B1 on the second-side gold finger 320B is electrically connected to three fourth pads 3212B. The third pads 3212A and fourth pads 3212B are spaced apart in the arrangement direction of the gold finger interface. As shown by the dotted lines in Figure 8 , the two third pads 3212A on either side of the first conductor patch 3213A1 and the two fourth pads 3212B1 on either side of the second conductor patch 3213B1 correspond one-to-one, and the corresponding third pads 3212A and fourth pads 3212B are formed through a single via. Furthermore, the GND pins on both sides of the board have the same ground potential, which helps maintain consistency and stability in high-speed signal transmission and effectively suppresses noise and interference.

[0091] Please refer to Figures 9 and 10 , where Figure 9 is a schematic diagram of a gold finger interface layout for another memory module provided in an embodiment of the present application, and Figure 10 is a partially enlarged schematic diagram of the serial bus pin area of ​​the gold finger interface shown in Figure 9 . To clearly illustrate the differences and connections between this embodiment and the gold finger interface layout described in Figures 3 and 6 , components or structures with the same functions are indicated with the same reference numerals in the figures.

[0092] The gold finger interface 320c provided in this embodiment includes both the first gold finger 320A and the second gold finger 320B, which include a first power pin area 322 with a 12V supply voltage, two serial bus pin areas 321c, two management control signal pin areas 323c, and three second power pin areas 324c. In terms of overall layout, as shown in Figure 9, the two management control signal pin areas 323c and the three second power pin areas 324c are defined between the two serial bus pin areas 321c, in the order of the first management control signal pin area 323c, the first second power pin area 324c, the second second power pin area 324c, the third second power pin area 324c, and the second management control signal pin area 323c. One serial bus pin area 321c is defined in the pin area adjacent to the first power pin area 322, while the other serial bus pin area 321c is defined in the pin area to the right.

[0093] A ground pin (GND) is defined between adjacent differential pairs of pins in the serial bus pin area 321c. Referring also to Figure 10 , a GND pin 3212 is defined between adjacent pairs of differential pins 3211 on the first-side gold finger 320A and the second-side gold finger 320B. Furthermore, the differential pins 3211 on the first-side gold finger 320A are interleaved with the differential pins 3211 on the second-side gold finger 320B. In other words, the pin on the second-side gold finger 320B corresponding to the differential pin 3211 on the first-side gold finger 320A is defined as either the GND pin 3212 or the differential pin 3211, while the pin on the second-side gold finger 320B corresponding to the GND pin 3212 on the first-side gold finger 320A is defined as the other of the differential pins 3211. Compared with the implementation schemes described in Figures 3 and 6, the differential signal definition of the serial bus pin area 321b in this implementation scheme is the most compact, and the number of pins used to define low-voltage power supply and low-speed signals is richer, which facilitates the implementation of corresponding layout according to the needs of different application scenarios.

[0094] Please refer to Figure 11, which shows a schematic diagram of the position relationship between the pins and pads on both sides of the serial bus pin area shown in Figure 9, wherein Figure 9 (a) shows the position relationship between the pins and pads of the first-side gold finger 320A, and Figure 9 (b) shows the position relationship between the pins and pads of the second-side gold finger 320B.

[0095] Within the circuit board, first pads 3211A electrically connected to differential pair pins 3211 on the first-side gold finger 320A and second pads 3211B electrically connected to differential pair pins 3211 on the second-side gold finger 320B are staggered, and are electrically connected to each other via conductors within the circuit board (not shown). Similarly, first pads 3211A and second pads 3211B of each differential pair pin 3211 are staggered relative to the pads of GND pin 3212.

[0096] As shown in Figure 11(a), the GND pin 3212 on the first-side gold finger 320A is connected to the first conductor plate 3213A1, and the first conductor plate 3213A2 is electrically connected to the two third pads 3212A. As shown in Figure 11(b), the GND pin 3212 on the second-side gold finger 320B is connected to the second conductor plate 3213B1, and the second conductor plate 3213B2 is electrically connected to the two fourth pads 3212B. The third pads 3212A and fourth pads 3212B are spaced apart in the arrangement direction of the gold finger interface. As shown by the dotted lines in Figure 11, the two third pads 3212A electrically connected to the first conductor plate 3213A2 correspond one-to-one with the two fourth pads 3212B1 electrically connected to the second conductor plate 3213B1. The corresponding third pads 3212A and fourth pads 3212B on either side are formed through a via, ensuring that the GND pins on both sides of the board have the same ground potential. This common ground connection helps maintain consistency and stability in high-speed signal transmission and effectively suppresses noise and interference.

[0097] Based on the gold finger interface definition methods described in the previous embodiments, selection can be made based on the actual needs of different application scenarios. For example, when the serial transmission rate needs to be increased to above 16GBPS, a memory module with the gold finger interface definition method described in Figure 3 can be selected to meet the functional needs of single-pair rate increase based on its excellent anti-crosstalk capability. For another example, when the motherboard needs to provide more low-speed signals and low-voltage power supply channels, a memory module with the gold finger interface definition method described in Figure 9 can be selected to achieve a corresponding layout based on the richer number of low-voltage power supply and low-speed signal pins.

[0098] In a specific implementation, taking a memory expansion card as an example, the memory expansion card is installed on the DIMM connector on the motherboard. The system can recognize and utilize the additional memory provided by the memory chip on the memory expansion card, and thereby provide more available memory capacity for the operating system and application programs. The application of the memory expansion card provided in the embodiment of the present application can effectively improve the performance and processing power of the computer system. For example, the computer system can determine the data storage location based on the access frequency. For example, data with a higher access frequency can be stored in the storage space provided by the system memory bar, and data with a relatively low access frequency can be stored in the storage space provided by the memory chip of the memory expansion card. In particular, when it is necessary to process large data sets, run memory-intensive applications, or perform complex computing tasks, the technical advantages are particularly significant.

[0099] It should be noted that the aforementioned memory modules, which are physically connected and electrically connected at high speed via DIMM connectors, can also be used in other scenarios requiring serial signal transmission based on DIMM connectors, such as, but not limited to, existing computing or storage products, as well as future computing or storage products. This is not limited in the present application.

[0100] Based on the aforementioned memory module, an embodiment of the present application further provides a signal transmission method, which includes the following steps:

[0101] Data signals, control signals and power signals are transmitted through the gold finger interface.

[0102] Optionally, the transmission of data signals, control signals and power signals through the gold finger interface includes: transmitting data signals through the serial bus pin area, transmitting control signals through the management control signal pin area, and transmitting the first power signal in the power signal through the first power pin area.

[0103] Further optionally, the transmitting of the data signal, the control signal and the power signal through the gold finger interface includes: transmitting the second power signal among the power signals through the second power pin area.

[0104] It should be noted that the directional terms "bottom," "left end," and "right end" used herein are defined based on the memory module's state as shown in the diagram. Memory modules assembled and used in actual scenarios are not limited to the states shown in the diagram. For example, when in use, the motherboard of an electronic device extends vertically, or the motherboard's extension direction forms a certain angle with the vertical. It should be understood that the use of these directional terms does not constitute a substantial limitation on the memory module described in this application.

[0105] In addition, the ordinal numbers "first," "second," "third," and "fourth" used herein are only used to describe components or structures with the same function in the technical solution. It is understood that the use of the above ordinal numbers does not constitute an understanding of the technical solution claimed in this application.

[0106] The above are only preferred embodiments of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A memory module, characterized in that: The memory module is a dual in-line memory module, comprising: A circuit board, wherein the circuit board is provided with an anti-foolproofing bayonet and a locking bayonet; A processing chip and a plurality of memory chips disposed on the circuit board; A gold finger interface located at the edge of the circuit board; The plurality of memory chips are connected to the processing chip via a parallel bus, and the processing chip is connected to the gold finger interface via a serial bus.

2. The memory module according to claim 1, characterized in that: The gold finger interface includes a first power pin area, a second power pin area, a management control signal pin area and a serial bus pin area, and is respectively arranged on two side surfaces of the circuit board; the first power pin area is used to provide a first voltage power supply, and the second power pin area is used to provide a second voltage power supply, and the voltage of the second voltage power supply is lower than the voltage of the first voltage power supply; Both side surfaces of the circuit board include two serial bus pin areas. In the arrangement direction of the gold finger interface, the first power pin area is located at one end of the circuit board, one of the two serial bus pin areas is arranged adjacent to the first power pin area, and the other of the two serial bus pin areas is located at the other end of the circuit board, and the management control signal pin area and the second power pin area are located between the two serial bus pin areas.

3. The memory module according to claim 2, wherein: Empty pins are arranged between the first power pin area and the adjacent serial bus pin area.

4. The memory module according to claim 3, characterized in that: The gold finger interface further includes a differential clock pin, and the differential clock pin is located between the empty pin and the serial bus pin area arranged adjacent to the first power pin area.

5. The memory module according to any one of claims 2 to 4, characterized in that: The serial bus pin area includes differential pair pins arranged at intervals, the differential pair pins include two differential signal pins for transmitting differential signals, and a ground pin is arranged between two adjacent pairs of the differential pair pins; the portion of the gold finger interface located on one side of the circuit board is the first side gold finger, and the portion of the gold finger interface located on the other side of the circuit board is the second side gold finger.

6. The memory module according to claim 5, characterized in that: The serial bus pin area includes eight pairs of differential pair pins arranged at intervals, and the differential pair pins of the first-side gold fingers and the differential pair pins of the second-side gold fingers are arranged in an alternating manner.

7. The memory module according to claim 6, wherein: Four ground pins are arranged between adjacent differential pair pins. Along the arrangement direction of the gold finger interface, the four ground pins on one of the first gold finger and the second gold finger are arranged continuously with a pair of differential pair pins on the other as the center.

8. The memory module according to claim 7, wherein: The four ground pins on one side of the first-side gold finger are connected through a first conductor sheet, and the four ground pins on one side of the second-side gold finger are connected through a second conductor sheet; the first conductor sheet is electrically connected to four third pads, and the second conductor sheet is electrically connected to four fourth pads, wherein the third pads on one side of the first-side gold finger correspond one to one with the fourth pads on one side of the second-side gold finger, and the corresponding third pads and fourth pads on both sides are formed by a via.

9. The memory module according to claim 6, wherein: Two ground pins are arranged between adjacent differential pair pins, the differential pair pins on one side of the first-side gold finger are arranged correspondingly to the two ground pins on one side of the second-side gold finger, and the differential pair pins on one side of the second-side gold finger are arranged correspondingly to the two ground pins on one side of the first-side gold finger.

10. The memory module according to claim 9, characterized in that: The two ground pins on one side of the first-side gold finger are connected through a first conductor sheet, and the two ground pins on one side of the second-side gold finger are connected through a second conductor sheet; the first conductor sheet is electrically connected to three third pads, and the second conductor sheet is electrically connected to three fourth pads, wherein the two third pads on both sides electrically connected to the first conductor sheet and the fourth pads on both sides electrically connected to the second conductor sheet correspond one to one, and the corresponding third pads and fourth pads on both sides are formed by a via.

11. The memory module according to claim 6, wherein: A ground pin is arranged between adjacent differential pair pins.

12. The memory module according to claim 11, wherein: The ground pin on one side of the first-side gold finger is connected to the first conductor sheet, and the first conductor sheet is electrically connected to two third pads; the ground pin on one side of the second-side gold finger is connected to the second conductor sheet, and the second conductor sheet is electrically connected to two fourth pads; wherein the third pad on one side of the first-side gold finger corresponds one to the fourth pad on one side of the second-side gold finger, and the corresponding third pad and fourth pad on both sides are formed by a via.

13. The memory module according to any one of claims 1 to 12, characterized in that: The memory module is a memory expansion card, and a plurality of memory chips are arranged on the circuit board. The processing chip is a memory expansion chip used for managing and controlling the plurality of memory chips.

14. An electronic device, characterized in that: It comprises a shell and a mainboard and a memory module arranged in the shell; a DIMM connector is arranged on the mainboard; the memory module is plugged into the DIMM connector on the mainboard, and the memory module is the memory module described in any one of claims 1 to 13.

15. A signal transmission method, characterized in that: The signal transmission method is applied to a memory module, which is a dual in-line memory module. The memory module includes a circuit board, a processing chip, a plurality of memory chips and a gold finger interface. The circuit board is provided with an anti-foolproofing bayonet and a locking bayonet. The processing chip and the plurality of memory chips are arranged on the circuit board, and the gold finger interface is located at the edge of the circuit board; wherein the plurality of memory chips are connected to the processing chip via a parallel bus, and the processing chip is connected to the gold finger interface via a serial bus; the method includes the following steps: Data signals, control signals and power signals are transmitted through the gold finger interface.

16. The signal transmission method according to claim 15, characterized in that: The gold finger interface includes a first power pin area, a second power pin area, a serial bus pin area and a management control signal pin area, and they are respectively arranged on both sides of the circuit board; the first power pin area is used to provide a first voltage power supply, and the second power pin area is used to provide a second voltage power supply, and the voltage of the second voltage power supply is lower than the voltage of the first voltage power supply; both sides of the circuit board include two serial bus pin areas, in the arrangement direction of the gold finger interface, the first power pin area is located at one end of the circuit board, one of the two serial bus pin areas is arranged adjacent to the first power pin area, and the other of the two serial bus pin areas is located at the other end of the circuit board, and the management control signal pin area and the second power pin area are located between the two serial bus pin areas; The transmitting of data signals, control signals and power signals through the gold finger interface includes: The data signal is transmitted through the serial bus pin area, the control signal is transmitted through the management control signal pin area, the first power signal among the power signals is transmitted through the first power pin area, and the second power signal among the power signals is transmitted through the second power pin area.

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