Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device which is driven at a high speed. This semiconductor device is provided with a transistor having first to fourth metal oxide layers. The second metal oxide layer is provided on the first metal oxide layer. The third and fourth metal oxide layers both have a region in contact with a side surface of the first and second metal oxide layers. The third metal oxide layer and the fourth metal oxide layer face each other across the first and second metal oxide layers. A gate electrode of the transistor has a region located between the first metal oxide layer and the second metal oxide layer, and is provided so as to surround the upper surface, lower surface, and side surfaces of the second metal oxide layer across a gate insulating layer in a predetermined cross-sectional view. A source electrode and a drain electrode of the transistor each have a region in contact with a side surface of the third and fourth metal oxide layers on the side opposite to the second metal oxide layer.

Description

Semiconductor device and method for manufacturing the same

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, the development of semiconductor devices has progressed, and semiconductor devices mainly use LSIs (Large Scale Integration), CPUs (Central Processing Units), memories, etc. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, metal oxides have also attracted attention as other materials.

[0007] Furthermore, it is known that transistors using metal oxides have extremely low leakage current in an off state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the low leakage current characteristic of transistors using metal oxides. Furthermore, for example, Patent Document 2 discloses a memory device that can retain stored content for a long period of time by utilizing the low leakage current characteristic of transistors using metal oxides.

[0008] In recent years, with the trend toward smaller and lighter electronic devices, there has been an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using a metal oxide film and a second transistor using a metal oxide film to provide multiple overlapping memory cells. Patent Document 4 also discloses a technique for increasing the density of integrated circuits by vertically arranging the channels of transistors using a metal oxide film.

[0009] JP 2012-257187 A JP 2011-151383 A WO 2021 / 053473 JP 2013-211537 A

[0010] M. Oota et. al. , “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53

[0011] As integrated circuits become denser and more multifunctional, semiconductor devices including the integrated circuits are required to operate at high speed. For example, in a memory device in which memory cells are arranged densely and capable of storing a large amount of data, it is required to write and read a large amount of data in a short time. Therefore, it is required to write and read data in a short time.

[0012] An object of one embodiment of the present invention is to provide a semiconductor device with high operating speed.An object of one embodiment of the present invention is to provide a semiconductor device including a transistor with high on-state current.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a low-cost semiconductor device.An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.An object of one embodiment of the present invention is to provide a novel semiconductor device.

[0013] An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high operating speed.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device including a transistor with high on-state current.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device at low cost.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device at low cost.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with low power consumption.An object of one embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device.

[0014] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0015] One embodiment of the present invention includes a first metal oxide layer, a second metal oxide layer, a third metal oxide layer, a fourth metal oxide layer, a first insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer, wherein the second metal oxide layer is provided on the first metal oxide layer, and the third metal oxide layer has a region in contact with a first side surface of the first metal oxide layer and a second side surface of the second metal oxide layer, and the fourth metal oxide layer has a region in contact with a third side surface of the first metal oxide layer opposite to the first side surface and a region in contact with a fourth side surface of the second metal oxide layer opposite to the second side surface, and the first insulating layer has a region in contact with a top surface of the first metal oxide layer and a bottom surface of the second metal oxide layer in a region between the first metal oxide layer and the second metal oxide layer. the first insulating layer has a region in contact with a fifth side of the first metal oxide layer, a region in contact with a sixth side opposite the fifth side, a region in contact with a seventh side of the second metal oxide layer, and a region in contact with an eighth side opposite the seventh side; the first conductive layer has a region located between the first metal oxide layer and the second metal oxide layer and is provided so as to surround the second metal oxide layer with the first insulating layer sandwiched between them; the second conductive layer has a region in contact with a side of the third metal oxide layer opposite to the second metal oxide layer, and the third conductive layer has a region in contact with a side of the fourth metal oxide layer opposite to the second metal oxide layer.

[0016] Alternatively, in the above aspect, the semiconductor device may include a fifth metal oxide layer, the fifth metal oxide layer being provided on the second metal oxide layer, a ninth side surface of the fifth metal oxide layer having a region in contact with the third metal oxide layer, a tenth side surface of the fifth metal oxide layer opposite to the ninth side surface having a region in contact with the fourth metal oxide layer, an upper surface of the second metal oxide layer, a lower surface of the fifth metal oxide layer, a side surface of the third metal oxide layer, and a side surface of the fourth metal oxide layer each having a region in contact with the first insulating layer in a region between the second metal oxide layer and the fifth metal oxide layer, an eleventh side surface of the fifth metal oxide layer and a twelfth side surface opposite to the eleventh side surface each having a region in contact with the first insulating layer, and a first conductive layer being provided to surround the fifth metal oxide layer with the first insulating layer sandwiched therebetween.

[0017] Alternatively, in the above embodiment, the third metal oxide layer and the fourth metal oxide layer may each have the same material as the second metal oxide layer.

[0018] Alternatively, in the above aspect, the semiconductor device may include a transistor, and the transistor may include first to fourth metal oxide layers, a first insulating layer, a second insulating layer, first to third conductive layers, and a fourth conductive layer, the second insulating layer being provided on the fourth conductive layer, and the first metal oxide layer being provided on the second insulating layer so as to have a region overlapping with the fourth conductive layer.

[0019] Alternatively, in the above aspect, the semiconductor device may have a base insulating layer, the first metal oxide layer is provided on the base insulating layer, and the lower surface of the first metal oxide layer, the side surface of the third metal oxide layer, and the side surface of the fourth metal oxide layer each have a region in contact with the first insulating layer in the region between the base insulating layer and the first metal oxide layer, and a first conductive layer may be provided having a region located between the base insulating layer and the first metal oxide layer, and surrounding the first metal oxide layer with the first insulating layer sandwiched therebetween.

[0020] Alternatively, in the above aspect, the third metal oxide layer may have a first layer having a region in contact with the second side surface and a second layer provided outside the first layer, and the fourth metal oxide layer may have a third layer having a region in contact with the fourth side surface and a fourth layer provided outside the third layer, and the first layer and the third layer may each have the same material as the second metal oxide layer.

[0021] Alternatively, in the above aspect, the second conductive layer may have a first layer having a region in contact with the third metal oxide layer and a second layer provided outside the first layer, and the third conductive layer may have a third layer having a region in contact with the fourth metal oxide layer and a fourth layer provided outside the third layer, and the first layer and the third layer may each have a metal oxide.

[0022] Alternatively, in the above embodiment, the first to fourth metal oxide layers each contain one or more elements selected from indium, zinc, and an element M, where the element M is one or more elements selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony, and the first layer and the third layer each may contain indium.

[0023] Alternatively, one embodiment of the present invention includes forming a first metal oxide layer, a first sacrificial layer on the first metal oxide layer, and a second metal oxide layer on the first sacrificial layer; depositing a third metal oxide layer so as to have a region in contact with a first side surface of the first metal oxide layer, a region in contact with a second side surface of the second metal oxide layer, a region in contact with a third side surface opposite to the first side surface, and a region in contact with a fourth side surface opposite to the second side surface, and to have a region located on the second metal oxide layer; forming a first conductive layer on the third metal oxide layer; a first conductive layer is processed to form a second conductive layer and a third conductive layer that faces the second conductive layer with the second metal oxide layer sandwiched therebetween; a fourth metal oxide layer is processed to form a fifth metal oxide layer that faces the fourth metal oxide layer with the second metal oxide layer sandwiched therebetween; the first sacrificial layer is removed; a first insulating layer is formed to cover the first metal oxide layer and the second metal oxide layer; and a fourth conductive layer is formed to cover the first insulating layer.

[0024] Alternatively, in the above aspect, before forming the third metal oxide layer, a second sacrificial layer may be formed on the second metal oxide layer, the third metal oxide layer may be formed to have a region located on the second sacrificial layer, and a planarization treatment may be performed on the second sacrificial layer in the same step as the planarization treatment on the first conductive layer and the third metal oxide layer.

[0025] Alternatively, in the above aspect, a second sacrificial layer may be formed having a first layer and a second layer on the first layer, and the thickness of the first layer may be equal to or less than the thickness of the second layer, and the planarization treatment of the second sacrificial layer may be performed until at least the top surface of the first layer is exposed.

[0026] Alternatively, in the above aspect, before the deposition of the third metal oxide layer, a second sacrificial layer is formed on the second metal oxide layer, and a sixth metal oxide layer is formed on the second sacrificial layer, the third metal oxide layer having a region in contact with the fifth side surface of the sixth metal oxide layer and a region in contact with the sixth side surface opposite the fifth side surface, and a region located on the sixth metal oxide layer, the second sacrificial layer is removed in the same step as the removal of the first sacrificial layer, and the first insulating layer may be formed to cover the sixth metal oxide layer.

[0027] Alternatively, in the above aspect, before the formation of the third metal oxide layer, a third sacrificial layer may be formed on the sixth metal oxide layer, the third metal oxide layer may be formed to have a region located on the third sacrificial layer, and a planarization treatment may be performed on the third sacrificial layer in the same step as the planarization treatment on the first conductive layer and the third metal oxide layer.

[0028] Alternatively, in the above aspect, a third sacrificial layer may be formed having a first layer and a second layer on the first layer, and the thickness of the first layer may be equal to or less than the thickness of the second layer, and the planarization treatment of the third sacrificial layer may be performed until at least the top surface of the first layer is exposed.

[0029] Alternatively, in the above aspect, after forming a fifth conductive layer and a second insulating layer on the fifth conductive layer, a first metal oxide layer may be formed on the second insulating layer, a first sacrificial layer on the first metal oxide layer, and a second metal oxide layer on the first sacrificial layer so as to have an area overlapping with the fifth conductive layer.

[0030] Alternatively, in the above-described embodiment, after forming a base insulating layer and a second sacrificial layer in contact with the upper surface of the base insulating layer, a first metal oxide layer may be formed on the second sacrificial layer, a first sacrificial layer on the first metal oxide layer, and a second metal oxide layer on the first sacrificial layer, and the second sacrificial layer may be removed in the same process as the removal of the first sacrificial layer.

[0031] According to one embodiment of the present invention, a semiconductor device with high operating speed can be provided. According to one embodiment of the present invention, a semiconductor device including a transistor with high on-state current can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a low-cost semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided.

[0032] According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high operating speed can be provided. Alternatively, according to one embodiment of the present invention, a method for manufacturing a semiconductor device including a transistor with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a method for manufacturing a semiconductor device at low cost can be provided. Alternatively, according to one embodiment of the present invention, a method for manufacturing a semiconductor device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a method for manufacturing a novel semiconductor device can be provided.

[0033] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0034] FIGS. 1A to 1D are perspective views showing a structural example of a semiconductor device. FIG. 2A is a plan view showing a structural example of a semiconductor device. FIGS. 2B to 2E are cross-sectional views showing a structural example of a semiconductor device. FIGS. 3A and 3B are cross-sectional views showing a structural example of a semiconductor device. FIGS. 4A to 4D are perspective views showing a structural example of a semiconductor device. FIG. 5A is a plan view showing a structural example of a semiconductor device. FIGS. 5B to 5E are cross-sectional views showing a structural example of a semiconductor device. FIGS. 6A to 6D are perspective views showing a structural example of a semiconductor device. FIGS. 7A to 7D are cross-sectional views showing a structural example of a semiconductor device. FIGS. 8A and 8B are cross-sectional views showing a structural example of a semiconductor device. FIG. 9A is a circuit diagram showing a structural example of a memory cell. FIG. 9B is a cross-sectional view showing a structural example of a memory device. FIGS. 10A and 10B are cross-sectional views showing a structural example of a memory device. FIG. 11A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 11B and 11C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 12A to 12D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 13A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 13B and 13C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 14A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 14B and 14C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 15 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. FIG. 16A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 16B and 16C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 17A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 17B and 17C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 18A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 18B and 18C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 19A to 19D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 20A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 20B and 20C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. Fig. 21A is a plan view illustrating an example of a method for manufacturing a semiconductor device. Fig. 21B to Fig. 21E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. Fig. 22 is a block diagram illustrating an example of a configuration of a memory device. Fig. 23A is a schematic diagram illustrating an example of a configuration of a memory device.FIG. 23B is a schematic diagram and a circuit diagram showing an example of the configuration of a storage device. FIGS. 24A and 24B are schematic diagrams showing an example of the configuration of a storage device. FIGS. 25A to 25C are circuit diagrams showing an example of the configuration of a storage device. FIG. 26 is a circuit diagram showing an example of the configuration of a storage device. FIG. 27 is a cross-sectional view showing an example of the configuration of a storage device. FIG. 28 is a cross-sectional view showing an example of the configuration of a storage device. FIG. 29 is a cross-sectional view showing an example of the configuration of a storage device. FIG. 30 is a cross-sectional view showing an example of the configuration of a storage device. FIGS. 31A and 31B are diagrams showing an example of a semiconductor device. FIGS. 32A and 32B are diagrams showing an example of an electronic component. FIGS. 33A and 33B are diagrams showing an example of an electronic device. FIGS. 33C to 33E are diagrams showing an example of a mainframe computer. FIG. 34 is a diagram showing an example of space equipment. FIG. 35 is a diagram showing an example of a storage system applicable to a data center. FIGS. 36A and 36B are perspective views showing an example of the configuration of a display device. FIG. 37 is a cross-sectional view showing an example of the configuration of a display device. FIG. 38 is a cross-sectional view showing an example of the configuration of a display device. Fig. 39 is a cross-sectional view showing an example of the configuration of a display device. Fig. 40A is a plan view showing an example of the configuration of a display device. Figs. 40B and 40C are cross-sectional views showing an example of the configuration of a display device. Figs. 41A and 41B are cross-sectional views showing an example of the configuration of a display device. Figs. 42A to 42D are diagrams showing an example of an electronic device. Figs. 43A to 43F are diagrams showing an example of an electronic device. Figs. 44A to 44G are diagrams showing an example of an electronic device.

[0035] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in the form and details without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0036] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0037] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0038] In this specification, the ordinal numbers such as "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, an ordinal number assigned to a component in one part of this specification may not match an ordinal number assigned to the same component in another part of this specification or in the claims.

[0039] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing a switching operation to control conduction or non-conduction. The term "transistor" used in this specification includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0040] In this specification and the like, a transistor using a metal oxide for a semiconductor layer and a transistor having a metal oxide for a channel formation region may be referred to as an OS transistor, and a transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0041] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0042] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. Therefore, in this specification, the terms "source" and "drain" may be used interchangeably.

[0043] Note that impurities in a semiconductor refer to, for example, elements other than the main components that constitute the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The inclusion of impurities can, for example, increase the defect level density of the semiconductor or reduce the crystallinity. When the semiconductor is a metal oxide, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the metal oxide. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. Furthermore, for example, the inclusion of impurities can cause oxygen deficiency (V) in the metal oxide. Ｏ (also called) may be formed.

[0044] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0045] To analyze the content of elements such as hydrogen, oxygen, carbon, or nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analytical techniques.

[0046] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0047] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0048] In this specification, "electrically connected" includes a connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistors, coils, capacitors, and other elements with various functions.

[0049] In this specification and the like, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the leakage current between the source and the gate when the voltage V ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0050] In this specification, the term "normally-on" refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, whereas the term "normally-off" refers to a state in which no current flows through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.

[0051] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0052] In this specification, when it is stated that A is located on B, at least a portion of A is located on B. Therefore, for example, it can be rephrased as "A has a region located on B." Similarly, when it is stated that A contacts B or A overlaps B, at least a portion of A contacts B or overlaps B. Therefore, it can be rephrased as "A has a region contacting B" or "A has a region overlapping B," respectively. Similarly, in this specification, when it is stated that A covers B, at least a portion of A covers B. Therefore, for example, it can be rephrased as "A has a region covering B."

[0053] In addition, for example, in the drawings related to this specification, arrows indicating the X direction, Y direction, and Z direction may be added. In this specification, etc., the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." Furthermore, the X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0054] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described with reference to drawings.

[0055] A semiconductor device according to one embodiment of the present invention includes a transistor in which a gate electrode surrounds the top, bottom, and side surfaces of a semiconductor layer in a cross-sectional view. A transistor with such a structure is also called a gate all around (GAA) transistor. The semiconductor layer can contain, for example, a metal oxide.

[0056] In this specification and the like, a layer containing a metal oxide is referred to as a metal oxide layer. The metal oxide layer can be, for example, a semiconductor layer containing a metal oxide. Note that, for example, a conductive layer containing a metal oxide can also be referred to as a metal oxide layer.

[0057] A transistor included in a semiconductor device of one embodiment of the present invention includes a first metal oxide layer, a second metal oxide layer, a third metal oxide layer, and a fourth metal oxide layer. The second metal oxide layer is provided over the first metal oxide layer. The third metal oxide layer and the fourth metal oxide layer each have a region in contact with a side surface of the first metal oxide layer and a side surface of the second metal oxide layer. The third metal oxide layer and the fourth metal oxide layer face each other with the first metal oxide layer and the second metal oxide layer interposed therebetween.

[0058] The gate electrode of the transistor has a region located between the first metal oxide layer and the second metal oxide layer and is provided to surround the upper, lower, and side surfaces of the second metal oxide layer, with the gate insulating layer of the transistor sandwiched therebetween, in a predetermined cross-sectional view. A fifth metal oxide layer may be provided on the second metal oxide layer. In this case, the gate electrode of the transistor has a region located between the second metal oxide layer and the fifth metal oxide layer, in addition to the region located between the first metal oxide layer and the second metal oxide layer. The gate electrode of the transistor is provided to surround not only the second metal oxide layer but also the upper, lower, and side surfaces of the fifth metal oxide layer, with the gate insulating layer of the transistor sandwiched therebetween, in a predetermined cross-sectional view. Furthermore, one or more metal oxide layers may be provided on the fifth metal oxide layer. In this case, the gate electrode of the transistor is provided to surround the upper, lower, and side surfaces of each of the metal oxide layers on the fifth metal oxide layer, with the gate insulating layer of the transistor sandwiched therebetween, in a predetermined cross-sectional view.

[0059] A channel is formed in a metal oxide layer having a region overlapping with a gate electrode of a transistor, specifically, the first metal oxide layer, the second metal oxide layer, the fifth metal oxide layer, or the like. Here, the first metal oxide layer, the second metal oxide layer, the fifth metal oxide layer, or the like can have a flat top surface. Therefore, the transistor included in the semiconductor device of one embodiment of the present invention can be said to be a transistor with a nanosheet structure.

[0060] One of the source electrode and the drain electrode of the transistor has a region in contact with a side surface of the third metal oxide layer, for example, opposite to the second metal oxide layer, and the other of the source electrode and the drain electrode of the transistor has a region in contact with a side surface of the fourth metal oxide layer, for example, opposite to the second metal oxide layer.

[0061] A transistor included in a semiconductor device of one embodiment of the present invention includes a plurality of metal oxide layers, and the top, bottom, and side surfaces of at least one of the plurality of metal oxide layers are surrounded by the gate electrode of the transistor in a predetermined cross-sectional view. This allows the transistor to more effectively apply an electric field for inducing a channel in the metal oxide layer compared to, for example, a transistor including only one metal oxide layer and in which a gate electrode covers only the top surface, only the top and side surfaces, or only the top and bottom surfaces of the metal oxide layer. Therefore, the transistor included in the semiconductor device of one embodiment of the present invention can have a large on-state current. Therefore, the semiconductor device of one embodiment of the present invention can have a high operating speed.

[0062] Furthermore, the more metal oxide layers whose top, bottom, and side surfaces are surrounded by the gate electrode in a cross-sectional view, the larger the volume of the region of the metal oxide layer surrounded by the gate electrode can be without increasing the channel length of the transistor. This allows the on-state current of the transistor to be increased. Therefore, the operating speed of the semiconductor device of one embodiment of the present invention can be increased. On the other hand, the more metal oxide layers there are, the more manufacturing steps there are for the semiconductor device. This increases the manufacturing cost of the semiconductor device, which may increase the price of the semiconductor device, for example. Therefore, it is preferable to determine the number of metal oxide layers in consideration of the performance and price of the semiconductor device.

[0063] The metal oxide layer preferably contains at least indium (In) or zinc (Zn). For example, indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO) can be used for the metal oxide layer. Here, the same material can be used for each of the metal oxide layers provided in the transistor included in the semiconductor device of one embodiment of the present invention. In this case, the boundary (interface) between the metal oxide layers may not be clearly visible. Note that, for example, even when different materials are used for two metal oxide layers and there is a region where these two metal oxide layers are in contact with each other, the boundary (interface) between the two metal oxide layers may not be clearly visible.

[0064] An example of a method for manufacturing a transistor having first, second, fourth, and fifth metal oxide layers, in which the top, bottom, and side surfaces of the second metal oxide layer are surrounded by a gate electrode in a cross-sectional view, is described below. First, a first metal oxide layer, a sacrificial layer, and a second metal oxide layer are sequentially formed on a substrate. The first metal oxide layer and the second metal oxide layer can be formed by, for example, a sputtering method or an atomic layer deposition (ALD) method. The sacrificial layer can be made of, for example, aluminum oxide.

[0065] Subsequently, the second metal oxide layer, the sacrificial layer, and the first metal oxide layer are processed. For example, the second metal oxide layer, the sacrificial layer, and the first metal oxide layer are processed in this order using a photolithography method and an etching method. The second metal oxide layer, the sacrificial layer, and the first metal oxide layer can be processed using the same mask pattern.

[0066] Subsequently, a third metal oxide layer is formed so as to cover the first metal oxide layer, the sacrificial layer, and the second metal oxide layer. The third metal oxide layer can be formed, for example, by an ALD method or a sputtering method. Using the same material for the third metal oxide layer as that used for the first metal oxide layer and the second metal oxide layer is preferable because it facilitates adhesion between the third metal oxide layer and the first metal oxide layer and the second metal oxide layer. In particular, using the same material for the third metal oxide layer as that used for the second metal oxide layer is preferable because it facilitates adhesion between the third metal oxide layer and the second metal oxide layer and prevents the second metal oxide layer from falling off when the sacrificial layer is removed in a later process. For example, when indium gallium zinc oxide is used for the first metal oxide layer and the second metal oxide layer, it is preferable to use indium gallium zinc oxide for the third metal oxide layer as well.

[0067] Subsequently, a first conductive layer is formed on the third metal oxide layer by, for example, CVD, ALD, or sputtering.

[0068] Next, an interlayer insulating layer is formed on the first conductive layer. The interlayer insulating layer can be formed by, for example, a CVD method. The interlayer insulating layer can be made of, for example, silicon oxide.

[0069] Next, the interlayer insulating layer, the first conductive layer, and the third metal oxide layer are subjected to a planarization process, which can be performed using, for example, a chemical mechanical polishing (CMP) method, until the top surface of the second metal oxide layer is exposed.

[0070] Subsequently, the interlayer insulating layer, the first conductive layer, and the third metal oxide layer are processed. For example, the interlayer insulating layer, the first conductive layer, and the third metal oxide layer are processed using a photolithography method and an etching method. The interlayer insulating layer, the first conductive layer, and the third metal oxide layer can be processed using the same mask pattern.

[0071] The first conductive layer is processed to form a second conductive layer and a third conductive layer, for example, facing the second conductive layer with the second metal oxide layer sandwiched therebetween. The third metal oxide layer is processed to form a fourth metal oxide layer and, for example, a fifth metal oxide layer, facing the fourth metal oxide layer with the second metal oxide layer sandwiched therebetween. Processing the first conductive layer and the third metal oxide layer exposes a portion of the side surface of the sacrificial layer. Specifically, the side surface of the sacrificial layer that is not covered by the fourth metal oxide layer and the fifth metal oxide layer is exposed.

[0072] The second conductive layer is formed outside the fourth metal oxide layer (on the opposite side to the second metal oxide layer) so as to have a region in contact with the fourth metal oxide layer. The third conductive layer is formed outside the fifth metal oxide layer (on the opposite side to the second metal oxide layer) so as to have a region in contact with the fifth metal oxide layer. The second conductive layer functions as one of the source electrode and drain electrode of the transistor. The third conductive layer functions as the other of the source electrode and drain electrode of the transistor.

[0073] Next, the sacrificial layer is removed. For example, the sacrificial layer is removed by wet etching. If the second metal oxide layer and the third metal oxide layer are made of the same material, the fourth metal oxide layer and the fifth metal oxide layer, which are formed by processing the third metal oxide layer in the previous step, can be easily adhered to the second metal oxide layer. This is preferable because it prevents the second metal oxide layer from falling off.

[0074] Subsequently, a gate insulating layer is formed so as to cover the first metal oxide layer and the second metal oxide layer. The gate insulating layer is preferably formed by a method that provides high coverage. In particular, forming the gate insulating layer by an ALD method is preferable because it can cover the first metal oxide layer and the second metal oxide layer, including the underside of the second metal oxide layer, with high coverage.

[0075] Next, a fourth conductive layer is formed to cover the gate insulating layer. The fourth conductive layer is preferably formed by a method that provides high coverage, such as ALD. This allows the fourth conductive layer to be easily formed in the region between the first metal oxide layer and the second metal oxide layer, for example. Therefore, the fourth conductive layer can cover the first metal oxide layer and the second metal oxide layer with good coverage, sandwiching the gate insulating layer therebetween. The fourth conductive layer functions as the gate electrode of the transistor.

[0076] Subsequently, the fourth conductive layer and the gate insulating layer are processed by, for example, photolithography and etching, removing, for example, regions of the fourth conductive layer and the gate insulating layer that overlap with the second conductive layer and the third conductive layer.

[0077] Through the above steps, a transistor included in a semiconductor device of one embodiment of the present invention can be manufactured.

[0078] <Configuration Example 1 of Semiconductor Device> Figure 1A is a perspective view illustrating a configuration example of a semiconductor device of one embodiment of the present invention. In Figure 1A, directions parallel to a surface of a substrate (not shown) are the X direction and the Y direction, and a direction perpendicular to the surface is the Z direction. The X direction, the Y direction, and the Z direction are perpendicular to each other. The same applies to the subsequent drawings unless otherwise specified.

[0079] 1B, 1C, and 1D are perspective views each showing a cutaway portion of the configuration shown in FIG. 1A. FIG. 1B shows a cross section in the XZ plane and a cross section in the YZ plane. FIG. 1C shows a cross section in the XZ plane. FIG. 1D shows a cross section in the YZ plane.

[0080] Fig. 2A is a plan view showing the configuration of the semiconductor device shown in Fig. 1A as seen from the Z direction. Fig. 2B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 2A. Fig. 2C is a cross-sectional view taken along dashed dotted line B1-B2 in Fig. 2A. Fig. 2A can also be said to show the configuration in the XY plane. Fig. 2B can also be said to show the configuration in the XZ plane. Fig. 2C can also be said to show the configuration in the YZ plane.

[0081] 1A to 1D and the plan view shown in Fig. 2A, some elements are omitted for clarity, and the same applies to the subsequent perspective views and plan views.

[0082] 1A to 1D and 2A to 2C includes an insulating layer 101 over a substrate (not shown), a transistor 11A, an insulating layer 131a, and an insulating layer 131b over the insulating layer 101, an insulating layer 133a over the insulating layer 131a, and an insulating layer 133b over the insulating layer 131b, an insulating layer 135 over the transistor 11A, the insulating layer 131a, the insulating layer 131b, the insulating layer 133a, and the insulating layer 133b, and an insulating layer 137 over the insulating layer 135. The insulating layer 101, the insulating layer 133a, the insulating layer 133b, and the insulating layer 137 function as interlayer insulating layers. Since the transistor 11A is provided over the insulating layer 101, the insulating layer 101 functions as a base insulating layer.

[0083] 3A and 3B are enlarged views of the transistor 11A shown in FIGS. 2B and 2C, respectively. In addition to the transistor 11A, insulating layers 101, 135, and 137 are also shown in FIGS. 3A and 3B. Also shown in FIG. 3B are insulating layers 131a, 131b, 133a, and 133b.

[0084] The transistor 11A includes a conductive layer 111, a semiconductor layer 113<1>, a semiconductor layer 113<2>, a semiconductor layer 113<3>, a semiconductor layer 114a, a semiconductor layer 114b, a conductive layer 115a, a conductive layer 115b, and an insulating layer 105. The semiconductor layer 113<1> is provided over the insulating layer 101 and can be in contact with, for example, the top surface of the insulating layer 101. The semiconductor layer 113<2> is provided over the semiconductor layer 113<1>, and the semiconductor layer 113<3> is provided over the semiconductor layer 113<2>.

[0085] For example, as shown in Figure 1A, the semiconductor layer 113<1>, the semiconductor layer 113<2>, and the semiconductor layer 113<3> can be a hexahedron with each face being a square. In this case, as shown in Figures 3A and 3B, the semiconductor layer 113<1> has a side surface 141a<1>, a side surface 141b<1>, a side surface 142a<1>, and a side surface 142b<1>. The side surface 141b<1> is the side surface opposite the side surface 141a<1>, and the side surface 142b<1> is the side surface opposite the side surface 142a<1>.

[0086] The side surface 141a<1> and the side surface 141b<1> can each be in contact with one side of the side surface 142a<1> and can also be in contact with one side of the side surface 142b<1>. For example, when the semiconductor layer 113<1> is a rectangular parallelepiped, the side surface 141a<1> and the side surface 141b<1> can be perpendicular to the side surface 142a<1> and can also be perpendicular to the side surface 142b<1>. 1A to 1D, 2B, 2C, 3A, and 3B show examples in which the side surface 141a<1>, the side surface 141b<1>, the side surface 142a<1>, and the side surface 142b<1> are perpendicular to the upper surface of the insulating layer 101, for example, but the side surface 141a<1>, the side surface 141b<1>, the side surface 142a<1>, and the side surface 142b<1> may have a tapered shape.

[0087] The semiconductor layer 113<2> has a side surface 141a<2>, a side surface 141b<2>, a side surface 142a<2>, and a side surface 142b<2>. The semiconductor layer 113<3> has a side surface 141a<3>, a side surface 141b<3>, a side surface 142a<3>, and a side surface 142b<3>. For the side surface 141a<2>, the side surface 141b<2>, the side surface 142a<2>, and the side surface 142b<2>, the above descriptions of the side surface 141a<1>, the side surface 141b<1>, the side surface 142a<1>, and the side surface 142b<1> can be referred to. Similarly, for side 141a<3>, side 141b<3>, side 142a<3>, and side 142b<3>, the above explanations for side 141a<1>, side 141b<1>, side 142a<1>, and side 142b<1> can be referred to.

[0088] Hereinafter, when describing matters common to the semiconductor layer 113<1>, the semiconductor layer 113<2>, and the semiconductor layer 113<3>, they may be simply referred to as the semiconductor layer 113. The same applies to other elements marked with the identification symbol "< >".

[0089] The semiconductor layer 114a has a region in contact with the side surface 141a<1> of the semiconductor layer 113<1>, a region in contact with the side surface 141a<2> of the semiconductor layer 113<2>, and a region in contact with the side surface 141a<3> of the semiconductor layer 113<3>. The semiconductor layer 114b has a region in contact with the side surface 141b<1> opposite the side surface 141a<1>, a region in contact with the side surface 141b<2> opposite the side surface 141a<2>, and a region in contact with the side surface 141b<3> opposite the side surface 141a<3>. As described above, the semiconductor layer 114a and the semiconductor layer 114b face each other with the semiconductor layer 113 sandwiched therebetween.

[0090] The semiconductor layer 114a has a region along the side surface 141a and a region along the top surface of the insulating layer 101. The semiconductor layer 114b has a region along the side surface 141b and a region along the top surface of the insulating layer 101. Here, the top surfaces of the semiconductor layers 114a and 114b can be aligned or approximately aligned with the top surface of the semiconductor layer 113<3>.

[0091] In this specification, the top surface of a layer refers to the top surface that is the highest among the multiple top surfaces of the layer from a reference surface. Also, the bottom surface of a layer refers to the bottom surface that is the lowest among the multiple bottom surfaces of the layer from a reference surface. The reference surface is preferably a flat surface. The reference surface can be, for example, the surface of the substrate or the top surface of the insulating layer 101.

[0092] As described above, the transistor 11A has a region surrounded by the semiconductor layer 113<1>, the semiconductor layer 113<2>, the semiconductor layer 114a, and the semiconductor layer 114b, and a region surrounded by the semiconductor layer 113<2>, the semiconductor layer 113<3>, the semiconductor layer 114a, and the semiconductor layer 114b.

[0093] The insulating layer 105 is provided to cover at least a part of each of the semiconductor layer 113<1>, the semiconductor layer 113<2>, the semiconductor layer 113<3>, the semiconductor layer 114a, and the semiconductor layer 114b. The insulating layer 105 is provided to cover at least the top surface of the semiconductor layer 113<1>, the bottom surface of the semiconductor layer 113<2>, the top surface of the semiconductor layer 113<2>, the bottom surface of the semiconductor layer 113<3>, side surfaces of the semiconductor layers 113<1> to 113<3> that are not in contact with the semiconductor layer 114a, and side surfaces of the semiconductor layers 113<1> to 113<3> that are not in contact with the semiconductor layer 114b.

[0094] In the region between the semiconductor layer 113<1> and the semiconductor layer 113<2>, specifically in the region surrounded by the semiconductor layer 113<1>, the semiconductor layer 113<2>, the semiconductor layer 114a, and the semiconductor layer 114b, the insulating layer 105 has a region in contact with the top surface of the semiconductor layer 113<1>, a region in contact with the bottom surface of the semiconductor layer 113<2>, a region in contact with the side surface of the semiconductor layer 114a, and a region in contact with the side surface of the semiconductor layer 114b. Furthermore, in the region between the semiconductor layer 113<2> and the semiconductor layer 113<3>, specifically in the region surrounded by the semiconductor layer 113<2>, the semiconductor layer 113<3>, the semiconductor layer 114a, and the semiconductor layer 114b, the insulating layer 105 has a region in contact with the top surface of the semiconductor layer 113<2>, a region in contact with the bottom surface of the semiconductor layer 113<3>, a region in contact with the side surface of the semiconductor layer 114a, and a region in contact with the side surface of the semiconductor layer 114b.

[0095] 3A , the insulating layer 105 has a region in contact with the side surface 142a<1> of the semiconductor layer 113<1> and a region in contact with the side surface 142b<1> opposite the side surface 142a<1>. The insulating layer 105 also has a region in contact with the side surface 142a<2> of the semiconductor layer 113<2> and a region in contact with the side surface 142b<2> opposite the side surface 142a<2>. The insulating layer 105 also has a region in contact with the side surface 142a<3> of the semiconductor layer 113<3> and a region in contact with the side surface 142b<3> opposite the side surface 142a<3>. The insulating layer 105 also has a region in contact with the side surfaces of the semiconductor layer 114a other than the side surface 141a and the side surfaces of the semiconductor layer 114b other than the side surface 141b.

[0096] The conductive layer 111 has a region 143<1> located between the semiconductor layer 113<1> and the semiconductor layer 113<2> and a region 143<2> located between the semiconductor layer 113<2> and the semiconductor layer 113<3>. The conductive layer 111 is provided to cover the upper surface of the semiconductor layer 113<1> with the insulating layer 105 sandwiched therebetween. The conductive layer 111 is provided to surround the upper surface, lower surface, side surface 142a<2>, and side surface 142b<2> of the semiconductor layer 113<2> with the insulating layer 105 sandwiched therebetween. The conductive layer 111 is provided to surround the upper surface, lower surface, side surface 142a<3>, and side surface 142b<3> of the semiconductor layer 113<3> with the insulating layer 105 sandwiched therebetween.

[0097] The conductive layer 115a is provided to have a region in contact with, for example, the side surface of the semiconductor layer 114a opposite to the semiconductor layer 113<2> and the semiconductor layer 113<3>, and a region in contact with the top surface other than the top surface (the top surface in the region along the top surface of the insulating layer 101). The conductive layer 115b is provided to have a region in contact with, for example, the side surface of the semiconductor layer 114b opposite to the semiconductor layer 113<2> and the semiconductor layer 113<3>, and a region in contact with the top surface other than the top surface (the top surface in the region along the top surface of the insulating layer 101).

[0098] In the semiconductor device having the above structure, at least a part of the conductive layer 111 functions as the gate electrode of the transistor 11A. At least a part of the conductive layer 115a functions as one of the source electrode and drain electrode of the transistor 11A. At least a part of the conductive layer 115b functions as the other of the source electrode and drain electrode of the transistor 11A. At least a part of the insulating layer 105 functions as the gate insulating layer of the transistor 11A.

[0099] From the above, the transistor 11A can be a transistor in which the gate electrode surrounds the upper, lower, and side surfaces of the semiconductor layer 113 in a predetermined cross-sectional view, for example, a cross-sectional view in the XZ plane. Therefore, the transistor 11A is a transistor with a GAA structure. Furthermore, channels are formed in the semiconductor layers 113<2> and 113<3> surrounded by the gate electrode. Here, the semiconductor layers 113<2> and 113<3> can have flat top surfaces. Therefore, the transistor 11A can be said to be a transistor with a nanosheet structure. Note that a channel can also be formed in the semiconductor layer 113<1>. Furthermore, the semiconductor layer 113<1> can also have a flat top surface.

[0100] The Y direction shown in FIGS. 1A to 1D, 2A to 2C, 3A, and 3B can be the channel length direction. One of the semiconductor layers 114a and 114b can be a source region, and the other of the semiconductor layers 114a and 114b can be a drain region. Specifically, a region of the semiconductor layer 114a in contact with the conductive layer 115a and a region nearby the region can be one of the source region and the drain region. A region of the semiconductor layer 114b in contact with the conductive layer 115b and a region nearby the region can be the other of the source region and the drain region. Note that a part of the semiconductor layer 113 may serve as the source region and the drain region. For example, the boundary (interface) of the semiconductor layer 113 with the semiconductor layer 114a and a region nearby the boundary may serve as one of the source region and the drain region. A region of the semiconductor layer 113 with the semiconductor layer 114b and a region nearby the boundary may serve as the other of the source region and the drain region.

[0101] By using the GAA structure for the transistor 11A, an electric field for inducing a channel in the semiconductor layer can be applied more effectively than in a transistor having only one semiconductor layer and a gate electrode covering only the top surface, only the top and side surfaces, or only the top and bottom surfaces of the semiconductor layer. Therefore, the transistor 11A can have a large on-state current. Therefore, the semiconductor device of one embodiment of the present invention can have a high operating speed.

[0102] As will be described later in detail, in the manufacturing process of the transistor 11A, semiconductor layers 113 and sacrificial layers on the semiconductor layers 113 are alternately formed, and then semiconductor films that will become the semiconductor layers 114a and 114b in a later process are formed to cover the semiconductor layers 113 and the sacrificial layers, and then the sacrificial layers are removed. Therefore, if the adhesion between the semiconductor layer 113 and the semiconductor films that will become the semiconductor layers 114a and 114b in a later process is poor, the semiconductor layer 113 may fall off after the sacrificial layers are removed. In the examples shown in FIGS. 1A to 1D , 2A to 2C , 3A , and 3B , the semiconductor layers 113<2> and 113<3> may fall off. To improve the adhesion between the semiconductor layer 113 and the semiconductor layers 114a and 114b, the semiconductor layers 114a and 114b are preferably made of the same material as the semiconductor layer 113. This facilitates, for example, atomic bonding between the semiconductor layer 114a and the semiconductor layer 114b and the semiconductor layer 113, thereby improving adhesion between the semiconductor layer 113 and the semiconductor layer 114a and the semiconductor layer 114b. Specifically, the semiconductor layer 114a and the semiconductor layer 114b are preferably made of the same material as the semiconductor layer 113<2> and the semiconductor layer 113<3>.

[0103] The boundaries (interfaces) between the semiconductor layers 113, 114a, and 114b may not be clearly visible. For example, if the semiconductor layers 113, 114a, and 114b are made of the same material, the boundaries (interfaces) between these conductive layers may not be clearly visible.

[0104] When the semiconductor films to be the semiconductor layers 114a and 114b are formed by a method with high coverage, the semiconductor films are easily in contact with the semiconductor layer 113. This is preferable because the semiconductor layers 114a and 114b are easily brought into close contact with the semiconductor layer 113. The semiconductor films to be the semiconductor layers 114a and 114b are preferably formed by, for example, an ALD method. Note that the semiconductor layer 113 does not have to be formed by the ALD method and may be formed by, for example, a sputtering method or a CVD method.

[0105] Here, for example, a semiconductor layer containing silicon is difficult to deposit using an ALD method. For these reasons, it is preferable to use a metal oxide layer that can be deposited using an ALD method as the semiconductor film that becomes the semiconductor layer 114a and the semiconductor layer 114b. As described above, it is preferable to use the same material as the semiconductor layer 114a and the semiconductor layer 114b. For these reasons, it is preferable to use a metal oxide layer as the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b. Note that if the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b can be deposited using an ALD method, metal oxide layers do not necessarily have to be used as the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b. Furthermore, the semiconductor film that becomes the semiconductor layer 114a and the semiconductor layer 114b may be deposited using, for example, a sputtering method or a CVD method. In this case, for example, silicon can be used as the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b.

[0106] When the semiconductor layer 113 is a metal oxide layer, the semiconductor layer 113 preferably contains at least indium (In) or zinc (Zn). For example, indium gallium zinc oxide (In—Ga—Zn oxide) can be used for the semiconductor layer 113.

[0107] 1A to 1D, 2B, 2C, 3A, and 3B illustrate an example in which the transistor 11A includes three semiconductor layers 113 (semiconductor layer 113<1>, semiconductor layer 113<2>, and semiconductor layer 113<3>). Also, for example, FIG. 3A illustrates an example in which the conductive layer 111 includes two regions 143 (region 143<1> and region 143<2>) located between the two semiconductor layers 113. Here, the transistor 11A may include two semiconductor layers 113. In this case, the conductive layer 111 may include one region 143. Alternatively, the transistor 11A may include four or more semiconductor layers 113. In this case, the conductive layer 111 may include three or more regions 143. When the transistor 11A has n semiconductor layers 113 (n is an integer of 2 or more), the conductive layer 111 can have n−1 regions 143 .

[0108] As the number of semiconductor layers 113 increases, that is, as n increases, the volume of the region surrounded by the gate electrode of the semiconductor layer 113 can be increased without increasing the channel length of the transistor 11A. This allows the on-state current of the transistor 11A to be increased. Therefore, the operating speed of the semiconductor device of one embodiment of the present invention can be increased. On the other hand, as n increases, the number of manufacturing steps of the semiconductor device increases. This increases the manufacturing cost of the semiconductor device, which may increase the price of the semiconductor device, for example. Therefore, it is preferable to determine n taking into consideration the performance and price of the semiconductor device.

[0109] As will be described later in detail, in a manufacturing process of the transistor 11A, after removing the sacrificial layer, the insulating layer 105 is formed to cover the semiconductor layer 113. Then, the conductive layer 111 is formed to cover the insulating layer 105. Here, it is preferable to form the conductive layer 111 by a method that provides high coverage, specifically, an ALD method, because the conductive layer 111 can have good coverage in the region 143, for example. When the conductive layer 111 is formed by the ALD method, the thickness of the conductive layer 111 can be, for example, 1 nm to 100 nm, preferably 3 nm to 50 nm, more preferably 4 nm to 30 nm, and even more preferably 5 nm to 20 nm.

[0110] The insulating layer 131a has a region along the side surface of the conductive layer 115a opposite to the semiconductor layer 114a and a region along the top surface of the conductive layer 115a other than the top surface (the top surface of the region along the top surface of the semiconductor layer 114a). The insulating layer 131b has a region along the side surface of the conductive layer 115b opposite to the semiconductor layer 114b and a region along the top surface of the conductive layer 115b other than the top surface (the top surface of the region along the top surface of the semiconductor layer 114b). The insulating layer 131a can have a region in contact with the side surface of the conductive layer 115a opposite to the semiconductor layer 114a and a region in contact with the top surface of the conductive layer 115a other than the top surface. The insulating layer 131b can have a region in contact with the side surface of the conductive layer 115b opposite to the semiconductor layer 114b and a region in contact with the top surface of the conductive layer 115b other than the top surface.

[0111] An insulating layer 133 is provided on the insulating layer 131. The insulating layer 133 may be a planarized layer. In this case, the top surfaces of the semiconductor layer 113<3>, the top surface of the semiconductor layer 114a, the top surface of the semiconductor layer 114b, the top surface of the conductive layer 115a, the top surface of the conductive layer 115b, the top surface of the insulating layer 131a, the top surface of the insulating layer 131b, the top surface of the insulating layer 133a, and the top surface of the insulating layer 133b may be the same or approximately the same height from a reference plane. For example, the surface of the substrate, a flat region of a film provided on the substrate, or the like may be used as the reference plane.

[0112] An insulating layer 135 is provided on the conductive layer 111, the semiconductor layer 113<3>, the semiconductor layer 114a, the semiconductor layer 114b, the conductive layer 115a, the conductive layer 115b, the insulating layer 131a, the insulating layer 131b, the insulating layer 133a, and the insulating layer 133b, and an insulating layer 137 is provided on the insulating layer 135.

[0113] The transistor 11A is covered with insulating layers 131a, 131b, and 135. The insulating layers 131a, 131b, and 135 preferably have a barrier property against impurities such as water and hydrogen. This can prevent impurities from diffusing from the outside of the transistor 11A to the transistor 11A. In particular, this can prevent impurities from diffusing into the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b, which can be, for example, metal oxide layers. This can improve the electrical characteristics and reliability of the transistor 11A. Therefore, the reliability of the semiconductor device of one embodiment of the present invention can be improved. Here, the insulating layer 133a provided over the insulating layer 131a, the insulating layer 133b provided over the insulating layer 131b, and the insulating layer 137 provided over the insulating layer 135 preferably function as interlayer insulating layers and are planarized as described above.

[0114] 2D and 2E are cross-sectional views showing an example in which a sacrificial layer 123a is provided on the semiconductor layer 113<3> shown in FIGS. 2B and 2C, respectively. Due to a manufacturing process of a semiconductor device described later, residues of the sacrificial layer 123a may be provided between the semiconductor layer 113<3> and the insulating layer 105 and the insulating layer 135. In this case, the top surface of the sacrificial layer 123a can be made to coincide or approximately coincide with the height from a reference plane of the top surfaces of the semiconductor layer 114a, 114b, 115a, 115b, 131a, 131b, 133a, and 133b.

[0115] The sacrificial layer 123a can be formed using, for example, a material shown in the "Insulating Layer" section described later. For example, an inorganic insulating film can be used for the sacrificial layer 123a, specifically, an oxide insulating film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film can be used. For example, silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide can be used for the sacrificial layer 123a. Note that a semiconductor material or a conductive material may also be used for the sacrificial layer 123a.

[0116] 4A, 4B, 4C, 4D, 5A, 5B, 5C, 5D, and 5E are diagrams illustrating examples in which the transistor 11A illustrated in FIGS. 1A, 1B, 1C, 1D, 2A, 2B, 2C, 2D, and 2E includes a conductive layer 119 and an insulating layer 109. Here, the transistor including the conductive layer 119 and the insulating layer 109 is referred to as transistor 11B. Below, configurations different from those of the transistor 11A will be mainly described, and descriptions of similar configurations will be omitted as appropriate.

[0117] The conductive layer 119 is provided over the insulating layer 101. The insulating layer 109 is provided over the conductive layer 119 and the insulating layer 101. The insulating layer 109 can be provided to cover, for example, the top surface and side surfaces of the conductive layer 119. The conductive layer 119 and the insulating layer 109 can have a region in contact with the top surface of the insulating layer 101.

[0118] The semiconductor layer 113 is provided over the insulating layer 109 so as to have a region overlapping with the conductive layer 119. For example, the semiconductor layer 113<1> is provided over the insulating layer 109 so as to have a region overlapping with the conductive layer 119. Here, the insulating layer 109 can be provided so as to have a region in contact with the top surface of the insulating layer 101, a region in contact with the bottom surface of the insulating layer 105, a region in contact with the top surface of the conductive layer 119, a region in contact with the side surface of the conductive layer 119, a region in contact with the bottom surface of the semiconductor layer 113<1>, a region in contact with the bottom surface of the semiconductor layer 114a, and a region in contact with the bottom surface of the semiconductor layer 114b.

[0119] At least a part of the conductive layer 119 functions as the gate electrode of the transistor 11B. At least a part of the insulating layer 109 functions as the gate insulating layer of the transistor 11B. In the transistor 11B, it can be said that at least a part of the conductive layer 111 functions as the first gate electrode, and at least a part of the conductive layer 119 functions as the second gate electrode. In the transistor 11B, it can be said that at least a part of the insulating layer 105 functions as the first gate insulating layer, and at least a part of the insulating layer 109 functions as the second gate insulating layer. Note that it can also be said that at least a part of the conductive layer 119 functions as the first gate electrode, and at least a part of the conductive layer 111 functions as the second gate electrode. It can also be said that at least a part of the insulating layer 109 functions as the first gate insulating layer, and at least a part of the insulating layer 105 functions as the second gate insulating layer.

[0120] In the transistor 11B, the semiconductor layer 113<1> can be sandwiched between the conductive layer 111 and the conductive layer 119, which function as a gate electrode, with the insulating layer 105 and the insulating layer 109, which function as a gate insulating layer, interposed therebetween. Therefore, an electric field for inducing a channel in the semiconductor layer 113<1> can be applied more effectively to the transistor 11B than to the transistor 11A. Therefore, the transistor 11B can have a larger on-state current than the transistor 11A. Therefore, the operating speed of the semiconductor device of one embodiment of the present invention can be increased. Meanwhile, the number of manufacturing steps for the transistor 11A can be reduced compared to the transistor 11B. Therefore, the manufacturing cost of a semiconductor device including the transistor 11A can be lower than that of a semiconductor device including the transistor 11B. Therefore, a semiconductor device including the transistor 11A can be manufactured at a lower cost than a semiconductor device including the transistor 11B.

[0121] Here, the electric field of the conductive layer 119 reaches the semiconductor layer 113<1>, allowing the conductive layer 119 to function as the gate electrode of the transistor 11B. Therefore, by shortening the distance between the top surface of the conductive layer 119 and the bottom surface of the semiconductor layer 113<1> to, for example, approximately the same as the distance between the conductive layer 111 and the top surface of the semiconductor layer 113<1>, the conductive layer 119 can function as the gate electrode of the transistor 11B. For example, by reducing the thickness of the insulating layer 109 to approximately the same as the thickness of the insulating layer 105, the conductive layer 119 can function as the gate electrode of the transistor 11B. For example, by setting the thickness of the insulating layer 109 to be equal to or less than the thicknesses of the insulating layers 133a and 133b, the conductive layer 119 can function as the gate electrode of the transistor 11B.

[0122] 4A to 5E show an example in which the conductive layer 119 extends in a direction perpendicular to the conductive layer 111. Specifically, an example in which the conductive layer 111 extends in the X direction and the conductive layer 119 extends in the Y direction is shown. This reduces the area of ​​the region where the conductive layer 119 and the conductive layer 111 overlap via the insulating layer 109 and the insulating layer 105, which function as gate insulating layers, compared to when the conductive layer 119 extends in a direction parallel to the conductive layer 111. Therefore, the parasitic capacitance between the conductive layer 119 and the conductive layer 111 can be reduced. In particular, the thinner the insulating layer 109 and the insulating layer 105 are, the smaller the parasitic capacitance between the conductive layer 119 and the conductive layer 111 can be compared to when the conductive layer 119 extends in a direction parallel to the conductive layer 111. Note that the conductive layer 119 may also extend in a direction parallel to the conductive layer 111. In this case, compared to when the conductive layer 119 extends in a direction perpendicular to the conductive layer 111, the parasitic capacitance between the conductive layer 119 and the conductive layer 115a and the parasitic capacitance between the conductive layer 119 and the conductive layer 115b can be reduced.

[0123] [Transistor 11C] Figures 6A, 6B, 6C, 6D, 7A, 7B, 7C, and 7D are diagrams showing examples in which the conductive layer 111 and the insulating layer 105 included in the transistor 11A shown in Figures 1A, 1B, 1C, 1D, 2B, 2C, 2D, and 2E each have a region located between the insulating layer 101 and the semiconductor layer 113<1>. For a plan view, see Figure 2A. Here, the transistor included in the semiconductor device shown in Figures 6A to 7D is referred to as transistor 11C. Below, configurations different from those of the transistor 11A will be mainly described, and descriptions of similar configurations will be omitted as appropriate.

[0124] The transistor 11C has a region surrounded by the insulating layer 101, the semiconductor layer 113<1>, the semiconductor layer 114a, and the semiconductor layer 114b. In this region, the insulating layer 105 is provided to cover the top surface of the insulating layer 101, the bottom surface of the semiconductor layer 113<1>, the side surfaces of the semiconductor layer 114a, and the side surfaces of the semiconductor layer 114b. Specifically, the top surface of the insulating layer 101, the bottom surface of the semiconductor layer 113<1>, the side surfaces of the semiconductor layer 114a, and the side surfaces of the semiconductor layer 114b can each have a region in contact with the insulating layer 105 in the region between the insulating layer 101 and the semiconductor layer 113<1>.

[0125] In the transistor 11C, the conductive layer 111 has a region 144 located between the insulating layer 101 and the semiconductor layer 113<1>. The conductive layer 111 is provided to surround the top surface, bottom surface, side surface 142a<1>, and side surface 142b<1> of the semiconductor layer 113<1> with the insulating layer 105 sandwiched therebetween.

[0126] In the transistor 11C, not only the semiconductor layer 113<2> and the semiconductor layer 113<3> but also the semiconductor layer 113<1> can be surrounded by the conductive layer 111 in a predetermined cross-sectional view, for example, a cross-sectional view taken along the XZ plane. Therefore, in the transistor 11C, an electric field for inducing a channel in the semiconductor layer 113<1> can be applied more effectively than in the transistor 11A. Therefore, the transistor 11C can have a larger on-state current than the transistor 11A. Therefore, the operating speed of the semiconductor device of one embodiment of the present invention can be increased. Meanwhile, the transistor 11A can be manufactured using fewer manufacturing steps than the transistor 11C. Therefore, a semiconductor device including the transistor 11A can be manufactured at a lower cost than a semiconductor device including the transistor 11C. Therefore, a semiconductor device including the transistor 11A can be manufactured at a lower cost than a semiconductor device including the transistor 11C.

[0127] As will be described in detail later, in the manufacturing process of the transistor 11C, sacrificial layers and semiconductor layers 113 on the sacrificial layers are alternately formed so that the number of sacrificial layers and the number of semiconductor layers 113 are equal. Then, a semiconductor film that will become the semiconductor layers 114a and 114b in a later process is formed to cover the semiconductor layer 113 and the sacrificial layer, and the sacrificial layer is then removed. Therefore, as described above, if the adhesion between the semiconductor layer 113 and the semiconductor film that will become the semiconductor layers 114a and 114b in a later process is poor, the semiconductor layer 113 may fall off after the sacrificial layer is removed. In the example shown in Figures 6A to 7D, the semiconductor layer 113<1>, the semiconductor layer 113<2>, and the semiconductor layer 113<3> may fall off. In order to improve the adhesion between the semiconductor layers 113<1> to 113<3> and the semiconductor layers 114a and 114b, the semiconductor layers 114a and 114b preferably contain the same material as the semiconductor layer 113. Specifically, the semiconductor layers 114a and 114b preferably contain the same material as the semiconductor layers 113<1> to 113<3>.

[0128] 8A is a cross-sectional view illustrating an example in which the semiconductor layer 114a, the semiconductor layer 114b, the conductive layer 115a, and the conductive layer 115b included in the transistor 11A illustrated in FIG. 3B have a two-layer stacked structure. Here, the transistor included in the semiconductor device illustrated in FIG. 8A is referred to as transistor 11D. Below, the following description will mainly focus on the configurations that are different from those of the transistor 11A, and descriptions of similar configurations will be omitted as appropriate.

[0129] In the transistor 11D, the semiconductor layer 114a includes a semiconductor layer 114a1 and a semiconductor layer 114a2. The semiconductor layer 114b includes a semiconductor layer 114b1 and a semiconductor layer 114b2. The conductive layer 115a includes a conductive layer 115a1 and a conductive layer 115a2. The conductive layer 115b includes a conductive layer 115b1 and a conductive layer 115b2.

[0130] The semiconductor layer 114a1 has a region in contact with the side surface 141a<1> of the semiconductor layer 113<1>, a region in contact with the side surface 141a<2> of the semiconductor layer 113<2>, and a region in contact with the side surface 141a<3> of the semiconductor layer 113<3>. The semiconductor layer 114a2 is provided outside the semiconductor layer 114a1 (e.g., on the opposite side from the semiconductor layers 113<2> and 113<3>). The semiconductor layer 114b1 has a region in contact with the side surface 141b<1> opposite to the side surface 141a<1>, a region in contact with the side surface 141b<2> opposite to the side surface 141a<2>, and a region in contact with the side surface 141b<3> opposite to the side surface 141a<3>. The semiconductor layer 114b2 is provided on the outer side of the semiconductor layer 114b1 (for example, on the opposite side to the semiconductor layer 113<2> and the semiconductor layer 113<3>).

[0131] It is preferable that the semiconductor layers 114a1 and 114b1 are made of the same material as the semiconductor layer 113, because this can improve adhesion between the semiconductor layer 113 and the semiconductor layers 114a and 114b. On the other hand, a material different from that of the semiconductor layer 114a1 can be used for the semiconductor layer 114a2, and a material different from that of the semiconductor layer 114b1 can be used for the semiconductor layer 114b2. In this case, the boundary (interface) between the semiconductor layer 113 and the semiconductor layer 114a1 and the boundary (interface) between the semiconductor layer 113 and the semiconductor layer 114b1 cannot be clearly confirmed, but the boundary (interface) between the semiconductor layer 114a1 and the semiconductor layer 114a2 and the boundary (interface) between the semiconductor layer 114b1 and the semiconductor layer 114b2 may be confirmed.

[0132] For example, the semiconductor layer 114a2 can be made of a material having a higher conductivity than the semiconductor layer 114a1, and the semiconductor layer 114b2 can be made of a material having a higher conductivity than the semiconductor layer 114b1. By using a material having a high conductivity for the semiconductor layer 114a2 in contact with the conductive layer 115a and the semiconductor layer 114b2 in contact with the conductive layer 115b, the contact resistance between the semiconductor layer 114a and the conductive layer 115a and the contact resistance between the semiconductor layer 114b and the conductive layer 115b can be reduced. Therefore, the transistor 11D can have a large on-state current.

[0133] The semiconductor layers 114a1 and 114b1 and the semiconductor layers 114a2 and 114b2 can be formed using different film formation methods. For example, the semiconductor layers 114a1 and 114b1 are preferably formed using a method that provides high coverage in order to improve adhesion to the semiconductor layer 113. The semiconductor layers 114a1 and 114b1 can be formed using, for example, an ALD method. The semiconductor layers 114a2 and 114b2 are preferably formed using a film formation method that provides a high film formation rate. The semiconductor layers 114a2 and 114b2 can be formed using, for example, a sputtering method.

[0134] Alternatively, for example, the semiconductor layer 114a1 and the semiconductor layer 114b1 may be formed by sputtering, and the semiconductor layer 114a2 and the semiconductor layer 114b2 may be formed by ALD. For example, the semiconductor layer 114a1 and the semiconductor layer 114b1 having a c-axis aligned crystalline (CAAC) structure may be formed by sputtering, and then the semiconductor layer 114a2 and the semiconductor layer 114b2, which have lower crystallinity than the CAAC structure, may be formed by ALD. This is expected to allow the atomic layer of the semiconductor layer 114a2 to fill or repair the gaps in the atomic-level crystalline portions of the CAAC structure of the semiconductor layer 114a1. Similarly, the atomic layer of the semiconductor layer 114b2 is expected to fill or repair the gaps in the atomic-level crystalline portions of the CAAC structure of the semiconductor layer 114b1. Here, the CAAC structure is a crystal structure in which multiple microcrystals (typically, multiple IGZO microcrystals) have a c-axis orientation and are connected without being oriented in the a-b plane. Furthermore, when a cross section of an OS film having a CAAC structure is observed using a high-resolution TEM image, it can be confirmed that metal atoms are arranged in layers in the crystalline portions. Therefore, an OS film having a CAAC structure can also be said to have a structure having layered crystalline portions.

[0135] Furthermore, after the semiconductor layer 114a2 and the semiconductor layer 114b2 are formed by the ALD method, heat treatment (for example, 100° C. to 500° C., preferably 200° C. to 450° C., more preferably 300° C. to 400° C.) is preferably performed. The heat treatment is expected to repair gaps in the atomic-level crystal portions of the CAAC structure of the semiconductor layer 114a1 by the semiconductor layer 114a2 (in other words, by the crystal molecules formed by the ALD method). Similarly, it is expected to repair gaps in the atomic-level crystal portions of the CAAC structure of the semiconductor layer 114b1 by the semiconductor layer 114b2. The semiconductor layers formed by the above-described two types of film formation methods may be referred to as a hybrid OS.

[0136] As described above, by forming the semiconductor layers 114a and 114b as a stacked structure, the range of film formation methods and the range of material selection used for forming the semiconductor layers 114a and 114b can be broadened compared to when the semiconductor layers 114a and 114b have a single-layer structure. On the other hand, when the semiconductor layers 114a and 114b have a single-layer structure, the number of steps for manufacturing a transistor can be reduced compared to when the semiconductor layers 114a and 114b have a stacked structure. Note that the semiconductor layers 114a and 114b may have a stacked structure of three or more layers. The semiconductor layer 113 may also have a stacked structure of two or more layers.

[0137] Note that when the semiconductor layers 114a1 and 114b1 and the semiconductor layers 114a2 and 114b2 are formed using different deposition methods, the same material may be used for the semiconductor layers 114a1 and 114b1 and the semiconductor layers 114a2 and 114b2. For example, the same material may be used for all of the semiconductor layers 113, 114a1, 114a2, 114b1, and 114b2. Even when the semiconductor layers 114a and 114b have a stacked structure of three or more layers, if at least one of these layers is formed using a deposition method different from that of the other layers, the same material may be used for each layer included in the semiconductor layers 114a and 114b and formed using different deposition methods.

[0138] The conductive layer 115a1 has a region in contact with, for example, a side surface of the semiconductor layer 114a opposite to the semiconductor layer 113<2> and the semiconductor layer 113<3>, and a region in contact with an upper surface other than the top surface (the upper surface in the region along the upper surface of the insulating layer 101). The conductive layer 115a2 is provided outside the conductive layer 115a1 (the opposite side to the semiconductor layer 114a). The conductive layer 115b1 has a region in contact with, for example, a side surface of the semiconductor layer 114b opposite to the semiconductor layer 113<2> and the semiconductor layer 113<3>, and a region in contact with an upper surface other than the top surface (the upper surface in the region along the upper surface of the insulating layer 101). The conductive layer 115b2 is provided outside the conductive layer 115b1 (the opposite side to the semiconductor layer 114b).

[0139] The conductive layer 115a1 and the conductive layer 115b1 can each contain a metal oxide, and thus, the conductive layer 115a1 and the conductive layer 115b1 can also be referred to as a metal oxide layer.

[0140] In this specification and the like, a metal oxide having conductivity is referred to as an oxide conductor. An oxide conductor can be used for the conductive layer 115a1 and the conductive layer 115b1. Examples of oxide conductors that can be used for the conductive layer 115a1 and the conductive layer 115b1 include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide containing silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide.

[0141] The conductive layer 115a2 and the conductive layer 115b2 can be formed using a conductor that does not contain oxygen, such as tungsten, copper, aluminum, ruthenium, titanium nitride, or tantalum nitride.

[0142] When the semiconductor layers 114a and 114b are metal oxide layers, the oxide conductor can have lower contact resistance with the semiconductor layers 114a and 114b than a conductor that does not contain oxygen. On the other hand, a conductor that does not contain oxygen can have higher conductivity than an oxide conductor. As described above, an oxide conductor can be used for the conductive layers 115a1 and 115b1, and a conductor that does not contain oxygen can be used for the conductive layers 115a2 and 115b2. In this case, the on-state current of the transistor can be larger than when the conductive layers 115a and 115b have, for example, a single-layer structure. On the other hand, when the conductive layers 115a and 115b have a single-layer structure, the number of manufacturing steps of the transistor can be reduced compared to when the conductive layers 115a and 115b have a stacked structure. Note that the conductive layers 115a and 115b may have a stacked structure of three or more layers. For example, the conductive layers 115a1 and 115b1 each using an oxide conductor can have a single-layer structure, and the conductive layers 115a2 and 115b2 each using a conductor not containing oxygen can have a stacked-layer structure. In this case, the conductive layers 115a2 and 115b2 can have a two-layer structure including, for example, a layer using titanium nitride or tantalum nitride and a layer using tungsten, copper, aluminum, or ruthenium.

[0143] 8A may be applied to not only the transistor 11A but also the transistor 11B or 11C. That is, the semiconductor layer 114a, the semiconductor layer 114b, the conductive layer 115a, and the conductive layer 115b included in the transistor 11B or 11C may have a stacked structure of two or more layers. Note that in the transistor 11D, one of the semiconductor layer 114a and the conductive layer 115a may have a single-layer structure, and one of the semiconductor layer 114b and the conductive layer 115b may have a single-layer structure.

[0144] [Transistor 11E] Figure 8B is a cross-sectional view of transistor 11D in which the semiconductor layers 114a and 114b are omitted. Here, the transistor included in the semiconductor device shown in Figure 8B is referred to as transistor 11E. Below, configurations different from those of transistor 11D will be mainly described, and descriptions of similar configurations will be omitted as appropriate.

[0145] In the transistor 11E, the conductive layer 115a1 has a region in contact with the side surface 141a of the semiconductor layer 113. The conductive layer 115b1 has a region in contact with the side surface 141b of the semiconductor layer 113. The transistor 11E has a region surrounded by the semiconductor layer 113<1>, the semiconductor layer 113<2>, the conductive layer 115a1, and the conductive layer 115b1, and a region surrounded by the semiconductor layer 113<2>, the semiconductor layer 113<3>, the conductive layer 115a1, and the conductive layer 115b1.

[0146] In the transistor 11E, the insulating layer 105 has a region in contact with the side surface of the conductive layer 115a1 and a region in contact with the side surface of the conductive layer 115b1 in the region between the semiconductor layer 113<1> and the semiconductor layer 113<2> and the region between the semiconductor layer 113<2> and the semiconductor layer 113<3>.

[0147] When the semiconductor layer 113 is a metal oxide layer and the conductive layers 115a1 and 115b1 are made of oxide conductors, that is, when the semiconductor layer 113, the conductive layer 115a1, and the conductive layer 115b1 are all made of metal oxide layers, the conductive layers 115a1 and 115b1 can contain the same material as at least a part of the material contained in the semiconductor layer 113. This allows the conductive layers 115a1 and 115b1 to be in close contact with the semiconductor layer 113. Therefore, even if the semiconductor layer 114a is not provided between the semiconductor layer 113 and the conductive layer 115a1 and the semiconductor layer 114b is not provided between the semiconductor layer 113 and the conductive layer 115b1, the semiconductor layer 113 can be prevented from falling during the manufacturing process of the semiconductor device.

[0148] By not providing the semiconductor layer 114a and the semiconductor layer 114b, the number of manufacturing steps of the semiconductor device can be reduced compared to a case where the semiconductor layer 114a and the semiconductor layer 114b are provided. Meanwhile, the semiconductor layer 114a and the semiconductor layer 114b can have compositions closer to that of the semiconductor layer 113 than the conductive layer 115a1 and the conductive layer 115b1. For example, the semiconductor layer 114a and the semiconductor layer 114b can have the same composition as the semiconductor layer 113. Therefore, the adhesion between the semiconductor layer 114a and the semiconductor layer 114b and the semiconductor layer 113 can be improved compared to the adhesion between the conductive layer 115a1 and the conductive layer 115b1 and the semiconductor layer 113. Therefore, by providing the semiconductor layer 114a and the semiconductor layer 114b, the reliability of the semiconductor device can be improved compared to a case where the semiconductor layer 114a and the semiconductor layer 114b are not provided. Furthermore, the yield of the semiconductor device can be increased in some cases.

[0149] <Constituent Materials of Semiconductor Device> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that unless otherwise specified, each layer that constitutes the semiconductor device of this embodiment may have a single-layer structure or a stacked-layer structure.

[0150] [Semiconductor Layer] As described above, the semiconductor layer 113 has a channel formation region. The channel formation region is i-type (intrinsic) or substantially i-type. The semiconductor layer 114a has one of a source region and a drain region, and the semiconductor layer 114b has the other of the source region and the drain region. The source region and the drain region are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region.

[0151] The crystallinity of the semiconductor material used for the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. The use of a single crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0152] As described above, the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b can be metal oxide layers. Hereinafter, materials that can be used for the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b will be described assuming that the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b are metal oxide layers.

[0153] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of a transistor can be reduced. Because the off-state current of an OS transistor is low, the power consumption of a semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0154] Examples of metal oxides that can be used for the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

[0155] The semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b may be formed using, for example, indium oxide (In oxide), indium zinc oxide (In—Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Z), or the like. Examples of usable oxides include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as AZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO, IGZAO, or IAGZO). Alternatively, examples of usable oxides include indium tin oxide containing silicon, gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0156] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased, and a transistor with a large on-state current can be realized.

[0157] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide. Therefore, including a metal element having a higher period number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0158] The metal oxide may also contain one or more nonmetallic elements. The presence of a nonmetallic element in the metal oxide may increase the carrier concentration or narrow the band gap, thereby increasing the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, bromine, and hydrogen.

[0159] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0160] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of all metal elements contained in the metal oxide, a metal oxide with a wide band gap can be obtained. Furthermore, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, resulting in a transistor with a low off-state current. Furthermore, a shift in the threshold voltage of the transistor can be suppressed. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, resulting in improved reliability.

[0161] The electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used for the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0162] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include In:M:Zn=1:1:0.5, In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:1:2, In:M:Zn=2:1:3, In:M:Zn=3:1:1, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, and compositions close to these. Note that the term "nearby composition" includes a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current, field-effect mobility, and the like of the transistor can be increased.

[0163] Furthermore, the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M. Examples of atomic ratios of metal elements in such In-M-Zn oxide include In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, and compositions close to these. By increasing the proportion of M atoms in the metal oxide, the generation of oxygen vacancies can be suppressed.

[0164] When the element M contains a plurality of metal elements, the total proportion of the number of atoms of the metal elements can be used as the proportion of the number of atoms of the element M.

[0165] In this specification and the like, the ratio of the number of indium atoms to the sum of the numbers of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements.

[0166] Furthermore, when the metal oxide is an In-Zn oxide, the atomic ratio of the metal elements in the In-Zn oxide may be, for example, In:Zn = 1:1, In:Zn = 2:1, In:Zn = 4:1, or a composition in the vicinity thereof. The In-Zn oxide may also contain a trace amount of element M. For example, when Sn is contained as element M, the atomic ratio of the metal elements in the metal oxide may be, for example, In:Sn:Zn = 2:0.1:1, In:Sn:Zn = 4:0.1:1, or a composition in the vicinity thereof.

[0167] The compositions of the metal oxides used in the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b can be analyzed by, for example, energy dispersive X-ray spectrometry (EDX), XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content. Furthermore, it may be difficult to quantify element M, or element M may not be detected.

[0168] The sputtering method or the ALD method can be suitably used for forming the metal oxide. When the metal oxide is formed by the sputtering method, the composition of the metal oxide after the film formation may differ from the composition of the target. In particular, the zinc content in the metal oxide after the film formation may decrease to about 50% compared with that of the target. The metal oxide film may also be formed by the CVD method, the MBE method, the PLD method, or the like.

[0169] The semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b may have a stacked structure including two or more metal oxide layers. For example, as shown in FIG. 8A , the semiconductor layer 114a may have a two-layer stacked structure including a semiconductor layer 114a1 and a semiconductor layer 114a2, and the semiconductor layer 114b may have a two-layer stacked structure including a semiconductor layer 114b1 and a semiconductor layer 114b2. The two or more metal oxide layers included in the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b may have the same or substantially the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs.

[0170] The two or more metal oxide layers included in the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b may have different compositions.

[0171] In the following, a specific example will be shown in which the semiconductor layer 114a has a two-layer laminated structure of semiconductor layers 114a1 and 114a2, and the semiconductor layer 114b has a two-layer laminated structure of semiconductor layers 114b1 and 114b2, as shown in FIG. 8A.

[0172] For example, as described above, the semiconductor layer 114a2 can be made of a material having higher conductivity than the semiconductor layer 114a1, and the semiconductor layer 114b2 can be made of a material having higher conductivity than the semiconductor layer 114b1. By using a material having high conductivity for the semiconductor layer 114a2 in contact with the conductive layer 115a and the semiconductor layer 114b2 in contact with the conductive layer 115b, the contact resistance between the semiconductor layer 114a and the conductive layer 115a and the contact resistance between the semiconductor layer 114b and the conductive layer 115b can be reduced. Therefore, the on-state current of the transistor can be increased.

[0173] Here, if a material with high conductivity is used for the semiconductor layer 114a1 and the semiconductor layer 114b1, which can be made of the same material as the semiconductor layer 113, the threshold voltage of the transistor may shift, and the drain current (hereinafter also referred to as cutoff current) that flows when the gate voltage is 0 V may become large. Specifically, in the case of an n-channel transistor, the threshold voltage may become low. Therefore, it is preferable to use a material with lower conductivity than the semiconductor layer 114a2 for the semiconductor layer 114a1 and a material with lower conductivity than the semiconductor layer 114b2 for the semiconductor layer 114b1. As a result, in the case of an n-channel transistor, the threshold voltage can be increased and the transistor can have a small cutoff current. Note that a small cutoff current is sometimes referred to as a normally-off transistor.

[0174] As described above, by using a material having a higher conductivity than the semiconductor layer 114a1 for the semiconductor layer 114a2 and a material having a higher conductivity than the semiconductor layer 114b1 for the semiconductor layer 114b2, a normally-off transistor with a large on-state current can be obtained, thereby providing a semiconductor device that achieves both low power consumption and high performance.

[0175] A specific example in which the same material as that of the semiconductor layer 113 is used for the semiconductor layer 114a1 and the semiconductor layer 114b1 will be described below.

[0176] The carrier concentration of the semiconductor layer 114a2 and the semiconductor layer 114b2 is preferably higher than that of the semiconductor layer 113, the semiconductor layer 114a1, and the semiconductor layer 114b1. Increasing the carrier concentration of the semiconductor layer 114a2 and the semiconductor layer 114b2 increases the conductivity. This reduces the contact resistance between the semiconductor layer 114a and the conductive layer 115a and the contact resistance between the semiconductor layer 114b and the conductive layer 115b. This increases the on-state current of the transistor. Furthermore, reducing the carrier concentration of the semiconductor layer 113 reduces the conductivity, enabling the transistor to be a normally-off transistor.

[0177] Note that the semiconductor layers 113, 114a, and 114b are not limited to the above-described structures. The semiconductor layers 114a2 and 114b2 may be made of a material having lower conductivity than the semiconductor layers 113, 114a1, and 114b1. The carrier concentrations of the semiconductor layers 114a2 and 114b2 may be lower than the carrier concentrations of the semiconductor layers 113, 114a1, and 114b1.

[0178] The band gap of the first metal oxide used in the semiconductor layer 113, the semiconductor layer 114a1, and the semiconductor layer 114b1 is preferably different from the band gap of the second metal oxide used in the semiconductor layer 114a2 and the semiconductor layer 114b2. For example, the difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more.

[0179] The band gap of the second metal oxide used for the semiconductor layer 114a2 and the semiconductor layer 114b2 is preferably smaller than the band gap of the first metal oxide used for the semiconductor layer 113, the semiconductor layer 114a1, and the semiconductor layer 114b1. This can reduce the contact resistance between the semiconductor layer 114a and the conductive layer 115a and the contact resistance between the semiconductor layer 114b and the conductive layer 115b. Therefore, a transistor with a large on-state current can be obtained. Furthermore, in the case of an n-channel transistor, the threshold voltage can be increased, and the transistor can be a normally-off transistor. Furthermore, the large band gap of the first metal oxide can suppress generation and induction of carriers in the semiconductor layer 113 and at the interface between the semiconductor layer 113 and the insulating layer 105, for example. This can improve the reliability of the transistor.

[0180] For example, the content of element M in the second metal oxide is preferably lower than the content of element M in the first metal oxide. More specifically, for example, it is preferable to use a metal oxide having a composition of In:M:Zn=1:1:1 (atomic ratio) or a composition thereabout for the semiconductor layers 114a2 and 114b2, and to use a metal oxide having a composition of In:M:Zn=1:3:2 (atomic ratio) or a composition thereabout for the semiconductor layers 113, 114a1, and 114b1. In this case, it is particularly preferable to use one or more of gallium, aluminum, and tin as the element M.

[0181] Note that the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b are not limited to the above-described structures, and the band gap of the second metal oxide may be larger than the band gap of the first metal oxide.

[0182] The content of element M in the second metal oxide is preferably lower than the content of element M in the first metal oxide. The second metal oxide may contain a trace amount of element M or may not contain element M. For example, it is preferable that the second metal oxide used in the semiconductor layers 114a2 and 114b2 be In—Zn oxide, and the first metal oxide used in the semiconductor layers 113, 114a1, and 114b1 be In-M-Zn oxide. Specifically, the second metal oxide may be In—Zn oxide, and the first metal oxide may be In—Ga—Zn oxide.

[0183] For example, as the semiconductor layer 114a2 and the semiconductor layer 114b2, it is preferable to use a metal oxide having a composition of In:Zn=1:1 (atomic ratio) or a composition thereabout, a metal oxide having a composition of In:Zn=2:1 (atomic ratio) or a composition thereabout, a metal oxide having a composition of In:Sn:Zn=2:0.1:1 (atomic ratio) or a composition thereabout, a metal oxide having a composition of In:Zn=4:1 (atomic ratio) or a composition thereabout, a metal oxide having a composition of In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, or indium oxide. Furthermore, for the semiconductor layer 113, the semiconductor layer 114a1, and the semiconductor layer 114b1, it is preferable to use a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or a composition thereof, a metal oxide having an atomic ratio of In:Ga:Zn=1:3:2 or a composition thereof, or a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or a composition thereof, which can provide a highly reliable transistor with a large on-state current and little variation.

[0184] 8A , when a metal oxide is used for the conductive layers 115a1 and 115b1, it is preferable to use In—Zn oxide or In—Sn—Zn oxide for the semiconductor layers 114a2 and 114b2 because the contact resistance can be reduced compared to when In—Ga—Zn oxide is used for the semiconductor layers 114a2 and 114b2. Specifically, it is preferable to use ITO or ITSO for the conductive layers 115a1 and 115b1, In—Zn oxide or In—Sn—Zn oxide for the semiconductor layers 114a2 and 114b2, and In—Ga—Zn oxide for the semiconductor layers 113, 114a1, and 114b1.

[0185] Note that the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b are not limited to the above-described structures, and the content of the element M in the second metal oxide may be higher than the content of the element M in the first metal oxide.

[0186] The crystallinity of the semiconductor materials used for the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b is not particularly limited, and any of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. The use of a single crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0187] The semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b each preferably include a crystalline metal oxide layer. Examples of the structure of a crystalline metal oxide include a CAAC structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide layer for the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b, the density of defect states in the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b can be reduced, and a highly reliable semiconductor device can be realized.

[0188] A polycrystalline structure has crystal grain boundaries. Furthermore, when a polycrystalline metal oxide layer is formed and then heat-treated, tiny gaps (also called nanocracks or microcracks) or tiny spaces (also called nanospaces or microspaces) can be formed between crystalline portions. When tiny gaps or tiny spaces are formed in a metal oxide layer, the electrical resistance of the metal oxide layer increases. This is because the electrical resistance of the tiny gaps or tiny spaces is very high, for example, infinite. When a metal oxide layer having tiny gaps or tiny spaces is used in a channel formation region of a transistor, the contact resistance between the metal oxide layer and one or both of the source electrode and the drain electrode increases. This adversely affects the initial characteristics or reliability of the transistor. The CAAC structure has fewer crystal grain boundaries in the a-b plane than a polycrystalline structure, and therefore can realize a highly reliable semiconductor device.

[0189] The higher the crystallinity of the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b, the more the density of defect states in the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0190] The higher the substrate temperature (stage temperature) during the formation of the metal oxide layer, the higher the crystallinity of the formed metal oxide layer.Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film formation gas used during the formation (hereinafter also referred to as oxygen flow rate ratio), the higher the crystallinity of the formed metal oxide layer.

[0191] The crystallinity of the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b can be analyzed by, for example, X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.

[0192] The thickness of the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b is preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, further preferably 5 nm to 100 nm, further preferably 10 nm to 100 nm, further preferably 10 nm to 70 nm, further preferably 15 nm to 70 nm, further preferably 15 nm to 50 nm, and further preferably 20 nm to 50 nm. In a transistor used in a finer semiconductor device, the thickness of the semiconductor layer 113 is preferably 1 nm to 20 nm, 1 nm to 15 nm, 3 nm to 12 nm, or 5 nm to 10 nm.

[0193] The hydrogen contained in the semiconductor layer 113 reacts with the oxygen that bonds with the metal atoms to form water, and oxygen vacancies (V 113) are formed in the semiconductor layer 113. Ｏ In addition, defects in which hydrogen enters oxygen vacancies (hereinafter referred to as V ＯHydrogen atoms (H) may function as donors and generate electrons as carriers. Furthermore, some of the hydrogen atoms may bond with oxygen atoms that bond to metal atoms to generate electrons as carriers. Therefore, a transistor using a metal oxide containing a large amount of hydrogen is likely to have normally-on characteristics (i.e., a negative threshold voltage). Furthermore, hydrogen atoms in a metal oxide are easily moved by stresses such as heat or an electric field. Therefore, if the semiconductor layer 113 contains a large amount of hydrogen, the reliability of the transistor may be degraded. Similarly, if the semiconductor layer 114a and the semiconductor layer 114b contain a large amount of hydrogen, the reliability of the transistor may be degraded.

[0194] V in the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b Ｏ It is preferable to reduce H as much as possible to make the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b highly intrinsic or substantially highly intrinsic. Ｏ To obtain a metal oxide with a sufficiently reduced amount of H, it is important to remove impurities such as water and hydrogen from the metal oxide (this may be referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the metal oxide to repair oxygen vacancies. Ｏ Stable electrical characteristics can be imparted by using a metal oxide in which impurities such as H are sufficiently reduced for a channel formation region of a transistor. Note that supplying oxygen to a metal oxide to repair oxygen vacancies may be referred to as oxygen-adding treatment.

[0195] The carrier concentration of the metal oxide in the region that functions as the channel formation region is 1×10 １８ cm −３ Preferably, it is 1×10 or less. １７ cm −３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３The lower limit of the carrier concentration of the metal oxide in the region that functions as the channel formation region is not particularly limited, but is preferably, for example, 1×10 −９ cm −３ It can be said that:

[0196] Here, the influence of each impurity in the metal oxide will be described.

[0197] When a metal oxide contains silicon or carbon, which is one of the group 14 elements, defect levels are formed in the metal oxide. Therefore, the carbon concentration in the channel formation region of the metal oxide obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10 １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The silicon concentration in the channel formation region of the metal oxide obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10 １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0198] Furthermore, when nitrogen is contained in a metal oxide, electrons serving as carriers are generated, the carrier concentration increases, and the metal oxide is likely to become n-type. As a result, a transistor using a nitrogen-containing metal oxide as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in a metal oxide, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the metal oxide obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 5×10, more preferably １８ atoms / cm ３ Less than 1×10, more preferably 1×10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ The following applies.

[0199] Furthermore, hydrogen contained in metal oxide reacts with oxygen bonded to metal atoms to form water, which may form oxygen vacancies. Hydrogen entering the oxygen vacancies may generate electrons, which serve as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons, which serve as carriers. Therefore, transistors using metal oxides containing hydrogen tend to exhibit normally-on characteristics. Therefore, it is preferable to reduce hydrogen as much as possible in the channel formation region of the metal oxide. Specifically, the hydrogen concentration in the channel formation region of the metal oxide obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10 １９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８atoms / cm ３ Less than.

[0200] Furthermore, when a metal oxide contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using a metal oxide containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the metal oxide obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0201] By using a metal oxide with sufficiently reduced impurities for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0202] Note that the semiconductor device of this embodiment may also be applied to a transistor using another semiconductor material in the channel formation region. Examples of such another semiconductor material include semiconductors made of simple elements or compound semiconductors. Examples of semiconductors made of simple elements include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. Note that the aforementioned oxide semiconductor is also a type of compound semiconductor. Note that these semiconductor materials may contain impurities as dopants.

[0203] Silicon that can be used as a semiconductor material for a transistor includes single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low temperature polysilicon (LTPS).

[0204] The semiconductor layer of the transistor may include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0205] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), and zirconium selenide (typically ZrSe ２ ) etc.

[0206] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 101, insulating layer 105, insulating layer 109, insulating layer 131a, insulating layer 131b, insulating layer 133a, insulating layer 133b, insulating layer 135, insulating layer 137, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and an oxide containing aluminum and hafnium (hafnium aluminate) film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. An insulating layer included in a semiconductor device may be an organic insulating film.

[0207] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-dielectric-constant (high-k) material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. Meanwhile, using a material with a low dielectric constant for the insulating layer that functions as an interlayer insulating layer can reduce the parasitic capacitance that occurs between conductive layers. Therefore, it is advisable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0208] Examples of high-k materials include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0209] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other examples of inorganic insulating materials with a low relative dielectric constant include silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0210] Furthermore, a material capable of exhibiting ferroelectricity may be used for the insulating layer of the semiconductor device. Examples of the material capable of exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ(X is a real number greater than 0). Ferroelectric materials include hafnium oxide to which element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added. The ratio of the number of hafnium atoms to the number of element J1 can be set as appropriate. For example, the ratio of the number of hafnium atoms to the number of element J1 can be set to 1:1 or close thereto. Ferroelectric materials include zirconium oxide to which element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added. The ratio of the number of zirconium atoms to the number of element J2 can be set as appropriate. For example, the ratio of the number of zirconium atoms to the number of element J2 can be set to 1:1 or close thereto. Furthermore, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0211] Furthermore, examples of materials that may exhibit ferroelectricity include metal nitrides containing the elements M1, M2, and nitrogen. Here, the element M1 is one or more selected from aluminum, gallium, indium, and the like. The element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, and the like. The ratio of the number of atoms of the element M1 to the number of atoms of the element M2 can be appropriately set. Furthermore, metal oxides containing the element M1 and nitrogen may exhibit ferroelectricity even without the element M2. Furthermore, examples of materials that may exhibit ferroelectricity include materials in which the element M3 is added to the above-mentioned metal nitrides. The element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, and the like. Here, the ratio of the number of atoms of the element M1, the number of atoms of the element M2, and the number of atoms of the element M3 can be set appropriately.

[0212] Furthermore, materials that can have ferroelectricity include SrTaO ２ N or BaTaO ２ Perovskite-type oxynitrides such as GaFeO and GaFeO with κ-alumina structure ３ etc.

[0213] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited thereto. For example, metal oxynitrides in which nitrogen is added to the above metal oxides, or metal oxynitrides in which oxygen is added to the above metal nitrides, etc. may also be used.

[0214] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound composed of multiple materials selected from the materials listed above can be used. Alternatively, the insulating layer of a semiconductor device can have a laminated structure composed of multiple materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above can change not only depending on the film formation conditions but also on various processes, in this specification and the like, not only materials that exhibit ferroelectricity are referred to as ferroelectrics, but also as materials capable of exhibiting ferroelectricity.

[0215] Metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in thin films of a few nanometers. Furthermore, metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in very small areas. Therefore, by using metal oxides containing either or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved.

[0216] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0217] Ferroelectricity is believed to be exhibited by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. Furthermore, it is believed that the exhibiting of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, for an insulating layer to exhibit ferroelectricity, the insulating layer must contain crystals. In particular, an insulating layer containing crystals having an orthorhombic crystal structure is preferred because it exhibits ferroelectricity. The crystal structure of the crystals contained in the insulating layer may be one or more selected from cubic, tetragonal, orthorhombic, monoclinic, and hexagonal crystals. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having an amorphous structure and a crystalline structure.

[0218] Furthermore, adding a Group 3 element (also referred to as a IIIa element) in the periodic table to a metal oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases the remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide and make it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in a metal oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0219] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, or a metal nitride such as aluminum nitride, silicon nitride oxide, or silicon nitride.

[0220] Specifically, examples of insulating layers that suppress the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of insulating layers that suppress the permeation of impurities such as water and hydrogen and oxygen include hafnium aluminate. Examples of insulating layers that suppress the permeation of impurities such as water and hydrogen and oxygen include metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, and silicon nitride.

[0221] When the semiconductor layer 113 is a metal oxide layer, an insulating layer in contact with the semiconductor layer 113, such as the insulating layer 101, the insulating layer 105, and the insulating layer 109, is preferably an insulating layer having a region containing oxygen (also referred to as excess oxygen) that is desorbed by heating. This allows oxygen vacancies in the semiconductor layer 113 to be reduced by the excess oxygen. Examples of insulating layers that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0222] The insulating layer 101, the insulating layer 133a, the insulating layer 133b, and the insulating layer 137 preferably have a low dielectric constant because they function as interlayer insulating layers. By using a material with a low dielectric constant for the interlayer insulating layer, parasitic capacitance generated between conductive layers can be reduced. Silicon oxide and silicon oxynitride are each thermally stable, and therefore are suitable for the insulating layer 101, the insulating layer 133a, the insulating layer 133b, and the insulating layer 137.

[0223] The concentrations of impurities such as water and hydrogen are preferably reduced in the insulating layer 101, the insulating layer 133a, the insulating layer 133b, and the insulating layer 137. This can suppress the intrusion of impurities such as water and hydrogen into a channel formation region of the semiconductor layer 113, for example.

[0224] It is preferable to use a barrier insulating layer against impurities such as water and hydrogen as the insulating layer 131a, the insulating layer 131b, and the insulating layer 135. In particular, it is preferable to use a barrier insulating layer against hydrogen as the insulating layer 131a, the insulating layer 131b, and the insulating layer 135. Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0225] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties refer to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0226] The insulating layer 105 and the insulating layer 109 preferably have a function of capturing and fixing hydrogen. This can reduce the hydrogen concentration in the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b (particularly, the hydrogen concentration in the channel formation region of the transistor). Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0227] Examples of materials for the insulating layer having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and hafnium aluminate. These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium. Metal oxides with an amorphous structure have dangling bonds in some oxygen atoms, which enhance their ability to capture or fix hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure may be achieved by including silicon in these oxides. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate). Metal oxides may have crystalline regions and / or grain boundaries in some parts.

[0228] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0229] The above-described barrier insulating layer against hydrogen is preferably used for the insulating layer 105 and the insulating layer 109. By using the barrier insulating layer against hydrogen for the insulating layer 105 and the insulating layer 109, diffusion of impurities contained in the conductive layer 111 and the conductive layer 119 to the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b can be suppressed. For example, silicon nitride has a high barrier property against hydrogen and is therefore suitable for the insulating layer 105 and the insulating layer 109. Furthermore, the insulating layer 105 and the insulating layer 109 may include an insulating layer having a heat-stable structure, such as silicon oxide or silicon oxynitride.

[0230] With such a structure, a semiconductor device having good electrical characteristics, high reliability, little variation in the electrical characteristics of the transistors, and a large on-state current can be provided.

[0231] Furthermore, the insulating layer 105 and the insulating layer 109 may have an insulating layer with a thermally stable structure, such as silicon oxide or silicon oxynitride.

[0232] The insulating layer 105 and the insulating layer 109 may have an insulating layer having a heat-stable structure between a pair of insulating layers having a function of capturing and fixing hydrogen.

[0233] The insulating layer 105 and the insulating layer 109 preferably have a barrier insulating layer against oxygen, which can suppress oxidation of the conductive layer 111, the conductive layer 119, and the like. When the insulating layer 105 has a stacked-layer structure, a layer in contact with the conductive layer 111 is preferably a barrier insulating layer against oxygen. When the insulating layer 109 has a stacked-layer structure, a layer in contact with the conductive layer 119 is preferably a barrier insulating layer against oxygen.

[0234] Examples of the oxygen barrier insulating layer include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, hafnium aluminate, and hafnium silicate.

[0235] Each of the layers constituting the insulating layer 105 and the insulating layer 109 is preferably a thin film. For example, when the insulating layer 105 and the insulating layer 109 each have a thickness of 1 nm to 20 nm, preferably 3 nm to 10 nm, the subthreshold swing (also referred to as S value), which is one of the transistor characteristics, can be reduced. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude with a constant drain voltage in the subthreshold region.

[0236] The insulating layer 105 and the insulating layer 109 can have a two-layer structure in which a first insulating layer and a second insulating layer are stacked in this order from the semiconductor layer 113 side. In this case, the first insulating layer is preferably made of a material with a low dielectric constant. Silicon oxide or silicon oxynitride is preferably used as the material with a low dielectric constant. In this case, the first insulating layer contains at least silicon and oxygen. The first insulating layer is a layer in contact with the semiconductor layer 113. By using an oxide insulating layer as the first insulating layer, oxygen can be supplied to the semiconductor layer 113. Furthermore, by providing the second insulating layer, oxygen contained in the first insulating layer can be prevented from diffusing into the conductive layer 111 or the conductive layer 119, and thus oxidation of the conductive layer 111 or the conductive layer 119 can be prevented. Furthermore, a decrease in the amount of oxygen supplied from the first insulating layer to the semiconductor layer 113 can be prevented.

[0237] The first insulating layer preferably has a function of capturing or fixing hydrogen. When the first insulating layer has a function of capturing or fixing hydrogen, hydrogen contained in the semiconductor layer 113 can be more effectively captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 113 can be reduced. For example, hafnium silicate is preferably used for the first insulating layer. In addition, the first insulating layer preferably has an amorphous structure.

[0238] By making the first insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. Suppressing the formation of crystal grain boundaries can improve the flatness of the first insulating layer. This makes it possible to uniformize the film thickness distribution of the first insulating layer and reduce extremely thin film thickness portions, thereby improving the breakdown voltage of the first insulating layer. Furthermore, it is possible to uniformize the film thickness distribution of the film provided on the first insulating layer.

[0239] Furthermore, by suppressing the formation of grain boundaries in the first insulating layer, leakage current due to defect levels in the grain boundaries can be reduced, allowing the first insulating layer to function as an insulating film with low leakage current.

[0240] Furthermore, since hafnium oxide is a high-k material, hafnium silicate can also be a high-k material depending on the silicon content. Therefore, when the first insulating layer is used as a gate insulating layer, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulating layer. Furthermore, it is possible to reduce the EOT.

[0241] The second insulating layer preferably includes a barrier insulating layer against hydrogen. By using a barrier insulating layer against hydrogen as the second insulating layer, diffusion of impurities contained in the conductive layer 111 and the conductive layer 119 into the semiconductor layer 113 can be suppressed. Silicon nitride is suitable for the second insulating layer because it has a high barrier property against hydrogen. When silicon nitride is used as the second insulating layer, the second insulating layer contains silicon and nitrogen.

[0242] The second insulating layer preferably includes a barrier insulating layer against oxygen, which can prevent the conductive layer 111 and the conductive layer 119 from being oxidized. Furthermore, oxygen contained in the semiconductor layer 113 can be prevented from diffusing into the conductive layer 111 or the conductive layer 119, which can prevent oxygen vacancies from being formed in the semiconductor layer 113.

[0243] With such a structure, a semiconductor device having good electrical characteristics, high reliability, little variation in the electrical characteristics of the transistors, and a large on-state current can be provided.

[0244] The insulating layer 105 and the insulating layer 109 may have a three-layer structure in which a first insulating layer, a third insulating layer, and a second insulating layer are stacked in this order from the semiconductor layer 113 side. That is, the third insulating layer may be provided between the first insulating layer and the second insulating layer.

[0245] For example, it is preferable to use a material with a low relative dielectric constant for the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen for the third insulating layer. Specifically, it is preferable to use silicon oxide for the first insulating layer and hafnium oxide for the third insulating layer. In this case, the first insulating layer contains silicon and oxygen, and the third insulating layer contains hafnium and oxygen. With this structure, oxygen can be supplied to the semiconductor layer 113. Furthermore, hydrogen contained in the semiconductor layer 113 can be more effectively captured or fixed.

[0246] Alternatively, for example, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer, and to use a material with a low relative dielectric constant as the third insulating layer. Specifically, it is preferable to use hafnium oxide as the first insulating layer, and silicon oxide as the third insulating layer. In this case, the first insulating layer contains hafnium and oxygen, and the third insulating layer contains silicon and oxygen. With this structure, oxygen can be supplied to the semiconductor layer 113. Furthermore, hydrogen contained in the semiconductor layer 113 can be more effectively captured or fixed.

[0247] The second insulating layer may have the same structure as described above.

[0248] The insulating layer 105 and the insulating layer 109 may have a four-layer structure in which a fourth insulating layer, a first insulating layer, a third insulating layer, and a second insulating layer are stacked in this order from the semiconductor layer 113 side. That is, in the above-described three-layer stacked structure, the fourth insulating layer may be added to the layer closest to the semiconductor layer 113. The fourth insulating layer may be a layer in contact with the semiconductor layer 113.

[0249] The above-described configuration can be applied to the first to third insulating layers.

[0250] The fourth insulating layer preferably has a barrier property against oxygen. As described above, the fourth insulating layer is a layer in contact with the semiconductor layer 113. When the fourth insulating layer has a barrier property against oxygen, oxygen can be prevented from being released from the semiconductor layer 113. For example, aluminum oxide can be used for the fourth insulating layer. In this case, the fourth insulating layer contains aluminum and oxygen. Aluminum oxide has a function of capturing or fixing hydrogen, and is therefore suitable as the fourth insulating layer in contact with the semiconductor layer 113.

[0251] To miniaturize transistors, the first to fourth insulating layers preferably have thin film thicknesses. The first to fourth insulating layers each have a film thickness of preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, still more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Note that each of the first to fourth insulating layers preferably has a region with the above film thickness in at least a portion thereof.

[0252] Typically, the thicknesses of the fourth insulating layer, the first insulating layer, the third insulating layer, and the second insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a structure, the transistor can have good electrical characteristics even when miniaturized or highly integrated.

[0253] [Conductive Layer] For the conductive layers (such as the conductive layer 111, the conductive layer 115a, the conductive layer 115b, and the conductive layer 119) included in the semiconductor device, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing any of the above metal elements or an alloy combining the above metal elements, etc. As the alloy containing any of the above metal elements, a nitride of the alloy or an oxide of the alloy may be used. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel, etc., is preferably used. Alternatively, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0254] In addition, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; conductive materials containing oxygen, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have the function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Note that oxide conductors can be used as the conductive material containing oxygen. Examples of oxide conductors include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, ITO, indium tin oxide containing titanium oxide, ITSO, IZO (registered trademark), and indium zinc oxide containing tungsten oxide.

[0255] Conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0256] The conductive layers 111 and 119 are preferably formed using a highly conductive material such as tungsten, copper, or aluminum. Furthermore, the conductive layers 111 and 119 are preferably formed using a conductive material that is resistant to oxidation, a conductive material that has a function of suppressing oxygen diffusion, or the like. As described above, examples of the conductive material include a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, and a conductive material containing oxygen, such as ruthenium oxide. By using a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion, or the like, for the conductive layer 111, a decrease in the conductivity of the conductive layer 111 due to oxidation of the conductive layer 111 can be suppressed. Similarly, by using a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion, or the like, for the conductive layer 119, a decrease in the conductivity of the conductive layer 119 due to oxidation of the conductive layer 119 can be suppressed.

[0257] For the conductive layer 111 and the conductive layer 119, a conductive material containing, for example, the metal element and oxygen contained in the semiconductor layer 113 may be used. Alternatively, a conductive material containing the above-described metal element and nitrogen (for example, titanium nitride, tantalum nitride, or the like) may be used. Alternatively, one or more of ITO, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, IZO (registered trademark), and ITSO may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, for example, hydrogen contained in the semiconductor layer 113 may be captured. Alternatively, hydrogen mixed in from an outer insulating layer or the like may be captured.

[0258] The conductive layer 115a and the conductive layer 115b may have a stacked structure including two or more conductive layers. A specific example will be described below in which the conductive layer 115a has a two-layer stacked structure including a conductive layer 115a1 and a conductive layer 115a2, and the conductive layer 115b has a two-layer stacked structure including a conductive layer 115b1 and a conductive layer 115b2, as shown in FIG. 8A .

[0259] The conductive layer 115a1 and the conductive layer 115b1 can be formed using the aforementioned conductive material containing oxygen. The conductive layer 115a2 can be formed using a material having higher conductivity than the conductive layer 115a1. The conductive layer 115b2 can be formed using a material having higher conductivity than the conductive layer 115b1. For example, the aforementioned oxide conductors can be used for the conductive layer 115a1 and the conductive layer 115b1. As described above, tungsten, copper, aluminum, ruthenium, titanium nitride, tantalum nitride, or the like can be used for the conductive layer 115a2 and the conductive layer 115b2. By using a conductive material containing oxygen for the conductive layer 115a1 in contact with the semiconductor layer 114a and the conductive layer 115b1 in contact with the semiconductor layer 114b, the contact resistance between the semiconductor layer 114a and the conductive layer 115a and the contact resistance between the semiconductor layer 114b and the conductive layer 115b can be reduced. Furthermore, by using a material having higher conductivity than the conductive layer 115a1 for the conductive layer 115a2 and a material having higher conductivity than the conductive layer 115b1 for the conductive layer 115b2, the conductivity of the conductive layer 115a and the conductive layer 115b can be increased.

[0260] [Substrate] Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride, substrates having a metal oxide, and the like. Examples of substrates include a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, and a memory element.

[0261] <Structure Example of Memory Device> An example in which the semiconductor device of one embodiment of the present invention is applied to a memory device will be described below.

[0262] 9A is a circuit diagram illustrating a configuration example of a memory cell 20 included in a memory device of one embodiment of the present invention. The memory cell 20 includes a transistor 11 and a capacitor 13. The transistor 11 can be, for example, any of the above-described transistors 11A to 11E.

[0263] A gate of the transistor 11 is electrically connected to a wiring 15. One of a source and a drain of the transistor 11 is electrically connected to a wiring 17. The other of the source and the drain of the transistor 11 is electrically connected to one electrode of a capacitor 13. The other electrode of the capacitor 13 is electrically connected to a wiring 19.

[0264] The wiring 15 functions as a word line. A signal for controlling the on / off of the transistor 11 is supplied to the wiring 15.

[0265] The wiring 17 functions as a bit line. A data signal to be supplied to the memory cell 20 is supplied to the wiring 17. When the transistor 11 is on, data corresponding to the potential of the wiring 17 is written to the memory cell 20. Alternatively, data held in the memory cell 20 is output to the wiring 17 and read out. When the transistor 11 is turned off, the data written to the memory cell 20 is held. Specifically, the charge of the capacitor 13 is held.

[0266] The wiring 19 functions as a power supply line. A power supply potential, for example, a low power supply potential, is supplied to the wiring 19.

[0267] 9B and 10A are cross-sectional views showing a configuration example of a memory device having the memory cell 20 shown in FIG. 9A. FIGS. 9B and 10A show an example in which a transistor 11A is used as the transistor 11. FIG. 10A shows an example in which a capacitor 13A is used as the capacitor 13. For the planar configuration of the transistor 11A shown in FIGS. 9B and 10A, refer to FIG. 2A. FIG. 9B is a cross-sectional view taken along dashed lines A1-A2 in FIG. 2A. FIG. 10A is a cross-sectional view taken along dashed lines B1-B2 in FIG. 2A.

[0268] 10A , the capacitor 13A is provided on the insulating layer 137. The capacitor 13A has a conductive layer 153c, an insulating layer 156 on the conductive layer 153c, and a conductive layer 157 on the insulating layer 156. The conductive layer 157 has a region that overlaps with the conductive layer 153c with the insulating layer 156 interposed therebetween.

[0269] At least a portion of the conductive layer 153c functions as one electrode of the capacitor 13A. At least a portion of the conductive layer 157 functions as the other electrode of the capacitor 13A. At least a portion of the insulating layer 156 functions as a dielectric layer of the capacitor 13A. The capacitor 13A is a parallel-plate MIM (Metal-Insulator-Metal) capacitor.

[0270] Openings reaching the conductive layer 111 are provided in the insulating layer 137 and the insulating layer 135, and the conductive layer 151a is provided to have a region located inside the openings. The conductive layer 151a can be in contact with the conductive layer 111 inside the openings.

[0271] Openings reaching the conductive layer 115a are provided in the insulating layers 137, 135, 133a, and 131a, and the conductive layer 151b is provided to have a region located inside the openings. The conductive layer 151b can be in contact with the conductive layer 115a inside the openings. Furthermore, openings reaching the conductive layer 115b are provided in the insulating layers 137, 135, 133b, and 131b, and the conductive layer 151c is provided to have a region located inside the openings. The conductive layer 151c can be in contact with the conductive layer 115b inside the openings.

[0272] The conductive layers 151a, 151b, and 151c each function as a plug, for example. Note that the conductive layers 151a, 151b, and 151c are also referred to as connection electrodes.

[0273] A conductive layer 153a is provided on the conductive layer 151a and the insulating layer 137. The conductive layer 153a may have a region in contact with the top surface of the conductive layer 151a and a region in contact with the top surface of the insulating layer 137. The conductive layer 111 and the conductive layer 153a are electrically connected via the conductive layer 151a. Similarly, the conductive layer 115a and the conductive layer 153b are electrically connected via the conductive layer 151b, and the conductive layer 115b and the conductive layer 153c are electrically connected via the conductive layer 151c.

[0274] An insulating layer 156 is provided over the conductive layer 153a, the conductive layer 153b, the conductive layer 153c, and the insulating layer 137. The insulating layer 156 can be provided so as to cover, for example, at least part of the top surface and side surface of the conductive layer 153a, the top surface and side surface of the conductive layer 153b, and the top surface and side surface of the conductive layer 153c.

[0275] As described above, the conductive layer 157 having a region overlapping with the conductive layer 153c is provided over the insulating layer 156. At least a portion of the conductive layer 153c, the insulating layer 156, and the conductive layer 157 is included in the capacitor 13A.

[0276] An insulating layer 159 is provided over the conductive layer 157 and the insulating layer 156. The insulating layer 159 is provided to cover a top surface of the conductive layer 157, side surfaces of the conductive layer 157, and a top surface of the insulating layer 156. The insulating layer 159 functions as an interlayer insulating layer and can be a planarized layer.

[0277] Openings reaching the conductive layer 153a are provided in the insulating layers 159 and 156, and the conductive layer 175 is provided to have a region located inside the openings. The conductive layer 175 can be in contact with the conductive layer 153a inside the openings.

[0278] A conductive layer 177 is provided over the conductive layer 175 and the insulating layer 159. The conductive layer 177 can have a region in contact with the top surface of the conductive layer 175 and a region in contact with the top surface of the insulating layer 159. The conductive layer 111 and the conductive layer 177 are electrically connected to each other through the conductive layer 151 a, the conductive layer 153 a, and the conductive layer 175.

[0279] An insulating layer 179 is provided over the conductive layer 177 and the insulating layer 159. The insulating layer 179 is provided to cover the top surface of the conductive layer 177, side surfaces of the conductive layer 177, and the top surface of the insulating layer 159. The insulating layer 179 functions as an interlayer insulating layer and can be a planarized layer.

[0280] At least a part of the conductive layer 177 can function as the wiring 15 shown in FIG. 9A . At least a part of the conductive layer 153b can function as the wiring 17 shown in FIG. 9A . At least a part of the conductive layer 157 can function as the wiring 19 shown in FIG. 9A . Note that at least a part of the conductive layer 175 may function as the wiring 15, at least a part of the conductive layer 153a may function as the wiring 15, or at least a part of the conductive layer 151a may function as the wiring 15. Furthermore, at least a part of the conductive layer 151b may function as the wiring 17. Furthermore, at least a part of the conductive layer 111 may function as the wiring 15, and at least a part of the conductive layer 115a may function as the wiring 17.

[0281] The conductive layers 151a, 151b, 151c, 153a, 153b, 153c, 157, 175, and 177 can each be formed using the conductive materials described in the above section [Conductive Layer]. The conductive layers 151a, 151b, 151c, and 175 can each be formed using, for example, the materials that can be used for the conductive layers 115a and 115b, respectively. The conductive layers 153a, 153b, 153c, 157, and 177 can each be formed using, for example, the materials that can be used for the conductive layer 111, in the form of a single layer or a stacked layer.

[0282] The insulating layer 156, the insulating layer 159, and the insulating layer 179 can each be formed using the insulating material described above in [Insulating Layer]. The insulating layer 156 can be formed using a material that can be used for the insulating layer 105. The insulating layer 159 and the insulating layer 179 can each be formed using a material that can be used for the insulating layer 137.

[0283] Fig. 10B is a cross-sectional view showing an example of the configuration of memory cell 20 when capacitor 13B is used as capacitor 13. Fig. 10B is a cross-sectional view taken along dashed dotted line B1-B2 shown in Fig. 2A.

[0284] In the example shown in FIG. 10B , capacitor 13B is provided on conductive layer 151c and on conductive layer 153c provided on insulating layer 137. Capacitor 13B has a conductive layer 163 on conductive layer 153c, an insulating layer 165 on conductive layer 163, and a conductive layer 167 on insulating layer 165. At least a portion of conductive layer 163 functions as one electrode of capacitor 13B. At least a portion of insulating layer 165 functions as a dielectric layer of capacitor 13B. At least a portion of conductive layer 167 functions as the other electrode of capacitor 13B. At least a portion of conductive layer 167 can function as wiring 19 shown in FIG. 9A .

[0285] 10B , an insulating layer 155 is provided over the conductive layer 153b, the conductive layer 153c, and the insulating layer 137. An opening reaching the conductive layer 153c is provided in the insulating layer 155. A conductive layer 163 is provided along the side surface of the opening and the top surface of the conductive layer 153c. The conductive layer 163 has a region in contact with the side surface of the insulating layer 155 in the opening and a region in contact with the top surface of the conductive layer 153c. The conductive layer 163 is electrically connected to the conductive layer 115b via the conductive layer 153c and the conductive layer 151c.

[0286] The insulating layer 165 is provided along the top surface and side surfaces of the conductive layer 163 so as to have a region located inside the opening of the insulating layer 155. The conductive layer 167 is provided on the insulating layer 165 so as to have a region located inside the opening of the insulating layer 155. The conductive layer 167 can be provided so as to fill the opening of the insulating layer 155.

[0287] As described above, the capacitor 13B is a trench-type MIM capacitor. The MIM structure of the capacitor 13B is formed not only on the top surface of the conductive layer 163 that functions as one of the electrodes, but also along the side surface. Therefore, the capacitance value of the capacitor 13B can be increased without increasing the occupied area compared to the capacitor 13A. On the other hand, the number of manufacturing steps for a semiconductor device including the capacitor 13A can be reduced compared to a semiconductor device including the capacitor 13B.

[0288] An insulating layer 169 is provided over the insulating layer 155 so as to cover the side surfaces of the conductive layer 163, the insulating layer 165, and the conductive layer 167. The insulating layer 169 can be formed by depositing an insulating film over the conductive layer 167 and the insulating layer 155 and performing planarization treatment on the insulating film until the top surface of the conductive layer 167 is exposed. Here, the conductive layer 167 may be planarized by the planarization treatment. An insulating layer 179 is provided over the conductive layer 167 and the insulating layer 169.

[0289] The conductive materials described in the above [Conductive Layer] can be used for the conductive layer 163 and the conductive layer 167. For the conductive layer 163 and the conductive layer 167, for example, the materials that can be used for the conductive layer 115a and the conductive layer 115b can be used for the conductive layer 163 and the conductive layer 167, respectively.

[0290] The insulating layer 155, the insulating layer 165, and the insulating layer 169 can each be formed using the insulating material described above in [Insulating Layer]. The insulating layer 155 and the insulating layer 169 can each be formed using the material that can be used for the insulating layer 137. The insulating layer 165 can be formed using the material that can be used for the insulating layer 105.

[0291] <Example of Manufacturing Method of Semiconductor Device> Next, a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described with reference to the drawings. Note that, with regard to materials and forming methods of elements, descriptions of parts similar to those described above may be omitted.

[0292] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting a semiconductor device can be formed using a sputtering method, a CVD method, a vacuum deposition method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0293] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to form insulating films, while DC sputtering is mainly used to form metal conductive films. Pulsed DC sputtering is mainly used to form films of compounds such as oxides, nitrides, or carbides using reactive sputtering.

[0294] CVD methods can be further classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, and photo-CVD (photo-CVD) methods that utilize light. CVD methods can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0295] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can reduce plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, and elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, or elements included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0296] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0297] The CVD and ALD methods differ from sputtering methods in that particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent film thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio, for example. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0298] Furthermore, the CVD method allows deposition of a film of any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0299] Furthermore, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0300] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a wet film formation method such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0301] The thin film can be processed by, for example, forming a resist mask by photolithography and then etching the thin film according to the pattern of the resist mask. Alternatively, the thin film may be processed by nanoimprinting, sandblasting, lift-off, or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask. Furthermore, a photosensitive thin film can be processed by exposure and development. In other words, a photosensitive thin film can be processed by photolithography.

[0302] In this specification and the like, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

[0303] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0304] The thin film can be etched by dry etching, wet etching, or the like.

[0305] Unless otherwise specified, an example of a method for manufacturing a semiconductor device including the transistor 11A shown in FIGS. 2A, 2B, and 2C will be described below.

[0306] First, an insulating layer 101 functioning as a base insulating layer is formed on a substrate (not shown), a semiconductor layer 113<1> is formed on the insulating layer 101, a sacrificial layer 121<1> is formed on the semiconductor layer 113<1>, a semiconductor layer 113<2> is formed on the sacrificial layer 121<1>, a semiconductor layer 113<2> is formed on the semiconductor layer 113<2>, a semiconductor layer 113<3> is formed on the sacrificial layer 121<2>, a semiconductor layer 113<3> is formed on the sacrificial layer 123, and a mask layer 125 is formed on the sacrificial layer 123 (FIGS. 11A, 11B, and 11C). FIG. 11A is a plan view, FIG. 11B is a cross-sectional view taken along dashed line A1-A2 in FIG. 11A, and FIG. 11C is a cross-sectional view taken along dashed line B1-B2 in FIG. 11A.

[0307] As described above, when n semiconductor layers 113 are formed, n-1 sacrificial layers 121 are formed. Note that the semiconductor layer 113<1> can be formed so as to be in contact with the upper surface of the insulating layer 101.

[0308] In a later step, an insulating layer 105 and a conductive layer 111 are formed in the region where the sacrificial layer 121 is formed. The thickness of the sacrificial layer 121 can be, for example, 3 nm to 300 nm, preferably 5 nm to 200 nm, more preferably 7 nm to 100 nm, and further preferably 10 nm to 50 nm.

[0309] The sacrificial layer 123 can have a stacked structure of multiple layers. Figures 11B and 11C show an example in which the sacrificial layer 123 has a two-layer stacked structure of a sacrificial layer 123a and a sacrificial layer 123b on the sacrificial layer 123a. Subsequent cross-sectional views illustrating examples of a method for manufacturing a semiconductor device also show an example in which the sacrificial layer 123 has a two-layer stacked structure of a sacrificial layer 123a and a sacrificial layer 123b on the sacrificial layer 123a. The thickness of the sacrificial layer 123a is preferably equal to or smaller than the thickness of the sacrificial layer 123b.

[0310] The insulating layer 101, the sacrificial layer 121<1>, the sacrificial layer 121<2>, the sacrificial layer 123a, the sacrificial layer 123b, and the mask layer 125 can be formed by, for example, a CVD method, an ALD method, a sputtering method, an MBE method, a PLD method, etc. The semiconductor layer 113<1>, the semiconductor layer 113<2>, and the semiconductor layer 113<3> can be formed by, for example, a sputtering method, an ALD method, etc.

[0311] The sacrificial layer 121<1>, the sacrificial layer 121<2>, the sacrificial layer 123a, and the sacrificial layer 123b can be made of, for example, the materials listed in the insulating layer section above. The sacrificial layer 121<1>, the sacrificial layer 121<2>, the sacrificial layer 123a, and the sacrificial layer 123b can be made of, for example, an inorganic insulating film, specifically, an oxide insulating film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film. The sacrificial layer 121<1> and the sacrificial layer 121<2> can be made of, for example, aluminum oxide, aluminum nitride, aluminum oxynitride, or aluminum nitride oxide. The sacrificial layer 123a and the sacrificial layer 123b can be made of, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide. Here, the sacrificial layer 123b preferably contains a different material from the sacrificial layer 123a. Note that an organic insulating film may also be used for the sacrificial layer 121<1>, the sacrificial layer 121<2>, the sacrificial layer 123a, and the sacrificial layer 123b. In particular, an organic insulating film may be used for the sacrificial layer 121<1> and the sacrificial layer 121<2>. Furthermore, a semiconductor material or a conductive material may be used for the sacrificial layer 121<1>, the sacrificial layer 121<2>, the sacrificial layer 123a, and the sacrificial layer 123b.

[0312] It is preferable to use a material for the sacrificial layer 123b that is different from the material for the insulating layer 133 that will be formed in a later step. As will be described in detail later, after forming the insulating layer 133, for example, planarization is performed with the sacrificial layer 123a as the end point. In this case, by using a material for the sacrificial layer 123b on the sacrificial layer 123a that is different from the material for the insulating layer 133, it is possible to easily detect the end point. Note that the sacrificial layer 123a can be made of the same material as the insulating layer 133. For example, when silicon oxide is used for the insulating layer 133, silicon oxide can be used for the sacrificial layer 123a and silicon nitride can be used for the sacrificial layer 123b.

[0313] The mask layer 125 is a layer that serves as a mask (also referred to as a hard mask) when processing the sacrificial layer 123, the semiconductor layer 113, and the sacrificial layer 121 in a later step. The mask layer 125 can be made of, for example, a metal material. The mask layer 125 can be made of, for example, tungsten. Note that the mask layer 125 may be made of a semiconductor material or an insulating material.

[0314] When the semiconductor layer 113 is a metal oxide layer and the ALD method is used as a film formation method for the semiconductor layer 113, by adopting a condition in which the substrate temperature is high during film formation and / or by performing an impurity removal treatment, the amount of carbon and chlorine contained in the film can be reduced compared to when the ALD method is used without applying these conditions.

[0315] For example, it is preferable to perform impurity removal treatment intermittently in an oxygen-containing atmosphere during the formation of the semiconductor layer 113. Furthermore, it is preferable to perform impurity removal treatment in an oxygen-containing atmosphere after the formation of the semiconductor layer 113. By performing the impurity removal treatment either during or after the formation of the semiconductor layer 113, impurities in the film can be removed. This can prevent impurities (such as hydrogen, carbon, and nitrogen) contained in raw materials such as precursors from remaining in the semiconductor layer 113. Therefore, the impurity concentration in the semiconductor layer 113 can be reduced. Furthermore, the crystallinity of the semiconductor layer 113 can be improved.

[0316] Examples of the impurity removal treatment include plasma treatment, microwave treatment, and heat treatment.

[0317] When performing the plasma treatment or microwave treatment, the substrate temperature is preferably set to room temperature (e.g., 25° C.) or higher, 100° C. or higher, 200° C. or higher, 300° C. or higher, or 400° C. or higher, and 500° C. or lower, or 450° C. or lower. The heat treatment temperature is preferably set to 100° C. or higher, 200° C. or higher, 300° C. or higher, or 400° C. or higher, and 500° C. or lower, or 450° C. or lower.

[0318] The temperature in the impurity removal treatment is preferably set to a temperature equal to or lower than the maximum temperature in the manufacturing process of a transistor or a semiconductor device, because the amount of impurities in the semiconductor layer 113 can be reduced without reducing productivity. For example, the productivity of the semiconductor device can be increased by setting the maximum temperature in the manufacturing process of the semiconductor device of one embodiment of the present invention to 500° C. or lower, preferably 450° C. or lower.

[0319] Here, the microwave treatment refers to, for example, a treatment using a device having a power source that generates high-density plasma using microwaves. In addition, in this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0320] In the microwave treatment, it is preferable to use a microwave treatment device having a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave treatment device is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, for example, it can be 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. Furthermore, the power of the power supply that applies microwaves in the microwave treatment device is preferably 1000 W to 10,000 W, preferably 2000 W to 5,000 W. Furthermore, the microwave treatment device may have a power supply that applies RF to the substrate side. By applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently introduced into the film.

[0321] The microwave treatment is preferably carried out under reduced pressure, and the pressure is preferably from 10 to 1000 Pa, and more preferably from 300 to 700 Pa. The treatment temperature is preferably from room temperature (25°C) to 750°C, more preferably from 300 to 500°C, and even more preferably from 400 to 450°C.

[0322] Alternatively, after the microwave treatment or plasma treatment, a heat treatment may be performed successively without exposure to the outside air. The temperature of the heat treatment is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0323] The microwave treatment can be carried out using, for example, oxygen gas and argon gas. Here, the oxygen flow rate ratio (O ２ / (O ２ The oxygen flow rate ratio (O + Ar) is greater than 0% and less than or equal to 100%. ２ / (O ２ The oxygen flow rate ratio (O ２ / (O ２ The oxygen flow rate ratio (O ２ / (O ２ +Ar)) is set to 10% or more and 30% or less.

[0324] The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen. The heat treatment may also be performed in an atmosphere of ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, and preferably 10 ppb or less).

[0325] By performing heat treatment in this manner, impurities such as hydrogen or carbon contained in the semiconductor layer 113 can be removed. For example, carbon in the semiconductor layer 113 can be removed by CO ２ and CO, and hydrogen in the semiconductor layer 113 is released as H ２ The impurities can be removed by the re-arrangement of metal atoms and oxygen atoms, resulting in improved crystallinity. Therefore, the semiconductor layer 113 having a highly crystalline layered crystal structure, particularly the semiconductor layer 113 having the CAAC structure, can be formed.

[0326] Furthermore, oxygen can be supplied to the semiconductor layer 113 by performing at least one of the above-described plasma treatment, microwave treatment, and heat treatment in an oxygen-containing atmosphere. Thus, when a metal oxide layer is used as the semiconductor layer 113, oxygen addition treatment can be performed on the semiconductor layer 113. Therefore, oxygen vacancies in the semiconductor layer 113 can be repaired, and a transistor with stable electrical characteristics can be manufactured. Here, the plasma treatment, microwave treatment, and heat treatment may be performed after the formation of the semiconductor layer 113<1> and before the formation of the sacrificial layer 121<1>, after the formation of the semiconductor layer 113<2> and before the formation of the sacrificial layer 121<2>, and after the formation of the semiconductor layer 113<3> and before the formation of the sacrificial layer 123, or may be performed all at once after the formation of the semiconductor layers 113<1> to 113<3>. Note that the plasma treatment, microwave treatment, and heat treatment for the oxygen-adding treatment can be performed even when the semiconductor layer 113 is formed by a method other than the ALD method, for example, a sputtering method.

[0327] Here, the insulating layer 101 can be formed to have a region containing excess oxygen. In this case, excess oxygen can be supplied to the semiconductor layer 113 by performing heat treatment after the formation of the semiconductor layer 113. Furthermore, the sacrificial layer 123, for example, the sacrificial layer 123a, can be formed to have a region containing excess oxygen. In this case, excess oxygen can be supplied to the semiconductor layer 113 by performing heat treatment after the formation of the sacrificial layer 123. In this manner, oxygen addition treatment can be performed on the semiconductor layer 113. Here, the conditions for the heat treatment can be the same as those that can be used for the above-described heat treatment.

[0328] 12A and 12B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device including the transistor 11B shown in Fig. 5B and Fig. 5C, respectively. When manufacturing a semiconductor device including the transistor 11B, a conductive layer 119 is formed and processed over the insulating layer 101, and an insulating layer 109 is formed over the insulating layer 101 and the conductive layer 119.

[0329] The conductive layer 119 can be formed by, for example, a CVD method, an ALD method, a sputtering method, or the like. After the conductive layer 119 is formed, a resist mask is formed by, for example, photolithography, and the conductive layer 119 is processed according to the pattern of the resist mask. This processing can be performed by, for example, an etching method, and is preferably performed by dry etching, which facilitates microfabrication. Subsequently, the resist mask is removed.

[0330] The insulating layer 109 can be formed to cover the conductive layer 119. The insulating layer 109 can be formed to cover, for example, the top surface of the conductive layer 119, the side surfaces of the conductive layer 119, and the top surface of the insulating layer 101. The conductive layer 119 and the insulating layer 109 can be formed to have a region in contact with the top surface of the insulating layer 101. The insulating layer 109 can be formed by using, for example, an ALD method.

[0331] Subsequently, a semiconductor layer 113<1> is formed on the insulating layer 109, a sacrificial layer 121<1> is formed on the semiconductor layer 113<1>, a semiconductor layer 113<2> is formed on the sacrificial layer 121<1>, a semiconductor layer 113<2> is formed on the sacrificial layer 121<2>, a semiconductor layer 113<3> is formed on the sacrificial layer 123, and a mask layer 125 is formed on the sacrificial layer 123. The subsequent steps can be similar to the manufacturing steps of a semiconductor device including the transistor 11A.

[0332] As described above, the electric field of the conductive layer 119 reaches the semiconductor layer 113<1>, allowing the conductive layer 119 to function as the gate electrode of the transistor 11B. Therefore, by shortening the distance between the top surface of the conductive layer 119 and the bottom surface of the semiconductor layer 113<1> to, for example, approximately the same as the distance between the conductive layer 111, which will be formed in a later step, and the top surface of the semiconductor layer 113<1>, the conductive layer 119 can function as the gate electrode of the transistor 11B. For example, by thinning the insulating layer 109 to approximately the same thickness as the insulating layer 105, which will be formed in a later step, the conductive layer 119 can function as the gate electrode of the transistor 11B. For example, by setting the thickness of the insulating layer 109 to be equal to or less than the thicknesses of the insulating layers 133a and 133b, which will be formed in a later step, the conductive layer 119 can function as the gate electrode of the transistor 11B.

[0333] 12C and 12D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device including the transistor 11C shown in FIGS. 7A and 7B , respectively. When manufacturing a semiconductor device including the transistor 11C, a sacrificial layer 121<0> is first formed on the insulating layer 101. The sacrificial layer 121<0> can be formed so as to be in contact with the top surface of the insulating layer 101.

[0334] Next, a semiconductor layer 113<1> is formed on the sacrificial layer 121<0>, a sacrificial layer 121<1> is formed on the semiconductor layer 113<1>, a semiconductor layer 113<2> is formed on the sacrificial layer 121<1>, a sacrificial layer 121<2> is formed on the semiconductor layer 113<2>, a semiconductor layer 113<3> is formed on the sacrificial layer 121<2>, a sacrificial layer 123 is formed on the semiconductor layer 113<3>, and a mask layer 125 is formed on the sacrificial layer 123.

[0335] As described above, when a semiconductor device including the transistor 11C is manufactured, the sacrificial layers 121 and the semiconductor layers 113 on the sacrificial layers 121 are alternately formed so that the number of sacrificial layers 121 is equal to the number of semiconductor layers 113. The subsequent steps can be similar to the manufacturing steps of the semiconductor device including the transistor 11A.

[0336] 11A to 11C and subsequent figures will be described below. These manufacturing steps can also be applied to manufacturing a semiconductor device including the transistor 11B and a semiconductor device including the transistor 11C.

[0337] 11A to 11C, the mask layer 125, the sacrificial layer 123b, the sacrificial layer 123a, the semiconductor layer 113<3>, the sacrificial layer 121<2>, the semiconductor layer 113<2>, the sacrificial layer 121<1>, and the semiconductor layer 113<1> are processed (FIGS. 13A, 13B, and 13C). Fig. 13A is a plan view, Fig. 13B is a cross-sectional view taken along dashed line A1-A2 in Fig. 13A, and Fig. 13C is a cross-sectional view taken along dashed line B1-B2 in Fig. 13A.

[0338] For example, a resist mask is formed by photolithography, and then the mask layer 125 is processed to match the pattern of the resist mask. This processing can be performed, for example, by etching, and is preferably performed by dry etching, which facilitates fine processing. Next, the resist mask is removed. Then, the sacrificial layer 123b, the sacrificial layer 123a, the semiconductor layer 113<3>, the sacrificial layer 121<2>, the semiconductor layer 113<2>, the sacrificial layer 121<1>, and the semiconductor layer 113<1> are processed to match the pattern of the mask layer 125.

[0339] After processing the sacrificial layer 123b, the sacrificial layer 123a, the semiconductor layer 113<3>, the sacrificial layer 121<2>, the semiconductor layer 113<2>, the sacrificial layer 121<1>, and the semiconductor layer 113<1>, at least one of the plasma treatment, the microwave treatment, and the heat treatment described above may be performed in an atmosphere containing oxygen. This allows oxygen to be supplied to the semiconductor layer 113, so that the semiconductor layer 113 can be subjected to oxygen addition treatment.

[0340] 13A, 13B, and 13C, it is preferable to form a dummy pattern so as to surround at least a portion of the region where a transistor is to be fabricated. This makes it easier to detect the end point of a planarization process such as a CMP process performed in a later step than when a dummy pattern is not formed. In FIGS. 13A to 13C, the semiconductor layer 113 and the mask layer 125 included in the dummy pattern are referred to as a semiconductor layer 113D and a mask layer 125D, respectively. This also applies to subsequent drawings showing examples of a method for fabricating a semiconductor device.

[0341] Next, the semiconductor layer 114 is formed so as to cover the semiconductor layer 113<1>, the sacrificial layer 121<1>, the semiconductor layer 113<2>, the sacrificial layer 121<2>, the semiconductor layer 113<3>, the sacrificial layer 123a, the sacrificial layer 123b, and the mask layer 125 (FIGS. 14A, 14B, and 14C). Fig. 14A is a plan view, Fig. 14B is a cross-sectional view taken along dashed line A1-A2 in Fig. 14A, and Fig. 14C is a cross-sectional view taken along dashed line B1-B2 in Fig. 14A.

[0342] It is preferable to use the same material for the semiconductor layer 114 as that for the semiconductor layers 113<1> to 113<3>, because the semiconductor layer 114 can be easily adhered to the semiconductor layers 113<1> to 113<3>. In particular, it is preferable to use the same material for the semiconductor layer 114 as that for the semiconductor layer 113<2>, because the semiconductor layer 114 can be easily adhered to the semiconductor layer 113<2> and the semiconductor layer 113<2> can be prevented from falling when the sacrificial layer 121 is removed in a later step. It is also preferable to use the same material for the semiconductor layer 114 as that for the semiconductor layer 113<3>, because the semiconductor layer 114 can be easily adhered to the semiconductor layer 113<3> and the semiconductor layer 113<3>, the sacrificial layer 123, and the mask layer 125 can be prevented from falling when the sacrificial layer 121 is removed in a later step. For example, when indium gallium zinc oxide is used for the semiconductor layers 113<1> to 113<3>, it is preferable to use indium gallium zinc oxide also for the semiconductor layer 114.

[0343] Fig. 15 is an enlarged view of the configuration shown in Fig. 14B and Fig. 14C. Note that dummy patterns are not shown in Fig. 15.

[0344] 15 , the semiconductor layer 114 is formed to have a region in contact with the side surface 141 a<1> of the semiconductor layer 113<1>, a region in contact with the side surface 141 a<2> of the semiconductor layer 113<2>, a region in contact with the side surface 141 a<3> of the semiconductor layer 113<3>, a region in contact with the side surface 141 b<1> opposite the side surface 141 a<1>, a region in contact with the side surface 141 b<2> opposite the side surface 141 a<2>, and a region in contact with the side surface 141 b<3> opposite the side surface 141 a<3>. The semiconductor layer 114 is also formed to have a region located on the semiconductor layer 113<3>, specifically, a region located on the mask layer 125. In addition, the semiconductor layer 114 can be formed to have a region in contact with the side surface 145a<1> of the sacrificial layer 121a<1>, a region in contact with the side surface 145a<2> of the sacrificial layer 121a<2>, a region in contact with the side surface 147a of the sacrificial layer 123, a region in contact with the side surface 148a of the mask layer 125, a region in contact with the side surface 145b<1> opposite the side surface 145a<1>, a region in contact with the side surface 145b<2> opposite the side surface 145a<2>, a region in contact with the side surface 147b opposite the side surface 147a, and a region in contact with the side surface 148b opposite the side surface 148a.

[0345] Here, when the semiconductor layer 114 is formed by a method with high coverage, the semiconductor layer 114 and the semiconductor layer 113 are easily brought into contact with each other. This is preferable because the semiconductor layer 114 can be easily brought into close contact with the semiconductor layer 113. The semiconductor layer 114 is preferably formed by, for example, an ALD method.

[0346] Here, for example, a semiconductor layer containing silicon is difficult to form using an ALD method. For these reasons, it is preferable to use a metal oxide layer that can be formed using an ALD method as the semiconductor layer 114. As described above, it is preferable to use the same material as the semiconductor layer 114 for the semiconductor layer 113. For these reasons, it is preferable to use metal oxide layers as the semiconductor layers 113 and 114. Note that if the semiconductor layers 113 and 114 can be formed using an ALD method, metal oxide layers do not necessarily have to be used. Furthermore, the semiconductor layer 114 may be formed using, for example, a sputtering method or a CVD method. In this case, the semiconductor layers 113 and 114 can be formed using, for example, silicon.

[0347] The semiconductor layer 114 may have a stacked structure of two or more layers. For example, when the semiconductor layer 114a and the semiconductor layer 114b to be formed in a later step have the structure shown in FIG. 8A , the semiconductor layer 114 can have a stacked structure of a first layer that will become the semiconductor layer 114a1 and the semiconductor layer 114b1 in a later step, and a second layer that will become the semiconductor layer 114a2 and the semiconductor layer 114b2 in a later step. In this case, the first layer can be made of the same material as the semiconductor layer 113, and the second layer can be made of a different material than the semiconductor layer 113. Note that when the semiconductor layer 114 has a stacked structure of three or more layers, the innermost layer (the layer closest to the semiconductor layer 113) can be made of the same material as the semiconductor layer 113, and the outer layer (e.g., the layer opposite the semiconductor layer 113<2> and the semiconductor layer 113<3>) can be made of a different material than the semiconductor layer 113.

[0348] When the semiconductor layer 114 has a stacked structure of two or more layers, different deposition methods can be used for each layer. For example, when the semiconductor layer 114a and the semiconductor layer 114b to be formed in a later step have the structure shown in FIG. 8A , the first layer of the semiconductor layer 114 can be deposited by a method that provides high coverage, and the second layer can be deposited by a method that provides a high deposition rate. For example, the first layer can be deposited by ALD, and the second layer can be deposited by sputtering. This allows the semiconductor device of one embodiment of the present invention to be manufactured with higher productivity than when the first layer is deposited by sputtering, for example.

[0349] 8A , the first layer of the semiconductor layer 114 may be formed by sputtering, and the second layer may be formed by ALD. For example, after forming the first layer of the CAAC structure by sputtering, the second layer having lower crystallinity than the CAAC structure may be formed by ALD. This is expected to allow the atomic layer of the second layer to fill or repair gaps in the atomic-level crystal portions of the CAAC structure of the first layer.

[0350] When the second layer of the semiconductor layer 114 is formed by the ALD method, it is preferable to perform heat treatment (for example, at 100° C. or higher and 500° C. or lower, preferably 200° C. or higher and 450° C. or lower, more preferably 300° C. or higher and 400° C. or lower) after the formation of the second layer. The heat treatment is expected to repair gaps in the atomic-level crystal portions of the CAAC structure of the first layer of the semiconductor layer 114 by the second layer (in other words, each crystal molecule formed by the ALD method).

[0351] Even if the first layer has minute gaps or spaces, the minute gaps or spaces in the first layer can be filled by forming a second layer on the first layer or by forming the second layer and then performing heat treatment. Thus, by forming a metal oxide layer with a CAAC structure as the first layer and forming a metal oxide layer with a microcrystalline structure or an amorphous structure as the second layer, a dense semiconductor layer 114 with an increased crystallinity can be formed. When the dense semiconductor layer 114 with an increased crystallinity is used in the channel formation region of a transistor, it is expected that an increase in the electrical resistance of the semiconductor layer 114 can be suppressed or the initial characteristics (particularly, on-state current) of the transistor can be improved, thereby enabling the manufacture of a transistor suitable for high-speed driving.

[0352] When the semiconductor layer 114 is formed by both the sputtering method and the ALD method, if the thickness of the layer formed by the ALD method is thin, the semiconductor layer 114 can be considered to have a single-layer structure, rather than a stacked structure of a layer formed by the sputtering method and a layer formed by the ALD method. For example, when the thickness of the layer formed by the ALD method is greater than 0 nm and less than or equal to 3 nm, preferably greater than 0 nm and less than or equal to 2 nm, and more preferably greater than 0 nm and less than or equal to 1 nm, the layer formed by the two film formation methods, the sputtering method and the ALD method, can be considered to have a single-layer structure. In such a case, for example, in a cross-sectional TEM image or a cross-sectional STEM image, the boundary between the layer formed by the sputtering method and the layer formed by the ALD method is not observed. On the other hand, when the thickness of the layer formed by the ALD method exceeds 3 nm, the semiconductor layer 114 may be considered to have a stacked structure, a multilayer structure, or a multiple structure of a layer formed by the sputtering method and a layer formed by the ALD method.

[0353] After the semiconductor layer 114 is formed, at least one of the plasma treatment, microwave treatment, and heat treatment may be performed in an oxygen-containing atmosphere. This allows oxygen to be supplied to the semiconductor layer 114, and oxygen addition treatment can be performed on the semiconductor layer 114. In addition, oxygen addition treatment can be performed on the semiconductor layer 113 in some cases.

[0354] In FIG. 15 , the thickness of the sacrificial layer 123a is indicated as thickness T123a, and the thickness of the sacrificial layer 123b is indicated as thickness T123b. As described above, thickness T123a is preferably equal to or less than thickness T123b. In a later step, the semiconductor layer 114 is planarized and then processed to form the semiconductor layers 114a and 114b shown in FIGS. 2A to 2C. Here, the planarization is performed, for example, by CMP, with the sacrificial layer 123a as the end point. By using the sacrificial layer 123a as the end point, the planarization of the upper surface of the semiconductor layer 113<3> can be suppressed compared to when the semiconductor layer 113<3> is used as the end point. This suppresses the thickness of the semiconductor layer 113<3> from becoming thin. Furthermore, the semiconductor layer 113<3> can be prevented from disappearing.

[0355] Here, if the thickness T123a is large, the sacrificial layer 123a may remain even after the planarization process is completed. If the remaining sacrificial layer 123a is thick, the insulating layers 133a and 133b also become thick. As a result, when an opening for providing a conductive layer functioning as a plug is provided in one or both of the insulating layers 133a and 133b, as shown in FIGS. 10A and 10B, it may be difficult to form the opening. As a result, for example, the conductive layer functioning as a source electrode, drain electrode, or gate electrode of a transistor manufactured by this manufacturing method example may not be electrically connected to the conductive layer functioning as a plug.

[0356] From the above, it is preferable that the thickness T123a is set so that the sacrificial layer 123a does not remain after the planarization treatment that ends at the sacrificial layer 123a, or the film thickness of the remaining sacrificial layer 123a is as thin as possible, and the planarization treatment is not performed on the semiconductor layer 113<3>. The thickness T123a is, for example, preferably 1 nm to 150 nm, more preferably 5 nm to 100 nm, more preferably 7 nm to 70 nm, more preferably 8 nm to 50 nm, more preferably 10 nm to 30 nm, and even more preferably 10 nm to 20 nm.

[0357] Subsequently, a conductive layer 115 is formed on the semiconductor layer 114 (FIGS. 16A, 16B, and 16C). Fig. 16A is a plan view, Fig. 16B is a cross-sectional view taken along dashed line A1-A2 in Fig. 16A, and Fig. 16C is a cross-sectional view taken along dashed line B1-B2 in Fig. 16A.

[0358] The conductive layer 115 can be formed by, for example, a CVD method, an ALD method, a sputtering method, or the like. The conductive layer 115 can be formed using, for example, titanium nitride, tungsten, ITO, or ITSO. The conductive layer 115 may have a stacked structure of two or more layers. For example, when the conductive layer 115a and the conductive layer 115b formed in a later step have the structure shown in FIG. 8A , the conductive layer 115 can have a stacked structure of a first layer that will become the conductive layer 115a1 and the conductive layer 115b1 in a later step, and a second layer that will become the conductive layer 115a2 and the conductive layer 115b2 in a later step. In this case, for example, ITO or ITSO can be used for the first layer, and titanium nitride or tungsten can be used for the second layer. Alternatively, the conductive layer 115 may have a three-layer stacked structure of a first layer, a second layer on the first layer, and a third layer on the second layer. In this case, for example, ITO or ITSO can be used for the first layer, titanium nitride can be used for the second layer, and tungsten can be used for the third layer. When the conductive layer 115 has the above three-layer structure, the first layer can be a layer that becomes the conductive layer 115a1 and the conductive layer 115b1 in a later step, and the second layer and the third layer can be a layer that becomes the conductive layer 115a2 and the conductive layer 115b2 in a later step.

[0359] When the conductive layer 115 has a stacked structure of two or more layers, different deposition methods can be used for each layer. Specifically, when the conductive layers 115a and 115b to be formed in a later step have the structure shown in FIG. 8A , the layers that will become the conductive layers 115a1 and 115b1 in a later step can be formed by, for example, a sputtering method. Furthermore, the layers that will become the conductive layers 115a2 and 115b2 in a later step can be formed by, for example, a CVD method. Furthermore, when the layers that will become the conductive layers 115a2 and 115b2 in a later step have a stacked structure of a first layer using titanium nitride and a second layer using tungsten on the first layer, the first layer can be formed by a CVD method, and the second layer can be formed by a sputtering method.

[0360] Subsequently, an insulating layer 131 is formed on the conductive layer 115, and an insulating layer 133 is formed on the insulating layer 131 (FIGS. 16A, 16B, and 16C). The insulating layer 131 and the insulating layer 133 can be formed by, for example, a CVD method, an ALD method, a sputtering method, an MBE method, or a PLD method. For example, silicon nitride can be used for the insulating layer 131, and silicon oxide can be used for the insulating layer 133.

[0361] Next, planarization treatment is performed on the insulating layer 133, the insulating layer 131, the conductive layer 115, the semiconductor layer 114, the mask layer 125, the sacrificial layer 123b, and the sacrificial layer 123a (FIGS. 17A, 17B, and 17C). Fig. 17A is a plan view, Fig. 17B is a cross-sectional view taken along dashed line A1-A2 in Fig. 17A, and Fig. 17C is a cross-sectional view taken along dashed line B1-B2 in Fig. 17A.

[0362] The planarization treatment for the insulating layer 133, the planarization treatment for the insulating layer 131, the planarization treatment for the conductive layer 115, the planarization treatment for the semiconductor layer 114, the planarization treatment for the mask layer 125, and the planarization treatment for the sacrificial layer 123 can be performed in the same step. At least some of the planarization treatment for the insulating layer 133, the planarization treatment for the insulating layer 131, the planarization treatment for the conductive layer 115, the planarization treatment for the semiconductor layer 114, the planarization treatment for the mask layer 125, and the planarization treatment for the sacrificial layer 123 can be performed in parallel in at least some periods.

[0363] The planarization treatment can be performed by, for example, a CMP method until the top surface of the semiconductor layer 113<3> is exposed.

[0364] By the above-described planarization treatment, regions of the insulating layer 133, the insulating layer 131, the conductive layer 115, and the semiconductor layer 114 that overlap with the semiconductor layer 113 can be removed.

[0365] The planarization treatment for the insulating layer 133, the insulating layer 131, the conductive layer 115, the semiconductor layer 114, the mask layer 125, the sacrificial layer 123b, and the sacrificial layer 123a is performed, for example, by CMP, with the sacrificial layer 123a as the end point. By using the sacrificial layer 123a as the end point, the planarization treatment for the upper surface of the semiconductor layer 113<3> can be suppressed compared to when the semiconductor layer 113<3> is used as the end point. This can suppress the thickness of the semiconductor layer 113<3> from becoming thin. Furthermore, the semiconductor layer 113<3> can be prevented from disappearing.

[0366] As described above, the semiconductor device of one embodiment of the present invention can be manufactured with a high yield. On the other hand, if the sacrificial layer 123a is thick, the sacrificial layer 123a may remain even after the planarization treatment is completed. As described above, the sacrificial layer 123a preferably has a thickness such that it does not remain after the planarization treatment that ends at the sacrificial layer 123a and that the planarization treatment is not performed on the semiconductor layer 113<3>. Note that, as shown in FIGS. 2D and 2E, for example, the sacrificial layer 123a may remain partially. Even in this case, it is preferable that the remaining sacrificial layer 123a has a thickness as thin as possible.

[0367] Furthermore, by forming a dummy pattern so as to surround at least a part of the region where a transistor is to be formed, the area of ​​the sacrificial layer 123a in a plan view can be increased, for example, compared to when no dummy pattern is formed. This makes it easier to detect the end point of the planarization process. Therefore, the semiconductor device of one embodiment of the present invention can be manufactured by a method with high yield.

[0368] As described above, it is preferable to use a material different from that of the insulating layer 133 for the sacrificial layer 123b. This makes it possible to easily detect the end point, for example, when the sacrificial layer 123a is used as the end point in the planarization process. Note that the sacrificial layer 123a can be made of the same material as that used for the insulating layer 133. For example, when silicon oxide is used for the insulating layer 133 as described above, silicon oxide can be used for the sacrificial layer 123a, and silicon nitride can be used for the sacrificial layer 123b.

[0369] Next, the insulating layer 133, the insulating layer 131, the conductive layer 115, and the semiconductor layer 114 are processed (FIGS. 18A, 18B, and 18C). FIG. 18A is a plan view, FIG. 18B is a cross-sectional view taken along dashed line A1-A2 in FIG. 18A, and FIG. 18C is a cross-sectional view taken along dashed line B1-B2 in FIG. 18A.

[0370] For example, after forming a resist mask by photolithography, the insulating layer 133, the insulating layer 131, the conductive layer 115, and the semiconductor layer 114 are processed according to the pattern of the resist mask. This processing can be performed by, for example, an etching method, and is preferably performed by a dry etching method, which facilitates fine processing. Subsequently, the resist mask is removed. As described above, the insulating layer 133, the insulating layer 131, the conductive layer 115, and the semiconductor layer 114 can be processed using the same mask pattern. Processing the insulating layer 133, the insulating layer 131, the conductive layer 115, and the semiconductor layer 114 using the same mask pattern is preferable because it reduces the number of masks required to manufacture a semiconductor device compared to processing the insulating layer 133, the insulating layer 131, the conductive layer 115, and the semiconductor layer 114 using different mask patterns.

[0371] By processing the insulating layer 133, the insulating layer 131, the conductive layer 115, and the semiconductor layer 114, insulating layers 133a, 131a, the conductive layer 115a, and the semiconductor layer 114a are formed, and insulating layers 133b, 131b, the conductive layer 115b, and the semiconductor layer 114b are formed, which face the insulating layer 133a, the insulating layer 131a, the conductive layer 115a, and the semiconductor layer 114a across the semiconductor layer 113 in a plan view. By processing the conductive layer 115, conductive layer 115a and conductive layer 115b are formed, which face the conductive layer 115a across the semiconductor layer 113<2> and the semiconductor layer 113<3> in a cross-sectional view in the YZ plane. The semiconductor layer 114 is processed to form a semiconductor layer 114a and a semiconductor layer 114b that faces the semiconductor layer 114a with the semiconductor layers 113<1> to 113<3> sandwiched therebetween in a cross section in the YZ plane.

[0372] The semiconductor layer 114a is formed to have regions in contact with the side surfaces 141a<1> to 141a<3> shown in Fig. 3B, for example. The semiconductor layer 114b is formed to have regions in contact with the side surfaces 141b<1> to 141b<3> shown in Fig. 3B, for example.

[0373] The conductive layer 115a and the conductive layer 115b are formed outside the semiconductor layer 114a (e.g., on the side opposite the semiconductor layer 113<2> and the semiconductor layer 113<3>) and outside the semiconductor layer 114b (e.g., on the side opposite the semiconductor layer 113<2> and the semiconductor layer 113<3>) so as to have regions in contact with the semiconductor layer 114a and the semiconductor layer 114b, respectively. At least a part of the conductive layer 115a functions as one of the source electrode and the drain electrode of the transistor manufactured by this manufacturing method example. At least a part of the conductive layer 115b functions as the other of the source electrode and the drain electrode of the transistor manufactured by this manufacturing method example.

[0374] The insulating layers 131a and 131b are formed over the conductive layers 115a and 115b, respectively. The insulating layers 133a and 133b are formed over the insulating layers 131a and 131b, respectively.

[0375] The insulating layer 133, the insulating layer 131, the conductive layer 115, and the semiconductor layer 114 are processed to expose part of the side surface of the sacrificial layer 121. Specifically, of the side surfaces of the sacrificial layer 121<1> and the sacrificial layer 121<2>, the side surfaces that are not covered with the semiconductor layer 114a and the semiconductor layer 114b are exposed.

[0376] Next, the sacrificial layers 121<1> and 121<2> are removed. This forms a space 122<1> in the region surrounded by the semiconductor layers 113<1>, 113<2>, 114a, and 114b. Furthermore, a space 122<2> is formed in the region surrounded by the semiconductor layers 113<2>, 113<3>, 114a, and 114b (FIGS. 19A and 19B). For a plan view, see FIG. 18A. FIG. 19A is a cross-sectional view taken along dashed line A1-A2 in FIG. 18A, and FIG. 19B is a cross-sectional view taken along dashed line B1-B2 in FIG. 18A.

[0377] The sacrificial layers 121<1> and 121<2> can be removed by, for example, etching, and are preferably removed by wet etching. As described above, when the semiconductor layers 113<2> and 113<3> are made of the same material as the semiconductor layers 114a and 114b, the semiconductor layers 114a and 114b are easily brought into close contact with the semiconductor layers 113<2> and 113<3>. This is preferable because it can prevent the semiconductor layers 113<2> and 113<3> from falling.

[0378] Here, the sacrificial layer 121<1> and the sacrificial layer 121<2> are left in at least a portion of the region where the dummy pattern is formed (also referred to as the dummy region) that is not shown in FIGS. 19A and 19B . This prevents the semiconductor layer 113D and the mask layer 125D from falling off. For example, by adjusting the etching time, it is possible to remove all of the sacrificial layer 121 in the region surrounded by the semiconductor layer 113 and the semiconductor layer 114, while leaving only a portion of the sacrificial layer in the dummy region. Here, removing the sacrificial layer 121 can be rephrased as processing the sacrificial layer 121.

[0379] After the sacrificial layer 121 is removed, at least one of the plasma treatment, microwave treatment, and heat treatment may be performed in an oxygen-containing atmosphere. This allows oxygen to be supplied to the semiconductor layer 113 and the semiconductor layer 114, thereby enabling oxygen-adding treatment to be performed on the semiconductor layer 113 and the semiconductor layer 114. By performing the above treatment after the sacrificial layer 121 is removed, oxygen may be more efficiently supplied to the semiconductor layer 113<2>, both of whose upper and lower surfaces are sandwiched between other semiconductor layers 113, compared to when the above treatment is performed before the sacrificial layer 121 is removed. On the other hand, by performing the above treatment before the sacrificial layer 121 is removed, oxidation of the conductive layer 115a and the conductive layer 115b may be suppressed.

[0380] Next, an insulating layer 105 is formed to cover the semiconductor layer 113<1>, the semiconductor layer 113<2>, the semiconductor layer 113<3>, and the semiconductor layer 113D ( FIGS. 19C and 19D ). For a plan view, refer to FIG. 18A . FIG. 19C is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 18A , and FIG. 19D is a cross-sectional view taken along dashed dotted line B1-B2 in FIG. 18A . At least a portion of the insulating layer 105 functions as a gate insulating layer of the transistor manufactured by this manufacturing method example.

[0381] The insulating layer 105 can be formed to cover the semiconductor layer 114a, the semiconductor layer 114b, the conductive layer 115a, the conductive layer 115b, the insulating layer 131a, the insulating layer 131b, the insulating layer 133a, and the insulating layer 133b in addition to the semiconductor layer 113. The insulating layer 105 can be formed to cover at least the top surface of the semiconductor layer 113<1>, the bottom surface of the semiconductor layer 113<2>, the top surface of the semiconductor layer 113<2>, the bottom surface of the semiconductor layer 113<3>, the top surface of the semiconductor layer 113<3>, and side surfaces of the semiconductor layers 114a and 114b that are not in contact with any of the semiconductor layer 113, the conductive layer 115a, and the conductive layer 115b.

[0382] The insulating layer 105 is preferably formed by a method that provides high coverage. In particular, forming the insulating layer 105 by an ALD method is preferable because the semiconductor layer 113<1>, the semiconductor layer 113<2>, the semiconductor layer 113<3>, and the semiconductor layer 113D can be covered with good coverage. For example, when the insulating layer 105 is formed by an ALD method, the insulating layer 105 can cover the lower surfaces of the semiconductor layers 113<2> and 113<3> with good coverage.

[0383] Here, the insulating layer 105 can be formed to have a region containing excess oxygen. In this case, by performing heat treatment after the insulating layer 105 is formed, excess oxygen can be supplied to the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b. As a result, oxygen addition treatment can be performed on the semiconductor layer 113, the semiconductor layer 114a, and the semiconductor layer 114b.

[0384] Next, a conductive layer 111 is formed to cover the insulating layer 105 (FIGS. 20A, 20B, and 20C). Fig. 20A is a plan view, Fig. 20B is a cross-sectional view taken along dashed line A1-A2 in Fig. 20A, and Fig. 20C is a cross-sectional view taken along dashed line B1-B2 in Fig. 20A.

[0385] The conductive layer 111 is preferably formed by a method that provides high coverage, such as an ALD method. This allows the conductive layer 111 to be formed with good coverage in a region surrounded by the semiconductor layer 113<1>, the semiconductor layer 113<2>, the semiconductor layer 114a, and the semiconductor layer 114b. The conductive layer 111 can also be formed with good coverage in a region surrounded by the semiconductor layer 113<2>, the semiconductor layer 113<3>, the semiconductor layer 114a, and the semiconductor layer 114b. For example, titanium nitride can be used as the conductive layer 111.

[0386] Next, the conductive layer 111 is processed (FIGS. 21A, 21B, and 21C). FIG. 21A is a plan view, FIG. 21B is a cross-sectional view taken along dashed line A1-A2 in FIG. 21A, and FIG. 21C is a cross-sectional view taken along dashed line B1-B2 in FIG. 21A.

[0387] For example, a resist mask is formed by photolithography, and then the conductive layer 115 and the insulating layer 105 are processed according to the pattern of the resist mask. This processing can be performed by, for example, an etching method, and is preferably performed by a dry etching method, which facilitates microfabrication. Subsequently, the resist mask is removed. The conductive layer 115 and the insulating layer 105 can be processed using the same mask pattern. Note that the insulating layer 105 does not necessarily need to be processed.

[0388] The conductive layer 111 is formed so as to cover the top surface of the semiconductor layer 113<1> and surround the top, bottom, and side surfaces of the semiconductor layer 113<2> and the semiconductor layer 113<3> in a predetermined cross-sectional view, for example, a cross-sectional view in the XZ plane. The conductive layer 111 is also formed so as not to overlap with the conductive layer 115a and the conductive layer 115b. This prevents parasitic capacitance from being formed between the conductive layer 111 and the conductive layer 115a and between the conductive layer 111 and the conductive layer 115b. While FIG. 21C shows an example in which the region of the conductive layer 111 located on the semiconductor layer 113<3> does not overlap with the semiconductor layer 114a and the semiconductor layer 114b, a portion of this region may overlap with the semiconductor layer 114a and the semiconductor layer 114b.

[0389] In this manner, the conductive layer 111 can be formed, at least a part of which functions as a gate electrode of a transistor manufactured by this example manufacturing method.

[0390] Next, an insulating layer 135 is formed on the insulating layer 101, the conductive layer 111, the semiconductor layer 113<3>, the semiconductor layer 114a, the semiconductor layer 114b, the conductive layer 115a, the conductive layer 115b, the insulating layer 131a, the insulating layer 131b, the insulating layer 133a, the insulating layer 133b, and the semiconductor layer 113D, and an insulating layer 137 is formed on the insulating layer 135 ( FIGS. 21D and 21E ). For a plan view, refer to FIG. 21A . FIG. 21D is a cross-sectional view taken along dashed line A1-A2 in FIG. 21A , and FIG. 21E is a cross-sectional view taken along dashed line B1-B2 in FIG. 21A . The insulating layer 135 and the insulating layer 137 can be formed using, for example, a CVD method, an ALD method, a sputtering method, an MBE method, or a PLD method. For example, the insulating layer 135 can be made of silicon nitride, and the insulating layer 137 can be made of silicon oxide.

[0391] In this manner, for example, the semiconductor device shown in FIGS. 2A to 2C can be manufactured.

[0392] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0393] Embodiment 2 In this embodiment, a memory device including a transistor of one embodiment of the present invention will be described with reference to drawings.

[0394] This embodiment will describe a configuration example of a memory device using a memory cell including the transistor described in the above embodiment, in which a layer including a functional circuit having a function of amplifying and outputting a data potential held in the memory cell is provided between layers including stacked memory cells.

[0395] <Configuration Example 1 of Storage Device> FIG. 22 illustrates a block diagram of a storage device of one embodiment of the present invention.

[0396] 22 includes a driver circuit 621 and a memory array 620. The memory array 620 includes a plurality of memory cells 610 and a functional layer 650 including a plurality of functional circuits 651.

[0397] 22 shows an example in which a memory array 620 has a plurality of memory cells 610 arranged in a matrix of m rows and n columns (m and n are each independently an integer of 2 or more). Also, Fig. 22 shows an example in which a functional circuit 651 is provided for each wiring BL that functions as a bit line, and an example in which a functional layer 650 has a plurality of functional circuits 651 provided corresponding to the n wirings BL.

[0398] In FIG. 22 , the memory cell 610 in the first row and first column is indicated as memory cell 610[1,1], and the memory cell 610 in the mth row and nth column is indicated as memory cell 610[m,n]. Furthermore, in this embodiment, for example, an arbitrary row may be referred to as row i. Furthermore, an arbitrary column may be referred to as column j. Therefore, i is an integer of 1 or more and m or less, and j is an integer of 1 or more and n or less. Furthermore, in this embodiment, for example, the memory cell 610 in the ith row and jth column is indicated as memory cell 610[i,j]. Furthermore, in this embodiment, for example, when "i+α" (α is a positive or negative integer) is used, "i+α" is not less than 1 and does not exceed m. Similarly, when "j+α" is used, "j+α" is not less than 1 and does not exceed n.

[0399] The memory array 620 also includes m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. For example, in this embodiment, the first wiring WL (first row) is referred to as wiring WL[1], and the mth wiring WL (mth row) is referred to as wiring WL[m]. Similarly, the first wiring PL (first row) is referred to as wiring PL[1], and the mth wiring PL (mth row) is referred to as wiring PL[m]. Similarly, the first wiring BL (first column) is referred to as wiring BL[1], and the nth wiring BL (nth column) is referred to as wiring BL[n].

[0400] The memory cells 610 in the i-th row are electrically connected to the wiring WL in the i-th row (wiring WL[i]) and the wiring PL in the i-th row (wiring PL[i]). The memory cells 610 in the j-th column are electrically connected to the wiring BL in the j-th column (wiring BL[j]).

[0401] The memory array 620 can be implemented using DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory). DOSRAM is a RAM having 1T (transistor) 1C (capacitor) type memory cells, and the access transistors are OS transistors. OS transistors have extremely low leakage current, i.e., current flowing between the source and drain in the off state. DOSRAM can retain charge corresponding to data stored in the capacitor for a long time by turning off (non-conducting) the access transistor. Therefore, DOSRAM can reduce the frequency of refresh operations compared to DRAMs configured with transistors having silicon in their channel formation regions (Si transistors). As a result, power consumption can be reduced. Furthermore, the high frequency characteristics of OS transistors enable high-speed reading and writing of data from and to a memory device. This allows for a memory device with high operating speed to be provided.

[0402] Furthermore, by using an OS transistor with low off-state current for a memory cell, stored data can be retained for a long time. That is, a refresh operation is not required or is performed very infrequently, which allows sufficient reduction in power consumption of the storage device. While a typical DRAM requires a refresh operation frequency of approximately once every 60 msec, the storage device of one embodiment of the present invention can perform a refresh operation frequency of approximately once every 10 sec, which is 10 or more times or 100 or more times higher. The storage device of one embodiment of the present invention can perform a refresh operation frequency of 1 sec to 100 sec, preferably 5 sec to 50 sec.

[0403] 22, a plurality of memory arrays 620[1] to 620[m] can be stacked. The memory arrays 620[1] to 620[m] included in the memory array 620 are arranged in a direction perpendicular to the surface of the substrate on which the driver circuit 621 is provided, thereby improving the memory density of the memory cells 610.

[0404] The wiring BL functions as a bit line for writing and reading data. The wiring WL functions as a word line for controlling the on / off (conducting state or non-conducting state) of an access transistor functioning as a switch. The wiring PL functions as a constant potential line connected to a capacitor.

[0405] The memory cells 610 included in each of the memory arrays 620[1] to 620[m] are connected to the functional circuit 651 via wirings BL. The wirings BL can be arranged perpendicular to the surface of the substrate on which the driver circuit 621 is provided. By arranging the wirings BL extending from the memory cells 610 included in the memory arrays 620[1] to 620[m] perpendicular to the surface of the substrate, the length of the wiring between the memory array 620 and the functional circuit 651 can be shortened. Therefore, the signal propagation distance between two circuits connected to the bit line can be shortened, and the resistance and parasitic capacitance of the bit line can be significantly reduced, thereby reducing power consumption and signal delay. Furthermore, the memory cells 610 can be operated even if the capacitance value of the memory cells 610 is reduced.

[0406] The functional circuit 651 has a function of amplifying a data potential held in the memory cell 610 and outputting the amplified data potential to a sense amplifier 646 included in the driver circuit 621 via a wiring GBL (not shown), which will be described later. This configuration allows a slight potential difference in the wiring BL to be amplified when reading data. The wiring GBL can be arranged perpendicular to the surface of the substrate on which the driver circuit 621 is provided, similar to the wiring BL. By arranging the wirings BL and GBL extending from the memory cells 610 included in the memory arrays 620[1] to 620[m] perpendicular to the surface of the substrate, the length of the wiring between the functional circuit 651 and the sense amplifier 646 can be shortened. Therefore, the signal propagation distance between two circuits connected to the wiring GBL can be shortened, and the resistance and parasitic capacitance of the wiring GBL can be significantly reduced, thereby reducing power consumption and signal delay.

[0407] The wiring BL is provided in contact with a semiconductor layer of a transistor included in the memory cell 610. Alternatively, the wiring BL is provided in contact with a region that functions as a source or a drain of the semiconductor layer of the transistor included in the memory cell 610. Alternatively, the wiring BL is provided in contact with a conductive layer that is provided in contact with a region that functions as a source or a drain of the semiconductor layer of the transistor included in the memory cell 610. In other words, the wiring BL can be said to be a wiring for electrically connecting one of the source and the drain of the transistor included in the memory cell 610 in each layer of the memory array 620 to the functional circuit 651 in the vertical direction.

[0408] The memory array 620 can be provided overlapping the drive circuit 621. By providing the drive circuit 621 and the memory array 620 overlapping each other, the signal propagation distance between the drive circuit 621 and the memory array 620 can be shortened. Therefore, the resistance and parasitic capacitance between the drive circuit 621 and the memory array 620 can be reduced, and power consumption and signal delay can be reduced. Furthermore, the storage device 600 can be made smaller.

[0409] The functional circuit 651 is configured with OS transistors similar to the transistors included in the memory cell 610 of the DOSRAM, and can be freely arranged on a circuit using Si transistors similar to the memory arrays 620[1] to 620[m], thereby facilitating integration. By configuring the functional circuit 651 to amplify signals, the sense amplifier 646, which is a subsequent circuit, can be miniaturized, for example. Therefore, the memory device 600 can be miniaturized.

[0410] The drive circuit 621 includes a PSW 622 (power switch), a PSW 623, and a peripheral circuit 631. The peripheral circuit 631 includes a peripheral circuit 641, a control circuit 632, and a voltage generation circuit 633.

[0411] In the storage device 600, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0412] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 632.

[0413] The control circuit 632 is a logic circuit having the function of controlling the overall operation of the memory device 600. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 600. Alternatively, the control circuit 632 generates a control signal for the peripheral circuit 641 so that this operation mode is executed.

[0414] The voltage generating circuit 633 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 633. For example, when an H-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generating circuit 633, and the voltage generating circuit 633 generates a negative voltage.

[0415] The peripheral circuit 641 is a circuit for writing and reading data to and from the memory cells 610. The peripheral circuit 641 is also a circuit for outputting various signals for controlling the functional circuit 651. The peripheral circuit 641 includes a row decoder 642, a row driver 643, a column decoder 644, a column driver 645, a sense amplifier 646, an input circuit 647, and an output circuit 648.

[0416] The row decoder 642 and the column decoder 644 have the function of decoding the signal ADDR. The row decoder 642 is a circuit for specifying a row to be accessed, and the column decoder 644 is a circuit for specifying a column to be accessed. The row driver 643 has the function of selecting the wiring WL specified by the row decoder 642. The column driver 645 has the function of writing data to the memory cell 610, the function of reading data from the memory cell 610, and the function of holding the read data.

[0417] The input circuit 647 has a function of holding a signal WDA. The data held by the input circuit 647 is output to the column driver 645. The output data of the input circuit 647 is data (Din) to be written to the memory cell 610. The data (Dout) read from the memory cell 610 by the column driver 645 is output to the output circuit 648. The output circuit 648 has a function of holding Dout. In addition, the output circuit 648 has a function of outputting Dout to the outside of the memory device 600. The data output from the output circuit 648 is a signal RDA.

[0418] The PSW 622 has a function of controlling the supply of VDD to the peripheral circuit 631. The PSW 623 has a function of controlling the supply of VHM to the row driver 643. In this example, the high power supply potential of the memory device 600 is VDD, and the low power supply potential is GND (ground potential). VHM is a high power supply potential used to set the word line to a high level and is higher than VDD. The on / off of the PSW 622 is controlled by a signal PON1, and the on / off of the PSW 623 is controlled by a signal PON2. In FIG. 22, the number of power domains to which VDD is supplied in the peripheral circuit 631 is one, but multiple domains may also be used. In this case, a power switch can be provided for each power domain.

[0419] The memory array 620 having the memory arrays 620[1] to 620[m] (m is an integer of 2 or more) and the functional layer 650 can be provided by stacking multiple layers of memory arrays 620 on a driver circuit 621. By stacking multiple layers of memory arrays 620, the memory density of the memory cells 610 can be increased. Figure 23A shows a perspective view of a memory device 600 having a functional layer 650 and five layers (m = 5) of memory arrays 620[1] to 620[5] stacked on a driver circuit 621.

[0420] 23A, the memory array 620 provided in the first layer is shown as memory array 620[1], the memory array 620 provided in the second layer is shown as memory array 620[2], and the memory array 620 provided in the fifth layer is shown as memory array 620[5]. Also shown in FIG. 23A are wiring WL and wiring PL extending in the X direction, and wiring BL extending in the Z direction (the direction perpendicular to the substrate surface on which the driver circuit is provided). Note that, to make the drawing easier to understand, the wiring WL and wiring PL of each memory array 620 are partially omitted.

[0421] 23B is a schematic diagram illustrating a configuration example of a functional circuit 651 connected to the wiring BL illustrated in FIG. 23A and memory cells 610 included in memory arrays 620[1] to 620[5] connected to the wiring BL. Also, FIG. 23B illustrates a wiring GBL provided between the functional circuit 651 and the driver circuit 621. Note that a configuration in which multiple memory cells (memory cells 610) are electrically connected to one wiring BL is also referred to as a "memory string." Note that in the drawings, the wiring GBL may be illustrated with a thick line to improve visibility.

[0422] 23B illustrates an example of a circuit configuration of a memory cell 610 connected to a wiring BL. The memory cell 610 includes a transistor 611 and a capacitor 612. The transistor 611, the capacitor 612, and the wirings (such as a wiring BL and a wiring WL) may also be referred to as wirings BL[1] and wirings WL[1], for example. The memory cell 610, the transistor 611, and the capacitor 612 correspond to the memory cell 20, the transistor 11, and the capacitor 13, respectively, described in the above embodiment.

[0423] In the memory cell 610, one of the source and drain of a transistor 611 is connected to a wiring BL. The other of the source and drain of the transistor 611 is connected to one electrode of a capacitor 612. The other electrode of the capacitor 612 is connected to a wiring PL. A gate of the transistor 611 is connected to a wiring WL. The wiring PL is a wiring that applies a constant potential to maintain the potential of the capacitor 612.

[0424] The wiring GBL shown in Figure 23B is provided to electrically connect the driver circuit 621 and the functional layer 650. Figure 24A is a schematic diagram of a memory device 600 including a functional circuit 651 and memory arrays 620[1] to 620[m] as a structure 670. Note that although one wiring GBL is shown in Figure 24A, the wiring GBL can be provided as appropriate depending on the number of functional circuits 651 provided in the functional layer 650.

[0425] The wiring GBL is provided in contact with a semiconductor layer of a transistor included in the functional circuit 651. Alternatively, the wiring GBL is provided in contact with a region that functions as a source or a drain of a semiconductor layer of a transistor included in the functional circuit 651. Alternatively, the wiring GBL is provided in contact with a conductive layer that is provided in contact with a region that functions as a source or a drain of a semiconductor layer of a transistor included in the functional circuit 651. In other words, the wiring GBL can be said to be a wiring for electrically connecting one of the source and the drain of a transistor included in the functional circuit 651 in the functional layer 650 to the driver circuit 621 in the vertical direction.

[0426] 24B , the functional circuit 651 and the structure 670 including the memory arrays 620[1] to 620[m] may be stacked. The memory device 600A of one embodiment of the present invention can have structures 670[1] to 670[p] (p is an integer of 2 or greater) as shown in FIG. 24B . The wiring GBL is connected to the functional layer 650 included in the structure 670. The wiring GBL can be provided as appropriate depending on the number of functional circuits 651.

[0427] In one embodiment of the present invention, OS transistors are stacked, and wirings functioning as bit lines are arranged in a direction perpendicular to the surface of a substrate on which a driver circuit 621 is provided. By providing the wirings functioning as bit lines extending from the memory array 620 in a direction perpendicular to the surface of the substrate, the length of the wiring between the memory array 620 and the driver circuit 621 can be shortened. Therefore, the parasitic capacitance of the bit lines can be significantly reduced.

[0428] In one embodiment of the present invention, a functional layer 650 including a functional circuit 651 having a function of amplifying and outputting a data potential held in a memory cell 610 is provided in a layer where the memory array 620 is provided. With this structure, a slight potential difference of a wiring BL functioning as a bit line can be amplified when reading data, and a sense amplifier 646 included in a driver circuit 621 can be driven. Since circuits such as a sense amplifier can be miniaturized, the memory device 600 can be miniaturized. Furthermore, the memory device 600 can operate even if the capacitance of the capacitor 612 included in the memory cell 610 is reduced.

[0429] Although the above describes a memory device having memory arrays 620[1] to 620[m], the semiconductor device according to the present invention can also be used for a single-layer memory device having only memory array 620[1].

[0430] Although the above description shows an example in which the memory cell 610 has a 1T (transistor) 1C (capacitor) configuration, the present invention is not limited to this. Fig. 25A is a circuit diagram showing an example of the configuration of a 2T1C type memory cell 610. The memory cell 610 shown in Fig. 25A has a transistor 611a, a transistor 611b, and a capacitor 612a.

[0431] 25A, one of the source and drain of the transistor 611a is electrically connected to the gate of the transistor 611b and one electrode of the capacitor 612a. The other of the source and drain of the transistor 611a, the gate of the transistor 611a, one of the source and drain of the transistor 611b, the other of the source and drain of the transistor 611b, and the other electrode of the capacitor 612a are electrically connected to wirings.

[0432] 25B is a circuit diagram showing a configuration example of a 3T1C memory cell 610, which shows an example in which a transistor 611c is added to the memory cell 610 shown in FIG. 25A. In the memory cell 610 shown in FIG. 25B, one of the source and drain of the transistor 611b is electrically connected to one of the source and drain of the transistor 611c. The other of the source and drain of the transistor 611c and the gate of the transistor 611c are electrically connected to wirings.

[0433] 25C is a circuit diagram showing an example of the configuration of a 2T0C memory cell 610, in which the capacitor 612a is omitted from the memory cell 610 shown in FIG. 25A. If the parasitic capacitances of the transistors 611a and 611b are sufficiently large, the capacitor 612a can be omitted, as shown in FIG. 25C. In this case, the memory cell 610 is configured using only the transistors 611a and 611b.

[0434] 26 will be used to describe a configuration example of the functional circuit 651 described with reference to FIGS. 22 to 24 and a configuration example of the sense amplifier 646 included in the memory array 620 and the driver circuit 621. In FIG. 26, a driver circuit 621 connected to wirings GBL (wirings GBL_A and GBL_B) connected to functional circuits 651 (functional circuits 651A and 651B) connected to memory cells 610 (memory cells 610A and 610B) connected to different wirings BL (wirings BL_A and BL_B) is illustrated. As the driver circuit 621 illustrated in FIG. 26, in addition to the sense amplifier 646, a precharge circuit 671A, a precharge circuit 671B, a switch circuit 672A, a switch circuit 672B, and a write / read circuit 673 are illustrated.

[0435] Transistors 652a, 652b, 653a, 653b, 654a, 654b, 655a, and 655b are illustrated as the functional circuits 651A and 651B. The transistors 652a, 652b, 653a, 653b, 654a, 654b, 655a, and 655b illustrated in Figure 26 are OS transistors, similar to the transistor 611 included in the memory cell 610. The functional layer 650 including the functional circuit 651 can be stacked in the same manner as the memory arrays 620[1] to 620[m].

[0436] The wiring BL_A is connected to the gate of the transistor 652a, and the wiring BL_B is connected to the gate of the transistor 652b. The wiring GBL_A is connected to one of the sources and drains of the transistors 653a and 654a. The wiring GBL_B is connected to one of the sources and drains of the transistors 653b and 654b. The wirings GBL_A and GBL_B are provided in the vertical direction like the wirings BL_A and BL_B, and are connected to the transistors included in the driver circuit 621. As shown in FIG. 26 , the selection signal MUX, the control signal WE, and the control signal RE are applied to the gates of the transistors 653a, 653b, 654a, 654b, 655a, and 655b, respectively.

[0437] 26 are configured with Si transistors. Switches 683A to 683D that configure the switch circuits 672A and 672B can also be configured with Si transistors. One of the source and drain of each of the transistors 653a, 653b, 654a, and 654b is connected to the transistor or switch that configures the precharge circuit 671A, the precharge circuit 671B, the sense amplifier 646, and the switch circuit 672A.

[0438] The precharge circuit 671A includes n-channel transistors 681_1 to 681_3. The precharge circuit 671A is a circuit for precharging the wirings BL_A and BL_B to an intermediate potential VPC corresponding to a potential VDD / 2 between a high power supply potential (VDD) and a low power supply potential (VSS) in response to a precharge signal applied to a precharge line PCL1.

[0439] The precharge circuit 671B includes n-channel transistors 681_4 to 681_6. The precharge circuit 671B is a circuit for precharging the wirings GBL_A and GBL_B to an intermediate potential VPC corresponding to a potential VDD / 2 between VDD and VSS in response to a precharge signal supplied to a precharge line PCL2.

[0440] The sense amplifier 646 includes p-channel transistors 682_1 and 682_2 and n-channel transistors 682_3 and 682_4, which are connected to a wiring VHH or a wiring VLL. The wiring VHH or the wiring VLL has a function of supplying VDD or VSS. The transistors 682_1 to 682_4 are transistors that form an inverter loop. The potentials of the precharged wirings BL_A and BL_B change when the memory cell 610A and the memory cell 610B are selected, and the potentials of the wirings GBL_A and GBL_B are set to VDD or VSS in response to the change. The potentials of the wirings GBL_A and GBL_B can be output to the outside via the switches 683C and 683D and the write / read circuit 673. The wirings BL_A and BL_B, and the wirings GBL_A and GBL_B correspond to bit line pairs. The write / read circuit 673 controls the writing of data signals in response to the signal EN_data.

[0441] The switch circuit 672A is a circuit for controlling the conduction state between the sense amplifier 646 and the wirings GBL_A and GBL_B. The switch circuit 672A is switched on or off under the control of a switching signal CSEL1. When the switches 683A and 683B are n-channel transistors, the switching signal CSEL1 is turned on at a high level and turned off at a low level. The switch circuit 672B is a circuit for controlling the conduction state between the write / read circuit 673 and the bit line pair connected to the sense amplifier 646. The switch circuit 672B is switched on or off under the control of a switching signal CSEL2. The switches 683C and 683D can be configured in the same way as the switches 683A and 683B.

[0442] 26, the memory device 600 can be configured such that the memory cell 610, the functional circuit 651, and the sense amplifier 646 are connected via wirings BL and GBL that are provided in the vertical direction, which is the shortest distance. Although the number of functional layers 650 including transistors that configure the functional circuit 651 is increased, the load on the wirings BL is reduced, thereby shortening the write time and making it easier to read data.

[0443] 26 , each transistor included in the functional circuit 651A and the functional circuit 651B is controlled in response to control signals WE, RE, and a selection signal MUX. Each transistor can output the potential of the wiring BL to the driver circuit 621 via the wiring GBL in response to the control signal and the selection signal. The functional circuit 651A and the functional circuit 651B can function as a sense amplifier including OS transistors. This configuration allows a slight potential difference in the wiring BL to be amplified during reading, thereby driving the sense amplifier 646 using Si transistors.

[0444] <Configuration Example 2 of Storage Device> A configuration example of the storage device 600 will be described with reference to FIG.

[0445] The memory device 600 includes, for example, a driver circuit 621 which is a layer including the transistor 310, a functional layer 650 which is a layer including transistors 652, 653, 654, and 655 over the driver circuit 621, and memory arrays 620[1] to 620[m] over the functional layer 650. Note that the transistor 652 corresponds to the transistors 652a and 652b. The transistor 653 corresponds to the transistors 653a and 653b. The transistor 654 corresponds to the transistors 654a and 654b. The transistor 655 corresponds to the transistors 655a and 655b.

[0446] 27 illustrates a transistor 310 included in the driver circuit 621. The transistor 310 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate electrode, an insulating layer 315 functioning as a gate insulating layer, a semiconductor region 313 including part of the substrate 311, a low-resistance region 314a functioning as one of a source region and a drain region, and a low-resistance region 314b functioning as the other of the source region and the drain region. The transistor 310 may be a p-channel transistor or an n-channel transistor. A single crystal silicon substrate, for example, can be used as the substrate 311.

[0447] Here, in the transistor 310 shown in FIG. 27 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 310 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulating layer that is in contact with the top of the convex portion and functions as a mask for forming the convex portion may be provided. Here, the case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0448] Note that the transistor 310 illustrated in FIG. 27 is just an example, and the structure is not limited thereto, and an appropriate transistor can be used depending on the circuit configuration or driving method.

[0449] Between each structure, a wiring layer provided with an interlayer insulating layer, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for conductive layers that function as plugs or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a portion of the conductive layer functions as the wiring, and cases where a portion of the conductive layer functions as the plug.

[0450] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer insulating layer over the transistor 310. A conductive layer 328 and the like are embedded in the insulating layer 320 and the insulating layer 322. A conductive layer 330 and the like are embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as contact plugs or wirings.

[0451] The insulating layer serving as an interlayer insulating layer may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 322 may be planarized by CMP treatment to improve the planarity.

[0452] 27 illustrates transistors 652, 653, and 655 included in the functional layer 650. In FIG. 27, the transistors 652, 653, and 655 have the same structure as the transistor 11A described in the above embodiment. Note that the transistors 652, 653, and 655 may have the same structure as any of the transistors 11B to 11E described in the above embodiment. The source electrodes and drain electrodes of the transistors 652, 653, and 655 are connected in series.

[0453] An insulating layer 208 is provided over the transistor 652, the transistor 653, and the transistor 655, and a conductive layer 207 is provided in an opening formed in the insulating layer 208. Furthermore, an insulating layer 210 is provided over the insulating layer 208, and a conductive layer 209 is provided in an opening formed in the insulating layer 210. Furthermore, an insulating layer 212 is provided over the insulating layer 210. A part of a conductive layer 240 provided in the memory array 620[1] is embedded in the opening formed in the insulating layer 212. Here, the conductive layer 240 is provided to extend in the Z direction and functions as a wiring BL.

[0454] The insulating layer 208 and the insulating layer 210 can be formed using an insulating layer applicable to the insulating layer 101 in the above embodiment. The insulating layer 212 can be formed using an insulating layer applicable to the insulating layer 135 in the above embodiment.

[0455] The bottom surface of the conductive layer 207 is in contact with the top surface of the conductive layer 111 of the transistor 652. The top surface of the conductive layer 207 is in contact with the bottom surface of the conductive layer 209. The top surface of the conductive layer 209 is in contact with the bottom surface of the conductive layer 240 provided in the memory array 620[1]. With this structure, the conductive layer 240 corresponding to the wiring BL can be electrically connected to the gate of the transistor 652.

[0456] Each of the memory arrays 620[1] to 620[m] includes a plurality of memory cells 610. As described above, the memory cell 610 includes a transistor 611 and a capacitor 612. FIG. 27 illustrates an example in which the transistor 611 and the capacitor 612 have the same structures as the transistor 11A and the capacitor 13A shown in FIG. 10A in the above embodiment, respectively. Note that the transistor 611 may have the same structure as any of the transistors 11B to 11E shown in the above embodiment. The capacitor 612 may have the same structure as the capacitor 13B shown in FIG. 10B in the above embodiment.

[0457] As shown in FIG. 27 , a conductive layer 240 is provided in contact with the conductive layer 115b of the transistor 611. As described above, the conductive layer 240 is provided extending in the Z direction and functions as a wiring BL. FIG. 27 shows an example in which the upper surface and side end portions of the conductive layer 115b have regions in contact with the conductive layer 240 extending in the Z direction. Since the conductive layer 240 directly contacts at least a portion of the upper surface and side end portions of the conductive layer 115b, there is no need to provide separate connection electrodes, and therefore the area occupied by the memory array 620 can be reduced. Furthermore, the integration density of the memory cells 610 can be improved, and the storage capacity of the storage device can be increased.

[0458] The conductive layer 240 of each memory cell 610 is electrically connected to the conductive layer 240 in the layer above and the conductive layer 240 in the layer below. The conductive layer 240 is shared between adjacent memory cells 610. Furthermore, in adjacent memory cells 610, the configuration on the right side and the configuration on the left side are arranged symmetrically with respect to the conductive layer 240.

[0459] In the memory array 620 described above, a plurality of memory arrays 620[1] to 620[m] can be stacked. The memory arrays 620[1] to 620[m] included in the memory array 620 can be arranged in the vertical direction of the substrate surface on which the driver circuit 621 is provided, thereby improving the memory density of the memory cells 610. Furthermore, the memory array 620 can be manufactured by repeatedly using the same manufacturing process in the vertical direction. The memory device 600 can reduce the manufacturing cost of the memory array 620.

[0460] <Configuration Example 3 of Memory Device> Figure 28 is a cross-sectional view showing a configuration example of a memory device 600, and shows an example in which the memory cell 610 shown in Figure 27 has the configuration shown in Figure 25A. Note that Figure 28 does not show the functional layer 650. Also, Figure 28 shows one memory cell 610 in one memory array 620, but memory arrays 620[1] to 620[m] can each include multiple memory cells 610. The following will mainly describe configurations that are different from Figure 27, and will omit descriptions of similar configurations as appropriate.

[0461] 28 includes a transistor 611a, a transistor 611b, and a capacitor 612a. Also, in FIG. 28, transistors 310a and 310b are illustrated as examples of transistors included in a driver circuit 621. The transistors 310a and 310b can have a structure similar to that of the transistor 310 illustrated in FIG.

[0462] 28 shows an example in which an insulating layer 350, an insulating layer 357, and an insulating layer 352 are stacked in this order as an interlayer insulating layer over an insulating layer 326. A conductive layer 328a electrically connected to the transistor 310a and a conductive layer 328b electrically connected to the transistor 310b are embedded in the insulating layer 320 and the insulating layer 322. A conductive layer 330a having a region in contact with the bottom surface of the conductive layer 328a and a conductive layer 330b having a region in contact with the bottom surface of the conductive layer 328b are embedded in the insulating layer 324 and the insulating layer 326. A conductive layer 356a having a region in contact with the bottom surface of the conductive layer 330a and a conductive layer 356b having a region in contact with the bottom surface of the conductive layer 330b are embedded in the insulating layer 350, the insulating layer 357, and the insulating layer 352. Note that the conductive layers 328a, 328b, 330a, 330b, 356a, and 356b function as contact plugs or wirings.

[0463] The memory arrays 620[1] to 620[m] include a conductive layer 240a and a conductive layer 240b. The conductive layer 240a and the conductive layer 240b extend in the Z direction. The conductive layer 240a has a region in contact with the upper surface of the conductive layer 356a. The conductive layer 240b has a region in contact with the upper surface of the conductive layer 356b.

[0464] As a result, the conductive layer 240a and the transistor 310a can be electrically connected. Also, the conductive layer 240b and the transistor 310b can be electrically connected. Figure 28 shows an example in which the low-resistance region 314a of the transistor 310a is electrically connected to the conductive layer 240a, and the low-resistance region 314a of the transistor 310b is electrically connected to the conductive layer 240b.

[0465] The transistors 611a and 611b can have a structure similar to that of any of the transistors 11A to 11E described in the above embodiments. The capacitor 612a can have a structure similar to that of the capacitor 13A shown in FIG. 10A or the capacitor 13B shown in FIG. 10B in the above embodiments. FIG. 28 illustrates an example in which the transistors 611a and 611b have a structure similar to that of the transistor 11A, and the capacitor 612a has a structure similar to that of the capacitor 13A.

[0466] The transistor 611a has a conductive layer 615a1 as one of a source electrode and a drain electrode and a conductive layer 615a2 as the other of the source electrode and drain electrode. The transistor 611b has a conductive layer 615b1 as one of a source electrode and a drain electrode and a conductive layer 615b2 as the other of the source electrode and drain electrode. The conductive layer 615a1 and the conductive layer 615b1 correspond to the conductive layer 115a included in the transistor 11A. The conductive layer 615a2 and the conductive layer 615b2 correspond to the conductive layer 115b included in the transistor 11A.

[0467] As shown in FIG. 28 , the conductive layer 240a is provided so as to have a region in contact with the conductive layer 615a2. The conductive layer 240b is also provided so as to have a region in contact with the conductive layer 615b2. FIG. 28 illustrates an example in which the upper surface and side edges of the conductive layer 615a2 have a region in contact with the conductive layer 240a extending in the Z direction. FIG. 28 also illustrates an example in which the upper surface and side edges of the conductive layer 615b2 have a region in contact with the conductive layer 240b extending in the Z direction. Since the conductive layer 240a is in direct contact with at least a portion of the upper surface and side edges of the conductive layer 615a2 and the conductive layer 240b is in direct contact with at least a portion of the upper surface and side edges of the conductive layer 615b2, there is no need to provide separate connection electrodes, thereby reducing the area occupied by the memory array 620. Furthermore, the integration density of the memory cells 610 is improved, thereby increasing the memory capacity of the memory device.

[0468] The conductive layer 240a of each memory cell 610 is electrically connected to the conductive layer 240a in the layer above and the conductive layer 240a in the layer below. The conductive layer 240a is shared between adjacent memory cells 610. Furthermore, in adjacent memory cells 610, the configuration on the right side and the configuration on the left side are arranged symmetrically with respect to the conductive layer 240a. The same applies to the conductive layer 240b.

[0469] <Configuration Example 3 of Memory Device> Figure 29 is a cross-sectional view showing a configuration example of a memory device 600, and shows an example in which a transistor 611c is added to the memory cell 610 shown in Figure 28. That is, Figure 29 shows an example in which the memory cell 610 has the configuration shown in Figure 25B. Below, configurations different from Figure 28 will be mainly described, and descriptions of similar configurations will be omitted as appropriate.

[0470] The transistor 611c can have a structure similar to that of any of the transistors 11A to 11E described in the above embodiment. In FIG. 29, the transistor 611c has a structure similar to that of the transistor 11A.

[0471] The transistor 611c includes a conductive layer 615b1 as one of a source electrode and a drain electrode, and a conductive layer 615c as the other of the source electrode and drain electrode. The conductive layer 615b1 corresponds to the conductive layer 115a included in the transistor 11A. The conductive layer 615c corresponds to the conductive layer 115b included in the transistor 11A.

[0472] As shown in Figure 29, the conductive layer 240b is provided so as to have a region in contact with the conductive layer 615c. Figure 29 shows an example in which the upper surface and side edges of the conductive layer 615c have regions in contact with the conductive layer 240b extending in the Z direction. Since the conductive layer 240b directly contacts at least a portion of the upper surface and side edges of the conductive layer 615c, there is no need to provide a separate connection electrode, and therefore the area occupied by the memory array 620 can be reduced. Furthermore, the integration density of the memory cells 610 can be improved, and the memory capacity of the memory device can be increased.

[0473] <Configuration Example of Memory Cell> A configuration example of a memory cell having a 2T1C type configuration will be described with reference to FIG.

[0474] 30 includes a transistor 310, a transistor 200 provided above the transistor 310, and a capacitor 400 provided above the transistor 310 and the transistor 200. In FIG. 30, the transistor 200 and the capacitor 400 have the same structures as the transistor 11A and the capacitor 13A shown in FIG. 10A in the above embodiment, respectively. Note that the transistor 200 may have the same structure as any of the transistors 11B to 11E shown in the above embodiment. The capacitor 400 may have the same structure as the capacitor 13B shown in FIG. 10B in the above embodiment.

[0475] The transistor 200 is a transistor that uses a metal oxide layer as a semiconductor layer. The transistor 200 has a low off-state current, and therefore, when used in a memory device, stored data can be retained for a long period of time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the memory device can be sufficiently reduced.

[0476] The memory device shown in FIG. 30 can be arranged in a matrix to form a memory cell array.

[0477] The above description of <Structure Example 2 of Memory Device> can be referred to for the structure of the transistor 310. Note that the transistor 310 illustrated in FIG. 30 is just an example and is not limited to the structure thereof. An appropriate transistor can be used depending on the circuit configuration or a driving method.

[0478] The capacitor 400 has a conductive layer 410 that functions as one of a pair of electrodes, a conductive layer 420 that functions as the other of the pair of electrodes, and an insulating layer 430 that functions as a dielectric layer.

[0479] The conductive layer 410 can be formed using, for example, the material that can be used for the conductive layer 153c in the above embodiment. The conductive layer 420 can be formed using, for example, the material that can be used for the conductive layer 157 in the above embodiment.

[0480] The conductive layer 412 can be formed, for example, at the same time as the conductive layer 410. Note that the conductive layer 412 functions as a plug or a wiring electrically connected to the capacitor 400, the transistor 200, or the transistor 310.

[0481] 30 shows the conductive layer 412 and the conductive layer 410 having a single-layer structure, the present invention is not limited to this structure and may have a stacked structure of two or more layers. For example, a conductive layer having a barrier property and a conductive layer having high adhesion to the conductive layer having high conductivity may be formed between the conductive layer having a barrier property and the conductive layer having high conductivity.

[0482] The insulating layer 430 can be an insulating layer that can be used as the insulating layer 156 in the above embodiment.

[0483] In the memory cell shown in FIG. 30 , a wiring 1001 is electrically connected to a low-resistance region 314a of the transistor 310. A wiring 1002 is electrically connected to a low-resistance region 314b of the transistor 310. A wiring 1003 is electrically connected to a conductive layer 115a of the transistor 200. A wiring 1004 is electrically connected to a conductive layer 111 of the transistor 200. A conductive layer 316 of the transistor 310 and a conductive layer 115b of the transistor 200 are electrically connected to a conductive layer 410 of the capacitor 400. A wiring 1005 is electrically connected to a conductive layer 420 of the capacitor 400.

[0484] Between each structure, a wiring layer may be provided, which includes an interlayer insulating layer, wiring, plugs, etc. Furthermore, a plurality of wiring layers may be provided depending on the design.

[0485] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer insulating layer over the transistor 310. A capacitor 400, or a conductive layer 328 and a conductive layer 330 electrically connected to the transistor 200 are embedded in the insulating layer 320, the insulating layer 322, the insulating layer 324, and the insulating layer 326. For these insulating layers and conductive layers, refer to the contents described above in <Structure Example 2 of Memory Device>.

[0486] A wiring layer may be provided on the insulating layer 326 and the conductive layer 330. For example, in Fig. 30, an insulating layer 350, an insulating layer 352, and an insulating layer 354 are stacked in this order. A conductive layer 356 is formed in the insulating layer 350, the insulating layer 352, and the insulating layer 354. The conductive layer 356 functions as a plug or a wiring.

[0487] 30 , an insulating layer 210, an insulating layer 212, and an insulating layer 216 are stacked in this order over the insulating layer 354 and the conductive layer 356. A conductive layer 213 is embedded in the insulating layer 210, the insulating layer 212, and the insulating layer 216. Note that the conductive layer 213 functions as a plug or wiring electrically connected to the capacitor 400 or the transistor 310.

[0488] A conductive layer 218 is embedded in the insulating layer 216. The conductive layer 218 is preferably provided so as to be in contact with part of the side surface and the top surface of the conductive layer 213. In other words, the conductive layer 218 is preferably provided so as to be in contact with a portion of the conductive layer 213 that is exposed from the insulating layer 212. An insulating layer 221 is provided over the insulating layer 216 and the conductive layer 218, and the transistor 200 is provided over the insulating layer 221.

[0489] Note that the conductive layer 218 functions as a plug or a wiring electrically connected to the capacitor 400, the transistor 200, or the transistor 310. Further, over the conductive layer 420 and the insulating layer 430, an insulating layer 450 is provided.

[0490] Openings reaching the conductive layer 218 are provided in the insulating layers 137, 135, and 221, and the conductive layer 241 is provided to have a region located inside the openings. Openings reaching the conductive layer 115a are provided in the insulating layers 137, 135, 133a, and 131a, and the conductive layer 245a is provided to have a region located inside the openings. Openings reaching the conductive layer 115b are provided in the insulating layers 137, 135, 133b, and 131b, and the conductive layer 245b is provided to have a region located inside the openings. Here, the conductive layers 241, 245a, and 245b can be formed in parallel.

[0491] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0492] Embodiment 3 In this embodiment, an example of a chip on which a memory device of one embodiment of the present invention is mounted will be described with reference to FIGS.

[0493] 31A and 31B, multiple circuits (systems) are implemented on a chip 1200. The technology for integrating multiple circuits (systems) on a single chip in this way is sometimes called a system on chip (SoC).

[0494] As shown in FIG. 31A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0495] Chip 1200 is provided with bumps (not shown), which are connected to a first surface of package substrate 1201 as shown in Fig. 31B. In addition, a plurality of bumps 1202 are provided on the back surface of the first surface of package substrate 1201, which are connected to motherboard 1203.

[0496] The motherboard 1203 may be provided with a storage device such as a DRAM 1221 or a flash memory 1222. For example, the DOSRAM described in the above embodiment can be used as the DRAM 1221. This allows the DRAM 1221 to have low power consumption, high speed, and large capacity.

[0497] The CPU 1211 preferably has multiple CPU cores. The GPU 1212 preferably has multiple GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The memory may be the DOSRAM described above. The GPU 1212 is suitable for parallel calculation of a large amount of data and can be used for image processing or multiply-and-accumulate operations. By providing the GPU 1212 with an image processing circuit or a multiply-and-accumulate circuit using the OS transistor described in the above embodiment, image processing or multiply-and-accumulate operations can be performed with low power consumption.

[0498] Furthermore, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed quickly.

[0499] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0500] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0501] The interface 1215 has an interface circuit with externally connected devices such as a display device, a speaker, a microphone, a camera, and a controller. Controllers include a mouse, a keyboard, a game controller, etc. As such an interface, a Universal Serial Bus (USB) or a High-Definition Multimedia Interface (HDMI (registered trademark)) can be used.

[0502] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network), and may also include a circuit for network security.

[0503] The above circuits (systems) can be formed in the same manufacturing process on the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0504] A package substrate 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided, can be called a GPU module 1204.

[0505] The GPU module 1204 includes the chip 1200 using SoC technology, allowing for a smaller size. Furthermore, due to its superior image processing capabilities, it is suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable (portable) game consoles. Furthermore, a multiply-and-accumulate circuit using the GPU 1212 can execute techniques such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs). Therefore, the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0506] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0507] In this embodiment, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)) that can use the semiconductor device described in the above embodiment will be described. The electronic components, electronic devices, mainframes, space equipment, and data centers that use the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0508] [Electronic Component] FIG. 32A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 32A has a semiconductor device 710 inside a mold 711. FIG. 32A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0509] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which a plurality of memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configu...

Claims

a first metal oxide layer, a second metal oxide layer, a third metal oxide layer, a fourth metal oxide layer, a first insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer; the second metal oxide layer is provided on the first metal oxide layer; the third metal oxide layer has a region in contact with a first side surface of the first metal oxide layer and a second side surface of the second metal oxide layer; the fourth metal oxide layer has a region in contact with a third side surface of the first metal oxide layer opposite to the first side surface, and a region in contact with a fourth side surface of the second metal oxide layer opposite to the second side surface, the first insulating layer has, in a region between the first metal oxide layer and the second metal oxide layer, a region in contact with an upper surface of the first metal oxide layer, a region in contact with a lower surface of the second metal oxide layer, a region in contact with a side surface of the third metal oxide layer, and a region in contact with a side surface of the fourth metal oxide layer; the first insulating layer has a region in contact with a fifth side surface of the first metal oxide layer, a region in contact with a sixth side surface opposite to the fifth side surface, a region in contact with a seventh side surface of the second metal oxide layer, and a region in contact with an eighth side surface opposite to the seventh side surface, the first conductive layer has a region located between the first metal oxide layer and the second metal oxide layer, and is provided so as to surround the second metal oxide layer with the first insulating layer interposed therebetween; the second conductive layer has a region in contact with a side surface of the third metal oxide layer opposite to the second metal oxide layer, A semiconductor device, wherein the third conductive layer has a region in contact with a side of the fourth metal oxide layer opposite to the second metal oxide layer. 　 In claim 1, a fifth metal oxide layer; the fifth metal oxide layer is provided on the second metal oxide layer; a ninth side surface of the fifth metal oxide layer has a region in contact with the third metal oxide layer; a tenth side surface of the fifth metal oxide layer opposite to the ninth side surface has a region in contact with the fourth metal oxide layer; an upper surface of the second metal oxide layer, a lower surface of the fifth metal oxide layer, a side surface of the third metal oxide layer, and a side surface of the fourth metal oxide layer each have a region in contact with the first insulating layer in a region between the second metal oxide layer and the fifth metal oxide layer; an eleventh side surface of the fifth metal oxide layer and a twelfth side surface opposite to the eleventh side surface each have a region in contact with the first insulating layer; The semiconductor device further comprises a first conductive layer disposed to surround the fifth metal oxide layer with the first insulating layer interposed therebetween. 　 In claim 1 or 2, The third metal oxide layer and the fourth metal oxide layer each have the same material as the second metal oxide layer. 　 In claim 1 or 2, A transistor is included. the transistor includes the first to fourth metal oxide layers, the first insulating layer, the second insulating layer, the first to third conductive layers, and a fourth conductive layer; the second insulating layer is provided on the fourth conductive layer; A semiconductor device, wherein the first metal oxide layer is provided on the second insulating layer so as to have a region overlapping with the fourth conductive layer. 　 In claim 1 or 2, It has an insulating base layer, the first metal oxide layer is provided on the underlying insulating layer; a lower surface of the first metal oxide layer, a side surface of the third metal oxide layer, and a side surface of the fourth metal oxide layer each have a region in contact with the first insulating layer in a region between the base insulating layer and the first metal oxide layer; A semiconductor device comprising: a first conductive layer having a region located between the base insulating layer and the first metal oxide layer, and surrounding the first metal oxide layer with the first insulating layer interposed therebetween. 　 In claim 1 or 2, the third metal oxide layer has a first layer having a region in contact with the second side surface, and a second layer provided outside the first layer, the fourth metal oxide layer includes a third layer having a region in contact with the fourth side surface, and a fourth layer provided outside the third layer, The first layer and the third layer each have the same material as the second metal oxide layer. 　 In claim 1 or 2, the second conductive layer includes a first layer having a region in contact with the third metal oxide layer, and a second layer provided outside the first layer; the third conductive layer includes a third layer having a region in contact with the fourth metal oxide layer, and a fourth layer provided outside the third layer; The semiconductor device, wherein the first layer and the third layer each include a metal oxide. 　 In claim 1 or 2, each of the first to fourth metal oxide layers contains one or more elements selected from indium, zinc, and an element M; The element M is one or more selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. 　 In claim 7, each of the first to fourth metal oxide layers contains one or more elements selected from indium, zinc, and an element M; The element M is one or more selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony; The semiconductor device, wherein the first layer and the third layer each contain indium. 　 forming a first metal oxide layer, a first sacrificial layer on the first metal oxide layer, and a second metal oxide layer on the first sacrificial layer; forming a third metal oxide layer so as to have a region in contact with a first side surface of the first metal oxide layer, a region in contact with a second side surface of the second metal oxide layer, a region in contact with a third side surface opposite to the first side surface, and a region in contact with a fourth side surface opposite to the second side surface, and to have a region located on the second metal oxide layer; forming a first conductive layer on the third metal oxide layer; performing a planarization treatment on the first conductive layer and the third metal oxide layer; forming a second conductive layer and a third conductive layer facing the second conductive layer with the second metal oxide layer interposed therebetween by processing the first conductive layer, and forming a fourth metal oxide layer and a fifth metal oxide layer facing the fourth metal oxide layer with the second metal oxide layer interposed therebetween by processing the third metal oxide layer; removing the first sacrificial layer; forming a first insulating layer so as to cover the first metal oxide layer and the second metal oxide layer; A method for manufacturing a semiconductor device, comprising forming a fourth conductive layer so as to cover the first insulating layer. 　 In claim 10, forming a second sacrificial layer on the second metal oxide layer prior to deposition of the third metal oxide layer; forming the third metal oxide layer having an area overlying the second sacrificial layer; A method for manufacturing a semiconductor device, comprising the steps of: planarizing the second sacrificial layer in the same step as planarizing the first conductive layer and the third metal oxide layer. 　 In claim 11, forming the second sacrificial layer having a first layer and a second layer on the first layer, the first layer having a thickness equal to or less than a thickness of the second layer; A method for manufacturing a semiconductor device, wherein a planarization treatment for the second sacrificial layer is performed at least until an upper surface of the first layer is exposed. 　 In claim 10, forming a second sacrificial layer on the second metal oxide layer and a sixth metal oxide layer on the second sacrificial layer before depositing the third metal oxide layer; the third metal oxide layer is formed to have a region in contact with a fifth side surface of the sixth metal oxide layer and a region in contact with a sixth side surface opposite to the fifth side surface, and to have a region located on the sixth metal oxide layer; removing the second sacrificial layer by the same process as removing the first sacrificial layer; a first insulating layer formed to cover the sixth metal oxide layer; 　 In claim 13, forming a third sacrificial layer on the sixth metal oxide layer before depositing the third metal oxide layer; the third metal oxide layer is deposited to have an area overlying the third sacrificial layer; A method for manufacturing a semiconductor device, comprising the steps of: planarizing the third sacrificial layer in the same step as planarizing the first conductive layer and the third metal oxide layer. 　 In claim 14, forming the third sacrificial layer such that the third sacrificial layer has a first layer and a second layer on the first layer, and the thickness of the first layer is equal to or less than the thickness of the second layer; A method for manufacturing a semiconductor device, wherein a planarization treatment for the third sacrificial layer is performed at least until an upper surface of the first layer is exposed. 　 In any one of claims 10 to 15, A method for manufacturing a semiconductor device, comprising the steps of: forming a fifth conductive layer and a second insulating layer on the fifth conductive layer; and then forming the first metal oxide layer on the second insulating layer, the first sacrificial layer on the first metal oxide layer, and the second metal oxide layer on the first sacrificial layer, so as to have an area overlapping with the fifth conductive layer. 　 In claim 10, forming a base insulating layer and a second sacrificial layer in contact with an upper surface of the base insulating layer, and then forming the first metal oxide layer on the second sacrificial layer, the first sacrificial layer on the first metal oxide layer, and the second metal oxide layer on the first sacrificial layer; A method for manufacturing a semiconductor device, comprising removing the second sacrificial layer in the same process as removing the first sacrificial layer.

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