Method for manufacturing semiconductor device

Abstract

A method for manufacturing a semiconductor device according to an embodiment includes a first film formation step, a second film formation step, and an oxidation step. In the first film formation step, a first coating film that is formed of silicon is formed on the surface of a base material that is formed of silicon carbide. In the second film formation step, a second coating film is formed on the surface of the first coating film. In the oxidation step, the first coating film is thermally oxidized from the surface side so as to form a third coating film. In the second film formation step, the second coating film is not formed on a part of the first coating film so as to expose the part. Alternatively, in the second film formation step, the film thickness of the second coating film formed on a part of the first coating film is less than the film thickness of the second coating film formed on the other parts.

Description

Semiconductor device manufacturing method

[0001] This application claims priority to Japanese Patent Application No. 2023-120158, filed on July 24, 2023, the contents of which are incorporated herein by reference.

[0002] In recent years, with the advancement of miniaturization of semiconductor devices, there has been a demand for a structure that can increase the withstand voltage while realizing miniaturization by locally thickening the insulating film in a location within the semiconductor device where dielectric breakdown is likely to occur. To address this, a method has been proposed in which a locally thick insulating film is formed using a film formation method such as chemical vapor deposition (CVD), but this method has the problem of easily introducing impurities into the insulating film.

[0003] JP 2014-56912 A

[0004] The problem to be solved by the present invention is to provide a method for manufacturing a semiconductor device that can form a locally thick insulating film while suppressing the inclusion of impurities.

[0005] The method for manufacturing a semiconductor device according to the embodiment includes a first film formation process, a second film formation process, and an oxidation process. In the first film formation process, a first film made of silicon is formed on the surface of a substrate made of silicon carbide. In the second film formation process, a second film is formed on the surface of the first film. In the oxidation process, the first film is thermally oxidized from the surface side to form a third film. In the second film formation process, the second film is not formed on a portion of the first film, leaving that portion exposed. Alternatively, in the second film formation process, the thickness of the second film formed on a portion of the first film is smaller than the thickness of the second film formed on other portions.

[0006] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment; a flowchart of a method for manufacturing a semiconductor device according to the first embodiment; a schematic view of a base material forming step according to the first embodiment; a schematic view of an ion implantation step according to the first embodiment; a schematic view of a trench forming step according to the first embodiment; a schematic view of a first film forming step according to the first embodiment; a schematic view of an inhibitor adsorption step in a second film forming step according to the first embodiment; a schematic view of a precursor adsorption step in a second film forming step according to the first embodiment; a schematic view of a film forming step in a second film forming step according to the first embodiment; a schematic view of a first oxidation step according to the first embodiment; a schematic view of an etching step according to the first embodiment; a schematic view of a second oxidation step according to the first embodiment; a schematic view of an electrode forming step according to the first embodiment; a schematic view of an interlayer insulating film forming step according to the first embodiment; a schematic view of a first oxidation step of a modified example that can be employed in the first embodiment; a schematic view of a second film forming step of a modified example that can be employed in the first embodiment; a part of a flowchart of a method for manufacturing a semiconductor device according to a second embodiment; a schematic view of a precursor adsorption step in a second film forming step according to the second embodiment. 1A and 1B are schematic views of a film formation step in a second film formation step of a second embodiment; a schematic view of a first oxidation step of a second embodiment; a schematic view of first and second etching steps of a second embodiment; a schematic view of a third etching step of a second embodiment; a schematic view of a third film formation step of a second embodiment; and a schematic view of a second oxidation step of a second embodiment.

[0007] Hereinafter, a method for manufacturing a semiconductor device according to an embodiment will be described with reference to the drawings.

[0008] In this specification, the concepts of "up" and "down" do not necessarily indicate a relationship with the direction of gravity. － and p, p － The notation indicates the relative level of impurity concentration in each conductivity type. － indicates that the n-type impurity concentration is relatively lower than that of n. － indicates that the p-type impurity concentration is relatively lower than that of p. － The type is simply n-type, p － The type may also be simply referred to as p-type.

[0009] 1 is a schematic cross-sectional view of a semiconductor device 1 according to a first embodiment. The semiconductor device 1 of this embodiment is a trench-type metal-oxide-semiconductor field-effect transistor (MOSFET, hereinafter referred to as MOSFET).

[0010] The semiconductor device 1 includes a base material 10 , an insulating film 30 (gate insulating film), a gate electrode 20 , an interlayer insulating film 40 , a source electrode 21 , a drain electrode 24 , a source wiring 22 , and a protective electrode 25 .

[0011] The substrate 10 is made of silicon carbide (SiC). The silicon carbide constituting the substrate 10 preferably has a hexagonal crystal structure, and more preferably has polytype 4H. The substrate 10 is formed by epitaxially growing silicon carbide on a single crystal substrate of silicon carbide. Silicon carbide (SiC) has a breakdown field strength approximately 10 times greater than that of silicon (Si). Therefore, by using silicon carbide as the substrate 10 of the semiconductor device 1, it is possible to increase the impurity concentration while maintaining the withstand voltage, and to construct a low-loss, low-resistance, high-power MOSFET. The substrate 10 is made of n － The semiconductor device includes a layer 12 , a p-type body layer 13 , an n-type region 14 , and a contact region 15 .

[0012] n － The layer 12 has n-type conductivity due to the addition of a donor. － The n-type region 14 is disposed on the layer 12. － Layer 12 is n － The n-type region 14 is provided on the p-type body layer 13. The n-type region 14 is n-type by the p-type body layer 13. － The n-type region 14 is separated from the n-type layer 12. － The contact region 15 has a relatively higher n-type impurity concentration than the layer 12. The p-type body layer 13 has a p －The contact region 15 is formed on a part of the p-type body layer 13 so as to be connected to the p-type body layer 13. The contact region 15 has a relatively higher p-type impurity concentration than the p-type body layer 13.

[0013] The substrate 10 has a trench 5. The trench 5 opens upward. The inner surface of the trench 5 includes a bottom surface 5b and a sidewall surface 5a extending upward from the bottom surface 5b. The bottom surface 5b of the trench 5 has a thickness of n － The sidewall surface 5 a of the trench 5 extends from the top surface of the n-type region 14 through the p-type body layer 13 to the n-type region 14 . － Extends to layer 12.

[0014] The insulating film 30 covers the inner surfaces of the trench 5, i.e., the sidewall surfaces 5a and the bottom surface 5b. The insulating film 30 includes a sidewall film 31 provided on the sidewall surfaces 5a of the trench 5 and a bottom film 32 provided on the bottom surface 5b. The sidewall film 31 extends upward from the bottom film 32. The thickness T2 of the bottom film 32 is greater than the thickness T1 of the sidewall film 31. When the semiconductor device 1 is operated, an electric field tends to concentrate at the corners between the bottom surface 5b and the sidewall surfaces 5a of the trench 5, which can cause problems with the withstand voltage at those locations. According to this embodiment, the semiconductor device 1 can be miniaturized by relatively reducing the thickness T1 of the sidewall film 31, while the thickness T2 of the bottom film 32 can be relatively increased by relatively increasing the thickness T2 of the bottom film 32, thereby increasing the withstand voltage at the corners and providing a semiconductor device 1 with excellent insulation characteristics. The thickness T2 of the bottom film 32 is preferably, for example, 1 nm or more larger than the thickness T1 of the sidewall film 31 (T2-T1≧1 nm), and more preferably 10 nm or more larger (T2-T1≧10 nm).

[0015] The gate electrode 20 is buried in the trench 5. An insulating film 30 is interposed between the gate electrode 20 and the inner side surface of the trench 5. That is, the insulating film 30 separates the substrate 10 and the gate electrode 20 within the trench 5. The gate electrode 20 faces the surface of the p-type body layer 13 via the insulating film 30. The upper surface of the gate electrode 20 is approximately flush with the upper surface of the portion of the insulating film 30 that is located above the upper surface of the n region 14. An interlayer insulating film 40 is provided to cover the gate electrode 20 and the portion of the insulating film 30 that extends onto the upper surface of the n region 14.

[0016] Source electrode 21 penetrates interlayer insulating film 40 and contacts n region 14 and contact region 15. Source wiring 22 is provided on source electrode 21 and interlayer insulating film 40 so as to contact source electrode 21. Drain electrode 24 is provided on the surface of substrate 10 opposite to the surface on which trench 5 is provided. Protecting electrode 25 covers drain electrode 24.

[0017] Next, a method for manufacturing the semiconductor device 1 will be described. Fig. 2 is a flowchart showing the steps of the method for manufacturing the semiconductor device 1 of this embodiment. The method for manufacturing the semiconductor device 1 of this embodiment includes a base material forming step S10, an ion implantation step S20, a trench forming step S30, a first film forming step S40, a second film forming step S50, a first oxidation step (oxidation step) S60, an etching step S70, a second oxidation step (oxide film forming step) S80, a gate electrode forming step S90, an interlayer insulating film forming step S100, a source electrode forming step S110, a source wiring forming step S120, a drain electrode forming step S130, and a protective electrode forming step S140.

[0018] 3 is a schematic diagram of the base material forming step S10 of this embodiment. In the base material forming step S10, for example, a silicon carbide single crystal substrate is formed on a silicon carbide single crystal substrate prepared in advance by introducing nitrogen (N) or phosphorus (P) into the silicon carbide. － The layer 12 is formed by epitaxial growth to produce the base material 10. The single crystal substrate is polished away in the final step, for example, but this is not shown here.

[0019] 4 is a schematic diagram of the ion implantation step S20 of this embodiment. In the ion implantation step S20, a p-type body layer 13, an n-region 14, and a contact region 15 are formed. In the ion implantation step S20, acceptor ions such as aluminum (Al) are implanted from the upper surface of the substrate 10 to form the p-type body layer 13. In the ion implantation step S20, donor ions such as phosphorus (P) are then implanted from the upper surface of the substrate 10 to form the n-region 14. As a result, the n －A substrate 10 is formed having a layer 12, a p-type body layer 13, and an n-type region 14. In an ion implantation step S20, ions of an acceptor such as aluminum are then implanted to form a contact region 15. Note that in the manufacturing method of this embodiment, the p-type body layer 13 and the n-type region 14 may be formed by epitaxial growth accompanied by the addition of impurities, instead of the ion implantation step S20.

[0020] Next, an activation heat treatment is performed to activate the impurities added by ion implantation. The temperature of this heat treatment is preferably 1500°C or higher and 1900°C or lower, for example, about 1700°C. The heat treatment time is, for example, about 30 minutes. The heat treatment atmosphere is preferably an inert gas atmosphere, for example, an argon (Ar) atmosphere.

[0021] 5 is a schematic diagram of the trench formation step S30 of this embodiment. In the trench formation step S30, a trench is formed in a substrate 10 made of silicon carbide. In the trench formation step S30, a mask 91 having an opening 91a that partially exposes the n-type region 14 is first formed on the substrate 10. The opening 91a of the mask 91 is formed to correspond to the position of the trench 5. In the opening 91a of the mask 91, the n-type region 14, the p-type body layer 13, and the n-type body layer 14 are exposed. － A portion of the layer 12 is removed by etching, thereby forming a trench 5 in the substrate 10. After the trench 5 is formed, the mask 91 is removed.

[0022] 6 is a schematic diagram of the first film-forming step S40 of this embodiment. The first film-forming step S40 is a step of forming a silicon coating (first coating) 50 on the inner surface of the trench 5. The silicon coating 50 is made of silicon. In the first film-forming step S40, the silicon coating 50 is formed by, for example, a low-pressure CVD method (LP-CVD).

[0023] 7 to 9 are schematic diagrams illustrating the steps of the second film-forming step S50 of this embodiment. The second film-forming step S50 of this embodiment includes an inhibitor adsorption step S51 (FIG. 7), a precursor adsorption step S52 (FIG. 8), and a film formation step S53 (FIG. 9). The second film-forming step S50 is a step of forming a barrier coating (second coating) 60 by atomic layer deposition (ALD, hereinafter referred to as ALD) on a portion of a silicon coating 50 provided on the inner surface of the trench 5. In the following description, a region of the silicon coating 50 provided on the sidewall surface 5a of the trench 5 is referred to as a sidewall coating 51, and a region provided on the bottom surface 5b of the trench 5 is referred to as a bottom coating 52. In the second film-forming step S50 of this embodiment, the barrier coating 60 is formed only on the bottom coating 52. In this embodiment, the barrier coating 60 is formed of silicon oxide (SiO ２ However, the material of the barrier coating 60 is not limited to this embodiment.

[0024] FIG. 7 is a schematic diagram of the inhibitor adsorption step S51 of this embodiment. The inhibitor adsorption step S51 is a step of adsorbing a factor (hereinafter referred to as an inhibitor 71) that inhibits adsorption of a precursor 72 (see FIG. 8 ), which will be described later, onto the sidewall coating 51. In the method for manufacturing the semiconductor device 1 of this embodiment, examples of the inhibitor 71 include self-assembled monolayers (SAMs), small molecule inhibitors (SIMs), and surface termination using nitrogen atoms (N) or hydrogen atoms (H). In the inhibitor adsorption step S51, the inhibitor 71 is formed on the silicon coating 50 by CVD. More specifically, a gas containing the inhibitor 71 is introduced into a processing chamber. After the inhibitor 71 is adsorbed, the gas containing the inhibitor 71 is exhausted from the processing chamber.

[0025] In the inhibitor adsorption step S51 of this embodiment, the pressure of the gas containing the inhibitor 71 and the gas introduction time are controlled so that the inhibitor 71 does not reach the deepest part of the inner surface of the trench 5. Therefore, the inhibitor 71 is adsorbed to the upper region of the sidewall coating 51 on the inner surface of the trench 5, but is not adsorbed to the lower region of the sidewall coating 51 or the bottom coating 52.

[0026] FIG. 8 is a schematic diagram of the precursor adsorption step S52 of this embodiment. In the precursor adsorption step S52, a gas containing a precursor 72 is introduced into a processing chamber. In the manufacturing method of the semiconductor device 1 of this embodiment, examples of the precursor 72 include TDMAS, Orthrus, 3DMAS, and SAM24. The precursor 72 does not adsorb to the portion of the surface of the silicon coating 50 where the inhibitor 71 is adsorbed. Therefore, the precursor 72 selectively adsorbs to the region below the sidewall coating 51 and the bottom coating 52 on the inner surface of the trench 5. After the precursor 72 is adsorbed, the gas containing the precursor 72 is exhausted from the processing chamber. Note that plasma may be generated when adsorbing the precursor 72.

[0027] 9 is a schematic diagram of the film formation step S53 of this embodiment. In the film formation step S53, a reaction gas containing a reactant that will be the basis of the barrier coating 60 is introduced into the processing chamber. In the manufacturing method of the semiconductor device 1 of this embodiment, in the film formation step S53, O ３ By reacting radicals in the plasma (e.g., O radicals) with adsorbed molecules (precursors), SiO ２ The reaction gas reacts with the atoms of the precursor 72 only at the positions where the precursor 72 is adsorbed to form silicon oxide (SiO ２ ) is formed. Therefore, the barrier coating 60 is formed only in the area below the sidewall coating 51 and the bottom coating 52. After forming the barrier coating 60, the reaction gas is exhausted from the processing chamber.

[0028] By undergoing the second film-forming step S50 described above, the barrier coating 60 is formed only in the region below the sidewall coating 51 and the bottom coating 52. That is, in the second film-forming step, a portion (bottom coating 52) of the silicon coating 50 provided on the inner surface of the trench 5 is covered with the barrier coating 60, and the other portion (sidewall coating 51) of the silicon coating 50 is exposed from the barrier coating 60. Therefore, the combined coating of the silicon coating 50 and the barrier coating 60 becomes locally thicker in the portion where the barrier coating 60 is formed. In this embodiment, the barrier coating 60 has a thickness TA. When ALD is employed in the second film-forming step S50, the thickness TA of the barrier coating 60 is preferably set to, for example, 300 nm or less, in consideration of the film-forming rate of ALD and from the viewpoint of productivity.

[0029] According to this embodiment, ALD is employed in the second film formation step S50. ALD allows atomic layers to be formed one by one, reducing impurity contamination and forming the barrier coating 60 with a stoichiometric composition. Therefore, by employing ALD in the second film formation step S50, the barrier coating 60 can be selectively formed on a portion of the inner surface of the trench 5 with a uniform and precisely controlled thickness. Furthermore, when ALD is employed in the second film formation step S50, deposition on the sidewall coating 51 can be partially restricted by using an inhibitor, for example, so that a portion of the silicon coating 50 (the sidewall coating 51) can be exposed. In this embodiment, the barrier coating 60 is not formed on the sidewall coating 51 in the second film formation step S50. However, as will be described in a later modified example ( FIG. 16 ), a thin-film barrier coating 60A may be formed on the sidewall coating 51. In this case, it is only necessary that the thickness of the barrier coating 60A formed on the sidewall coating 51 is smaller than the thickness of the barrier coating 60A formed on the bottom coating 52.

[0030] 10 is a schematic diagram of the first oxidation step S60 of this embodiment. The first oxidation step S60 is a step of thermally oxidizing the silicon coating 50 from the surface side to form silicon oxide (SiO ２In the first oxidation step S60, the temperature, time, oxygen concentration, and the like are adjusted to thermally oxidize only a portion of the surface side of the silicon coating 50, thereby forming the first oxide coating (third coating) 80. This thermal oxidation is performed at a temperature at which silicon is thermally oxidized but silicon carbide is not substantially thermally oxidized.

[0031] In the following description, the portion of the first oxide layer 80 formed on the sidewall coating 51 is referred to as the first portion 80a, and the portion formed on the bottom coating 52 is referred to as the second portion 80b. Through the first oxidation step S60, the first portion 80a having a thickness T3 is formed on the surface of the sidewall coating 51. Furthermore, the second portion 80b having a thickness T4 is formed on the interface of the bottom coating 52 with the barrier coating 60. Because the thermal oxidation of the bottom coating 52 occurs below the first oxide layer 80, it proceeds slightly more slowly than the thermal oxidation of the sidewall coating 51. Therefore, the thickness T4 of the second portion 80b of the first oxide layer 80 is slightly smaller than the thickness T3 of the first portion 80a.

[0032] By undergoing the first oxidation step S60, a silicon oxide (SiO ) film consisting only of the first oxide film 80 (first portion 80 a) having a thickness T3 is formed on the sidewall film 51. ２ ) is formed on the bottom coating 52 after the first oxidation step S60. On the other hand, a laminated coating is formed on the bottom coating 52 after the first oxidation step S60, in which the barrier coating 60 having a thickness TA and the first oxide coating 80 (second portion 80b) having a thickness T4 are stacked. Here, the sum of the thicknesses of the barrier coating 60 and the first oxide coating 80 on the bottom coating 52 (TA + T4) is greater than the thickness T3 of the first oxide coating 80 on the sidewall coating 51 (TA + T4 > T3). Therefore, the thickness (TA + T4) of the oxide coating on the silicon coating 50 at the portion formed on the bottom surface 5b of the trench 5 is greater than the thickness T3 of the portion formed on the sidewall surface 5a.

[0033] 11 is a schematic diagram of the etching step S70 of this embodiment. The etching step S70 is a step of etching away the barrier coating 60 and a portion of the first oxide coating 80. The etching step S70 can be performed by various means, such as wet etching using hydrofluoric acid, chemical dry etching, or reactive ion etching (RIE).

[0034] In the etching step S70 of this embodiment, a predetermined thickness of the oxide film formed on the surface of the substrate 10 is removed from the surface side. The thickness TB removed in the etching step S70 is greater than the thickness T3 of the first portion 80a shown in FIG. 10 and less than the sum (TA + T4) of the thicknesses of the barrier film 60 and the second portion 80b (T3 < TB < TA + T4). Therefore, after the etching step S70, only the second portion 80b of the first oxide film 80 located on the bottom surface 5b remains on the inner surface of the trench 5, and the first portion 80a on the sidewall surface 5a is removed.

[0035] It is preferable that the thickness TB of the film removed in the etching step S70 is larger than the thickness TA of the barrier coating 60 (TB>TA). This makes it possible to prevent an oxide film derived from the barrier coating 60 from remaining on the bottom surface 5b, and to leave only the oxide film formed by thermal oxidation, thereby improving the crystalline uniformity of the insulating film 30. It is not necessary to completely remove the barrier coating 60, and it is acceptable for it to remain.

[0036] 12 is a schematic diagram of the second oxidation step S80 of this embodiment. The second oxidation step S80 is a step of thermally oxidizing the entire silicon coating 50 remaining after the first oxidation step S60 and the etching step S70 to form the insulating film 30. That is, the second oxidation step S80 is a step of forming the insulating film (fourth coating) 30 made of silicon oxide on the inner surface of the trench 5. This thermal oxidation is performed at a temperature at which silicon is thermally oxidized but silicon carbide is not substantially thermally oxidized.

[0037] Through the second oxidation step S80, the sidewall coating 51 and bottom coating 52 of the silicon coating 50 are oxidized, and a second oxide coating 59 derived from the silicon coating 50 is formed on the inner surface of the trench 5. The second oxide coating 59 derived from the silicon coating 50 and the first oxide coating 80 formed on the second oxide coating 59 combine to form the insulating film 30 on the inner surface of the trench 5. As described above, the first oxide coating 80 remains only on the bottom surface 5b of the trench 5, so the bottom film 32 of the insulating film 30 is composed of the second oxide coating 59 derived from the silicon coating 50 and the first oxide coating 80. On the other hand, the sidewall film 31 of the insulating film 30 is composed only of the second oxide coating 59 derived from the silicon coating 50. Therefore, in the insulating film 30, the thickness T2 of the bottom film 32 is greater than the thickness T1 of the sidewall film 31.

[0038] 13 is a schematic diagram of the gate electrode formation step S90 of this embodiment. In the gate electrode formation step S90, the gate electrode 20 is formed inside the trench 5 and on the insulating film 30. The gate electrode 20 can be formed by, for example, depositing a conductor or doped polysilicon film and performing CMP (Chemical Mechanical Polishing).

[0039] 14 is a schematic diagram of the interlayer insulating film forming step S100 of this embodiment. In the interlayer insulating film forming step S100, an interlayer insulating film 40 is formed on the gate electrode 20 and the insulating film 30 so as to cover the exposed surface of the gate electrode 20.

[0040] Next, although not specifically shown in the drawings, a source electrode forming step, a source wiring forming step, a drain electrode forming step, and a protective electrode forming step are performed, and source electrode 21, source wiring 22, drain electrode 24, and protective electrode 25 are formed in this order, as shown in Fig. 1. Source electrode 21 is formed after forming openings in interlayer insulating film 40 and insulating film 30 by etching to expose n region 14 and contact region 15.

[0041] Through the above steps, it is possible to manufacture a semiconductor device 1 having an insulating film 30 whose film thickness T2 on the bottom surface 5b of the trench is larger than the film thickness T1 on the sidewall surface 5a.

[0042] Next, a first modification that can be employed in this embodiment will be described. In the manufacturing method of the semiconductor device 1 of this embodiment, the silicon film 50 is only partially oxidized from the surface side in the first oxidation step S60, and the oxidized portion is then removed in the subsequent etching step S70. However, the entire silicon film 50 may be oxidized in the first oxidation step S60 and used as is as part of the insulating film 30. FIG. 15 is a schematic diagram of the first oxidation step S60 of this modification that can be employed in this embodiment. In the first oxidation step S60 of this modification, the entire silicon film 50 is thermally oxidized to form a first oxide film 80A. A film consisting of the barrier film 60 and the first oxide film 80A is referred to as the insulating film 30A of this modification. In the insulating film 30A of this modification, only the first oxide film 80A is disposed on the sidewall surface 5a of the trench, while the barrier film 60 is disposed on the bottom surface 5b in addition to the first oxide film 80A. Therefore, the insulating film 30A can have a thickness T5b on the bottom surface 5b larger than the thickness T5a on the sidewall surface 5a. After the first oxidation step S60 of this modification is performed, the gate electrode formation step S90 and subsequent steps are performed in the above-described order without performing the etching step S70 and the second oxidation step S80. In other words, this modification makes it possible to omit some of the steps for forming the insulating film 30A, thereby simplifying the manufacturing process of the semiconductor device 1. Note that in the above-described embodiment, the barrier film 60 is removed in the etching step S70, and the thickness of the insulating film 30 is ensured by separate thermal oxidation. As a result, in the above-described embodiment, only the oxide film formed by thermal oxidation is used as the insulating film 30, thereby improving the crystalline uniformity of the insulating film 30.

[0043] Next, a second modification that can be employed in this embodiment will be described. In this embodiment, only the silicon film 50 that remains unoxidized in the first oxidation step S60 ( FIG. 10 ) is thermally oxidized in the second oxidation step S80 ( FIG. 12 ) and used as the insulating film 30. However, after the etching step S70 ( FIG. 11 ), a new silicon film may be formed on the silicon film 50 and the first oxide film 80. In this case, the new silicon film is thermally oxidized together with the silicon film 50 in the second oxidation step S80, and together with the first oxide film 80 that remains after the etching step S70 ( FIG. 11 ), they form the insulating film 30. In this case, a thicker insulating film 30 can be formed than in this embodiment.

[0044] Next, a third modified example that can be employed in this embodiment will be described. In this embodiment, the second film formation step S50 employs ALD. However, a modified example of the second film formation step S50 may employ CVD. FIG. 16 is a schematic diagram showing the second film formation step S50 of this modified example. Examples of CVD that can be employed in the second film formation step S50 of this modified example include HDPCVD (high density plasma chemical vapor deposition), SACVD (selective area chemical vapor deposition), and PECVD (plasma-enhanced chemical vapor deposition). In this modified example, the barrier film 60A is formed not only on the bottom surface 5b of the trench 5 but also on the sidewall surface 5a. However, the thickness TCa of the barrier film 60A on the sidewall surface 5a is smaller than the thickness TCb of the barrier film 60A on the bottom surface 5b. That is, in the second film formation step S50, the thickness TCa of the barrier coating 60A formed on a portion (sidewall coating 51) of the silicon coating 50 is smaller than the thickness TCb of the barrier coating 60A formed on the other portion (bottom coating 52). In this modification, as in the above-described embodiment, the entire barrier coating 60A is removed in the etching step S70 after the silicon coating 50 is thermally oxidized to form the first oxide coating 80 in the first oxidation step S60. As in the above-described embodiment, in the etching step S70, the first oxide coating 80 on the bottom surface 5b can be left in accordance with the difference in thickness of the barrier coating 60A.

[0045] The components of the first embodiment are summarized below. The manufacturing method of the semiconductor device 1 of this embodiment includes a first film formation step S40, a second film formation step S50, and a first oxidation step (oxidation step) S60. The first film formation step S40 is a step of forming a silicon coating 50 made of silicon (Si) on the surface of a substrate 10 made of silicon carbide (SiC). The second film formation step S50 is a step of forming a barrier coating 60 on a portion of the surface of the silicon coating 50. The first oxidation step S60 is a step of thermally oxidizing the silicon coating 50 from the surface side to form a first oxide coating 80. In the second film formation step S50, the barrier coating 60 is not formed on a portion of the silicon coating 50, leaving that portion exposed, or the thickness of the barrier coating 60 formed on that portion of the silicon coating 50 is smaller than the thickness of the barrier coating 60 formed on other portions.

[0046] According to the above-described configuration, after the first oxidation step S60, the thickness of the composite coating of the barrier coating 60 and the first oxide coating 80 can be locally varied on the surface of the substrate 10. In the above-described embodiment, the composite coating is etched (etching step S70), leaving a portion of the first oxide coating 80, thereby forming a locally thick insulating film 30. In the above-described modified example (see FIG. 15 ), the composite coating is used as the insulating film 30A, forming a locally thick insulating film 30A in which the barrier coating 60 and the first oxide coating 80 are stacked. Thus, according to the above-described configuration, by selectively adjusting the thickness of the barrier coating 60, it is possible to form insulating films 30, 30A with freely adjustable placement and thickness. As a result, the insulating films 30, 30A can be thickened only in areas where enhanced insulating performance is required, thereby manufacturing a semiconductor device 1 that is small in size and has excellent voltage resistance. According to the above-described configuration, the insulating film 30A can be formed of an oxide film obtained by thermally oxidizing a film formed as silicon, or an oxide film formed by ALD. That is, according to the above-described configuration, a film formed by CVD is not used as the insulating film 30, 30A. Therefore, compared to forming an insulating film by CVD, it is possible to form locally thick insulating films 30, 30A with reduced incorporation of impurities.

[0047] In the above-described configuration, the first oxidation step S60 may be a step of thermally oxidizing only a portion of the silicon coating 50 to form the first oxide coating 80 (see FIG. 10 ), or a step of thermally oxidizing the entire silicon coating 50 to form the first oxide coating 80A (see FIG. 15 ).

[0048] The method for manufacturing the semiconductor device 1 of this embodiment includes an etching step S70 and a second oxidation step (oxide film forming step) S80. The etching step S70 is a step of etching the barrier film 60 and at least a part of the first oxide film 80. The second oxidation step S80 is a step of forming silicon oxide (SiO ２ ) is formed as an insulating film (fourth coating) 30.

[0049] According to the above-described configuration, the barrier coating 60 can be removed by etching in the etching step S70, and then the insulating film 30 can be formed in the second oxidation step S80. Therefore, the insulating film 30 can be formed by thermal oxidation alone without leaving any film derived from the barrier coating 60 on the insulating film 30, and the crystal uniformity of the insulating film 30 can be improved.

[0050] The manufacturing method of the semiconductor device 1 of this embodiment includes a trench formation step S30, which forms a trench 5 in the substrate 10 before the first film formation step S40. The portion of the silicon coating 50 on which the barrier coating 60 is not formed (or on which only a thin barrier coating is formed) is the portion formed on the sidewall surface 5a of the trench 5. The other portion of the silicon coating 50 on which the barrier coating 60 is formed is the portion formed on the bottom surface 5b of the trench 5. This configuration allows the barrier coating 60 to be formed only on the bottom surface 5b of the trench 5, or the barrier coating 60 on the bottom surface 5b to be thicker than the barrier coating 60 on the sidewall surface 5a. This allows the insulating performance of the bottom film 32 of the insulating film 30, 30A to be improved compared to the insulating performance of the thin portion (sidewall film 31). When the semiconductor device 1 is a trench-type MOSFET, electric fields tend to concentrate near the corners of the bottom surface 5b of the trench 5, making dielectric breakdown more likely. As shown in this embodiment, by making the bottom film 32 of the insulating film 30 thicker than other portions, the insulating characteristics of the trench MOSFET can be improved.

[0051] In the method for manufacturing the semiconductor device 1 of this embodiment, the barrier film 60 is made of silicon oxide (SiO ２ ) In this configuration, both the barrier coating 60 and the first oxide coating 80 are made of silicon oxide. Therefore, the oxygen diffusion coefficients of the barrier coating 60 and the first oxide coating 80 are approximately the same, and an oxide coating of sufficient thickness can be formed below the barrier coating 60 in the first oxidation step S60. Furthermore, when the etching step S70 is performed, the barrier coating 60 and the first oxide coating 80 can be etched simultaneously, which simplifies the manufacturing process.

[0052] 17 is a flowchart showing some steps of a manufacturing method of a semiconductor device 1 according to a second embodiment. In the following description of each embodiment, the same components as those in the previously described embodiments are denoted by the same reference numerals, and the description thereof will be omitted.

[0053] 17 , the second embodiment includes a second film formation step S150, a first oxidation step S160, an etching step S170, and an oxide film formation step S180. Note that the same components of the manufacturing method of the second embodiment as those of the manufacturing method of the first embodiment will not be described. That is, in the second embodiment, descriptions of the base material formation step S10, the ion implantation step S20, the trench formation step S30, and the first film formation step S40, which are performed before the steps shown in FIG. 17 , and descriptions of the gate electrode formation step S90, the interlayer insulating film formation step S100, the source electrode formation step S110, the source wiring formation step S120, the drain electrode formation step S130, and the protective electrode formation step S140, which are performed after the steps shown in FIG. 17 , will be omitted.

[0054] The second film formation step S150 of this embodiment includes a precursor adsorption step S151 and a film formation step S152. The second film formation step S150 is a step of forming a barrier coating (second coating) 160 by ALD on a portion of the silicon coating 50 provided on the inner surface of the trench 5. In this embodiment, the barrier coating 160 is silicon nitride (SiN).

[0055] 18 is a schematic diagram of the precursor adsorption step S151 of this embodiment. In the precursor adsorption step S151, a gas containing a precursor 172 is introduced into the processing chamber. Examples of the precursor 172 in this embodiment include chlorosilane, organosilane, and heterosilane. The gas containing the precursor 172 is exhausted from the processing chamber before it reaches the bottom surface 5b of the trench 5. As a result, in the precursor adsorption step S151 of this embodiment, the precursor 172 is adsorbed to the sidewall coating 51 on the inner surface of the trench 5, but is not adsorbed to the bottom coating 52 or the sidewall coating 51 near the bottom coating 52.

[0056] 19 is a schematic diagram of the film formation step S152 of this embodiment. In the film formation step S152, a reaction gas containing a reactant that will be the basis of the barrier coating 160 is introduced into the processing chamber. The reaction gas includes NH ３The reactive gas reacts with atoms of the precursor 172 only at the positions where the precursor 172 is adsorbed to form the barrier coating 160. Therefore, the barrier coating 160 is formed only in the region above the sidewall coating 51 in the trench 5. After forming the barrier coating 160, the reactive gas is exhausted from the processing chamber.

[0057] By undergoing the second film-forming step S150 described above, the barrier film 160 made of silicon nitride (SiN) is formed only in the region above the sidewall film 51 in the trench 5. That is, in the second film-forming step S150, the barrier film 160 is not formed on a portion (bottom film 52) of the silicon film 50, and the portion is exposed.

[0058] As a modification of the second film formation step S150, the barrier coating 160 may be formed with a uniform thickness on the entire inner surface of the trench 5, including the bottom surface 5b, by ALD, and then only the barrier coating 160 on the bottom coating 52 may be removed by reactive ion etching (RIE). In this case, in the precursor adsorption step, the precursor is adsorbed onto the entire inner surface of the trench 5. As a result, in the film formation step, a barrier coating is formed on the entire inner surface of the trench 5.

[0059] 20 is a schematic diagram of the first oxidation step S160 of this embodiment. The first oxidation step S160 is a step of thermally oxidizing the silicon coating 50 from the surface side to form a first oxide coating (third coating) 180. Silicon nitride (SiN) constituting the barrier coating 160 is a silicon oxide (SiO ２) has a smaller oxygen diffusion coefficient than that of the barrier coating 160. Therefore, in the first oxidation step S160, the thermal oxidation progresses more slowly below the barrier coating 160. Therefore, in the first oxidation step S160, the thickness T6 of the first portion 180a of the first oxide coating 180 formed below the barrier coating 160 is smaller than the thickness T7 of the second portion 180b exposed from the barrier coating 160. In this embodiment, only a portion of the silicon coating 50 below the barrier coating 60 on the boundary side with the barrier coating 60 becomes the first oxide coating 180. On the other hand, the silicon coating 50 exposed from the barrier coating 160 is oxidized throughout its entire thickness to become the first oxide coating 180.

[0060] In this embodiment, the case where silicon nitride is used as the barrier coating 160 has been described, but if the barrier coating 160 has an oxygen diffusion coefficient smaller than that of silicon oxide, a similar first oxide coating 180 can be formed.

[0061] 21 and 22 are schematic diagrams of the etching step S170 of this embodiment. The etching step S170 of this embodiment includes a first etching step S171 and a second etching step S172 shown in FIG. 21 , and a third etching step S173 shown in FIG. 22 . As shown in FIG. 21 , the first etching step S171 and the second etching step S172 are steps of etching and removing the barrier coating 160 and a portion of the first oxide coating 180. Furthermore, as shown in FIG. 22 , the third etching step S173 is a step of etching and removing the silicon coating 50. That is, in the etching step S170 of this embodiment, etching to remove the barrier coating 160 made of silicon nitride, etching to remove the first oxide coating 180 made of silicon oxide, and etching to remove the silicon coating 50 made of silicon are performed in stages.

[0062] As shown in FIG. 21 , in the first etching step S171, the barrier film 160 is entirely removed. Furthermore, in the second etching step S172, only the first portion 180a of the first oxide film 180 is etched away by a thickness T6. Therefore, after the second etching step S172, only the first oxide film 180 remains on the inner surface of the trench 5 in the lower region of the sidewall surface 5a and the bottom surface 5b, and only the silicon film 50 remains in the upper region of the sidewall surface 5a. As shown in FIG. 22 , in the third etching step S173, the silicon film 50 is entirely removed. After the etching step S170, only the first oxide film 180 remains in the trench 5.

[0063] 23 and 24 are schematic diagrams of the oxide film forming step S180. The oxide film forming step S180 is a step of forming a silicon oxide (SiO ２ 24. The oxide film forming step S180 of this embodiment includes a third film forming step S181 shown in FIG. 23 and a second oxidation step S182 shown in FIG. 24.

[0064] 23, the third film-forming step S181 is a step of forming a silicon coating 155 made of silicon (Si) and having a uniform thickness on the surface of the substrate 10. In the third film-forming step S181, the silicon coating 155 is formed by, for example, a low-pressure CVD method (LP-CVD).

[0065] As shown in FIG. 24 , the second oxidation step S182 is a step of thermally oxidizing the silicon film 155 formed in the third film formation step S181 to form a second oxide film 159. The second oxidation step S182 is performed at a temperature at which silicon is thermally oxidized but silicon carbide is not substantially thermally oxidized. Through the second oxidation step S182, a first oxide film 180 and a second oxide film 159 derived from the silicon film 155 are formed on the inner surface of the trench 5. The first oxide film 180 and the second oxide film 159 form the insulating film 130. As described above, the first oxide film 180 remains only on the bottom surface 5 b of the trench 5 and on the sidewall surfaces 5 a near the bottom surface 5 b. Therefore, after the oxide film formation step S180, a locally thick insulating film 130 is formed on the inner surface of the trench 5 in the lower regions of the bottom surface 5 b and the sidewall surfaces 5 a.

[0066] According to the manufacturing method of the semiconductor device 1 of this embodiment, it is possible to form an insulating film 130 with a locally thick film thickness on the inner surface of the trench 5. This makes it possible to improve the insulating performance of the thickly formed portion compared to the thinly formed portion, and to manufacture a semiconductor device 1 that is small and has excellent withstand voltage. Furthermore, according to this embodiment, a coating formed by CVD is not used as the insulating film 130, and it is possible to form a locally thick insulating film 130 with reduced impurity contamination compared to when an insulating film is formed by CVD.

[0067] In the manufacturing method of the semiconductor device 1 of this embodiment, as shown in Fig. 20, in the second film-forming step S150, the barrier coating 160 is provided only in the upper region of the sidewall coating 51, but not in the lower region. Therefore, as shown in Fig. 24, the insulating film 130 that is finally formed has a stepped shape on the sidewall surface 5a of the trench 5, which further improves the insulating properties of the corners of the trench 5. However, by providing the barrier coating 160 over the entire sidewall coating 51 in the second film-forming step S150, an insulating film 30 having a uniform film thickness on the sidewall surface 5a may be formed.

[0068] The configuration of the second embodiment will be summarized below. According to the manufacturing method of the semiconductor device 1 of this embodiment, in the second film formation step S150, the silicon coating 50 (i.e., the sidewall coating 51) provided on the sidewall surface 5a of the trench 5 is covered with the barrier coating 160, and the silicon coating 50 (i.e., the bottom coating 52) provided on the bottom surface 5b of the trench 5 is exposed from the barrier coating 160. This configuration allows the barrier coating 160 to be formed on the sidewall surface 5a of the trench 5, and allows the silicon coating 50 and the barrier coating 160 to form a coating that is locally thick on the sidewall surface 5a of the trench 5.

[0069] As in the first embodiment (see FIG. 2 ), the method for manufacturing the semiconductor device 1 of this embodiment includes a trench formation step S30 of forming a trench 5 in the substrate 10 before the first film formation step S40. As shown in FIG. 19 , the portion of the silicon coating 50 on which the barrier coating 160 is not formed (or on which only a thin barrier coating is formed) is the portion that is formed on the bottom surface 5 b of the trench 5. The other portion of the silicon coating 50 on which the barrier coating 160 is formed is the portion that is formed on the sidewall surface 5 a of the trench 5. In this way, the region on which the barrier coating 160 is formed may be selected to locally thicken the film thickness of the insulating film 130.

[0070] In the manufacturing method of the semiconductor device 1 of this embodiment, the barrier coating 160 has a smaller oxygen diffusion coefficient than silicon oxide. With this configuration, in the first oxidation step S160, the first oxide coating 180 can be formed thinly under the barrier coating 160 and thickly in the portion exposed from the barrier coating 160, as shown in FIG.

[0071] In the above-described embodiments and their modifications, the film thickness of the insulating film 30, 30A, 130 on the bottom surface 5b of the trench 5 is locally thickened compared to other portions. However, by using a similar technique, it is also possible to locally thicken the insulating film near the opening of the trench 5. Furthermore, a locally thick insulating film can be formed even in a structure that does not have a trench 5.

[0072] Furthermore, the above-described embodiments and their variations can be combined with each other. As an example, a barrier coating made of the material (silicon nitride) described in the second embodiment may be provided in the position of the barrier coating described in the first embodiment. Similarly, a barrier coating made of the material (silicon oxide) described in the first embodiment may be provided in the position of the barrier coating described in the second embodiment. In these cases, for example, an insulating film can be formed in which the thicknesses of the bottom and sidewall portions are reversed.

[0073] According to at least one of the embodiments described above, the barrier coatings 60, 60A, 160 can be used to form coatings of different thicknesses on the surface of the substrate 10, thereby forming locally thick insulating films 30, 30A that suppress the inclusion of impurities.

[0074] The present invention includes the following supplementary aspects: (Supplementary Note 1) A method for manufacturing a semiconductor device, comprising: a first film formation step of forming a first coating made of silicon on a surface of a base material made of silicon carbide; a second film formation step of forming a second coating on the surface of the first coating; and an oxidation step of thermally oxidizing the first coating from the surface side to form a third coating, wherein in the second film formation step, the second coating is not formed on a portion of the first coating, leaving the portion exposed, or the thickness of the second coating formed on the portion of the first coating is smaller than the thickness of the second coating formed on other portions. (Supplementary Note 2) The method for manufacturing a semiconductor device according to Supplementary Note 1, comprising: an etching step of etching the second coating and at least a portion of the third coating; and an oxide film formation step of forming a fourth coating made of silicon oxide on the surface of the base material. (Supplementary Note 3) The method for manufacturing a semiconductor device according to Supplementary Note 1 or 2, further comprising a trench formation step of forming a trench in the substrate before the first film formation step, wherein the portion of the first coating is a portion formed on a sidewall surface of the trench, and the other portion of the first coating is a portion formed on a bottom surface of the trench. (Supplementary Note 4) The method for manufacturing a semiconductor device according to Supplementary Note 1 or 2, further comprising a trench formation step of forming a trench in the substrate before the first film formation step, wherein the portion of the first coating is a portion formed on a bottom surface of the trench, and the other portion of the first coating is a portion formed on a sidewall surface of the trench. (Supplementary Note 5) The method for manufacturing a semiconductor device according to any one of Supplementary Notes 1 to 4, wherein the second film formation step is a step of forming the second coating by atomic layer deposition. (Supplementary Note 6) The method for manufacturing a semiconductor device according to any one of Supplementary Notes 1 to 5, wherein the second coating is silicon oxide. (Supplementary Note 7) The method for manufacturing a semiconductor device according to any one of Supplementary Notes 1 to 5, wherein the second coating has a smaller oxygen diffusion coefficient than silicon oxide.

[0075] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents.

[0076] DESCRIPTION OF SYMBOLS 1...Semiconductor device, 5...Trench, 5a...Side wall surface, 5b...Bottom surface, 10...Base material, 12...Layer, 30, 130...Insulating film (fourth film), 50...Silicon film (first film) film), 60,160...barrier film (second film), 80,180...first oxide film (third film), S30...trench formation step, S40...first film formation step, S5 0, S150...second film formation step, S53, S152...film formation step, S60...first oxidation step (oxidation step), S70, S170...etching step, S80...th 2 oxidation step (oxide film formation step), S180... oxide film formation step, T1, T2, T3, T4, T6, T7, TA, T5a, T5b, TCa, TCb... film thickness

Claims

1. A method for manufacturing a semiconductor device, comprising: a first film formation step of forming a first coating made of silicon on the surface of a substrate made of silicon carbide; a second film formation step of forming a second coating on the surface of the first coating; and an oxidation step of thermally oxidizing the first coating from the surface side to form a third coating, wherein in the second film formation step, the second coating is not formed on a portion of the first coating, leaving the portion exposed, or the thickness of the second coating formed on the portion of the first coating is smaller than the thickness of the second coating formed on other portions.

2. A method for manufacturing a semiconductor device as described in claim 1, comprising: an etching step of etching the second coating and at least a portion of the third coating; and an oxide coating formation step of forming a fourth coating made of silicon oxide on the surface of the substrate.

3. A method for manufacturing a semiconductor device as described in claim 1, further comprising a trench formation step of forming a trench in the substrate prior to the first film formation step, wherein the portion of the first coating is a portion formed on a sidewall surface of the trench, and the other portion of the first coating is a portion formed on a bottom surface of the trench.

4. A method for manufacturing a semiconductor device as described in claim 1, further comprising a trench formation step of forming a trench in the substrate prior to the first film formation step, wherein the portion of the first coating is a portion formed on a bottom surface of the trench, and the other portion of the first coating is a portion formed on a sidewall surface of the trench.

5. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the second film forming step is a step of forming the second coating by atomic layer deposition.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the second coating is silicon oxide.

7. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the second coating has a smaller oxygen diffusion coefficient than silicon oxide.

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