Electronic circuit board and pad-on-via arrangement method

Abstract

This electronic circuit board, in which a plurality of insulating layers and a plurality of wiring layers are alternately laminated, has a pad-on-via which has formed therein a pad for soldering an electronic component having electrodes formed on at least the lower surface or a side surface thereof, and in which the pad and a wiring layer positioned below the pad, and at least one wiring layer interval positioned below said wiring layer are electrically connected by a plurality of vias. In addition, in a plan view, a via in direct electrical connection with at least the pad among the plurality of vias constituting the pad-on-via is disposed at a position overlapping an electrode formed on the lower surface of the electronic component, or a via located below the via in direct electrical connection with the pad among the plurality of vias constituting the pad-on-via is disposed at a position not overlapping with the via in direct electrical connection with the pad.

Description

Electronic circuit board and pad-on-via layout method

[0001] The present invention relates to an electronic circuit board to which electronic components are soldered, and a pad-on-via arrangement method.

[0002] In recent years, there has been an increasing demand for pad-on-vias as described in International Publication No. WO 2012 / 124421 (Patent Document 1) for electronic circuit boards due to the need to improve the packaging density of electronic components or to adopt narrow-pitch ball grid arrays (BGAs). A pad-on-via is a via formed in a pad on the surface of an electronic circuit board, which is a through-hole for electrical connection. The inner surface of the via is copper-plated for electrical connection.

[0003] International Publication No. 2012 / 124421

[0004] In the pad-on-via described in Patent Document 1, a via is formed approximately at the center of a pad on an electronic circuit board. In this case, when the temperature of an electronic circuit board on which an electronic component is mounted changes, tensile stress is generated in the solder fillet located above the pad-on-via in the Z direction perpendicular to the surface of the electronic circuit board due to the difference in the linear expansion coefficient between the electronic circuit board and the via. If this tensile stress is repeatedly generated, the solder fillet gradually fatigues, potentially causing a crack originating from the pad-on-via. If a void occurs at the same position as the crack in the solder fillet for some reason, the crack may grow toward the void, potentially damaging the electrical connection between the pad on the electronic circuit board and the electrode of the electronic component.

[0005] Therefore, an object of the present invention is to provide an electronic circuit board and a pad-on-via arrangement method that can suppress the growth of cracks that occur in solder fillets in an electronic circuit board on which pad-on-vias are formed.

[0006] An electronic circuit board in which multiple insulating layers and multiple wiring layers are alternately laminated has pads formed on at least the bottom and side surfaces for soldering electronic components having electrodes formed thereon, and has pad-on-vias in which the pads, the wiring layers located thereunder, and at least one wiring layer located below the wiring layers are electrically connected by multiple vias. Of the multiple vias constituting the pad-on-vias, at least the vias that are directly connected to the pads are arranged in positions that overlap, in a plan view, with the electrodes formed on the bottom surfaces of the electronic components.

[0007] Furthermore, an electronic circuit board in which a plurality of insulating layers and a plurality of wiring layers are alternately laminated has pads formed on at least the bottom and side surfaces for soldering electronic components having electrodes formed thereon, and has pad-on-vias in which the pads, the wiring layers located thereunder, and at least one wiring layer located thereunder are electrically connected by a plurality of vias. Of the plurality of vias constituting the pad-on-vias, vias located in a layer below a via directly connected to a pad are arranged in positions that do not overlap the via directly connected to the pad in a plan view.

[0008] According to the present invention, it is possible to suppress the growth of cracks that occur in solder fillets in an electronic circuit board on which pad-on-vias are formed.

[0009] Fig. 1 is a cross-sectional view showing an example of an electronic circuit board having pad-on-via in the prior art; Fig. 2 is an explanatory diagram of distortion occurring in an electronic circuit board in the prior art; Fig. 3 is a cross-sectional view showing a state in which voids have occurred in a solder fillet; Fig. 4 is a cross-sectional view showing an example of an electronic circuit board that solves the problems of the prior art; Fig. 5 is a cross-sectional view showing another example of an electronic circuit board that solves the problems of the prior art; Fig. 6 is a cross-sectional view showing an example of an electronic circuit board that suppresses the occurrence of voids;

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, referring to FIG. 1, a conventional electronic circuit board 100 having pad-on-vias and its problems will be described.

[0011] The electronic circuit board 100 has a laminated structure in which multiple insulating layers 120 and multiple wiring layers 140 are alternately stacked, and pads 160 are formed on at least one surface thereof for soldering electronic components EC, such as chip components. Each insulating layer 120 may be, for example, a glass epoxy substrate made of woven glass fiber and impregnated with epoxy resin. Each wiring layer 140 is, for example, a wiring pattern made of copper foil formed on the surface of the insulating layer 120, and is formed through a well-known process. The pad 160 is, for example, made of copper foil formed on one surface of the insulating layer 120, and the electronic component EC is solder-bonded to its upper surface using a well-known method. An electrode ER formed on the end of the electronic component EC is solder-bonded to the upper surface of the pad 160 via a solder fillet SF. The electrodes ER of the electronic component EC may be formed on at least the bottom and side surfaces of the end of the electronic component EC.

[0012] Approximately at the center of the pad 160, specifically at a position overlapping the electrode ER formed on the side surface of the electronic component EC in a plan view, a pad-on-via 180 is formed in the form of a three-layer blind via, penetrating from the surface of the pad 160 to the three underlying wiring layers 140 for electrical connection. The pad-on-via 180 is formed, for example, by drilling or laser processing to form a via hole in the pad 160, the underlying insulating layer 120, and the underlying wiring layer 140, and then copper plating the inner surface of the via hole. The number of layers of the pad-on-via 180 is not limited to three as shown in FIG. 1 , but can be any number, such as at least one layer (as in this embodiment). Furthermore, the pad-on-via 180 is not limited to a blind via, but may also be a through-hole via (as in this embodiment).

[0013] The coefficient of linear expansion of the via (copper) constituting the pad-on-via 180 is 16.8×10 －６ / K, and the linear expansion coefficient of the insulating layer 120 (glass epoxy resin) is 40.0×10 －６ / K. Therefore, when the temperatures of the insulating layer 120 and the pad-on-via 180 of the electronic circuit board 100 rise in the thickness direction of the electronic circuit board 100 (the direction perpendicular to the board surface), the pad-on-via 180 shrinks relative to the insulating layer 120, as shown in FIG. 2 . When the pad-on-via 180 shrinks relative to the insulating layer 120, tensile stress is generated in the solder fillet SF located above the pad-on-via 180. When the temperature of the electronic circuit board 100 repeatedly rises and falls, the solder fillet SF gradually fatigues, and cracks may occur in the solder fillet SF.

[0014] 3, the electronic circuit board 100 to which the electronic component EC is solder-bonded has minute recesses on the surface of the pad-on-via 180, which means that for some reason, voids VD are likely to occur in the solder fillet SF located above the pad-on-via 180. Therefore, if a crack occurs in the solder fillet SF located above the pad-on-via 180 when a void VD has occurred in the solder fillet SF, the crack may grow toward the void VD, potentially damaging the electrical connection between the pad 160 of the electronic circuit board 100 and the electrode ER of the electronic component EC.

[0015] Therefore, in this embodiment, by adopting a configuration described in detail below, the growth of cracks occurring in the solder fillet SF located above the pad-on-via 180 is suppressed even when temperature changes are repeated. In the following description, components common to the prior art will be assigned the same reference numerals and their description will be omitted. Please refer to the description of the prior art if necessary.

[0016] FIG. 4 shows an example of an electronic circuit board 100 according to this embodiment. The electronic circuit board 100 employs a laminated structure in which multiple insulating layers 120 and multiple wiring layers 140 are alternately stacked, as in the prior art. Pads 160 are formed at predetermined locations on the electronic circuit board 100 for soldering electronic components EC, each having electrodes ER formed on at least its bottom and side surfaces. The electronic circuit board 100 also includes a three-layer pad-on-via structure 200, in which the pads 160, the underlying wiring layer 140, and at least one underlying wiring layer 140 are electrically connected by multiple vias VA. Here, the electronic components EC may be chip components such as chip resistors and chip capacitors.

[0017] Among the multiple vias VA constituting the pad-on-via 180, at least the via VA that is directly conductive with the pad 160 is arranged at a position that overlaps with an electrode ER formed on the underside of the electronic component EC in a plan view. This pad-on-via 200 is formed in the same manner as the conventional technology, for example, by forming a via hole in the pad 160 and the insulating layer 120 and wiring layer 140 arranged thereunder by drilling or laser processing, and then copper plating the inner surface of the via hole.

[0018] By arranging the pad-on-via 200 in this position, even if a crack occurs in the solder fillet SF located above the pad-on-via 200 through a process similar to that of the conventional technology, the range of the crack is limited to the range of the electrode ER formed on the underside of the electronic component EC. In this case, because the distance from the pad-on-via 200 to the electrode ER formed on the side surface of the electronic component EC is relatively long, a crack occurring in the solder fillet SF is less likely to extend to the electrode ER formed on the side surface of the electronic component EC in a plan view. As a result, even if a crack occurs in the solder fillet SF, the electrode ER formed on the side surface of the electronic component EC ensures electrical connection with the pad 160, thereby preventing damage to the electrical connection between the pad 160 of the electronic circuit board 100 and the electrode ER of the electronic component EC.

[0019] Furthermore, even if a crack occurs in the solder fillet SF located above the pad-on-via 200 when a void VD has occurred in the solder fillet SF located above the pad-on-via 200, the void VD and crack occur within a limited range, which provides the following effect: That is, the void VD and crack occur in the solder fillet SF located between the pad 160 of the electronic circuit board 100 and the electrode ER formed on the underside of the electronic component EC, so the crack does not grow toward the void VD. In this case, a crack occurs in the solder fillet SF within this range, but it does not grow to the electrode ER formed on the side surface of the electronic component EC, and the electrode ER can ensure electrical connection with the pad 160.

[0020] In short, by optimizing the arrangement position of the pad-on-via 200, the range of cracks that occur due to repeated temperature changes is limited to the solder fillet SF located between the pad 160 of the electronic circuit board 100 and the electrode ER formed on the underside of the electronic component EC. This suppresses the growth of cracks that occur in the solder fillet SF, making it possible to maintain the electrical connection between the electrode ER of the electronic component EC and the pad 160 of the electronic circuit board 100 for a long period of time.

[0021] Here, it is desirable that, among the multiple vias VA constituting the pad-on-via 200, at least the vias VA that are directly conductive with the pad 160 are arranged in a position that avoids the electrodes ER formed on the side surfaces of the electronic component EC in a plan view. In this way, the region where cracks occur is further limited, and the effects and advantages of this embodiment can be effectively achieved.

[0022] 5 shows another example of the electronic circuit board 100 according to this embodiment. In the electronic circuit board 100, of the multiple vias VA constituting the pad-on-via 220, at least the via VA that is in direct conduction with the pad 160 is arranged in the following position of the solder fillet SF that solder-joins the pad 160 and the electrode ER of the electronic component EC. That is, in a plan view, this via VA is arranged outside the solder fillet SF that is located at the end in the direction from the electrode ER formed on the side surface of the electronic component EC to the electrode ER formed on its underside, or in a position where it partially overlaps with the solder fillet SF.

[0023] Furthermore, if the pad-on-via 220 is positioned outside the solder fillet SF, there is no solder fillet SF above the pad-on-via 220, and therefore no voids VD will occur in the solder fillet SF located there. Furthermore, if the pad-on-via 220 is positioned so that it partially overlaps the solder fillet SF, even if voids VD occur in the solder fillet SF, an escape route for the voids VD is ensured, thereby suppressing the occurrence of voids VD. When this configuration is adopted, via fill plating that fills the interior of the via VA that is directly conductive with the pad 160, among the multiple vias VA that make up the pad-on-via 220, can be omitted. In this case, since via fill plating is not applied to the vias VA, costs can also be reduced.

[0024] 6 shows yet another example of the electronic circuit board 100 according to this embodiment. Based on the electronic circuit board 100 shown in FIG. 4 , a pad-on-via 240 in the form of a three-layer blind via is formed so that the two vias VA located in the uppermost layer do not overlap in a planar view. Specifically, among the multiple vias VA constituting the pad-on-via 240, the via VA located in the layer below the via VA directly conducting with the pad 160 is positioned so that it does not overlap the via VA directly conducting with the pad 160 in a planar view. In this case, since the two vias VA located in the uppermost layer are positioned at offset positions in a planar view, the insulating layer 120 in the uppermost layer and the insulating layer 120 located below it, as well as the wiring layer 140 respectively located between the insulating layer 120 and the insulating layer 120 located below it, are formed longer than the wiring layer 140 of the electronic circuit board 100 shown in FIG. 4 .

[0025] In this way, the total length of the via VA located directly below the pad 160 is shortened, and the amount of change in the via VA that expands and contracts due to temperature changes is reduced, thereby reducing the tensile stress generated in the solder fillet SF located above the pad-on-via 240. Therefore, in addition to the action and effect due to the arrangement position of the pad-on-via 240, the tensile stress generated in the solder fillet SF located above the pad-on-via 240 is further reduced, making it less likely for cracks to occur in the solder fillet SF.

[0026] 6, it is desirable that the via VA located in the layer below the via VA that is in direct electrical contact with the pad 160 is located at a position that is at least the diameter of the via VA from the via VA that is in direct electrical contact with the pad 160 within the range of the pad 160 in a planar view. In this way, of the multiple vias VA that make up the pad-on-via 240, the via VA that is in direct electrical contact with the pad 160 and the via VA located in the layer below it are located at positions that do not completely overlap each other in a planar view, thereby minimizing the tensile stress that occurs in the solder fillet SF due to temperature changes.

[0027] Those skilled in the art will readily understand that new embodiments can be created by omitting parts of the technical ideas of the various above-described embodiments, combining parts of the ideas appropriately, or replacing parts of the ideas with well-known technology.

[0028] For example, the electronic circuit board 100 is not limited to a single-sided board in which the pads 160 are formed on only one side, but may be a double-sided board in which the pads 160 are formed on both sides. Furthermore, the electronic component EC is not limited to a chip component, but may be a well-known electronic component in which electrodes are arranged at least on the bottom surface and side surfaces of the end portion.

[0029] Furthermore, the pad-on-via 240 as shown in Fig. 6 can be applied not only to the electronic circuit board 100 as shown in Fig. 4 but also to the electronic circuit board 100 as shown in Fig. 5 and the conventional electronic circuit board 100 as shown in Fig. 1. In this case, when applied to the conventional electronic circuit board 100 as shown in Fig. 1, the position at which cracks occur in the solder fillet SF is not limited, but the occurrence of cracks is suppressed by reducing the tensile stress, so that the original purpose can be achieved.

[0030] 100...electronic circuit board, 120...insulating layer, 140...wiring layer, 160...pad, 200...pad-on-via, 220...pad-on-via, 240...pad-on-via, EC...electronic component, ER...electrode, SF...solder fillet, VA...via

Claims

1. An electronic circuit board having a plurality of insulating layers and a plurality of wiring layers alternately stacked, with pads formed on at least the bottom and side surfaces for soldering electronic components having electrodes formed thereon, and having pad-on-vias electrically connecting the pads, the wiring layer located below the pads, and at least one wiring layer located below the wiring layer by a plurality of vias, wherein at least one of the vias constituting the pad-on-vias that is directly conductive with the pads is positioned so as to overlap, in a plan view, with an electrode formed on the bottom surface of the electronic component.

2. The electronic circuit board according to claim 1, wherein at least one of the vias constituting the pad-on-via that is in direct electrical contact with the pad is positioned to avoid electrodes formed on the side surface of the electronic component in a plan view.

3. The electronic circuit board according to claim 1, wherein at least one of the vias constituting the pad-on-via that is in direct electrical contact with the pad is disposed, in a plan view, outside a solder fillet located at the end in the direction from the electrode formed on the side surface of the electronic component to the electrode formed on the underside thereof, or in a position that overlaps partially with the solder fillet.

4. The electronic circuit board according to claim 3, wherein via-fill plating that fills the interior of said via is omitted from a via that is directly conductive with said pad among a plurality of vias that constitute said pad-on-via.

5. The electronic circuit board according to claim 1, wherein among the multiple vias constituting the pad-on-via, a via located in a layer below a via that directly conducts with the pad is arranged in a position that does not overlap the via that directly conducts with the pad in a plan view.

6. The electronic circuit board according to claim 5, wherein a via located in a layer below a via that directly conducts with said pad is disposed at a position at least the diameter of said via within the range of said pad in a plan view from the via that directly conducts with said pad.

7. The electronic circuit board according to claim 1, wherein the insulating layer is made of a glass epoxy substrate.

8. The electronic circuit board according to claim 1, wherein the plurality of vias constituting the pad-on-via are made of copper.

9. An electronic circuit board having a plurality of insulating layers and a plurality of wiring layers alternately stacked, with pads formed on at least the bottom and side surfaces for soldering electronic components having electrodes formed thereon, and having pad-on-vias electrically connecting the pads, the wiring layer located therebelow, and at least one of the wiring layers located below the wiring layer by a plurality of vias, wherein, of the plurality of vias constituting the pad-on-vias, vias located below a via that directly conducts with the pad are positioned so as not to overlap the via that directly conducts with the pad in a planar view.

10. The electronic circuit board according to claim 9, wherein a via located in a layer below a via that directly conducts with said pad is disposed at a position at least the diameter of the via that directly conducts with said pad within the range of said pad in a plan view.

11. A method for arranging pads on an electronic circuit board in which a plurality of insulating layers and a plurality of wiring layers are alternately stacked, pads are formed for soldering electronic components having electrodes formed on at least the bottom and side surfaces, and the pads, the wiring layer located below the pads, and at least one of the wiring layers located below the wiring layers are electrically connected by a plurality of vias, the method comprising arranging at least one via that is directly conductive with the pad among the plurality of vias constituting the pad-on-via in a position that overlaps with an electrode formed on the bottom surface of the electronic component in a planar view.

12. The pad-on-via arrangement method according to claim 11, further comprising arranging at least one of the vias constituting the pad-on-via, the via that is in direct electrical communication with the pad, at a position that avoids electrodes formed on a side surface of the electronic component in a plan view.

13. A pad-on-via arrangement method as described in claim 11, wherein at least one of the vias constituting the pad-on-via that is in direct electrical contact with the pad is arranged, in a plan view, outside a solder fillet located at an end in a direction from an electrode formed on a side surface of the electronic component to an electrode formed on its underside, or in a position where it partially overlaps with the solder fillet.

14. A method for arranging pads on an electronic circuit board in which a plurality of insulating layers and a plurality of wiring layers are alternately stacked to form pads for soldering electronic components having electrodes formed on at least the bottom and side surfaces, and the pads, the wiring layer located below the pads, and at least one wiring layer located below the wiring layer are electrically connected by a plurality of vias, the method comprising: arranging, among the plurality of vias constituting the pads, vias located below a via that directly conducts with the pads, in a position that does not overlap with the via that directly conducts with the pads in a planar view.

15. The pad-on-via arrangement method according to claim 14, further comprising arranging a via located in a layer below the via that is in direct electrical contact with the pad at a position at least the diameter of the via that is in direct electrical contact with the pad within the range of the pad in a plan view.

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