Silicon carbide semiconductor wafer, silicon carbide semiconductor device, and method for manufacturing silicon carbide single crystal

Abstract

Provided is an SiC wafer constituting an SiC substrate 11 constituted from n-type SiC doped with n-type impurities, wherein B is included in the SiC substrate 11, and the B concentration in the SiC substrate 11 is 9.0×1016 / cm3 or greater.

Description

Silicon carbide semiconductor wafer, silicon carbide semiconductor device, and method for manufacturing silicon carbide single crystal CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Japanese Patent Application No. 2023-120242, filed on July 24, 2023, the contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a silicon carbide (hereinafter referred to as SiC) semiconductor wafer, a SiC semiconductor device, and a method for manufacturing a SiC single crystal.

[0003] Due to its excellent semiconductor properties, SiC is being put to practical use as a material for various semiconductor devices such as automotive power devices. However, SiC single crystal substrates contain wavy dislocations called basal plane dislocations (hereinafter referred to as BPDs), which have dislocation lines on the (0001) plane.

[0004] When an epitaxial film is grown on such a SiC single crystal substrate to form a SiC semiconductor device equipped with a switching element such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a built-in diode is formed. When this SiC semiconductor device is applied to an inverter circuit or the like, and the built-in diode operates in bipolar mode due to reflux during switching, BPDs may expand into Shockley stacking faults (hereinafter referred to as SSFs). Specifically, holes passing near BPDs recombine with electrons in the n-type layer, generating large recombination energy, which causes BPDs to expand into SSFs. SSFs occupy a larger area than BPDs and are more likely to degrade the electrical characteristics of SiC semiconductor devices. Therefore, it is desirable to suppress the expansion of BPDs into SSFs.

[0005] Meanwhile, a technology for suppressing the expansion of BPDs into SSFs has been proposed in Patent Document 1. In this technology, when manufacturing a SiC semiconductor device in which an epitaxial film is disposed on one surface of a SiC single crystal substrate, p-type impurities are mixed into the ingot used to form the n-type SiC single crystal substrate during production. This improves the crystallinity within the SiC single crystal substrate, and increases the energy required for the expansion of BPDs into SSFs, thereby suppressing the expansion of BPDs into SSFs.

[0006] Japanese Patent Application Laid-Open No. 2021-57381

[0007] However, although the incorporation of p-type impurities into a SiC single crystal substrate can suppress the expansion of BPDs into SSFs, this effect cannot be sufficiently obtained depending on the current flowing through the built-in diode provided in the SiC semiconductor device. An object of the present disclosure is to provide a silicon carbide semiconductor wafer, a silicon carbide semiconductor device, and a method for manufacturing a silicon carbide single crystal that can suppress the expansion of BPDs into SSFs.

[0008] One aspect of the present disclosure is a SiC wafer constituting a SiC substrate made of n-type SiC doped with an n-type impurity, wherein the SiC substrate contains B (boron), and the B concentration in the SiC substrate is 9.0×10 １６ / cm ３ That is said to be the case.

[0009] In this way, while introducing B into the n-type SiC substrate, the B concentration is limited to 9.0×10 １６ / cm ３ This makes it possible to prevent the BPD from expanding into the SSF.

[0010] Another aspect of the present disclosure is a trench gate structure comprising: a SiC substrate made of n-type SiC doped with n-type impurities; an n-type low-concentration layer formed on the SiC substrate and having a lower n-type impurity concentration than the SiC substrate; a p-type deep layer formed on the low-concentration layer and having a plurality of linear portions longitudinally extending in one plane direction of the SiC substrate; an n-type JFET section disposed on the low-concentration layer and having linear portions sandwiched between the deep layers; a p-type base region disposed on the JFET section and the deep layer; an n-type source region formed in a surface layer portion of the base region; a gate insulating film formed on a wall surface of a gate trench penetrating the source region and the base region; and a gate electrode formed on the gate insulating film; a source electrode electrically connected to the source region and the base region; and a drain electrode electrically connected to the SiC substrate, A built-in diode is formed by a pn junction including the deep layer, the JFET portion, and the low concentration layer, and the current density of the current flowing when the built-in diode operates as a reflux junction is 11.6 A / mm ２ or more, the SiC substrate contains B, and the B concentration in the SiC substrate is 9.0×10 １６ / cm ３ That is said to be the case.

[0011] In this way, the current density of the current flowing when the built-in diode operates as a freewheel is 11.6 A / mm ２ In applications where the B concentration in the SiC substrate is 9.0×10 １６ / cm ３ This makes it possible to prevent the BPD from expanding into the SSF.

[0012] Another aspect of the present disclosure is a method for producing an n-type SiC single crystal, the method comprising: arranging a seed crystal for growing an SiC single crystal on one surface of a pedestal placed in a growth crucible; and supplying a pyrolyzed SiC raw material, an n-type dopant, and B to the surface of the seed crystal, thereby producing an SiC ingot composed of an n-type SiC single crystal on the surface of the seed crystal, wherein, in growing the SiC ingot, a B concentration in the SiC ingot is increased to 9.0×10 １６ / cm ３ That's all.

[0013] In this way, when producing n-type SiC single crystals, the B concentration in the SiC ingot is 9.0 × 10 １６ / cm ３ For this reason, when a SiC wafer sliced ​​from a SiC ingot is used, the current density of the current flowing when the built-in diode operates as a reflux rectifier is set to 11.6 A / mm ２ When a vertical MOSFET having the above structure is manufactured, it is possible to suppress the expansion of BPD into SSF.

[0014] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below.

[0015] 10A is a perspective cross-sectional view of a SiC semiconductor device described in a first embodiment; FIG. 10B is an explanatory diagram of a current path in a SiC semiconductor device; FIG. 10C is an explanatory diagram showing the state of holes and electrons near a built-in diode; FIG. 10D is an explanatory diagram of defect growth due to BPD near a built-in diode; FIG. 10E is a binarized image of a photoluminescence (PL) image confirming the degree of SSF expansion by non-destructive testing using a PL method; FIG. 10F is a diagram showing the relationship between the B concentration, the area occupancy rate of SSF, and the amount of warpage of a SiC wafer; FIG. 10G is a diagram showing the change in hole density for each portion near a buffer layer when the B concentration in a SiC substrate is changed; FIG. 10H is a diagram showing the change in hole density at the interface between a SiC substrate and a buffer layer with respect to the B concentration; FIG. 10I is a diagram showing the relationship between the B concentration and the electrical stress at which the SSF becomes 3% when there is no drop in n-type impurity concentration and the electrical stress at which the SSF becomes 3% when there is a drop in n-type impurity concentration; FIG. 10I is a diagram showing the N concentration of a SiC substrate, a buffer layer, and a low-concentration layer; FIG. 10I is a cross-sectional view showing a manufacturing process of the SiC semiconductor device shown in FIG. 10A is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 10A is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 10B. A cross-sectional view showing a manufacturing process of a SiC semiconductor device subsequent to FIG. 10B. A cross-sectional view showing a manufacturing process of a SiC semiconductor device shown in FIG. 10C. A cross-sectional view showing a manufacturing process of a SiC semiconductor device subsequent to FIG. 10D. A cross-sectional view showing a manufacturing process of a SiC semiconductor device subsequent to FIG. 10E. A cross-sectional view showing a manufacturing process of a SiC semiconductor device subsequent to FIG. 10F. A diagram showing the amount of warpage of a plurality of SiC wafer samples before an element formation process and after a deep layer formation process. A diagram schematically showing a state in which SiC wafers are sliced ​​and cut out from a SiC ingot. A diagram showing the relationship between the B concentration and the amount of warpage in a 6-inch wafer. A diagram showing the relationship between the B concentration and the amount of warpage in an 8-inch wafer. A perspective cross-sectional view of a SiC semiconductor device described in a second embodiment. A cross-sectional view showing a manufacturing process of the SiC semiconductor device shown in FIG. 14. A cross-sectional view showing a manufacturing process of a SiC semiconductor device subsequent to FIG. 15A. A cross-sectional view showing a manufacturing process of a SiC semiconductor device subsequent to FIG. 15B. A cross-sectional view showing a manufacturing process of a SiC semiconductor device shown in FIG. 15C. A cross-sectional view showing a manufacturing process of a SiC semiconductor device subsequent to FIG. 15D. A cross-sectional view showing a manufacturing process of a SiC semiconductor device subsequent to FIG. 15E.1 is a cross-sectional view showing the growth of a SiC ingot in a growth crucible; 2 is a graph showing the content of various impurity elements contained in a SiC substrate; 3 is a graph showing the content of various impurity elements contained in a raw material powder; 4 is a diagram showing the relationship between the concentration of each p-type impurity in the raw material powder and the concentration of each p-type impurity in a SiC substrate; and 5 is a ratio R of the concentration of each p-type impurity in the raw material powder to the concentration of each p-type impurity in the SiC substrate. Ｐ／Ｓ and magnification R Ｓ／Ｐ 1 is a diagram showing the relationship between the concentration of p-type impurities in a normal crucible that has not been purified and in a high-purity crucible that has been purified.

[0016] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following, including other embodiments described below, identical or equivalent parts will be denoted by the same reference numerals.

[0017] First Embodiment A first embodiment of the present disclosure will be described. First, the configuration of a SiC semiconductor device according to this embodiment will be described with reference to FIG.

[0018] [Configuration of SiC Semiconductor Device] The SiC semiconductor device according to this embodiment has an inverted vertical MOSFET with a trench gate structure as shown in FIG. 1 formed as a semiconductor element. The vertical MOSFET shown in these figures is formed in a cell region of the SiC semiconductor device, and a peripheral breakdown voltage structure is formed to surround the cell region, thereby constituting the SiC semiconductor device; however, only the vertical MOSFET is shown here. In the following description, mutually orthogonal directions as shown in FIG. 1 will be referred to as the X direction, Y direction, and Z direction, respectively. Specifically, the width direction of the vertical MOSFET is referred to as the X direction, the depth direction of the vertical MOSFET intersecting the X direction as the Y direction, and the thickness direction or depth direction of the vertical MOSFET, i.e., the direction normal to the XY plane, as the Z direction.

[0019] As shown in FIG. 1, the SiC semiconductor device has n-type impurity doped n-type impurities. ＋The SiC substrate 11 is a portion that constitutes the drain region of the vertical MOSFET 30. The SiC substrate 11 has an off-angle of 0 to 8° with respect to the (0001) Si plane, and has an n-type impurity concentration of 1.0×10 １９ / cm ３ The thickness is specified as 350 μm or 500 μm. The 350 μm thickness means that the thickness is in the range of 325 to 375 μm, and the 500 μm thickness means that the thickness is in the range of 475 to 525 μm.

[0020] Although the SiC substrate 11 is n-type, it contains at least B (boron) as a p-type impurity. The reason for this will be described later, but the forward current flowing through the built-in diode 40 of the vertical MOSFET 30 shown in the equivalent circuit of FIG. 2 is 600 A or more, and the current density is 11.6 A / mm. ２ If the above is assumed, the B concentration is 9 x 10 １６ / cm ３ In addition, the forward current flowing through the built-in diode 40 is set to 800 A or more, and the current density is set to approximately 15 A / mm ２ If the above is assumed, the B concentration is 1.5 × 10 １７ / cm ３ The forward current assumed to flow through built-in diode 40 refers to a current that can flow as a reflux current during reflux operation when the SiC semiconductor device is applied to an inverter circuit or the like, or in other words, refers to the magnitude of the current stress applied to built-in diode 40. Hereinafter, this forward current assumed to flow through built-in diode 40 is also referred to as current stress.

[0021] Preferably, when the thickness of the SiC substrate 11 is 350 μm, the B concentration is 1.75×10 １７ / cm ３ In the case of a 500 μm specification, the B concentration is set to 7.2×10 １７ / cm ３ It would be better to use the following.

[0022] On the main surface of the SiC substrate 11, a n-type SiC layer that constitutes a part of the drift layer is formed.－ The buffer layer 12 is formed on the surface of the SiC substrate 11 by epitaxial growth, and has an n-type impurity concentration between that of the SiC substrate 11 and that of a low-concentration layer 13 (described later). The buffer layer 12 has a thickness of, for example, about 1 μm and an n-type impurity concentration of 6.0×10 １７ ~1.5 x 10 １８ / cm ３ On the buffer layer 12, a n-type SiC layer is formed, which is a part of the drift layer and has a lower concentration than the SiC substrate 11. － A low concentration layer 13 of the mold is formed.

[0023] In the cell region, an n-type JFET section 14 that constitutes a part of the drift layer made of SiC is formed on the low-concentration layer 13. The low-concentration layer 13 is connected to the JFET section 14 on the side opposite to the SiC substrate 11. Furthermore, in addition to the JFET section 14, a p-type deep layer 15 is formed on the low-concentration layer 13.

[0024] The JFET section 14 and the deep layer 15 constitute a saturation current suppression layer, and both are extended in the X direction as the longitudinal direction, and are arranged alternately and repeatedly in the Y direction. That is, when viewed from the normal direction to the main surface of the SiC substrate 11, at least a part of the JFET section 14 and the deep layer 15 are each formed into a plurality of lines, in other words, stripes, and are arranged alternately.

[0025] In this embodiment, the JFET portion 14 is formed below the deep layer 15. Therefore, the striped portions of the JFET portion 14 are connected below the deep layer 15, and each striped portion is disposed between a plurality of deep layers 15.

[0026] The deep layer 15 is an ion-implanted layer formed by ion-implanting p-type impurities. As described above, the deep layer 15 is striped, and each line-shaped portion of the striped deep layer 15 has a constant width and is arranged at equal intervals. The p-type impurity concentration is constant in the depth direction, for example, 5×10 １７ / cm ３ The deep layer 15 has a thickness of 1 μm or less, which is the dimension in the Z direction from the top surface to the bottom.

[0027] Furthermore, an n-type current spreading layer 16 that constitutes part of the drift layer made of SiC is formed on the JFET portion 14 and the deep layer 15. The current spreading layer 16 is a layer that allows the current flowing through the channel of the vertical MOSFET 30 to be diffused in the Y direction, and is formed in contact with the tip end side of the gate trench 21 in the depth direction, which will be described later, and has, for example, a higher n-type impurity concentration than the low concentration layer 13. However, it is not essential that the impurity concentration of the current spreading layer 16 be higher than that of the low concentration layer 13, and it may have, for example, the same impurity concentration as the low concentration layer 13.

[0028] In this embodiment, the drift layer is composed of the buffer layer 12, the low-concentration layer 13, the JFET portion 14, and the current spreading layer 16, but the configuration of the drift layer is arbitrary, and for example, it may have a structure without a buffer layer.

[0029] A p-type base region 17 made of SiC is formed on the current spreading layer 16. Also, an n-type base region 17 made of SiC is formed on the base region 17. ＋ The base region 17 has a p-type impurity concentration lower than that of the deep layer 15. The source region 18 has an n-type impurity concentration higher than that of the current spreading layer 16.

[0030] The p-type impurity concentration of the source region 18 is higher than that of the base region 17 so that the p-type impurity concentration of the source region 18 reaches the base region 17. ＋In this embodiment, the contact region 19 is formed in a line shape with the Y direction as its longitudinal direction. Furthermore, a p-type coupling layer 20 that connects the base region 17 and the deep layer 15 is formed below the contact region 19. The coupling layer 20 is formed in a line shape with the Y direction as its longitudinal direction together with the contact region 19, and is disposed on both sides of the current spreading layer 16.

[0031] The contact region 19 and the coupling layer 20 serve to couple the deep layer 15 and the base region 17 to a source electrode 25 (described later) in order to fix the deep layer 15 and the base region 17 to the source potential.

[0032] The contact regions 19 and the coupling layers 20 may be formed at any interval, but in this embodiment, they are formed on both sides of a trench gate structure (described later). The width of the contact regions 19 and the coupling layers 20 may be any width, but in this embodiment, they are set to be equal to or less than the interval between adjacent trench gate structures.

[0033] Furthermore, a gate trench 21 having a predetermined width and a predetermined depth is formed so as to penetrate the source region 18 and the base region 17 and reach the current spreading layer 16. The base region 17 and the source region 18 are formed so as to contact the side surfaces of the gate trench 21, and the contact region 19 is arranged away from the gate trench 21. The gate trench 21 is formed in a linear layout with the X direction as the width direction, a direction intersecting the longitudinal directions of the JFET section 14 and the deep layer 15, the Y direction as the length direction here, and the Z direction as the depth direction. As shown in FIG. 1 , the gate trenches 21 are formed in a stripe shape with multiple gate trenches 21 arranged at equal intervals in the X direction, and the base region 17, the source region 18, the contact region 19, and the coupling layer 20 are arranged between each of the gate trenches.

[0034] A portion of the base region 17 located on the side surface of the gate trench 21 serves as a channel region that connects the source region 18 and the current spreading layer 16 when the vertical MOSFET 30 is in operation, and the inner wall surface of the gate trench 21, including the channel region, is covered with a gate insulating film 22. A gate electrode 23 made of doped Poly-Si is formed on the surface of the gate insulating film 22, and the gate insulating film 22 and gate electrode 23 are disposed within the gate trench 21 to form a trench gate structure. Furthermore, an interlayer insulating film 24 is formed to cover the gate electrode 23.

[0035] As shown in FIG. 1 , a source electrode 25 and the like are formed on the surfaces of the source region 18 and the gate electrode 23 via an interlayer insulating film 24. The source electrode 25 is made of a plurality of metals, such as Ni / Al. At least the n-type SiC, specifically the portion in contact with the source region 18 or the gate electrode 23 in the case of n-type doping, is made of a metal capable of making ohmic contact with the n-type SiC. At least the p-type SiC, specifically the portion in contact with the contact region 19, is made of a metal capable of making ohmic contact with the p-type SiC. The source electrode 25 is electrically insulated from the SiC portion by being formed on the interlayer insulating film 24, but is electrically connected to the source region 18 and the contact region 19 through contact holes 24 a formed in the interlayer insulating film 24.

[0036] Meanwhile, a drain electrode 26 electrically connected to the SiC substrate 11 is formed on the back surface side of the SiC substrate 11. With this structure, an n-channel type inversion trench gate vertical MOSFET 30 is formed. A cell region is formed by arranging a plurality of such vertical MOSFETs 30. Then, although not shown, a peripheral breakdown withstand structure such as a guard ring is formed to surround the periphery of the cell region, thereby forming a SiC semiconductor device.

[0037] In the SiC semiconductor device having such a configuration, a built-in diode 40 is formed in the vertical MOSFET 30 by pn junctions between the low concentration layer 13, the JFET portion 14, etc. and the deep layer 15, the coupling layer 20, etc.

[0038] The above is an example of the basic configuration of the SiC semiconductor device according to this embodiment. As will be described later, this SiC semiconductor device is used, for example, in an inverter circuit for driving a three-phase motor, which uses the vertical MOSFET 30 as a switching element.

[0039] [Defect Growth Caused by BPDs] As described above, the SiC semiconductor device has a structure in which the cell region includes the vertical MOSFET 30 with a trench gate structure and the built-in diode 40 formed by a pn junction. BPDs exist in the drift layer including the SiC substrate 11 and the buffer layer 12, and defects caused by these BPDs can occur in the SiC semiconductor device.

[0040] As shown in FIG. 2, an equivalent circuit of the SiC semiconductor device is shown as a circuit configuration having a MOSFET 30 and a built-in diode 40. When the vertical MOSFET 30 is on, an on-current I flows from the drain electrode 26 to the source electrode 25. ＯＮ 2 correspond to the source electrode 25, the drain electrode 26, and the gate electrode 23, respectively. Specifically, when a predetermined voltage, such as 20 V, is applied to the gate electrode 23, a channel region is formed in the surface of the base region 17 that contacts the gate trench 21, and an on-current I flows between the source electrode 25 and the drain electrode 26. ＯＮ is playing.

[0041] Thereafter, when the SiC semiconductor device is turned off, a reverse bias is applied and the device is in a reverse conduction state, so that the built-in diode 40 functions as a freewheeling diode, and a freewheeling current I ＯＦＦAt this time, as shown in FIG. 3A, holes that have diffused from the p-type layer side to the n-type layer side of the pn junction that constitutes the built-in diode 40 recombine with electrons in the n-type layer. Because the recombination energy between these holes and electrons is large, the BPD 50 expands, generating an SSF 60, as shown in FIG. 3B. The SSF 60 expands as the current stress on the built-in diode 40 accumulates. Since the SSF 60 occupies a larger area than the BPD 50, the on-current I ＯＮ and reflux current I ＯＦＦ Furthermore, since the SSF 60 expands in response to the stress of current flowing through the built-in diode 40, the electrical characteristics after operation deteriorate compared to the electrical characteristics immediately after manufacture, i.e., before the SSF 60 is generated.

[0042] For example, a reverse bias is applied to the SiC semiconductor device of this embodiment to generate a reflux current I ＯＦＦ Current was passed through the SSF 60, and the state of the SSF 60 after the current was passed was confirmed. Figure 4 is a binarized image of a PL image in which the degree of expansion of the SSF 60 was confirmed by non-destructive testing using the PL method. The multiple white linear portions present at the top and bottom of the figure are the SSF 60. As shown in this figure, it can be seen that the SSF 60 has expanded in the portion that becomes the active region of the cell region of the SiC semiconductor device, that is, the region where the source electrode 25 is arranged and where current is passed. This expansion of the SSF 60, which occupies a large area, increases the on-current I ＯＮ and reflux current I ＯＦＦ This hinders the formation of the conductive layer, resulting in a deterioration in the electrical characteristics.

[0043] To suppress this deterioration in electrical characteristics, it is necessary to provide a SiC semiconductor device with excellent diode conduction degradation characteristics, which can suppress the expansion of BPD 50 into SSF 60 even when stress is accumulated on built-in diode 40.

[0044] In particular, when a SiC semiconductor device is applied to an in-vehicle power card or the like, the amount of current flowing through one chip becomes large, and therefore it is unavoidable that the built-in diode 40 turns on even when current is passed through the channel region. Also, even when a large current is used in a freewheeling mode in which a freewheeling current flows, it is important to provide a SiC semiconductor device with excellent diode current-degradation characteristics so as to suppress hole injection and prevent the SSF 60 from expanding.

[0045] [B Concentration in SiC Substrate] As shown in the above-mentioned Patent Document 1, by doping a p-type impurity into an n-type SiC single crystal substrate, it is possible to obtain the effect of suppressing the expansion of BPD 50 into SSF 60. However, it has been confirmed that the effect of suppressing the expansion of BPD 50 into SSF 60 cannot be sufficiently obtained by simply doping a p-type impurity. ＋ It was found that by introducing B, which is a p-type impurity, into the SiC substrate 11 and adjusting the B concentration to a predetermined concentration or higher, it is possible to obtain the effect of suppressing the required expansion of BPD 50 into SSF 60. Furthermore, it was found that the B concentration required to obtain this effect varies depending on the magnitude of the reflux current flowing in the forward direction of the built-in diode 40 when the SiC semiconductor device is applied to an inverter or the like, and the larger the current, the higher the required B concentration.

[0046] Specifically, assuming that the SiC semiconductor device is applied to an inverter and the energization stress is 600 A or more and 800 A or more, a reverse bias was applied to the SiC semiconductor device and a forward current was passed through the built-in diode 40. Then, the B concentration in the SiC substrate 11 was changed and the change in the SSF area occupancy rate (%) after energization was examined, and the results shown in Figure 5 were obtained. An energization stress of 600 A or more means that the current density calculated by dividing this current value by the area of ​​the active region through which current actually flows in the cell region where the vertical MOSFET 30 is formed is 11.6 A / mm ２ In the experiment, the actual current value that flowed was 656 A, assuming a current stress of 600 A or more. In this case, the current density was 12.66 A / mm ２In addition, the current density of the current flowing in the active region was 14.6 A / mm ２ In the experiment, the actual current value that flowed was 900 A, assuming a current stress of 800 A or more. In this case, the current density was 16.41 A / mm ２ It was.

[0047] As shown in this figure, in both cases where the electrical stress is 600 A or more and 800 A or more, the SSF area occupancy rate is reduced by introducing B into the SiC substrate 11. However, when the B concentration is 9.0×10 １６ / cm ３ If the SSF area occupancy is less than 1 / 2, the SSF area occupancy is high. This indicates that the effect of suppressing the expansion of the BPD 50 into the SSF 60 is not sufficiently obtained. Therefore, excellent diode conduction degradation characteristics cannot be obtained.

[0048] On the other hand, when the reflux current is 600 A or more, in this case 656 A, the B concentration is at least 9.0 × 10 １６ / cm ３ When the SSF area occupancy rate is 800 A or more, even in the case of 900 A, the B concentration is at least 1.5 × 10 １７ / cm ３ As a result, the SSF area occupancy rate can be reduced to 3% or less. In other words, the effect of suppressing the expansion of BPD50 to SSF60 can be sufficiently obtained.

[0049] From this result, when the SiC semiconductor device is applied in a form in which the current stress of the built-in diode 40 is 600 A or more in order to ensure the diode current degradation characteristics, the B concentration in the SiC substrate 11 should be set to 9.0×10 １６ / cm ３ In addition, when the SiC semiconductor device is applied in a form in which the current stress of the built-in diode 40 is 800 A or more, the B concentration in the SiC substrate 11 is set to 1.5×10 １７ / cm ３This makes it possible to obtain a SiC semiconductor device that exhibits excellent diode current degradation characteristics. Note that the greater the current stress, the higher the B concentration in the SiC substrate 11 required to obtain excellent diode current degradation characteristics. Here, the current that actually flowed in the experiment assuming a 600 A specification was 656 A, and the B concentration required at that time was 9.0×10 １６ / cm ３ However, in the case of 600A, the required B concentration is less than that, so it is at least 9.0 × 10 １６ / cm ３ Similarly, in an experiment assuming an 800 A specification, the actual current that flowed was 900 A, and the required B concentration was 1.5 × 10 １７ / cm ３ However, in the case of 800A, the required B concentration is less than that, so it is at least 1.5 × 10 １７ / cm ３ Anything above that is good.

[0050] On the other hand, the SSF area occupancy rate decreases as the B concentration in the SiC substrate 11 increases. However, it has been found that if the B concentration in the SiC substrate 11 is made too high, problems occur when the SiC substrate 11 is in a wafer state.

[0051] The SiC substrate 11 is ＋ Specifically, the SiC wafer is subjected to an element formation process to form vertical MOSFETs 30 and the like, and then the resulting wafer is diced into chips to form the SiC semiconductor device. The portion of the SiC wafer that was the SiC wafer is called the SiC substrate 11.

[0052] SiC wafers are wafers of a specified number of inches, for example, 6-inch or 8-inch wafers, and are transported to various devices such as epitaxial growth devices and ion implantation devices to undergo device formation processes. Depending on the amount of warpage in the SiC wafer, the vacuum chuck provided in the device may be unable to hold the SiC wafer, or the SiC wafer may move from the desired transport position during transport, making it impossible to perform the device formation process properly. For this reason, it is necessary to keep the amount of warpage of the SiC wafer within a specified range.

[0053] However, increasing the B concentration in the SiC substrate 11 increases the amount of warpage of the SiC wafer, making it impossible to keep it within the specified range, and the device formation process cannot be performed satisfactorily. The relationship between the amount of warpage and the B concentration of the SiC wafer was investigated by conducting an experiment using a 6-inch SiC wafer with a thickness of 350 μm. The results are shown in FIG. 5.

[0054] As shown in this figure, the higher the B concentration in the SiC substrate 11, the greater the amount of warpage. To facilitate smooth transportation during the device fabrication process and smooth adsorption of the SiC wafer on a vacuum chuck, it is preferable that the amount of warpage be 300 μm or less. To achieve this, when the SiC wafer is a 6-inch wafer with a 350 μm diameter, the B concentration should be 1.75×10 as shown in FIG. 5 and FIG. 13A (described later). １７ / cm ３ Therefore, when a 6-inch wafer with a thickness of 350 μm is used as the SiC wafer, the B concentration in the SiC substrate 11 is preferably 1.75×10 １７ / cm ３ The following is stated.

[0055] In addition, when the SiC wafer was an 8-inch wafer, similar experiments were performed for both a 350 μm thickness and a 500 μm thickness. As a result, as shown in FIG. 13B described later, the B concentration in the SiC substrate 11 was 1.8×10 １７ / cm ３ It is preferable to set it to 7.2×10 or less for a 500 μm specification. １７ / cm ３ It has been confirmed that the following is preferable.

[0056] That is, whether the SiC wafer is a 6-inch wafer or an 8-inch wafer, if the thickness is 350 μm, the B concentration in the SiC substrate 11 is 1.75×10 １７ / cm ３ If the SiC wafer is an 8-inch wafer and has a thickness of 500 μm, the B concentration in the SiC substrate 11 is set to 7.2×10 １７ / cm ３ The amount of warpage can be suppressed if the following conditions are met: Therefore, the B concentration in the SiC substrate 11 is set so as to satisfy these conditions.

[0057] The term "warpage" as used herein refers to the magnitude of warpage occurring during the device formation process. The "warpage" is calculated as the difference in height between the highest and lowest points on one surface of a SiC wafer when the SiC wafer is placed on a flat surface. Typically, SiC wafers are not completely flat and have some warpage even initially, before the device formation process begins. During transport, the SiC wafer experiences not only the warpage occurring during the device formation process but also the initial warpage of the SiC wafer. However, it is difficult to completely eliminate the initial warpage. Even if the warpage can be reduced, it can be as large as about 200 μm. Therefore, it is necessary to adjust the warpage to a level that does not interfere with the device formation process, even with the initial warpage. The B concentration in the SiC substrate 11 is specified so that the warpage does not interfere with the device formation process.

[0058] When the built-in diode 40 is operated in bipolar mode by refluxing, the hole density at the interface between the SiC substrate 11 and the buffer layer 12 is set to 1.2×10 １６ / cm ３It has been confirmed that hole injection into the SiC substrate 11 can be suppressed if the B concentration in the SiC substrate 11 is set within the above range as in this embodiment, and the hole density at the interface between the buffer layer 12 and the low concentration layer 13 can be suppressed to 1.2×10 １６ / cm ３ It was also possible to meet the condition of keeping the value below.

[0059] Simulations were carried out to confirm the change in hole density at each location when the current stress of the built-in diode was set to 600 A or more and trap sites were formed in the SiC substrate 11 by acceptors assumed to be B. Specifically, when the B concentration in the SiC substrate 11 was set to 1.0×10 １５ / cm ３ , 1.0×10 １７ / cm ３ , 1.0×10 １９ / cm ３ The change in hole density for each portion near the buffer layer 12 was investigated. FIG. 6 shows the results. FIG. 7 is a linear approximation diagram of the hole density at the interface between the SiC substrate 11 and the buffer layer 12 for each B concentration used in the simulation. The measurement conditions were a gate voltage Vg of 3.5 V, a source-drain current Isd of 470 A, a gate-source voltage Vgs of −3.5 V, and a temperature Tj of 175° C.

[0060] As shown in FIGS. 6 and 7, the B concentration in the SiC substrate 11 is set to 1.0×10 １５ / cm ３ In this case, the hole density is 1.8 × 10 １６ / cm ３ However, when the B concentration in the SiC substrate 11 was 1.0×10 １７ / cm ３ In this case, the hole density is 1.1 × 10 １６ / cm ３ The B concentration is 1.0×10 １９ / cm ３ In this case, the hole density is 2.0 × 10 １５ / cm ３ As shown in FIG. 7, when linearly approximated, the B concentration is approximately 7.0×10 １６ / cm ３ When the hole density is 1.2 × 10 １６ / cm ３ This is what happened.

[0061] Therefore, when the current stress of the built-in diode 40 is set to 600 A or more, the B concentration in the SiC substrate 11 is set to 7.0×10 １６ / cm ３ or more, it is possible to suppress the hole current from flowing to the buffer layer 12 side. In this embodiment, when the current stress of the built-in diode 40 is set to 600 A or more, the B concentration in the SiC substrate 11 is set to 9.0×10 １６ / cm ３ Therefore, the hole density is set to 1.2 × 10 １６ / cm ３ Since the hole current can be prevented from flowing to the buffer layer 12 side, it is possible to prevent the BPDs 50 in the SiC substrate 11 from expanding into the SSFs 60.

[0062] A similar simulation was also performed when the current stress of the built-in diode 40 was set to 800 A or more. In this case, as described above, the B concentration was set to 1.5×10 １７ / cm ３ If the hole density is 1.2 × 10 １６ / cm ３ Therefore, in this case as well, it is possible to suppress the BPDs 50 in the SiC substrate 11 from expanding into the SSFs 60, as in the above case.

[0063] As described above, in this embodiment, when the current stress of the built-in diode 40 is set to 600 A or more, the B concentration in the SiC substrate 11 is set to 9.0×10 １６ / cm ３ However, 7.0 x 10 １６ / cm ３ Furthermore, when the current stress of the built-in diode 40 is set to 800 A or more, the B concentration is set to 1.5×10 １７ / cm ３These are expressed as the B concentration in the SiC substrate 11 for two cases where the magnitude of the forward current flowing through the built-in diode 40, in other words, the magnitude of the current stress, is 600 A or more and 800 A or more, and can be quantified as the B concentration relative to the magnitude of the current stress. As shown in FIG. 8A, when the current stress is 12.66 A / mm ２ B density in the case of 7.0×10 １６ / cm ３ The current stress is 16.41 A / mm ２ B density in the case of 1.5 × 10 １７ / cm ３ A straight line L1 can be drawn connecting the plots of the two points. This straight line L1 is the boundary line at which the SSF area occupancy rate becomes 3% after the application of electrical stress. Therefore, by setting the B concentration in the SiC substrate 11 with respect to the expected electrical stress so that the relationship between the B concentration in the SiC substrate 11 and the magnitude of the electrical stress is located in the region to the right of the straight line L1, it is possible to suppress the expansion of BPDs 50 into SSFs 60.

[0064] It is possible to suppress the expansion of BPDs 50 into SSFs 60 by adjusting the B concentration in the SiC substrate 11, but it has been confirmed that the n-type impurity concentration in the buffer layer 12 can also have an effect. Specifically, as shown by the dashed line La in Fig. 9, the concentration of N doped as an n-type impurity is gradually decreased depending on the location, from the SiC substrate 11, to the buffer layer 12, and to the low-concentration layer 13. For the buffer layer 12, the n-type impurity concentration is 6.0 × 10 １７ ~1.5 x 10 １８ / cm ３ The concentration profile is set to a value of 1.0×10, which reduces the concentration distribution in the thickness direction. １８ / cm ３ is the target value, ±0.5 × 10 １８ / cm ３ However, as shown by the solid line Lb, the n-type impurity concentration of the buffer layer 12 on the SiC substrate 11 side drops to 6.0×10 １７ / cm ３In this case, the ratio of BPD50 expanding into SSF60 may be higher than in the case of the concentration profile indicated by the dashed line La. For this reason, it is preferable to keep the n-type impurity concentration of the buffer layer 12 within a concentration range of ±50% of the target value, and to prevent a drop in the n-type impurity concentration. Although it is preferable to prevent a drop, even if a drop occurs, it is possible to deal with this by defining a boundary line at which the SSF area occupancy rate becomes 3% after applying electrical stress. For example, when the electrical stress is 11.6 A / mm ２ In this case, the B concentration is 9 × 10 １６ / cm ３ It was also confirmed that the electrical stress was preferably 16.0 A / mm or more. ２ In the case of above, the B concentration is 1.5×10 １７ / cm ３ In this case, as shown in FIG. 8B, it was confirmed that the current stress was 11.6 A / mm ２ B density 9.0 x 10 １６ / cm ３ The electrical stress is 16.0 A / mm ２ B density in the case of 1.5 × 10 １７ / cm ３ A straight line L2 can be drawn connecting the plots of the two points. This straight line L2 can be used as the boundary line at which the SSF area occupancy rate becomes 3% after applying electrical stress.

[0065] [Method for Manufacturing SiC Semiconductor Device] Next, a method for manufacturing the SiC semiconductor device of this embodiment will be described with reference to Figures 10A to 10G. Figures 10A to 10G are cross-sectional perspective views showing the part corresponding to Figure 1 during the manufacturing process.

[0066] [Step shown in FIG. 10A] First, n ＋ A SiC wafer for forming the SiC substrate 11 is prepared. In this case, when the electrical stress is 600 A or more, the B concentration of the SiC wafer is set to 9.0×10 １６ / cm ３ If the B concentration is 1.5×10 or more, the B concentration is 1.5×10 １７ / cm ３In addition, if the SiC wafer to be prepared has a thickness of 350 μm, the B concentration is set to 1.75×10 １７ / cm ３ If the thickness is 500 μm, the B concentration is preferably 7.2×10 or less, taking into consideration the amount of warping. １７ / cm ３ It is preferable to set it as follows.

[0067] An epitaxial film is then grown on the surface of the SiC substrate 11 to form a buffer layer 12 and a low-concentration layer 13 made of SiC. Next, a mask (not shown) is formed on the surface of the low-concentration layer 13, and the mask is patterned by photolithography or the like so that the region where the JFET section 14 is to be formed is opened. Specifically, the mask is patterned so that only the cell region is opened. Then, n-type impurities such as N or P are ion-implanted through the mask and heat treatment is performed to form the JFET section 14. The mask is then removed. For example, an LTO (low-temperature oxide) film or the like is used as the mask. In this embodiment, masks are also used in the processes described below, and each mask is, for example, an LTO film or the like.

[0068] [Step shown in FIG. 10B] A mask 31 is formed and patterned by photolithography or the like so that an area where the deep layer 15 is to be formed is opened. Then, p-type impurities such as Al are ion-implanted from above the mask 31 and heat treatment is performed to form the deep layer 15.

[0069] 10C ] A current spreading layer 16 made of SiC is epitaxially grown on the low-concentration layer 13, the JFET portion 14, and the deep layer 15. As a result, a drift layer is formed by the buffer layer 12, the low-concentration layer 13, the JFET portion 14, and the current spreading layer 16.

[0070] Next, a mask (not shown) is formed and patterned by photolithography or the like so that an opening is formed in the region where the coupling layer 20 is to be formed. Then, p-type impurities such as Al are ion-implanted from above the mask and heat treatment is performed to form the coupling layer 20. At this time, the coupling layer 20 is extended in a direction intersecting the extension direction of the deep layer 15. Therefore, even if there is some positional misalignment when the coupling layer 20 is formed, it is possible to prevent the deep layer 15 and the coupling layer 20 from being disconnected.

[0071] 10D: A p-type impurity layer is epitaxially grown on the current spreading layer 16 and the coupling layer 20 to form the base region 17. Subsequently, an n-type impurity layer is epitaxially grown on the base region 17 to form the source region 18.

[0072] [Step shown in FIG. 10E] A mask (not shown) is formed and patterned by photolithography or the like so that an opening is formed in a region where the contact region 19 is to be formed. Furthermore, p-type impurities such as Al are ion-implanted from above the mask and heat treatment is performed, thereby forming the contact region 19.

[0073] [Step shown in FIG. 10F] After forming a mask (not shown), the mask is patterned so as to open an area where the gate trench 21 is to be formed. Then, anisotropic etching is performed, and if necessary, isotropic etching or sacrificial layer oxidation is performed to form the gate trench 21.

[0074] [Step shown in FIG. 10G] A gate insulating film 22 is formed by thermal oxidation or CVD (chemical vapor deposition) in locations including inside the gate trench 21. Next, a polysilicon layer doped with n-type impurities is formed on the surface of the gate insulating film 22, and then an etch-back process or the like is performed so that the gate insulating film 22 and the gate electrode 23 remain in the gate trench 21. This completes the trench gate structure.

[0075] Although not shown, subsequent steps include depositing an interlayer insulating film 24, forming contact holes 24a, forming source electrodes 25 and gate wiring, and forming a drain electrode 26 on the back surface of the SiC substrate 11. In this manner, the SiC semiconductor device of this embodiment is manufactured.

[0076] Vertical devices, such as SiC power MOSFETs, can be fabricated with high-field resistance over a shorter vertical distance, i.e., a shorter Z-axis distance (thickness), compared to Si devices. Furthermore, because impurities do not diffuse in SiC as they do in Si, the ion implantation dose used to form the impurity layer tends to be increased to increase the impurity concentration. Furthermore, to improve the breakdown voltage of the gate insulating film 22, the ion implantation depth for forming the deep layer 15 must be increased, and ion implantation is performed at high acceleration energy. For example, in the ion implantation process for the deep layer 15 described above, ions are implanted to a relatively shallow depth of 1 μm or less, so high-acceleration ion implantation is performed at 1 MeV or less, even though the ion implantation energy is still high.

[0077] An ion implantation process that increases the impurity concentration and achieves a deep implantation depth tends to cause significant warpage in the SiC wafer that constitutes the SiC substrate 11. However, as a result of careful investigation, it was found that the amount of warpage itself does not depend on the impurity concentration or implantation depth in the ion implantation, but rather on the B concentration in the SiC wafer, i.e., the amount of B mixed in during the production of the SiC ingot.

[0078] FIG. 11 shows the results of measuring the amount of warpage of multiple SiC wafer samples before the device formation process and after the deep layer 15 formation process. The horizontal axis of FIG. 11 indicates the sample number, with the first English letters A to J indicating the ingot number and the following numbers 1 to 15 indicating the order of the sliced ​​SiC wafers. The same ingot number indicates SiC wafers sliced ​​from the same SiC ingot. For example, A-1 indicates the first SiC wafer sliced ​​from the SiC ingot numbered "A." The order of the sliced ​​SiC wafers indicates the numbering when the wafers are sliced ​​sequentially from the tip end of the SiC ingot. For example, assume that the SiC ingot 100 shown in FIG. 12 is obtained. In this case, SiC wafers 102 are sliced ​​sequentially from the growth surface 101 side of the SiC ingot 100 toward the seed crystal 110 side, and the order of the sliced ​​SiC wafers 102 is indicated by the numbers.

[0079] When SiC wafers 102 obtained from the same SiC ingot 100 are compared in regions R1 and R2 enclosed by dashed lines in Figure 11, the amounts of warpage are similar before the device formation process and also after the step of forming the deep layer 15. However, when the SiC wafers 102 in region R1 and the SiC wafers 102 in region R2 are compared, although the amounts of warpage before the device formation process are similar, the amounts of warpage after the step of forming the deep layer 15 are not similar. This is due to the B concentration in the SiC wafers 102. Since the B concentrations are similar in the same SiC ingot 100, the amounts of warpage after the step of forming the deep layer 15 are similar. However, if the B concentrations are different, the amounts of warpage after the formation of the deep layer 15 will not be similar.

[0080] As described above, it can be seen that the amount of warpage of SiC wafer 102 during the device formation process depends on the B concentration in SiC wafer 102, that is, the amount of B contained in SiC ingot 100 during the production of SiC ingot 100. Therefore, in order to control the amount of warpage, it is necessary to adjust the B concentration in the SiC wafers that make up SiC substrate 11 in advance.

[0081] When the relationship between the amount of warpage and the B concentration in the SiC substrate 11 was investigated, the results shown in FIG. 13A were obtained for 6-inch wafers, and the results shown in FIG. 13B were obtained for 8-inch wafers. For 6-inch wafers, the investigation was conducted for a thickness of 350 μm. For 8-inch wafers, the investigation was conducted for thicknesses of 350 μm and 500 μm. This relationship was basically obtained by actual measurements, but where there were gaps between the plots of multiple actual measurements, values ​​calculated by interpolation and extrapolation were used.

[0082] 13A and 13B, regardless of the size of the SiC wafer 102, the amount of warpage increased as the B concentration in the SiC substrate 11 increased. In the case of a 6-inch wafer, the B concentration at which the amount of warpage reached 300 μm was 1.75×10 １７ / cm ３ Similarly, in the case of an 8-inch wafer, the B concentration when the warpage amount is 300 μm is 1.8×10 １７ / cm ３ , 7.2 × 10 for 500 μm specifications １７ / cm ３ It was.

[0083] Therefore, as explained in the process shown in FIG. 10A, in the case of a thickness specification of 350 μm, the B concentration is preferably 1.75×10 １７ / cm ３ If the thickness is 500 μm, the B concentration is preferably 7.2×10 １７ / cm ３ This not only makes it possible to produce a SiC semiconductor device with excellent diode conduction characteristics, but also makes it possible to suppress the amount of warpage of the SiC wafer 102 during the device formation process within a specified range. This therefore enables good transport during the device formation process and good chucking of the SiC wafer 102 by a vacuum chuck, making it possible to smoothly carry out the device formation process.

[0084] Second Embodiment A second embodiment will be described. This embodiment is different from the first embodiment in that the configuration of the vertical MOSFET 30 provided in the SiC semiconductor device is changed, and the other aspects are the same as those of the first embodiment. Therefore, only the differences from the first embodiment will be described.

[0085] In the first embodiment, the deep layer 15 is connected to the base region 17 via the coupling layer 20, but in this embodiment, as shown in Figure 14, the coupling layer 20 is eliminated and the deep layer 15 is directly connected to the base region 17.

[0086] Also in this embodiment, the current spreading layer 16 is formed so as to contact the tip end side in the depth direction of the gate trench 21, but it may be omitted. Moreover, since the current spreading layer 16 is provided on the part of the JFET section 14 located between the deep layers 15, the n-type impurity concentration in the surface layer part of the JFET section 14 may be made higher than that of the part located below it, and this may be used as the current spreading layer 16.

[0087] Furthermore, a p-type electric field relaxation layer 27 is provided along the bottom surface of the gate trench 21. The electric field relaxation layer 27 is composed of, for example, a p-type layer having a lower impurity concentration than the deep layer 15. Specifically, the electric field relaxation layer 27 is formed along the longitudinal direction of the gate trench 21. In other words, the electric field relaxation layer 27 extends along the Y-axis direction intersecting with the deep layer 15. Furthermore, although the electric field relaxation layer 27 in this embodiment is formed shallower than the JFET portion 14 and the deep layer 15, it may also be formed so that its bottom surface reaches the low concentration layer 13, penetrating the JFET portion 14 and the deep layer 15.

[0088] In this way, the deep layer 15 can be directly connected to the base region 17. In a SiC semiconductor device having this structure, the B concentration in the SiC substrate 11 can be set to the concentration described in the first embodiment, thereby preventing the BPDs 50 from expanding into the SSFs 60. Furthermore, by setting the B concentration in consideration of the amount of warpage, it is possible to keep the amount of warpage of the SiC wafer 102 during the device formation process within a specified range.

[0089] Furthermore, in the structure of this embodiment, the distance from the bottom of the deep layer 15 to the bottom of the gate insulating film 22 is shorter than in the first embodiment, which raises concerns about the penetration of an electric field into the gate insulating film 22. However, since the electric field relaxation layer 27 is provided along the bottom surface of the gate trench 21, the penetration of an electric field into the gate insulating film 22 located at the bottom of the gate trench 21 can be suppressed, thereby suppressing breakdown of the gate insulating film. Furthermore, by forming the electric field relaxation layer 27 so as to be in contact with the bottom surface of the gate trench 21, the electrostatic capacitance between the gate electrode 23 and the drain electrode 26, i.e., feedback capacitance, can be reduced, thereby improving switching speed. Furthermore, the provision of the electric field relaxation layer 27 suppresses the creeping of an electric field into the JFET portion 14 located between the electric field relaxation layer 27, thereby improving the breakdown voltage.

[0090] The electric field relaxation layer 27 may be divided into a plurality of pieces along the Y-axis direction, but the electric field relaxation layer 27 is formed so as to be electrically connected to the base region 17 via the deep layer 15.

[0091] Next, a method for manufacturing the SiC semiconductor device of this embodiment will be described with reference to FIGS. 15A to 15F.

[0092] 10A of the first embodiment is performed to prepare a SiC wafer constituting a SiC substrate 11 with a desired B concentration, and then epitaxially grow a buffer layer 12 and a low-concentration layer 13. At this time, the thickness of the low-concentration layer 13 is set to a thickness that is the sum of the thicknesses of the JFET portion 14, the current spreading layer 16, the base region 17, the source region 18, and the contact region 19.

[0093] 15B] After forming a mask (not shown), n-type impurities such as N and P are ion-implanted into the surface of the low-concentration layer 13 and heat-treated to form the JFET section 14 and current spreading layer 16, which are made up of ion-implanted layers. The JFET section 14 and the current spreading layer 16 are implanted using different doses of n-type impurities and different ion implantation energies.

[0094] 10B of the first embodiment is performed, and a mask (not shown) is formed so as to open the region where the deep layer 15 is to be formed. Then, p-type impurities such as Al are ion-implanted from above the mask, and heat treatment is performed to form the deep layer 15 composed of an ion-implanted layer.

[0095] 15B, the low-concentration layer 13 made of an epitaxial film is formed thick. In this case, when forming the deep layer 15, the ion implantation energy is increased so that ions can be implanted to a depth of 1 μm or more from the surface of the low-concentration layer 13, which will become the source region 18 in a subsequent process. For example, the deep layer 15 is formed by high-acceleration ion implantation with a high ion implantation energy of 1 MeV or more.

[0096] An ion implantation process that increases the impurity concentration and deepens the implantation depth tends to cause significant warpage in the SiC wafer 102 used to form the SiC substrate 11. However, this does not depend on the impurity concentration or implantation depth during ion implantation, but rather on the B concentration in the SiC wafer 102, i.e., the amount of B mixed in during the production of the SiC ingot 100. Therefore, even when an ion implantation process is performed with a high ion implantation energy of 1 MeV or more, as in this embodiment, it is possible to keep the amount of warpage of the SiC wafer 102 during the device formation process within a specified range.

[0097] 15D ] After a mask having an opening for a cell region (not shown) is placed on the surface layer of the low-concentration layer 13, p-type impurities such as Al are ion-implanted and heat-treated, thereby forming a base region 17 made of an ion-implanted layer on the JFET portion 14, the deep layer 15, and the current spreading layer 16.

[0098] [Process shown in FIG. 15E] A mask (not shown) having an opening corresponding to a region where the source region 18 is to be formed is formed, and then n-type impurities such as N or P are ion-implanted into the surface layer of the low-concentration layer 13 through the mask, followed by heat treatment. This forms the source region 18, which is an ion-implanted layer, on the base region 17. Next, a mask (not shown) having an opening corresponding to a region where the contact region 19 is to be formed is formed, and then p-type impurities such as Al are ion-implanted through the mask, followed by heat treatment. This forms the contact region 19, which is an ion-implanted layer.

[0099] [Step shown in FIG. 15F] After forming a mask (not shown), the mask is patterned so as to open an area where the gate trench 21 is to be formed. Anisotropic etching is then performed to form the gate trench 21. Furthermore, using the mask (not shown) as is, p-type impurities such as Al are ion-implanted into the bottom surface of the gate trench 21 and heat treatment is performed, thereby forming an electric field relaxation layer 27.

[0100] The subsequent steps are the same as those shown in Figure 10G and subsequent steps in the first embodiment. In this manner, the SiC semiconductor device of this embodiment is manufactured.

[0101] As described above, in this embodiment, the ion implantation energy in the ion implantation step is higher than in the first embodiment, but the amount of warpage of the SiC wafer 102 can be kept within a specified range. This allows for good transport during the device formation process and good adsorption of the SiC wafer 102 by a vacuum chuck, making it possible to smoothly carry out the device formation process.

[0102] Third Embodiment A third embodiment will be described. This embodiment is different from the first and second embodiments in that it specifies the relationship with other p-type impurities in addition to the B concentration in the SiC substrate 11, but is otherwise similar to the first and second embodiments.

[0103] To prepare the SiC wafer 102 for forming the SiC substrate 11, a SiC single crystal is grown in a growth crucible by sublimation or gas growth. Specifically, a SiC ingot made of the SiC single crystal is manufactured and sliced ​​to form the SiC wafer 102. The B concentration of the SiC ingot is adjusted to a desired value so that the B concentration in the SiC substrate 11 will be the same. That is, the B concentration of the SiC ingot is adjusted to 9.0×10 when the electrical stress is 600 A or more. １６ / cm ３ or more, 1.5 x 10 for 800 A or more １７ / cm ３ Furthermore, taking into account the amount of warpage, if the specification is 350 μm, the value is 1.75×10 １７ / cm ３ Below, for 500 μm specifications, x 10 １７ / cm ３ The B concentration of the SiC ingot is adjusted to be as follows: At this time, it has been found that the element ratio of the p-type impurity element finally contained in SiC substrate 11 is determined depending on the element ratio of the SiC raw material used for growing the SiC single crystal.

[0104] As an example, a case will be described in which an experiment was conducted to grow crystals by sublimation using a SiC single crystal manufacturing apparatus 200 shown in FIG. 16 . In the sublimation method, a raw material powder 201, which is a powder of SiC as a SiC raw material, is heated and sublimated, thereby producing a SiC ingot 203 on the surface of a seed crystal 202 made of a SiC single crystal. In the experiment, a growth crucible 204 made of graphite or the like was induction heated to approximately 2500°C to thermally decompose the raw material powder 201 placed below a pedestal 205, and the SiC ingot 203 was grown on the surface of the seed crystal 202 attached to the pedestal 205. In addition to SiC powder made of powdered SiC, B powder containing boron carbide or boron nitride was introduced as a B raw material for the raw material powder 201. Furthermore, N was used as an n-type dopant. ２ By introducing the gas, an n-type SiC ingot 203 was obtained.

[0105] In addition to B, raw material powder 201 contains various impurities including p-type impurity elements, and the content of these impurities depends on the purity of raw material powder 201. Experiments were conducted to measure the content of various p-type impurity elements contained in raw material powder 201 and the content of various p-type impurity elements contained in SiC substrate 11 obtained by manufacturing SiC wafer 102 using SiC ingot 203 manufactured using raw material powder 201. Fig. 17A is a graph showing the content of various impurity elements contained in SiC substrate 11, and Fig. 17B is a graph showing the content of various impurity elements contained in raw material powder 201.

[0106] In addition, the ratio R Ｐ／Ｓ and the ratio R of the p-type impurity content in the raw material powder 201 to the p-type impurity content in the SiC substrate 11. Ｓ／Ｐ The ratio R Ｐ／Ｓ and magnification R Ｓ／Ｐ indicates the ease of incorporation of an element into the SiC substrate 11. Ｐ／Ｓ The larger the magnification R Ｓ／Ｐ It is shown that the smaller the value of , the easier the element is incorporated into the SiC substrate 11. Figures 18A and 18B summarize the results.

[0107] As shown in FIG. 18B, the B concentration in the raw material powder 201 is 7.0×10 １７ / cm ３ At this time, the B concentration in the SiC substrate 11 is 9.5×10 １７ / cm ３ The ratio R Ｐ／Ｓ is 136%, the magnification R Ｓ／Ｐ The ratio R Ｐ／Ｓ and magnification R Ｓ／Ｐ18A , the ratio of the content of each element in raw material powder 201 to the content in SiC substrate 11 approximates a straight line of 1:1. In other words, the level of impurity content in raw material powder 201, in other words, the quality of raw material powder 201, is important, and once this is determined, the B concentration in SiC substrate 11, etc., can be adjusted.

[0108] For example, for B, the magnification R Ｓ／Ｐ is 0.7 times, that is, if the B concentration in the raw material powder 201 is 0.7 times the target value, the B concentration in the SiC substrate 11 can be set to the target value. Therefore, the SiC ingot 203 is grown with the B concentration in the raw material powder 201 set to about 0.7 times the target value of the B concentration in the SiC substrate 11. Similarly, for Al, the SiC ingot 203 is grown with the Al concentration in the raw material powder 201 set to about 1.4 times the target value. For Nb, the SiC ingot 203 is grown with the Nb concentration in the raw material powder 201 set to about 1.5 times the target value. For Ti, the SiC ingot 203 is grown with the Ti concentration in the raw material powder 201 set to about 6.7 times the target value. For V, the SiC ingot 203 is grown with the V concentration in the raw material powder 201 set to about 10 times the target value. As for Fe, the SiC ingot 203 is grown so that the Fe concentration in the raw material powder 201 is about 1.7 times the target value, thereby allowing the concentrations of various p-type impurities in the SiC substrate 11 to be set to desired target values.

[0109] In addition, when the impurity concentration in the SiC substrate 11 has an upper limit and the target value is set to be equal to or less than the upper limit, the impurity concentration in the raw material powder 201 is set to be equal to or less than the target value of the impurity concentration multiplied by R Ｓ／Ｐ This allows the impurity concentration in the SiC substrate 11 to be set to a desired upper limit or lower. In addition, if the impurity concentration in the SiC substrate 11 has a lower limit and the target value is set to be equal to or higher than the lower limit, the impurity concentration in the raw material powder 201 is set to be equal to or lower than the target value of the impurity concentration multiplied by the multiplication factor R of the impurity. Ｓ／Ｐ This allows the impurity concentration in the SiC substrate 11 to be set to a desired lower limit or higher.

[0110] Furthermore, the B concentration in the SiC substrate 11 is 7.0×10 １６ ~ × 1.4 × 10 １７ / cm ３ The concentrations of various p-type impurities were measured when the concentration of various p-type impurities other than B was 0.01, and it was investigated whether the expansion of BPD50 to SSF60 was affected by changes in the concentration of various p-type impurities other than B. It was also investigated whether the amount of warpage of the SiC wafer 102 was affected. As a result, it was confirmed that the influence of the expansion of BPD50 to SSF60 and the influence of the amount of warpage of the SiC wafer 102 were limited, and that it was sufficient to mainly adjust the B concentration. Specifically, the B concentration in the SiC substrate 11 was set to a range that suppressed the expansion of BPD50 to SSF60 while keeping the amount of warpage within a specified range, and the amount of other impurities contained therein was measured. As a result, it was found that the total impurity concentration of p-type impurities other than B was 2.3 × 10 for a 6-inch wafer. １７ / cm ３ For an 8-inch wafer, the １７ / cm ３ In addition, the Al concentration was 5.0 × 10 or less for both the 6-inch wafer and the 8-inch wafer. １５ / cm ３ Hereinafter, when the Ti concentration is 1.0 × 10 １６ / cm ３ Below, V concentration is 4.0 × 10 １５ / cm ３ Below, Fe concentration is 6.0 × 10 １６ / cm ３ Therefore, if the total impurity concentration of p-type impurities other than B is equal to or less than these concentrations, by adjusting at least only the B concentration to the range described in the first and second embodiments, it is possible to suppress the expansion of BPD 50 into SSF 60 and also to keep the amount of warpage within the specified range.

[0111] Although the case where the SiC ingot 203 is produced by the sublimation method has been described as an example here, it may also be produced by a gas growth method. In the gas growth method, a gas inlet is provided at the bottom of the growth crucible 204, and an exhaust port is provided at the top or side of the growth crucible 204, and the SiC source gas, n-type dopant, and B dopant gas are introduced into the growth crucible 204 to produce the SiC ingot 203.

[0112] In the case of sublimation growth, after placing the raw material powder 201 in the growth crucible 204, the state of the raw material powder 201 cannot be observed during growth, whereas in the case of gas growth, the introduced gas can be controlled. Therefore, gas growth makes it easier to control the concentration of p-type impurities, including B, in the SiC ingot 203 than sublimation growth. In fact, SiC ingots 203 were manufactured using both sublimation growth and gas growth, and the concentrations of each p-type impurity were measured. When the deviation of the actual impurity concentration from the target value was confirmed, the gas growth method brought the actual impurity concentration closer to the target value for B concentration than the sublimation method. For other p-type impurities, the gas growth method sometimes brought the actual impurity concentration closer to the target value, while the sublimation method sometimes brought the actual impurity concentration closer to the target value. Therefore, gas growth is recommended for more precise control of the B concentration, but when controlling the concentrations of other p-type impurities, both gas growth and sublimation methods provide similar control.

[0113] When the SiC ingot 203 is manufactured by the gas growth method, a B-containing gas is introduced into the growth crucible 204 in addition to the SiC source gas and the n-type dopant gas. ４ , H ２ SiCl ２ , HSiCl ３ and C, which is a C raw material. ３ H ８ , C ２ H ４ Either of the above is introduced as a SiC source gas. ２ etc. as n-type dopant gas, and BCl ３ Or B ２ H ３In this case, a B-containing gas such as HCl or H is introduced. This allows the production of a SiC single crystal ingot having the above-mentioned B concentration. ２ By introducing a carrier gas such as the above into the growth crucible 204, it becomes possible to optimize the atmosphere inside the crucible and suppress the generation of polycrystals, thereby making it possible to produce the SiC ingot 203 more satisfactorily.

[0114] Furthermore, it was also measured whether the purity of the growth crucible 204 affects the accuracy of the p-type impurity concentration in the sublimation method. Specifically, Cl was added to the growth crucible 204 before the growth of the SiC ingot 203. ２ By performing a metal removal process by supplying a gas or the like, the constituent material of the growth crucible 204, such as graphite or graphite coated with a high-melting-point metal, can be highly purified. SiC ingots 203 were manufactured with and without this high-purity process, and SiC wafers 102 cut from the ingots were used to manufacture SiC semiconductor devices. The p-type impurity concentration in the SiC substrate 11 was measured. Figure 19 shows the results, and it was confirmed that there was little difference in the p-type impurity concentration in the SiC substrate 11 whether or not high-purity process was performed, and that the p-type impurity concentration could be accurately controlled in both cases. Therefore, it is possible to control the p-type impurity concentration regardless of whether high-purity process was performed.

[0115] Here, when manufacturing the SiC ingot 203 by sublimation, a B raw material powder containing boron carbide or boron nitride as the B raw material was added to the raw material powder 201 to adjust the B concentration. In addition to this, for example, aluminum carbide powder may be added as the Al raw material to adjust the Al concentration, titanium carbide powder may be added as the Ti raw material to adjust the Ti concentration, or tantalum carbide powder may be added as the Ta raw material to adjust the Ta concentration. Of course, when adjusting the concentrations of multiple p-type impurity elements, multiple combinations of these elements may be added to the raw material powder 201. Furthermore, a sintered body may be used instead of a powder containing a p-type impurity element.

[0116] Furthermore, only highly pure SiC is used as the raw material powder 201, and a chloride gas, for example, BCl 2 for the B raw material, is used as the p-type dopant gas. ３ , or hydride gas, for example, B ２ H ３ may be introduced into the growth crucible 204.

[0117] Furthermore, in addition to the fine-grained SiC powder, a coarser grained SiC powder with a B concentration of 1.2 × 10 １７ / cm ３ The above-described SiC powders may be prepared and stacked in two layers to be used as raw material powder 201. Specifically, fine-grained SiC powder may be placed on coarse-grained SiC powder, and the p-type impurity element may be supplied to the growth surface of SiC ingot 203 through the gaps between the fine-grained SiC powder.

[0118] While the present disclosure has been described based on the above-described embodiment, it is not limited to the embodiment and encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0119] For example, in the third embodiment, a case has been described in which p-type impurities other than B are introduced when the SiC ingot 203 is produced. However, it is also possible to prevent p-type impurities other than B from being introduced into the SiC ingot 203. For example, before the seed crystal 202 used to produce the SiC ingot 203 is placed in a growth crucible, a heat treatment is performed to remove p-type impurities other than B from the raw material powder 201. At this time, if the raw material powder 201 contains a B raw material powder containing boron carbide or boron nitride, sufficient B remains even after the heat treatment, and therefore the B is not completely removed. Alternatively, the B raw material powder containing boron carbide or boron nitride may be placed after the heat treatment to remove p-type impurities other than B from the raw material powder 201. Then, after the p-type impurities other than B have been removed, the seed crystal 202 is placed in a growth crucible and an SiC ingot 203 is produced, whereby it is possible to achieve a desired B concentration in the SiC ingot 203 while keeping the concentration of p-type impurities other than B as low as possible.

[0120] Furthermore, in the above embodiments, a 6-inch wafer or an 8-inch wafer is used as an example of the SiC wafer 102, but the present disclosure can also be applied to wafers of different dimensions. Even in such cases, the B concentration that can suppress the expansion of BPD 50 to SSF 60 is set to 9.0×10 when the electrical stress is 600 A or more. １６ / cm ３ When the electrical stress is 800 A or more, the B concentration is 1.5 × 10 １７ / cm ３ It would be better to do more than that.

[0121] (Viewpoints of the Present Disclosure) The above-described present disclosure can be understood from the following viewpoints, for example.

[0122] [First Aspect] A silicon carbide wafer constituting a silicon carbide substrate (11) made of n-type silicon carbide doped with n-type impurities, wherein the silicon carbide substrate contains boron, and the boron concentration in the silicon carbide substrate is 9.0 × 10 １６ / cm ３[Second Aspect] A silicon carbide wafer, wherein the boron concentration is 1.5×10 or more. １７ / cm ３ The silicon carbide wafer according to the first aspect is a 6-inch or 8-inch wafer having a thickness of 325 to 375 μm, and the boron concentration is 1.75×10 １７ / cm ３ The silicon carbide wafer according to the first or second aspect, wherein the silicon carbide wafer is an 8-inch wafer having a thickness of 475 to 525 μm, and the boron concentration is 7.2×10 １７ / cm ３ The silicon carbide wafer according to the first or second aspect, wherein: a trench gate structure including: a silicon carbide substrate (11) made of n-type silicon carbide doped with n-type impurities; an n-type low-concentration layer (13) formed on the silicon carbide substrate and having a lower n-type impurity concentration than the silicon carbide substrate; a p-type deep layer (15) formed on the low-concentration layer and having a plurality of linear portions extending in one direction in the surface direction of the silicon carbide substrate; an n-type JFET section (14) disposed on the low-concentration layer and having linear portions sandwiched between the deep layers; a p-type base region (17) disposed on the JFET section and the deep layer; an n-type source region (18) formed in a surface layer portion of the base region; a gate insulating film (22) formed on a wall surface of a gate trench (21) penetrating the source region and the base region; and a gate electrode (23) formed on the gate insulating film; and a source electrode (25) electrically connected to the source region and the base region. a drain electrode (26) electrically connected to the silicon carbide substrate, wherein the deep layer, the JFET portion, and the low concentration layer constitute a built-in diode (40), and the current density of the current flowing when the built-in diode performs a reflux operation is 11.6 A / mm ２ or more, wherein the silicon carbide substrate contains boron, and the boron concentration in the silicon carbide substrate is 9.0×10 １６ / cm ３[Sixth Aspect] A silicon carbide semiconductor device, wherein the current density of the current flowing when the built-in diode is in freewheeling operation is 14.6 A / mm ２ or more, and the boron concentration is 1.5×10 １７ / cm ３ The silicon carbide semiconductor device according to the fifth aspect is characterized in that the silicon carbide substrate has a thickness of 325 to 375 μm and the boron concentration is 1.75×10 １７ / cm ３ The silicon carbide semiconductor device according to the fifth or sixth aspect, wherein the silicon carbide substrate has a thickness of 475 to 525 μm, and the boron concentration is 7.2×10 １７ / cm ３The silicon carbide semiconductor device according to the fifth or sixth aspect, wherein: [Ninth Aspect] The silicon carbide semiconductor device according to any one of the fifth to eighth aspects, wherein the deep layer has a thickness of 1 μm or less. [Tenth Aspect] The silicon carbide semiconductor device according to any one of the fifth to eighth aspects, wherein the silicon carbide semiconductor device comprises: an n-type current spreading layer (16) formed on the JFET portion and the deep layer, and in contact with a tip end side of the gate trench in a depth direction; and a p-type linking layer (20) linking the base region and the deep layer, wherein the base region is formed on the current spreading layer and the linking layer, and the deep layer is constituted by an ion-implanted layer, and wherein the depth from a surface of the source region to a bottom of the deep layer is 1 μm or more. [Eleventh Aspect] The silicon carbide semiconductor device according to any one of the fifth to tenth aspects, wherein the low-concentration layer is constituted by an epitaxial film formed on the silicon carbide substrate. [Twelfth Aspect] A method for producing an n-type silicon carbide single crystal, comprising: arranging a seed crystal (202) for growing the silicon carbide single crystal on one surface of a pedestal (205) arranged in a growth crucible (204); and supplying a pyrolyzed silicon carbide raw material, an n-type dopant, and boron to the surface of the seed crystal, thereby producing a silicon carbide ingot (203) composed of an n-type silicon carbide single crystal on the surface of the seed crystal, wherein, in growing the silicon carbide ingot, a boron concentration in the silicon carbide ingot is increased to 9.0×10 １６ / cm ３a silicon carbide single crystal production method according to the twelfth aspect, wherein, in growing the silicon carbide ingot, a raw material powder (201) containing a boron raw material powder containing boron carbide or boron nitride as a boron raw material in addition to silicon carbide powder as the silicon carbide raw material is placed below the pedestal, an n-type dopant is supplied, and the raw material powder is heated to decompose before being supplied to the seed crystal, thereby producing the silicon carbide ingot by a sublimation method; a silicon carbide raw material gas and an n-type dopant gas are supplied below the pedestal, and the silicon carbide raw material gas is heated to decompose before being supplied to the seed crystal, thereby producing the silicon carbide ingot by a gas growth method;

Claims

1. A silicon carbide wafer constituting a silicon carbide substrate (11) made of n-type silicon carbide doped with an n-type impurity, wherein the silicon carbide substrate contains boron, and the boron concentration in the silicon carbide substrate is 9.0×10 １６ / cm ３ Silicon carbide wafers are said to be as follows:

2. The boron concentration is 1.5 x 10 １７ / cm ３ The silicon carbide wafer according to claim 1 .

3. A 6-inch or 8-inch wafer having a thickness of 325 to 375 μm, and the boron concentration is 1.75×10 １７ / cm ３ The silicon carbide wafer according to claim 1 or 2, wherein:

4. An 8-inch wafer having a thickness of 475 to 525 μm, and the boron concentration is 7.2×10 １７ / cm ３ The silicon carbide wafer according to claim 1 or 2, wherein:

5. A silicon carbide substrate (11) made of n-type silicon carbide doped with n-type impurities; an n-type low-concentration layer (13) formed on the silicon carbide substrate and having a lower n-type impurity concentration than the silicon carbide substrate; a p-type deep layer (15) formed on the low-concentration layer and having a plurality of linear portions with a longitudinal direction in one direction in the surface direction of the silicon carbide substrate; an n-type JFET section (14) arranged on the low-concentration layer and having linear portions sandwiched between the deep layers; a p-type base region (17) arranged on the JFET section and the deep layer; an n-type source region (18) formed in a surface layer portion of the base region; a gate insulating film (22) formed on a wall surface of a gate trench (21) penetrating the source region and the base region; and a gate electrode (23) formed on the gate insulating film; and a source electrode (25) electrically connected to the source region and the base region. a drain electrode (26) electrically connected to the silicon carbide substrate, wherein a built-in diode (40) is formed by the deep layer, the JFET portion, and the low concentration layer, and a current density of a current flowing when the built-in diode performs a reflux operation is 11.6 A / mm ２ or more, the silicon carbide substrate contains boron, and the boron concentration in the silicon carbide substrate is 9.0×10 １６ / cm ３ The silicon carbide semiconductor device is as described above.

6. The current density of the current flowing when the built-in diode operates as a freewheel is 14.6 A / mm ２ or more, and the boron concentration is 1.5×10 １７ / cm ３ The silicon carbide semiconductor device according to claim 5 .

7. The silicon carbide substrate has a thickness of 325 to 375 μm and a boron concentration of 1.75×10 １７ / cm ３ The silicon carbide semiconductor device according to claim 5 or 6, wherein:

8. The silicon carbide substrate has a thickness of 475 to 525 μm and a boron concentration of 7.2×10 １７ / cm ３ The silicon carbide semiconductor device according to claim 5 or 6, wherein:

9. The silicon carbide semiconductor device according to claim 5, wherein the deep layer has a thickness of 1 μm or less.

10. A silicon carbide semiconductor device as described in claim 5 or 6, comprising: an n-type current spreading layer (16) formed on the JFET portion and the deep layer and in contact with the depth-wise tip side of the gate trench; and a p-type coupling layer (20) connecting the base region and the deep layer, wherein the base region is formed on the current spreading layer and the coupling layer, the deep layer is composed of an ion-implanted layer, and the depth from the surface of the source region to the bottom of the deep layer is 1 μm or more.

11. The silicon carbide semiconductor device according to claim 5, wherein the low concentration layer is constituted by an epitaxial film formed on the silicon carbide substrate.

12. A method for producing an n-type silicon carbide single crystal, comprising: arranging a seed crystal (202) for growing a silicon carbide single crystal on one surface of a pedestal (205) arranged in a growth crucible (204); and supplying a thermally decomposed silicon carbide raw material, an n-type dopant, and boron to a surface of the seed crystal, thereby producing a silicon carbide ingot (203) composed of an n-type silicon carbide single crystal on the surface of the seed crystal, wherein in growing the silicon carbide ingot, a boron concentration in the silicon carbide ingot is increased to 9.0×10 １６ / cm ３ The above is a method for producing a silicon carbide single crystal.

13. A method for producing a silicon carbide single crystal according to claim 12, wherein, in growing the silicon carbide ingot, a raw material powder (201) containing boron raw material powder containing boron carbide or boron nitride as a raw material of the boron in addition to silicon carbide powder as the silicon carbide raw material is placed below the pedestal, an n-type dopant is supplied, and the raw material powder is heated and decomposed before being supplied to the seed crystal, thereby producing the silicon carbide ingot by a sublimation method.

14. The method for producing a silicon carbide single crystal according to claim 12, wherein, in growing the silicon carbide ingot, a boron dopant gas is supplied in addition to a silicon carbide source gas and an n-type dopant gas from below the pedestal, and the silicon carbide source gas is heated and decomposed before being supplied to the seed crystal, thereby producing the silicon carbide ingot by a gas growth method.

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