Silicon carbide semiconductor device and manufacturing method therefor

Abstract

A first impurity region (14) is an ion implantation layer. A second impurity region (15) is a recoil layer as an ion implantation layer containing impurities of a first conductivity type, wherein the impurity concentration of a second conductivity type is made higher than the impurity concentration of the first conductivity type to make the second impurity region (15) the second conductivity type. In the depth direction of a semiconductor substrate (10) from a reference surface which is along the interface between the first impurity region (14) and an electrode (20), a second peak position at which the impurity concentration of the second conductivity type in the second impurity region (15) is highest is set to a position deeper than a first peak position at which the impurity concentration of the first conductivity type in the first impurity region (14) is highest. The electrode (20) is configured with a metal silicide layer (21) that is a compound with SiC and is in contact with the semiconductor substrate (10).

Description

Silicon carbide semiconductor device and manufacturing method thereof CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Japanese Patent Application No. 2023-122606, filed on July 27, 2023, the contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a SiC semiconductor device made of silicon carbide (hereinafter also simply referred to as SiC) and having a first impurity region and a second impurity region, and a method for manufacturing the same.

[0003] Conventionally, SiC semiconductor devices made of SiC and having a first impurity region and a second impurity region have been proposed. For example, Patent Document 1 proposes a SiC semiconductor device in which a MOSFET is formed on a semiconductor substrate made of SiC. Specifically, this SiC semiconductor device has an n-type source region as the first impurity region, a p-type contact region as the second impurity region, and electrodes connected to the source region and the contact region. Note that MOSFET stands for Metal Oxide Semiconductor Field Effect Transistor. The source region and contact region in such a SiC semiconductor device are formed as follows. That is, the source region is formed by ion-implanting n-type impurities into the semiconductor substrate using a mask having an opening in a region where the source region is to be formed. The contact region is formed by ion-implanting p-type impurities into the semiconductor substrate using a mask having an opening in a region where the contact region is to be formed.

[0004] Patent No. 5408248

[0005] However, when forming the source region and the contact region as described above, a mask for forming the source region and a mask for forming the contact region must be prepared separately, which tends to increase the number of manufacturing steps.Furthermore, when forming the source region and the contact region as described above, a mask for forming the source region and a mask for forming the contact region must be prepared separately, which requires consideration of misalignment of the masks, which tends to increase the size of the SiC semiconductor device.

[0006] For this reason, the present inventors have considered manufacturing a SiC semiconductor device as follows: First, an n-type source region is formed in a semiconductor substrate without forming a mask. Then, a mask that exposes a portion of the source region is placed, and p-type impurities are ion-implanted to drive a portion of the source region back into a p-type contact region, thereby manufacturing a SiC semiconductor device. This method only requires preparing a mask for forming the contact region, and eliminates the need to separately prepare a mask for forming the source region and a mask for forming the contact region.

[0007] However, when manufacturing a SiC semiconductor device in this manner, if the peak position where the impurity concentration in the source region is highest and the peak position where the impurity concentration in the contact region is highest are the same, damage may be significant. Specifically, if the peak positions of the regions are the same, a large amount of p-type impurity ions must be ion-implanted to return part of the source region to the contact region, which may result in significant damage due to ion implantation. In this case, this damage may cause fluctuations in the characteristics of the SiC semiconductor device.

[0008] The present disclosure aims to provide a SiC semiconductor device and a manufacturing method thereof that can suppress an increase in the number of manufacturing steps, suppress an increase in size, and further suppress the occurrence of characteristic fluctuations.

[0009] According to one aspect of the present disclosure, a SiC semiconductor device includes: a semiconductor substrate made of SiC and having one side and another side opposite to the first side; a first impurity region of a first conductivity type formed on one side of the semiconductor substrate; a second impurity region of a second conductivity type formed on the one side of the semiconductor substrate and having a portion abutting the first impurity region; and an electrode electrically connected to the first impurity region and the second impurity region, wherein the first impurity region is an ion-implanted layer; the second impurity region is a counter-implanted layer serving as an ion-implanted layer containing impurities of the first conductivity type, and is of the second conductivity type by having a higher impurity concentration of the second conductivity type than a higher impurity concentration of the first conductivity type; a surface along the interface between the first impurity region and the electrode is used as a reference plane, and a second peak position at which the impurity concentration of the second conductivity type in the second impurity region is highest is located deeper than a first peak position at which the impurity concentration of the first conductivity type in the first impurity region is highest; and the electrode includes a metal silicide layer that is a compound with SiC and abuts the semiconductor substrate.

[0010] According to this, the second impurity region is a counter-imposed layer containing impurities of the first conductivity type. Therefore, a mask is not required when forming the first impurity region, and an increase in the number of manufacturing steps can be suppressed. Furthermore, since a mask is not required when forming the first impurity region, it is only necessary to consider misalignment of one mask, and an increase in the size of the SiC semiconductor device can be suppressed.

[0011] In addition, in this SiC semiconductor device, the second peak position is deeper than the first peak position. Therefore, compared to when the second peak position is set at the same depth as the first peak position, the amount of second conductivity type impurity required to form the second impurity region by striking back the first impurity region can be reduced, thereby reducing damage that may occur to the semiconductor substrate. Therefore, the occurrence of characteristic fluctuations can be suppressed.

[0012] Furthermore, in this SiC semiconductor device, the electrodes are configured to include a metal silicide layer. The metal silicide layer is configured to include SiC that constitutes the semiconductor substrate. That is, the metal silicide layer is configured by reacting portions that are damaged by ion implantation. Therefore, in this SiC semiconductor device, fewer portions remain that are damaged by ion implantation, and the occurrence of characteristic fluctuations is suppressed.

[0013] According to another aspect of the present disclosure, the method for manufacturing a SiC semiconductor device described above includes: preparing a semiconductor substrate; ion-implanting a first impurity of a first conductivity type from one surface side of the semiconductor substrate to form a first conductivity type region; arranging a mask on the one surface side of the semiconductor substrate, the mask having an opening corresponding to a region where a second impurity region is to be formed; ion-implanting a second impurity of a second conductivity type from the one surface side of the semiconductor substrate to return a portion of the first conductivity type region to form a second impurity region, and designating a region of the first conductivity type region different from the second impurity region as the first impurity region; and, after ion-implanting the second impurity, arranging a metal layer on the one surface side of the semiconductor substrate and reacting the metal layer with the semiconductor substrate to form a metal silicide layer that constitutes an electrode. In the ion-implantation of the second impurity, the second impurity is ion-implanted so that the second peak position is located at a position deeper than the first peak position.

[0014] According to this method, the first impurity region is irradiated to form the second impurity region. Therefore, a mask is not required when forming the first impurity region, and an increase in the number of manufacturing steps can be suppressed. Furthermore, since a mask is not required when forming the first impurity region, it is only necessary to consider misalignment of one mask, and an increase in the size of the SiC semiconductor device can be suppressed.

[0015] In this method for manufacturing a SiC semiconductor device, the second peak position is positioned deeper than the first peak position. Therefore, compared to when the second peak position is positioned at the same depth as the first peak position, the amount of second conductivity type impurity required to strike back the first impurity region and form the second impurity region can be reduced, thereby reducing damage that may occur to the semiconductor substrate. Therefore, a SiC semiconductor device with reduced characteristic variations can be manufactured.

[0016] Furthermore, in this method for manufacturing a SiC semiconductor device, an electrode including a metal silicide layer is formed. The metal silicide layer is composed of SiC that constitutes the semiconductor substrate. In other words, the metal silicide layer is formed by reacting portions that are damaged by ion implantation. Therefore, this method for manufacturing a SiC semiconductor device can reduce the remaining portions that are damaged by ion implantation, and can manufacture a SiC semiconductor device that suppresses characteristic fluctuations.

[0017] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below.

[0018] 3A is a cross-sectional view of a SiC semiconductor device in a first embodiment; FIG. 3B is a view showing impurity concentrations along line IIA-IIA in FIG. 1; FIG. 3C is a cross-sectional view showing impurity concentrations along line IIB-IIB in FIG. 1; FIG. 3D is a cross-sectional view showing impurity concentrations along line IV-IV in FIG. 3D; FIG. 3E is a cross-sectional view of a SiC semiconductor device in a second embodiment; FIG. 3F is a cross-sectional view showing impurity concentrations along line IV-IV in FIG. 3F; FIG. 3G is a cross-sectional view of a SiC semiconductor device in a second embodiment;

[0019] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following embodiments, identical or equivalent parts will be denoted by the same reference numerals.

[0020] First Embodiment A first embodiment will be described with reference to the drawings. In this embodiment, an SiC semiconductor device in which an inversion MOSFET having a trench gate structure is formed will be described as an example.

[0021] 1, the SiC semiconductor device is configured using a semiconductor substrate 10 made of SiC. Specifically, the semiconductor substrate 10 of the SiC semiconductor device is a n-type semiconductor substrate made of SiC. ＋ In this embodiment, the substrate 11 has an off-angle of 0 to 8° with respect to the (0001) Si plane, and an n-type impurity concentration of nitrogen, phosphorus, or the like of 1.0×10 １９ / cm ３ The substrate 11 has a thickness of about 50 to 300 μm. In this embodiment, the substrate 11 constitutes a drain region.

[0022] On the surface of the substrate 11, a n-type SiC substrate is formed. － A p-type drift layer 12 and a p-type base layer 13 are formed by epitaxial growth, etc. In the following description, the surface of semiconductor substrate 10 facing base layer 13 is referred to as one surface 10a of semiconductor substrate 10, and the surface of semiconductor substrate 10 facing substrate 11 is referred to as the other surface 10b of semiconductor substrate 10.

[0023] The drift layer 12 has an n-type impurity concentration of, for example, 1.0 to 50.0×10 １５ / cm ３ The base layer 13 is formed on the drift layer 12 and has a p-type impurity concentration of, for example, 2.0×10 １７ / cm ３ The thickness is about 0.5 to 2 μm.

[0024] The surface layer of the base layer 13 is ＋ type source region 14 and p ＋ A contact region 15 of a type is formed in the source region 14. The source region 14 is formed so as to contact the side surface of a trench 17, which will be described later. The contact region 15 is formed on the opposite side of the source region 14 from the trench 17, with the source region 14 in between, and is formed to a depth deeper than the source region 14.

[0025] In this embodiment, a recess 16 recessed from the surface 10a of the semiconductor substrate 10 is formed in the surface 10a. The contact region 15 is formed so as to be exposed from the bottom surface of the recess 16, and the source region 14 is formed so as to be exposed from a portion of the surface 10a of the semiconductor substrate 10 different from the portion where the recess 16 is formed. In other words, in the normal direction to the surface 10a of the semiconductor substrate 10, the contact region 15 is formed so as to overlap with the recess 16, and the source region 14 is formed in a region different from the region overlapping with the recess 16. In other words, in the normal direction to the surface 10a of the semiconductor substrate 10, it can also be said that when viewed from the normal direction to the surface 10a of the semiconductor substrate 10.

[0026] Furthermore, as will be described later, the contact region 15 in this embodiment is formed by ion-implanting a larger amount of p-type impurities than n-type impurities into the n-type region, thereby driving the n-type region back into the p-type region. Therefore, the contact region 15 is also formed to contain n-type impurities. In this embodiment, the source region 14 corresponds to the first impurity region, and the contact region 15 corresponds to the second impurity region. Furthermore, the source region 14 and the contact region 15 are ion-implanted layers formed by ion implantation, as will be described later, and the contact region 15 corresponds to a driving layer into which the n-type region is driven back.

[0027] Trenches 17, for example, with a width of about 0.8 μm, are formed in semiconductor substrate 10 so as to penetrate base layer 13 and source region 14 and reach drift layer 12. Although two trenches 17 are shown in FIG. 1 , in reality, multiple trenches 17 are formed in the shape of stripes that are equally spaced in the left-right direction of the page.

[0028] Each trench 17 is filled with a gate insulating film 18 formed to cover the wall surface of the trench 17 and a gate electrode 19 made of polysilicon or the like formed on the gate insulating film 18. In this embodiment, a trench gate structure is configured in this manner. In this embodiment, the portion of the wall surface of the trench 17 that contacts the base layer 13 becomes the surface of the base layer 13 sandwiched between the first impurity region and the drift layer 12.

[0029] An upper electrode 20 electrically connected to the source region 14 and the contact region 15 is formed on one surface 10a of the semiconductor substrate 10. In this embodiment, the upper electrode 20 has a metal silicide layer 21 formed at the interface with the semiconductor substrate 10, and a main portion 22 disposed on the metal silicide layer 21.

[0030] Specifically, the metal silicide layer 21 is a metal layer that is a compound that has undergone a silicidation reaction with SiC (i.e., the semiconductor substrate 10), and serves to reduce the contact resistance with SiC to provide ohmic contact. The metal silicide layer 21 is formed along one surface 10a of the semiconductor substrate 10. In this embodiment, since the recess 16 is formed in the one surface 10a of the semiconductor substrate 10, the portion of the metal silicide layer 21 that is located above the recess 16 is recessed.

[0031] The metal silicide layer 21 is composed of a refractory metal-based or noble metal-based silicide, such as a nickel silicide layer, a titanium silicide layer, a tantalum silicide layer, a tungsten silicide layer, or a molybdenum silicide layer. In this case, the metal silicide layer 21 may be composed of one type of metal or multiple types of metals. For example, the types of metals constituting the metal silicide layer 21 may differ between n-type SiC and p-type SiC. In this embodiment, an example will be described in which the metal silicide layer 21 is composed of a nickel silicide layer. The film thickness of the metal silicide layer 21 can be changed as appropriate, but is set to, for example, about 10 to 100 nm.

[0032] The main portion 22 is made of, for example, aluminum silicon or the like, and is formed to be thicker than the metal silicide layer 21. Although not particularly shown, the main portion 22 may have a plated film of nickel, gold, or the like formed on the surface opposite to the metal silicide layer 21 side.

[0033] A lower electrode 23 electrically connected to the substrate 11 is formed on the other surface 10b of the semiconductor substrate 10. In the SiC semiconductor device of this embodiment, this structure forms an n-channel inversion-type trench-gate MOSFET. In this embodiment, the n-type corresponds to the first conductivity type, and the p-type corresponds to the second conductivity type.

[0034] In such a SiC semiconductor device, when a voltage equal to or greater than a predetermined threshold voltage is applied to the gate electrode 19 while a voltage lower than that of the lower electrode 23 is applied to the upper electrode 20, an n-type inversion layer (i.e., a channel) is formed in the portion of the base layer 13 that contacts the trench 17. Then, electrons are supplied from the source region 14 to the drift layer 12 through the inversion layer, turning the device on.

[0035] The above is the basic configuration of the SiC semiconductor device according to this embodiment. Next, the impurity concentrations of the source region 14 and the contact region 15 in the SiC semiconductor device will be described with reference to Figures 2A and 2B. In the following description, the plane along the interface between the source region 14 and the upper electrode 20 is used as the reference plane.

[0036] As will be described later, the contact region 15 in this embodiment is formed by ion-implanting p-type impurities into the n-type region and driving a part of the n-type region back into the p-type region. The source region 14 is formed from a part of the n-type region that is different from the contact region 15, as will be described later.

[0037] 2A , the first peak position P1 where the n-type impurity concentration is highest is used as the reference plane for the source region 14. In other words, the first peak position P1 where the n-type impurity concentration of the source region 14 is highest is the interface with the metal silicide layer 21. Hereinafter, the first peak position P1 where the n-type impurity concentration of the source region 14 is highest will also be simply referred to as the first peak position P1 of the source region 14.

[0038] The contact region 15 is formed by doping an n-type region with a p-type region. Therefore, as shown in FIG. 2B , the contact region 15 also contains n-type impurities, and is configured as a p-type region by making the p-type impurity concentration higher than the n-type impurity concentration. The second peak position P2, where the p-type impurity concentration is highest, of the contact region 15 is located at the interface with the bottom surface of the recess 16. In other words, the second peak position P2, where the p-type impurity concentration of the contact region 15 is highest, is located at the interface with the metal silicide layer 21. Hereinafter, the second peak position P2, where the p-type impurity concentration of the contact region 15 is highest, will also be simply referred to as the second peak position P2 of the contact region 15.

[0039] In this embodiment, as described above, the first peak position P1 of the source region 14 and the second peak position P2 of the contact region 15 are different, and the second peak position P2 is formed at a deeper position than the first peak position P1. Note that, because the source region 14 and the contact region 15 are formed by ion implantation, the impurity concentrations decrease in the depth direction from each of the peak positions P1 and P2. Therefore, the n-type impurity concentration at the second peak position P2 is lower than the n-type impurity concentration at the first peak position P1.

[0040] Furthermore, the contact region 15 contains n-type impurities as described above. In such contact region 15, the contact resistance with the upper electrode 20 (metal silicide layer 21) depends on the concentration difference d between the p-type impurity concentration and the n-type impurity concentration, and decreases as the concentration difference d increases. For this reason, in this embodiment, the impurity concentration at the second peak position P2 is set higher than the impurity concentration at the first peak position P1.

[0041] Next, a method for manufacturing the source region 14 and the contact region 15 in the SiC semiconductor device will be described with reference to Figures 3A to 3F. Note that Figures 3A to 3F omit the portion of the other surface 10b of the semiconductor substrate 10.

[0042] 3A, a semiconductor substrate 10 formed up to the base layer 13 is prepared, and without placing a mask, n-type impurities are ion-implanted from one surface 10a of the semiconductor substrate 10 to form an n-type region 30 on the base layer 13. Note that a part of the n-type region 30 will become the source region 14, and corresponds to a first conductivity type region.

[0043] 3B, a mask 40 is placed on the surface 10a of the semiconductor substrate 10. Then, the mask 40 is patterned so that an area on the surface 10a of the semiconductor substrate 10 where the contact region 15 is to be formed is opened.

[0044] 3C, RIE (abbreviation of reactive ion etching) or the like is performed to form recesses 16 in the portions of one surface 10a of semiconductor substrate 10 that are exposed from mask 40. The depth of recesses 16 is set according to the amount of SiC to be reacted when forming metal silicide layer 21, and after the step of FIG. 3C is completed, recesses 16 are shallower than recesses 16 of the SiC semiconductor device shown in FIG.

[0045] 3D , the mask 40 used to form the recess 16 is used as is to implant p-type impurities into the bottom surface of the recess 16, thereby driving the exposed portion of the n-type region 30 back into the p-type region. As a result, the contact region 15 is formed in the driven portion of the n-type region 30, and the source region 14 is formed in a portion of the n-type region 30 different from the contact region 15.

[0046] In this embodiment, the p-type impurity ions are implanted at approximately the same acceleration voltage as that used for implanting n-type impurities. Therefore, the relationship between the first peak position P1 of the source region 14 and the second peak position P2 of the contact region 15 after the step of FIG. 3D is as shown in FIG. 4 . Although not specifically shown, the ion implantation of n-type and p-type impurities causes damage and defects on the surface 10a of the semiconductor substrate 10. FIG. 4 also shows the n-type impurity concentration in the source region 14 and the p-type impurity concentration in the contact region 15 along line IV-IV in FIG. 3D . The n-type impurity concentration in the contact region 15, located deeper than the bottom of the recess 16 in FIG. 4 , is the same as that in the source region 14. Furthermore, the period after the step of FIG. 3D can be rephrased as the period before the metal silicide layer 21 is formed.

[0047] When n-type impurities and p-type impurities are ion-implanted at approximately the same acceleration voltage, the distance between the implantation surface and the peak position where the impurity concentration is highest is approximately the same. Therefore, as shown in Figure 4, a first distance L1 between the surface 10a of the semiconductor substrate 10 and the first peak position P1 is approximately equal to a second distance L2 between the bottom surface of the recess 16 and the second peak position P2. In this embodiment, the first distance L1 and the second distance L2 are adjusted depending on the amount of SiC reacted when forming the metal silicide layer 21, which will be described later.

[0048] As described above, the contact resistance between the contact region 15 and the upper electrode 20 depends on the concentration difference d between the p-type impurity concentration and the n-type impurity concentration. Therefore, in this embodiment, the p-type impurity concentration at the second peak position P2 is made higher than the n-type impurity concentration at the first peak position P1, thereby increasing the concentration difference d and reducing the contact resistance. Note that if the first peak position P1 and the second peak position P2 are at the same depth, achieving the same contact resistance as in this embodiment requires further increasing the p-type impurity concentration, which would make the surface 10a of the semiconductor substrate 10 more rough.

[0049] 3E, a mask (not shown) is placed and anisotropic etching such as RIE is performed to form trenches 17. Thereafter, a gate insulating film 18 and a gate electrode 19 are formed in the trenches 17 by a method such as CVD (short for chemical vapor deposition). Then, unnecessary portions of the gate insulating film 18 and the gate electrode 19 formed on one surface 10a of the semiconductor substrate 10 are removed.

[0050] Next, as shown in FIG. 3F , a metal layer such as nickel is formed on one surface 10a of the semiconductor substrate 10 by sputtering or the like, and a heat treatment is performed to react the metal layer with the semiconductor substrate 10 (i.e., SiC) to form a metal silicide layer 21. That is, the metal silicide layer 21 is formed by reacting the damaged portions of the semiconductor substrate 10. In this embodiment, the thickness of the metal silicide layer 21 is adjusted by adjusting the heating temperature or the like so that the first peak position P1 of the source region 14 and the second peak position P2 of the contact region 15 are located at the interface with the metal silicide layer 21. That is, by adjusting the thickness of the metal silicide layer 21 by adjusting the amount of reaction with the metal layer of the semiconductor substrate 10, the first peak position P1 of the source region 14 and the second peak position P2 of the contact region 15 are located at the interface with the metal silicide layer 21. As a result, the impurity concentration in the depth direction of the source region 14 becomes as shown in FIG. 2A , and the impurity concentration in the depth direction of the contact region 15 becomes as shown in FIG. 2B .

[0051] In this step, the semiconductor substrate 10 reacts with the metal layer to form the metal silicide layer 21, so that the surface 10a of the semiconductor substrate 10 and the bottom surface of the recess 16 are dug deeper than before the formation of the metal silicide layer 21. In this step, the metal silicide layer 21 is formed so that the first peak position P1 of the source region 14 and the second peak position P2 of the contact region 15 are located at the interface with the metal silicide layer 21, but some deviation from the target positions can be tolerated due to manufacturing errors, etc.

[0052] Thereafter, although not shown, a metal layer that will become the main portion 22 is disposed to form the upper electrode 20 and the lower electrode 23, thereby manufacturing the SiC semiconductor device shown in FIG.

[0053] According to the present embodiment described above, the contact region 15 is a counter-imposed layer containing n-type impurities. This eliminates the need for a mask when forming the source region 14, thereby preventing an increase in the number of manufacturing steps. Furthermore, because the need for a mask when forming the source region 14 is eliminated, only misalignment of the mask when forming the contact region 15 needs to be considered, preventing the SiC semiconductor device from becoming larger.

[0054] Furthermore, in the SiC semiconductor device of this embodiment, the second peak position P2 is set deeper than the first peak position P1. Therefore, compared to when the second peak position is set at the same depth as the first peak position, the amount of p-type impurity required to drive back the source region 14 and form the contact region 15 can be reduced, thereby reducing damage that may occur to the semiconductor substrate 10. Therefore, the occurrence of characteristic variations is suppressed.

[0055] Furthermore, in this SiC semiconductor device, the upper electrode 20 is configured to include a metal silicide layer 21. The metal silicide layer 21 is configured to include SiC that constitutes the semiconductor substrate 10. In other words, the metal silicide layer 21 is formed by reacting a portion that is damaged by ion implantation. Therefore, in this SiC semiconductor device, fewer portions that are damaged by ion implantation remain, and the occurrence of characteristic fluctuations is suppressed.

[0056] (1) In this embodiment, the second peak position P2 is made deeper than the first peak position P1 by forming the recess 16 and ion-implanting p-type impurities into the bottom surface of the recess 16. This allows ion-implantation of n-type impurities and p-type impurities at the same acceleration voltage, further simplifying the manufacturing process.

[0057] (2) In this embodiment, the first peak position P1 and the second peak position P2 are positioned at the interface with the metal silicide layer 21 that constitutes the upper electrode 20. This allows the contact resistance between the upper electrode 20 and both the source region 14 and the contact region 15 to be reduced.

[0058] In this embodiment, the contact region 15 contains n-type impurities. The contact resistance between the contact region 15 and the metal silicide layer 21 is caused by a concentration difference d between the n-type impurity concentration and the p-type impurity concentration at the interface between the contact region 15 and the metal silicide layer 21, and decreases as the concentration difference d increases. In this embodiment, the second peak position P2 is formed at a position deeper than the first peak position P1. Therefore, compared to the case where the first peak position P1 is the same as the second peak position P2, it is easier to increase the concentration difference d without increasing the p-type impurity concentration, and it is easier to reduce the contact resistance.

[0059] Second Embodiment A second embodiment will be described. This embodiment is different from the first embodiment in that the method of forming the contact region 15 is changed. As the other aspects are the same as those of the first embodiment, a description thereof will be omitted here.

[0060] 5, in the SiC semiconductor device of this embodiment, the metal silicide layer 21 has a planarized surface on the side opposite to the semiconductor substrate 10. In this embodiment, the metal silicide layer 21 is made thicker in the portion located above the contact region 15 than in the portion located above the source region 14.

[0061] The above is the configuration of the SiC semiconductor device according to this embodiment. Next, a manufacturing process of the SiC semiconductor device according to this embodiment will be described.

[0062] In this embodiment, after performing the step of Fig. 3B, p-type impurities are ion-implanted to drive the portion of n-type region 30 exposed from mask 40 back into the p-type region, thereby forming contact region 15 and source region 14. Specifically, in this embodiment, unlike the step of Fig. 3C, p-type impurities are ion-implanted without forming recess 16. At this time, in this embodiment, the p-type impurities are ion-implanted at a higher acceleration voltage than when n-type impurities are ion-implanted to form n-type region 30, so that second peak position P2 is deeper than first peak position P1.

[0063] In this case, the acceleration voltage when ion-implanting p-type impurities is set higher than the acceleration voltage when ion-implanting n-type impurities, so the portion of one surface 10a of the semiconductor substrate 10 into which the p-type impurities are ion-implanted is likely to suffer significant damage and its crystallinity is likely to be destroyed.

[0064] Next, the steps of FIGS. 3E and 3F are performed. When forming the metal silicide layer 21 in the step of FIG. 3F, the more the crystallinity is degraded, the more likely the metal layer and the semiconductor substrate 10 will react to form the metal silicide layer 21. Therefore, the metal silicide layer 21 is more likely to be formed in the contact region 15 than in the source region 14, and the metal silicide layer 21 is formed deep in the contact region 15. As a result, a recess 16 is formed in the semiconductor substrate 10 in the portion where the contact region 15 is to be formed. In addition, in this embodiment, the SiC that reacts with the metal layer is adjusted by roughening one surface 10a of the semiconductor substrate 10, so the surface of the metal silicide layer 21 opposite the semiconductor substrate 10 side is planarized.

[0065] Thereafter, in the same manner as in the first embodiment, the main portion 22 is disposed, the upper electrode 20 is formed, and the lower electrode 23 is also formed, thereby manufacturing the SiC semiconductor device shown in FIG.

[0066] According to the present embodiment described above, since the contact region 15 is a reverse layer, the same effects as those of the first embodiment can be obtained.

[0067] (1) In this embodiment, the second peak position P2 is made deeper than the first peak position P1 by changing the acceleration voltage. Therefore, a step for forming the recess 16 is not required, and the number of manufacturing steps can be reduced.

[0068] (Other Embodiments) While the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0069] For example, in each of the above embodiments, an example has been described in which a SiC semiconductor device is configured by forming an n-channel type trench gate MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type. However, the SiC semiconductor device may be configured by forming a p-channel type trench gate MOSFET in which the first conductivity type is p-type and the second conductivity type is n-type. Furthermore, the SiC semiconductor device may be configured such that, in addition to a MOSFET, an IGBT having a similar structure is formed. In the case of an IGBT, the n-channel type MOSFET in each of the above embodiments may be formed by forming a p-channel type trench gate MOSFET in which the first conductivity type is p-type and the second conductivity type is n-type. ＋ The substrate 11 is ＋ Other than the change to the collector layer of the type, this is the same as the vertical MOSFET described in each of the above embodiments.

[0070] In the above embodiments, a method has been described in which p-type impurities are ion-implanted after the n-type region 30 is formed, and a portion of the n-type region 30 is driven back into the p-type region. However, the p-type region may be formed first, and then n-type impurities are ion-implanted to drive a portion of the p-type region back into the n-type region.

[0071] In each of the above embodiments, the n-type impurity concentration at the first peak position P1 and the p-type impurity concentration at the second peak position P2 may be the same, or the n-type impurity concentration at the first peak position P1 may be higher than the p-type impurity concentration at the second peak position P2.

Claims

1. A silicon carbide semiconductor device made of silicon carbide, comprising: a semiconductor substrate (10) made of silicon carbide and having one surface (10a) and another surface (10b) opposite to the one surface; a first impurity region (14) of a first conductivity type formed on one surface side of the semiconductor substrate; a second impurity region (15) of a second conductivity type formed on one surface side of the semiconductor substrate and having a portion abutting the first impurity region; and an electrode (20) electrically connected to the first impurity region and the second impurity region, wherein the first impurity region is an ion-implanted layer, and the second impurity region is a counter-implanted layer serving as an ion-implanted layer containing impurities of the first conductivity type, and is of the second conductivity type by having a higher impurity concentration of the second conductivity type than a higher impurity concentration of the first conductivity type, a second peak position (P2) at which the concentration of the second conductivity type impurity in the second impurity region is highest is located deeper than a first peak position (P1) at which the concentration of the first conductivity type impurity in the first impurity region is highest, in a depth direction of the semiconductor substrate from a reference plane that is a plane along the interface between the first impurity region and the electrode; and the electrode is configured to include a metal silicide layer (21) that is a compound with the silicon carbide and abuts the semiconductor substrate.

2. The silicon carbide semiconductor device according to claim 1, wherein the semiconductor substrate has a recess (16) formed on the one surface side, and the second impurity region is formed at a position overlapping the recess in a normal direction to the one surface of the semiconductor substrate.

3. The silicon carbide semiconductor device according to claim 1, wherein the first peak position and the second peak position are located at an interface with the metal silicide layer.

4. A semiconductor substrate (10) made of silicon carbide and having one surface (10a) and another surface (10b) opposite to the first surface; a first impurity region (14) of a first conductivity type formed on the one surface side of the semiconductor substrate; a second impurity region (15) of a second conductivity type formed on the one surface side of the semiconductor substrate and having a portion abutting the first impurity region; and an electrode (20) electrically connected to the first impurity region and the second impurity region, wherein the first impurity region is an ion-implanted layer, and the second impurity region is a counter-implanted layer serving as an ion-implanted layer containing impurities of the first conductivity type, and is of the second conductivity type by having a higher impurity concentration of the second conductivity type than a higher impurity concentration of the first conductivity type, a first peak position (P2) at which the impurity concentration of the second conductivity type in the second impurity region is highest is located deeper than a first peak position (P1) at which the impurity concentration of the first conductivity type in the first impurity region is highest in a depth direction of the semiconductor substrate from a reference plane that is a plane along an interface between the first impurity region and the electrode, and the electrode is configured to include a metal silicide layer (21) that is a compound with the silicon carbide and is in contact with the semiconductor substrate, the method comprising the steps of: preparing the semiconductor substrate; ion-implanting a first impurity of the first conductivity type from one surface side of the semiconductor substrate to form a first conductivity type region (30); arranging a mask (40) on the one surface side of the semiconductor substrate, the mask having an opening in a region where the second impurity region is to be formed; ion-implanting a second impurity of the second conductivity type from the one surface side of the semiconductor substrate, and driving back a portion of the first conductivity type region to form the second impurity region, and defining a region of the first conductivity type region different from the second impurity region as the first impurity region; a metal layer is disposed on one surface side of the semiconductor substrate after the second impurity is ion-implanted, and the metal layer is reacted with the semiconductor substrate to form the metal silicide layer that constitutes the electrode; and in the ion-implantation of the second impurity, the second impurity is ion-implanted such that the second peak position is located at a position deeper than the first peak position.

5. A method for manufacturing a silicon carbide semiconductor device as described in claim 4, wherein the ion implantation of the second impurity includes forming a recess (16) in a region of one surface of the semiconductor substrate in which the second impurity region is to be formed, and ion implanting the second impurity into a bottom surface of the recess.

6. A method for manufacturing a silicon carbide semiconductor device as described in claim 5, wherein, in forming the recess, a mask (40) having an opening in a region where the second impurity region is to be formed is placed to form the recess, and, in ion-implanting the second impurity, the mask is used as is to ion-implant the second impurity from the bottom surface of the recess.

7. A method for manufacturing a silicon carbide semiconductor device as described in claim 4, wherein the second impurity region is ion-implanted at an acceleration voltage higher than an acceleration voltage used for ion-implanting the first impurity, thereby making the second peak position deeper than the first peak position.

8. A method for manufacturing a silicon carbide semiconductor device according to any one of claims 4 to 7, wherein, in forming the metal silicide layer, a thickness of the metal silicide layer is adjusted so that the first peak position and the second peak position are located at the interface between the metal silicide layer and the semiconductor substrate.

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