Low-EMI switchable inductors

Abstract

A low-EMI (electromagnetic interference) switchable inductor includes a first winding and a second winding, the first and second windings configured in a figure-eight shape, the first winding includes a first loop and a second loop, the second winding includes a third loop having two portions, and a switch coupled between the two portions of the third loop. The first loop is longer than the second loop, disposed around the second loop, and the first and second loops share a first cross-over structure. The first and third loops share a second cross-over structure, and in some embodiments, the switch may be implemented as a field effect transistor (FET). The first and third loops share a second cross-over structure. The first loop comprises a first conductive material having a first width, and the second loop comprises a second conductive material having a second width, and the first width and the second width are different from each other.

Description

LOW-EMI SWITCHABLE INDUCTORSBACKGROUND

[0001] Embodiments of the present disclosure relate to a low-EMI (electromagnetic interference) switchable inductor.

[0002] Phase-locked loop (PLL) circuits that include a voltage-controlled oscillator (VCO) having an inductor may be found in a wide variety of high-frequency applications, such as clock clean-up circuits, local oscillators for high performance radio communication links, and ultra-fast switching frequency synthesizers in vector network analyzers, for example. The design of a VCO presents a fundamental trade-off between phase noise, frequency coverage, and power consumption. There is an inverse relationship between the quality factor (Q) of the oscillator and the VCO phase noise, i.e., as the quality factor of the oscillator increases, the VCO phase noise decreases. However, there is also an inverse relationship between Q and oscillator frequency range, i.e., higher Q circuits have narrower frequency ranges.SUMMARY

[0003] According to one aspect of this disclosure, a switchable inductor includes a first winding and a second winding, the first winding and the second winding together configured in a figure-eight shape, wherein the first winding includes a first loop and a second loop, wherein the second winding includes a third loop having two portions, and a switch coupled between the two portions of the third loop.

[0004] According to another aspect, a switchable inductor includes a first patterned conductor, a second patterned conductor, a third patterned conductor, and a fourth patterned conductor, wherein the first, second, and third patterned conductors are disposed on a first interconnect level of an integrated circuit, and the fourth patterned conductor is disposed on a second interconnect level of the integrated circuit, a first cross-over structure coupled between the first patterned conductor and the third patterned conductor, a second cross-over structure coupled between the second patterned conductor and the third patterned conductor, and a switch coupled between the first patterned conductor and the second patterned conductor, wherein the first patterned conductor forms a first portion of a first loop and a first portion of athird loop, the second patterned conductor forms a second portion of the third loop, and the third patterned conductor forms a second portion of the first loop.

[0005] According to yet another aspect, a voltage-controlled oscillator includes a first transistor having a gate terminal, a drain terminal, and a source terminal, coupled drain-to- source between a first node and a tail tune circuit, a second transistor having a gate terminal, a drain terminal, and a source terminal, coupled drain-to-source between a second node and the tail tune circuit, a figure-eight switchable inductor coupled between the drain terminal of the first transistor and the drain terminal of the second transistor; and a programmable tail tune circuit coupled to the source terminal of the first transistor, coupled to the source terminal of the second transistor, and coupled to a ground node, wherein the gate terminal of the first transistor is coupled to the drain terminal of the second transistor, and the gate terminal of the second transistor is coupled to the drain terminal of the first transistor, and wherein the figureeight switchable inductor includes a first winding and a second winding, the first winding and the second winding together configured in a figure-eight shape, wherein the first winding includes a first loop and a second loop, wherein the second winding includes a third loop having two portions, and a switch coupled between the two portions of the third loop.

[0006] These illustrative embodiments are mentioned not to limit or define the present disclosure, but to provide examples to aid understanding thereof. Additional embodiments are discussed in the Detailed Description, and further description is provided there.BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

[0008] FIG. 1 is a high-level block diagram of a phase-locked loop including a voltage- controlled oscillator.

[0009] FIG. 2 is a circuit schematic of an illustrative voltage-controlled oscillator including a baseline switchable inductor.

[0010] FIG. 3 A is a representation of a baseline switchable inductor including two switches.

[0011] FIG. 3B is a layout diagram showing a physical layout pattern of the baseline switchable inductor of FIG. 3 A.

[0012] FIG. 4A is a representation of a switchable inductor having a figure-eight configuration and one switch in accordance with this disclosure.

[0013] FIG. 4B is a layout diagram showing a physical layout pattern of the figure-eight switchable inductor of FIG. 4A in accordance with this disclosure.

[0014] FIG. 5 is a layout diagram showing an alternative physical layout pattern of the switchable inductor having a figure-eight configuration and one switch in accordance with this disclosure.

[0015] FIG. 6 is a circuit schematic of a voltage-controlled oscillator having a switchable inductor in accordance with this disclosure.

[0016] FIG. 7 illustrates the connection of a field effect transistor switch to the winding of a switchable inductor by way of a stack of metal interconnect levels and vias, in accordance with this disclosure.

[0017] Various illustrative embodiments of this disclosure will be described with reference to the accompanying drawings.DETAILED DESCRIPTION

[0018] In modem communication systems, such as but not limited to 5G communication systems, there is a need to achieve VCO operation over a wide band of frequencies.Unfortunately, the use of high-Q inductors to achieve low phase noise in conventional VCO designs results in VCO operation over a relatively narrow band of frequencies. In some cases, the lack of low-phase noise, wideband VCOs has resulted in designers choosing to use two or more VCOs each having a different frequency band of operation. However, having two or more low phase noise, narrow-band VCOs take up a greater amount of an integrated circuit’s area. This extra area may be due not only to the presence of one or more additional VCOs, but may also be due to the EMI between them, thus requiring additional spacing between those VCOs. And, the presence of additional VCOs may also result in an undesirable increase in power consumption.

[0019] Various embodiments of this disclosure provide switchable inductors having characteristics that are desirable for use in at least low-phase noise, wideband VCOsimplemented on integrated circuits. Various embodiments provide switchable inductors with high-Q and suitability for wideband oscillator operation.

[0020] An inductor is a circuit element that is used in many types of electronic circuits. An inductor is a passive electronic component that can store energy in a magnetic field when current flows through it. However, when the current in an inductor changes, it can create an electromagnetic field that can interfere with nearby electronic devices. This phenomenon is known as electromagnetic interference (EMI). The EMI generated by an inductor depends on the rate of change of the current flowing through it, its inductance value, and the frequency of the signal that is provided to the inductor. The EMI from an inductor can be conducted or radiated. Conducted EMI occurs when the electromagnetic field generated by the inductor induces unwanted signals in nearby conductors. This can happen through direct physical contact or through a shared ground or power supply. Radiated EMI occurs when the electromagnetic field generated by the inductor is emitted as electromagnetic waves. These waves can interfere with other electronic devices that are sensitive to electromagnetic radiation. For example, if an inductor is placed near a radio receiver, the EMI generated by the inductor can cause unwanted interference in the radio signal. Traditionally, to reduce EMI from an inductor, shielding techniques have been used, such as placing the inductor in a shielded enclosure. However, shielding enclosures may be less desirable for electronic products implemented as integrated circuits where the area consumed by various features is at a premium. In the past, careful circuit layout and proper grounding have helped to reduce the effects of EMI.

[0021] Historically, inductors were implemented as discrete components. However, as circuit technology has advanced, the implementation of inductors has expanded beyond discrete components to include inductors fabricated on integrated circuits. As indicated above, the amount of area required to implement circuit elements and structures on an integrated circuit is at a premium. Thus, designers have sought to achieve the desired electrical characteristics in smaller and smaller areas.

[0022] A figure-eight inductor, also known as a spiral inductor, is a type of inductor that may be used in integrated circuits (ICs) for radio frequency (RF) applications. As its name suggests, a figure-eight inductor is shaped like the number “8” or a spiral, with multiple loops of a conductor. In IC design, a figure-eight inductor is typically fabricated by providing and patterning a thin layer of conductive material, such as but not limited to, aluminum, aluminumalloys, and copper and various conductive barrier layers used to produce patterned conductive layers on one or more levels of a partially fabricated integrated circuit. Figure-eight inductors are commonly used in RF circuits, such as filters, oscillators, and amplifiers, where they can provide a compact and efficient means of creating inductance.

[0023] The inductance of a figure-eight inductor depends on the number of turns, the width of the conductor, the spacing between the turns, and its size and shape in general. The inductance may be tuned by adjusting these parameters, and / or even by adding capacitive elements to the circuit in which the inductor is included.

[0024] Inductors have a number of properties and characteristics that affect their performance in a circuit. For example, the quality factor (Q factor) of an inductor is a measure of its efficiency and is defined as the ratio of its inductive reactance to its resistance. The Q factor describes the ability of an inductor to store energy in its magnetic field and to passively transfer that energy to the rest of the circuit without dissipating heat. The Q factor is a dimensionless quantity that is defined mathematically as Q = coL / R, where co is the angular frequency of the signal, L is the inductance of the inductor, and R is the resistance of the inductor. A high-Q inductor has a low resistance and a high inductive reactance, which means that it can store energy efficiently in its magnetic field and transfer that energy to the rest of the circuit without significant losses due to resistance. On the other hand, a low-Q inductor, as compared to a high-Q inductor, has a relatively higher resistance and / or a relatively lower inductive reactance, which means that it dissipates more energy as heat and is less efficient at storing energy in its magnetic field.

[0025] For switchable inductors fabricated on integrated circuits, the switches may be implemented with, for example, metal-oxide-semiconductor (MOS) field effect transistors (FETs) such as n-channel FETs, p-channel FETs, or both. Historically, MOSFETs have been planar devices, but as semiconductor manufacturing technology has advanced, MOSFETs have taken on three-dimensional configurations such as, but not limited to, FinFETs and Gate- All-Around FETs. Various embodiments in accordance with this disclosure are not limited to any particular FET device architecture.

[0026] It is noted that the on-resistance of FET switches is not zero, and therefore the Q factor of a switchable inductor depends, at least in part, on the on-resistance of a FET switch, and may reduce the Q factor of the switchable inductor in accordance with Q = coL / R (seediscussion of Q = coL / R above). This leads to a trade-off in terms of chip area versus Q factor. Larger FETs (i.e., FETs with a larger Width / Length ratio (W / L)) may have lower on- resistance resulting in higher Q but may require more chip area (i.e., area of the integrated circuit) to implement. On the other hand, chip area may be saved by reducing the area consumed by large FETs (i.e., reducing W / L), resulting in smaller switchable inductors, but which have lower Q as a result of the on-resistance of the FET switches being increased.

[0027] It is noted that the switches in various embodiments of this disclosure are not limited to FETs, and other suitable materials and / or structures may be used to implement switches having an on-resistance that is low enough to provide the high Q needed for low phase noise operation.

[0028] The Q factor of an inductor is an important parameter in many applications, particularly in RF circuits such as, for example, filters and oscillators, where the Q factor affects the selectivity, bandwidth, and frequency stability of the circuit. A higher Q factor generally leads to better performance in such applications.

[0029] Typical VCO designs include a high-Q inductor in order to achieve low-phase noise operation. As noted elsewhere in this disclosure, there is an inverse relationship between the Q of the oscillator and the VCO phase noise, i.e., as the quality factor of the oscillator increases, the VCO phase noise decreases. However, there is also an inverse relationship between Q and oscillator frequency range, i.e., higher Q circuits have narrower frequency ranges Thus, the choice of a high-Q inductor in the VCO results in narrow-band operation of the VCO.

[0030] Various embodiments, in accordance with this disclosure, provide a switchable low-EMI figure-eight inductor suitable for use in integrated circuits. Some embodiments in accordance with this disclosure, provide a switchable low-EMI inductor having a figure-eight layout configuration. Various embodiments provide a switchable inductor suitable for use in multi-band voltage-controlled oscillator applications that are implemented as integrated circuits, where multi-band operation provides a low-phase noise VCO with wideband operation.

[0031] In some embodiments in accordance with this disclosure, to achieve a wideband VCO without sacrificing an unacceptable amount of Q, which would undesirably increase the amount of phase noise, a switchable inductor having a figure-eight configuration and only oneswitchable pathway is provided. Embodiments of this disclosure may be implemented in integrated circuits, which are sometimes referred to as “chips.” Embodiments of this disclosure may form part of a system-on-a-chip (SoC), or may be implemented as chiplets. Implementations and embodiments of this disclosure are not limited to any particular semiconductor technology or manufacturing process.

[0032] Table 1, below, shows a comparison between the key performance parameters of a baseline switchable inductor (described below in connection with FIGs. 3 A-3B), and a low- EMI figure-eight switchable inductor in accordance with this disclosure (described below in connection with FIGs. 4A-4B and 5).TABLE 1

[0033] FIGs. 1, 2, 3 A, and 3B illustrate, respectively, a general PLL architecture including a VCO, a VCO including a baseline switchable inductor, a schematic representation of a baseline inductor, and a layout diagram of the baseline inductor showing the conductive loops of the baseline switchable inductor.

[0034] Phase-locked loops are one type of application that may benefit from a VCO that provides wideband operation and low phase noise, both of which are enabled by a high-Q, wideband, low-EMI, switchable inductor in accordance with this disclosure. FIG. l is a high- level block diagram of an illustrative phase-locked loop 100 including a voltage-controlled oscillator. A high-Q, low-EMI, figure-eight switchable inductor, in accordance with this disclosure, may be used in the voltage-controlled oscillator of a phase-locked loop such as, for example, phase-locked loop 100 to improve the performance thereof in comparison to the performance of a phase-locked loop using a baseline switchable inductor.

[0035] Still referring to FIG. 1, phase-locked loop 100 receives a reference signal FREF at a node 102. Node 102 is coupled to a first input terminal of a phase detector 104. Phase detector 104 has an output terminal coupled to a node 106. Node 106 is further coupled to an input terminal of a low-pass filter 108. Low-pass filter 108 has an output terminal coupled to a node 110. Node 110 is further coupled to an input terminal of voltage-controlled oscillator 112. Voltage-controlled oscillator 112 has an output terminal coupled to a node 114. Node 114 is further coupled to an input terminal of a divide-by-N counter 116. Divide-by-N counter 116 has an output terminal coupled to a node 118. Node 118 is further coupled to a second input terminal of phase detector 104.

[0036] FIG. 2 is a circuit schematic of a voltage-controlled oscillator (VCO) 200 including a baseline switchable inductor. A first n-channel FET 202 is coupled drain-to- source between a node 204 and a node 206. By “drain-to-source” it is meant that the drain terminal of a FET is coupled to a first node, and the source terminal of that FET is coupled to a second node, thereby forming an electrical path between the first node and the second node that can be switched, i.e., turned on and off by controlling the gate terminal of the FET.

[0037] Still referring to FIG. 2, a second n-channel FET 208 is coupled drain-to-source between a node 210 and node 206. First n-channel FET 202 and second n-channel FET 208 are cross-coupled such that the gate terminal of first n-channel FET 202 is coupled to the drain of second n-channel FET 208; and the gate terminal of second n-channel FET 208 is coupled to the drain terminal of first n-channel FET 202. More specifically, the gate terminal of first n-channel FET 202 is coupled to node 210, and the gate terminal of second n-channel FET 208 is coupled to node 204. A first variable capacitor 214 is coupled between node 204 and a node 216. A second variable capacitor 218 is coupled between node 216 and node 210. A baseline switchable inductor 220 is coupled between node 204 and node 210, in other words, between the drain terminal of first n-channel FET 202 and the drain terminal of second n- channel FET 208.

[0038] Still referring to FIG. 2, a tail tune circuit 221 is coupled between node 206 and a ground node. Tail tune circuit 221 includes an inductor 222 coupled between node 206 and the ground node. Tail tune circuit 221 further includes a capacitor 224 is coupled, in parallel with inductor 222, between node 206 and the ground node.

[0039] A baseline switchable inductor, such as baseline switchable inductor 220 used in VCO 200, is described in greater detail with reference to FIGs. 3A-3B.

[0040] FIG. 3 A is a representation of a baseline switchable inductor 300 including two switches. Baseline switchable inductor 300 has an outer loop 302 and an inner loop 304. A first transistor 306 forms part of outer loop 302, and a second transistor 308 forms part of inner loop 304. The gate terminal of first transistor 306 is coupled to a control signal SW1, and the gate terminal of second transistor 308 is coupled to a control signal SW2.

[0041] Still referring to FIG. 3 A, when first transistor 306 is “on” and second transistor 308 is “off,” then the path for current in baseline switchable inductor 300 is outer loop 302. When first transistor 306 is “off’ and second transistor 308 is “on,” then the path for current in switchable inductor 300 is, in this example, through a first half of outer loop 302, then through inner loop 304, then through a second half of outer loop 302.

[0042] FIG. 3B is a layout diagram showing a physical layout pattern 350 of the baseline switchable inductor 300 of FIG. 3 A. Physical layout pattern 350 of the baseline switchable inductor 300 includes a first patterned conductor 352, a second patterned conductor 354, and a third patterned conductor 356. A first cross-over structure 358 is disposed so as to electrically couple second patterned conductor 354 and third patterned conductor 356. First transistor 306 is coupled between first patterned conductor 352 and second patterned conductor 354. Second transistor 308 is coupled between first patterned conductor 352 and third patterned conductor 356

[0043] FIG. 4A is a representation of a low-EMI, high-Q, switchable inductor having a figure-eight configuration and one switch in accordance with this disclosure. The figure-eight configuration switchable inductor of FIG. 4 A includes a first loop 402, a second loop 404, a third loop having a first portion 406a and a second portion 406b, and a FET 408 coupled between first portion 406a and second portion 406b of the third loop. In this illustrative embodiment, when FET 408 is in its on-state it provides a low on-resistance path between first portion 406a and second portion 406b of third loop. When FET 408 is in its off-state it provides a high impedance between first portion 406a and second portion 406b of third loop. It is noted that, in alternative embodiments, FET 408 may be implemented with structures or circuit elements other than a FET, such as, but not limited to, a MEMS (microelectricalmechanical system) switch.

[0044] Still referring to FIG. 4A, first loop 402 is configured to have two terminals for connection to input signals. In this illustrative embodiment, the connection terminals of first loop 402 are labelled as VCO P and VCO N. FET 408 has a gate terminal coupled to a control signal labelled SW1 in FIG. 4A. Control signal SW1 is used to switch FET 408 between its low-resistance on-state and its high-impedance off-state. This illustrative figureeight switchable inductor is characterized by its low EMI performance, which allows closer placement of such components without those components suffering from interference. This illustrative figure-eight switchable inductor is further characterized by its high-Q and wideband performance.

[0045] FIG. 4B is a layout diagram showing a physical layout pattern of the switchable inductor of FIG. 4 A. While FIG. 4B shows layout features corresponding to the features of FIG. 4A’s representation of the illustrative switchable inductor, FIG. 4B further shows physical implementation details such as first cross-over structure 410 and second cross-over structure 412. Both first cross-over structure 410 and second cross-over structure 412 include a conductive path between physically separated conductors. In this illustrative embodiment, the conductive path is formed by a metal interconnect line on an interconnect level below the physically separated conductors. Contact, or via, structures are used to couple the physically separated conductors to the conductive path. Thus, first cross-over structure 410 and second cross-over structure 412 act as “jumpers” to electrically connect the physically separated conductors. In this way, the conductors that form the loops of the switchable inductor in accordance with this disclosure may form electrically continuous paths that overlap with each other. It will be appreciated that in alternative embodiments, the cross-over structures may be disposed on an interconnect level above the physically separated conductors.

[0046] FIG. 5 is a layout diagram showing an alternative physical layout 500 of the switchable inductor having a figure-eight configuration and one switch in accordance with this disclosure. Alternative physical layout 500 is similar to the physical layout pattern shown in FIG. 4B, but physical layout 500 is different in the number of loops that it includes. Referring back to FIG 4B, it can be seen that one portion of the figure eight has no inner loops and the other portion of the figure eight has one inner loop. However, alternative physical layout pattern 500 has no inner loops in one portion of the figure-eight, but has two inner loops in the other portion of the figure eight.

[0047] Still referring to FIG. 5, alternative physical layout 500 of a low-EMI, high-Q, figure-eight switchable inductor in accordance with this disclosure includes a first patterned conductor 502, a second patterned conductor 504, a third patterned conductor 506, and a fourth patterned conductor 508. First patterned conductor 502 is coupled to fourth patterned conductor 508 by a first cross-over structure 510. Second patterned conductor 504 is coupled to third patterned conductor 506 by second cross-over structure 512. Third patterned conductor 506 is coupled to fourth patterned conductor 508 by third cross-over structure 514. Transistor 516 is coupled drain-to-source between first patterned conductor 502 and second patterned conductor 504. In some embodiments, transistor 516 is a field effect transistor. In this illustrative embodiment, first, second, third, and fourth patterned conductors 502, 504, 506, and 508 are all formed on the same level of interconnect on an integrated circuit. In this illustrative embodiment, first, second, third, and fourth patterned conductors 502, 504, 506, and 508 may be all formed on an uppermost interconnect level of an integrated circuit. In some embodiments, first, second, third, and fourth patterned conductors 502, 504, 506, and 508 may all be formed on an interconnect level of an integrated circuit that permits the greatest width for metal lines.

[0048] FIG. 6 is a circuit schematic of a voltage-controlled oscillator having a low-EMI, figure-eight, switchable inductor in accordance with this disclosure. The VCO of FIG. 6, is similar to the VCO of FIG. 2, except (1) the baseline switchable inductor in the VCO of FIG.2 has been replaced with a low-EMI, figure-eight, switchable inductor, and (2) the tuning tail of FIG. 2 has been modified, as shown in FIG. 6, to include an additional n-channel FET and an additional capacitor in series with the n-channel FET.

[0049] Still referring to FIG. 6, an illustrative VCO 600 in accordance with this disclosure includes a first n-channel FET M0 coupled drain-to-source between a node 602 and a node 604, a second n-channel FET Ml coupled drain-to-source between a node 606 and node 604. The gate terminal of first n-channel FET M0 is coupled to the drain terminal of second n-channel FET Ml at node 606. Similarly, the gate terminal of second n-channel FET Ml is coupled to the drain terminal of first n-channel FET M0 at node 602. A first variable capacitor CO is coupled between node 602 and a node 608. A second variable capacitor Cl is coupled between node 608 and node 606. A figure-eight switchable inductor 610, in accordance with this disclosure, is coupled between node 602 and node 606.

[0050] Still referring to FIG. 6, VCO 600 further includes a programmable tail tune circuit 612 coupled between node 604 and a ground node. Programmable tail tune circuit 612 includes an inductor Ltail coupled between node 604 and the ground node; a capacitor Ctail coupled between node 604 and the ground node; a capacitor Cose coupled between node 604 and a node 613. An n-channel FET 614 is coupled drain-to-source between node 613 and the ground node.

[0051] FIG. 7 illustrates the connection of a field effect transistor switch to a pair of conductors of a low-EMI, high-Q, figure-eight switchable inductor by way of a stack of metal interconnect levels and vias, in accordance with this disclosure. Referring to both FIGs. 4B and 7, the first portion 406a of the third loop and the second portion 406b of the third loop are switchably coupled by FET 408. In the illustrative embodiment of FIG. 7, the first and second portions of the third loop are implemented in “metal 10,” i.e., the uppermost interconnect level of this particular integrated circuit implementation. In this illustrative embodiment, metal 10 provides the metal lines with the greatest width. Other embodiments are not limited to a particular interconnect level, and it will be understood that the number of interconnect levels may vary among many semiconductor manufacturing processes.

[0052] Still referring to FIG. 7, while the loops of the inductor are implemented on the uppermost interconnect level, i.e., metal 10, FET 408 is implemented below the interconnect levels at the surface of the substrate. Thus, the drain terminal and the source terminal of FET 408 must be connected, respectively, to first portion 406a, and second portion 406b, of the third loop. These connections are made possible by stacks of vias and interconnect metal, as shown in FIG. 7. Additionally, the control signal “SWT” is connected to the gate terminal of FET 408 by way of a stack of vias and interconnect metal, as shown in FIG. 7. It will be understood that although this example shows control SW1 routed to the gate terminal of FET 408 by way of metal 7, there is no such limitation in various embodiments of this disclosure. That is, control signal SW1 may be routed to the gate terminal of FET 408 through any suitable combination of interconnect levels and vias.

[0053] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Various circuit and layout examples presented herein are for illustrative purposes, and it will be understood that various nominal values for the inductance of inductors, the capacitance of capacitors, and width / length (W / L) of FETs may be used in various implementations in accordance with this disclosure.

[0054] A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to a person skilled in the pertinent art that this disclosure can also be employed in a variety of other applications.

[0055] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.

[0056] In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

[0057] As used herein, the term “nominal / nominally” refers to a desired, or target, value of a characteristic or parameter for a component or a process operation, set during the design phase of a product or a process, together with a range of values above and / or below the desired value. The range of values can be due to slight variations in manufacturing processes or tolerances.

[0058] As used herein, the acronym “SoC” refers to System-on-a-Chip. An SoC is an integrated circuit (IC) with the circuits and subsystems to implement a particular system, such as, for example, a smartphone, smartwatch, or other product of similar complexity.

[0059] Integrated circuits in accordance with this disclosure may be implemented in any suitable process technology including, but not limited to, complementary metal oxide semiconductor (CMOS). Such integrated circuits may be custom designed, synthesized, or a combination of both. And, embodiments of the circuitry disclosed herein may be implemented on a single chip, or partitioned over one or more chips, or one or more die in a single package, or one or more chiplets in a single package, or any combination of these or similar integrated circuit and packaging configurations.

[0060] Further, embodiments of the circuitry disclosed herein may be implemented with one or more chiplets. In some embodiments, chiplets may be disposed on an interposer in a single package. The interposer may be a silicon interposer. Various embodiments in accordance with this disclosure may be implemented with any suitable packaging technology.

[0061] Various integrated circuit embodiments of this disclosure may further include “low-power,” or “power-down” circuitry to reduce leakage currents that result in unwanted power consumption.

[0062] In some embodiments, one or more circuit blocks or subsystems of an integrated circuit in accordance with this disclosure may be configured to enter a low-power state responsive to one or more signals indicating that those circuit blocks or subsystems do not have work to do at the moment. A low-power state refers to an integrated circuit operating in a manner that reduces or eliminates unneeded power consumption. The low-power state may be achieved by any suitable circuit technique. In one illustrative circuit technique, the low- power state may be achieved by stopping the clock signal or signals to a circuit block or subsystem of the integrated circuit. Stopping the clock signal or signals may be appropriate if the circuit block is implemented with a static logic design in CMOS process technology. However, since the static logic design may consume more chip area than dynamic logic design, a different trade-off that may make stopping the clocks an appropriate approach may be to ensure that the period for which the clocks are stopped is less than the period of time for the charge on one or more dynamic nodes in the circuit block or subsystem to decay to a point that the logic state on the one or more dynamic nodes cannot be reliably maintained. Such charge decay may occur through mechanisms such as, e.g., leakage or capacitive coupling to nearby circuit nodes. Alternatively, the low-power state may be achieved by decoupling the circuit block or subsystem from one or more power supply nodes. For example, the circuit block or subsystem may have a transistor coupled in series between itself and a positive powersupply node such that the circuit block or subsystem is decoupled from the positive power supply node when the transistor is turned off. In another example, the circuit block or subsystem may have a transistor coupled in series between itself and a ground supply node such that the circuit block or subsystem is decoupled from the ground supply node when the transistor is turned off. In still another example, the circuit block or subsystem may have a first transistor coupled in series between itself and a positive power supply node, and a second transistor coupled in series between itself and a ground supply node such that the circuit block or subsystem is decoupled from the positive power supply node and from the ground supply node when both the first and second transistors are turned off.

[0063] Power consumption is related to the magnitude of a circuit’s power supply voltage, and is also related to its operating frequency. Many integrated circuits, including but not limited to those designed for use in wireless communication, are designed to be used in products that rely, at least in part, on batteries for power. Since extending battery life is important to customers of such products, it is also important for designers to reduce the amount of power needed for the integrated circuits to perform their intended functions, and to provide hardware support for integrated circuits to enter one of one or more states in which unneeded power consumption is reduced or eliminated. Such states may be referred to as “low-power states,” “low-power modes,” “low-power operation,” or similarly descriptive terms. In further examples of low-power operation, it is possible to reduce power consumption in circuits that are unused or unneeded for a period of time, by reducing the magnitude of the circuit’s power supply voltage, reducing its operating frequency, or both.Some Embodiments

[0064] In one embodiment, a switchable inductor includes a first winding and a second winding, the first winding and the second winding together configured in a figure-eight shape, wherein the first winding includes a first loop and a second loop, wherein the second winding includes a third loop having two portions, and a switch coupled between the two portions of the third loop.

[0065] In some embodiments, the first loop is longer than the second loop, and the first loop is disposed, at least in part, around the second loop.

[0066] In some embodiments, the first loop and the second loop share a first cross-over structure.

[0067] In some embodiments, the switch comprises a field effect transistor (FET).

[0068] In some embodiments, the first loop and the third loop share a second cross-over structure.

[0069] In some embodiments, the first loop comprises a first conductive material having a first width, and the second loop comprises a second conductive material having a second width, wherein the first width and the second width are different from each other.

[0070] In some embodiments, the third loop comprises the first conductive material and has the first width, and the first width is greater than the second width.

[0071] In some embodiments, the first conductive material is different from the second conductive material.

[0072] In some embodiments, the first cross-over structure comprises at least a first contact structure, and the second cross-over structure comprises at least a second contact structure.

[0073] In some embodiments, the first loop is disposed on a first level of interconnect on an integrated circuit, and the second loop is disposed on a second level of interconnect on the integrated circuit.

[0074] In another embodiment, a switchable inductor includes a first patterned conductor, a second patterned conductor, a third patterned conductor, and a fourth patterned conductor, wherein the first, second, and third patterned conductors are disposed on a first interconnect level of an integrated circuit, and the fourth patterned conductor is disposed on a second interconnect level of the integrated circuit, a first cross-over structure coupled between the first patterned conductor and the third patterned conductor, a second cross-over structure coupled between the second patterned conductor and the third patterned conductor, and a switch coupled between the first patterned conductor and the second patterned conductor, wherein the first patterned conductor forms a first portion of a first loop and a first portion of a third loop, the second patterned conductor forms a second portion of the third loop, and the third patterned conductor forms a second portion of the first loop.

[0075] In some embodiments, the first, second, and third patterned conductors each have a first width, the fourth patterned conductor has a second width, and the first width is greater than the second width. It is common for integrated circuits to have multiple levels of metalinterconnect. Each level of interconnect is typically separated from another level of interconnect below it by a layer of dielectric material. Likewise, a level of interconnect may be separated from another level of interconnect above it by a layer of dielectric material. Connections between the levels of interconnect are provided by vias, or contacts, i.e., structures that provide a conductive pathway between levels of interconnect through the dielectric material separating those levels of interconnect. It is also common for different levels of interconnect to provide different conductor widths, with an uppermost level of interconnect having the widest interconnect, and lower levels of interconnect having narrower widths.

[0076] In some embodiments, the switch is a FET. A FET may be an n-channel FET or a p-channel FET. FETs are manufactured in a number of physical arrangements including, but not limited to, planar, 3-D, FinFET, and Gate-All-Around. Various embodiments are not limited to using FET switches. Switches can be implemented with other types of active or passive switches such as, but not limited to, bipolar transistors or microelectromechanical (MEMS) switches, for example.

[0077] In some embodiments, the first loop is larger than a second loop, and larger than the third loop.

[0078] In some embodiments, the first, second, third, and fourth patterned conductors each have at least one angled turn of less than 90 degrees.

[0079] In a further embodiment, a voltage-controlled oscillator includes a first transistor having a gate terminal, a drain terminal, and a source terminal, coupled drain-to-source between a first node and a tail tune circuit, a second transistor having a gate terminal, a drain terminal, and a source terminal, coupled drain-to-source between a second node and the tail tune circuit, a figure-eight switchable inductor coupled between the drain terminal of the first transistor and the drain terminal of the second transistor, and a programmable tail tune circuit coupled to the source terminal of the first transistor, coupled to the source terminal of the second transistor, and coupled to a ground node, wherein the gate terminal of the first transistor is coupled to the drain terminal of the second transistor, and the gate terminal of the second transistor is coupled to the drain terminal of the first transistor, wherein the figureeight switchable inductor includes a first winding and a second winding, the first winding and the second winding together configured in a figure-eight shape, wherein the first windingincludes a first loop and a second loop, wherein the second winding includes a third loop having two portions, and a switch coupled between the two portions of the third loop.

[0080] In some embodiments, the voltage-controlled oscillator further includes a first variable capacitor coupled to the drain terminal of the first transistor and further coupled to a first node, and a second variable capacitor coupled to the drain terminal of the second transistor and further coupled to the first node.

[0081] In some embodiments, the programmable tail tune circuit includes a first inductor having a first terminal and a second terminal, a first capacitor having a first terminal and a second terminal, a second capacitor having a first terminal and a second terminal, and a third transistor having a gate terminal, a drain terminal, and a source terminal, wherein the first terminal of the first inductor is coupled to the first terminal of the first capacitor and the first terminal of the second capacitor, wherein the second terminal of the second capacitor is coupled to the drain terminal of the third transistor, and wherein the second terminal of the first inductor is coupled to the second terminal of the first capacitor, and is further coupled to the source terminal of the third transistor.

[0082] In some embodiments, the second terminal of the first inductor is coupled to a ground node.

[0083] In some embodiments, the first transistor is a FET, the second transistor is a FET, and the third transistor is a FET. A FET may be an n-channel FET or a p-channel FET. FETs are manufactured in a number of physical arrangements including, but not limited to, planar, 3-D, FinFET, and Gate- All-Around.

[0084] The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and / or adapt for various applications of such specific embodiments, without undue experimentation, and without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

[0085] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the embodiment of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

[0086] The Summary and Abstract sections may set forth one or more but not all embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0087] The breadth and scope of the present disclosure should not be limited by any of the above-described illustrative embodiments, but should be defined only in accordance with the subjoined claims and their equivalents.

Claims

WHAT IS CLAIMED IS:

1. A switchable inductor, comprising: a first winding and a second winding, the first winding and the second winding together configured in a figure-eight shape, wherein the first winding includes a first loop and a second loop, wherein the second winding includes a third loop having two portions, and a switch coupled between the two portions of the third loop.

2. The switchable inductor of claim 1, wherein the first loop is longer than the second loop, and the first loop is disposed, at least in part, around the second loop.

3. The switchable inductor of claim 2, wherein the first loop and the second loop share a first cross-over structure.

4. The switchable inductor of claim 1, wherein the switch comprises a field effect transistor (FET).

5. The switchable inductor of claim 3, wherein the first loop and the third loop share a second cross-over structure.

6. The switchable inductor of claim 1, wherein the first loop comprises a first conductive material having a first width, and the second loop comprises a second conductive material having a second width, wherein the first width and the second width are different from each other.

7. The switchable inductor of claim 6, wherein the third loop comprises the first conductive material and has the first width, and the first width is greater than the second width.

8. The switchable inductor of claim 6, wherein the first conductive material is different from the second conductive material.

9. The switchable inductor of claim 5, wherein the first cross-over structure comprises at least a first contact structure, and the second cross-over structure comprises at least a second contact structure.

10. The switchable inductor of claim 9, wherein the first loop is disposed on a first level of interconnect on an integrated circuit, and the second loop is disposed on a second level of interconnect on the integrated circuit.

11. A switchable inductor, comprising: a first patterned conductor, a second patterned conductor, a third patterned conductor, and a fourth patterned conductor, wherein the first, second, and third patterned conductors are disposed on a first interconnect level of an integrated circuit, and the fourth patterned conductor is disposed on a second interconnect level of the integrated circuit; a first cross-over structure coupled between the first patterned conductor and the third patterned conductor; a second cross-over structure coupled between the second patterned conductor and the third patterned conductor; and a switch coupled between the first patterned conductor and the second patterned conductor, wherein the first patterned conductor forms a first portion of a first loop and a first portion of a third loop, the second patterned conductor forms a second portion of the third loop, and the third patterned conductor forms a second portion of the first loop.

12. The switchable inductor of claim 11, wherein the first, second, and third patterned conductors each have a first width, the fourth patterned conductor has a second width, and the first width is greater than the second width.

13. The switchable inductor of claim 11, wherein the switch is a FET.

14. The switchable inductor of claim 12, wherein the first loop is larger than a second loop, and larger than the third loop.

15. The switchable inductor of claim 12, wherein the first, second, third, and fourth patterned conductors each have at least one angled turn of less than 90 degrees.

16. A voltage-controlled oscillator, comprising: a first transistor having a gate terminal, a drain terminal, and a source terminal, coupled drain-to-source between a first node and a tail tune circuit; a second transistor having a gate terminal, a drain terminal, and a source terminal, coupled drain-to-source between a second node and the tail tune circuit; and a figure-eight switchable inductor coupled between the drain terminal of the first transistor and the drain terminal of the second transistor; and a programmable tail tune circuit coupled to the source terminal of the first transistor, coupled to the source terminal of the second transistor, and coupled to a ground node, wherein the gate terminal of the first transistor is coupled to the drain terminal of the second transistor, and the gate terminal of the second transistor is coupled to the drain terminal of the first transistor, and wherein the figure-eight switchable inductor comprises: a first winding and a second winding, the first winding and the second winding together configured in a figure-eight shape, wherein the first winding includes a first loop and a second loop, wherein the second winding includes a third loop having two portions, and a switch coupled between the two portions of the third loop.

17. The voltage-controlled oscillator of claim 16, further comprising: a first variable capacitor coupled to the drain terminal of the first transistor and further coupled to a first node; and a second variable capacitor coupled to the drain terminal of the second transistor and further coupled to the first node.

18. The voltage-controlled oscillator of claim 17, wherein the programmable tail tune circuit comprises: a first inductor having a first terminal and a second terminal; a first capacitor having a first terminal and a second terminal;a second capacitor having a first terminal and a second terminal; and a third transistor having a gate terminal, a drain terminal, and a source terminal; wherein the first terminal of the first inductor is coupled to the first terminal of the first capacitor and the first terminal of the second capacitor, wherein the second terminal of the second capacitor is coupled to the drain terminal of the third transistor, and wherein the second terminal of the first inductor is coupled to the second terminal of the first capacitor, and is further coupled to the source terminal of the third transistor.

19. The voltage-controlled oscillator of claim 18, wherein the second terminal of the first inductor is coupled to a ground node.

20. The voltage-controlled oscillator of claim 18, where the first transistor is a FET, the second transistor is a FET, and the third transistor is a FET.

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