Clock divider, clock division method, and system on chip

Abstract

The present disclosure relates to a clock divider, a clock division method, and a system on a chip. The clock divider comprises: a drive clock input end, used for receiving a drive clock signal; a division ratio input end, used for receiving a division ratio signal; a gated input end, used for receiving a gated signal; a clock output end, used for outputting a target clock signal; a first processing module, configured to process, when the gated signal indicates enabling the clock divider, the drive clock signal on the basis of the division ratio signal so as to generate the target clock signal corresponding to the division ratio signal; and a second processing module, configured to stop the operation of the first processing module when the gated signal indicates disabling the clock divider.

Description

Clock divider, clock division method and system on chip

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims priority to an application filed in China with application number 202310966607.4 and filing date August 2, 2023. The disclosure of the application in China is hereby incorporated as a whole into this application. Technical Field

[0003] The present disclosure relates to a clock divider, and more particularly to a circuit, method, and related system-on-chip for performing frequency division processing on a clock signal. Background Art

[0004] Existing chip systems often require multiple clock specifications to operate, and therefore require complex clock circuit structures to achieve these specifications and ensure smooth operation. For example, the system clock frequency required by a chip may vary when executing different tasks, and different module resources on the chip may also operate at different clock frequencies at the same time. Typically, a frequency divider circuit within the chip divides the main clock frequency to generate clock signals of different frequencies, which are provided to different tasks and modules. The quality of the clock signal generated by the frequency divider circuit significantly affects the chip's operational functions and performance.

[0005] There is therefore a need for improved techniques for clock division.

[0006] Summary of the Invention

[0007] One of the objectives of the present disclosure is to provide a clock divider.

[0008] According to one aspect of the present application, a clock divider is provided, comprising: a driving clock input terminal for receiving a driving clock signal; a frequency division ratio input terminal for receiving a frequency division ratio signal; a gating input terminal for receiving a gating signal; a clock output terminal for outputting a target clock signal; a first processing module, configured to process the driving clock signal according to the frequency division ratio signal when the gating signal indicates to enable the clock divider, so as to generate a target clock signal corresponding to the frequency division ratio signal; and a second processing module, configured to stop the operation of the first processing module when the gating signal indicates to disable the clock divider.

[0009] In one embodiment of the present application, the second processing module is configured to process a gating signal and a driving clock signal, so that when the gating signal indicates to disable the clock divider, the input of the first processing module is switched to an invalid level signal at the invalid level of the output target clock signal.

[0010] In one embodiment of the present application, the clock divider also includes a third processing module. When the division ratio signal indicates a change from the first division ratio to the second division ratio, the third processing module is configured to switch the output target clock signal to the target clock signal corresponding to the second division ratio generated by the first processing module after the current signal cycle ends.

[0011] In one embodiment of the present application, when the frequency division ratio signal indicates that the frequency division ratio is changed to 1, the third processing module is configured to switch the output target clock signal to the driving clock signal after the current signal cycle ends.

[0012] In one embodiment of the present application, the clock divider further includes a fourth processing module configured to asynchronously process the driving clock signal and the frequency division ratio signal.

[0013] In one embodiment of the present application, the clock divider further includes a fifth processing module configured to asynchronously process the driving clock signal and the gating signal.

[0014] In one embodiment of the present application, the maximum division ratio of the clock divider depends on the bit width of the first processing module and the division ratio signal is between one and the maximum division ratio.

[0015] According to one aspect of the present application, a clock division method is provided, comprising: receiving a driving clock signal; receiving a division ratio signal; receiving a gating signal; when the gating signal indicates enable, processing the driving clock signal according to the division ratio signal to output a target clock signal corresponding to the division ratio signal; and when the gating signal indicates disable, stopping processing the driving clock signal.

[0016] In one embodiment of the present application, the method further includes: processing a gating signal and a driving clock signal so that when the gating signal indicates disablement, the received driving clock signal is switched to an invalid level signal at an invalid level of the output target clock signal.

[0017] In one embodiment of the present application, the method further includes: when the division ratio signal indicates a change from the first division ratio to the second division ratio, processing the division ratio signal and the driving clock signal so that the output target clock signal switches to the target clock signal corresponding to the second division ratio after the current signal cycle ends.

[0018] In one embodiment of the present application, the method further includes: when the frequency division ratio signal indicates that the frequency division ratio is changed to 1, switching the output target clock signal to the driving clock signal after the current signal cycle ends.

[0019] In one embodiment of the present application, the method further includes: asynchronously processing the driving clock signal and the frequency division ratio signal.

[0020] In one embodiment of the present application, the method further includes: asynchronously processing the driving clock signal and the gating signal.

[0021] According to another aspect of the present application, a system on chip is provided, comprising the clock divider as described above.

[0022] Other characteristic features and advantages of the present application will become apparent from the following description with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The included drawings are for illustrative purposes only and are intended only to provide examples of possible structures and arrangements of the inventive apparatus and methods of applying the same to computing devices disclosed herein. These drawings in no way limit any changes in form and detail that may be made to the embodiments by those skilled in the art without departing from the spirit and scope of the embodiments. The embodiments will be more readily understood by the following detailed description taken in conjunction with the accompanying drawings, wherein like reference numerals represent similar structural elements.

[0024] FIG1 shows a schematic diagram of a clock divider according to an embodiment of the present application.

[0025] FIG2 shows a schematic diagram of an implementation of a clock divider according to an embodiment of the present application.

[0026] FIG3 shows a timing diagram of signals processed by a clock divider according to an embodiment of the present application.

[0027] FIG4 shows a schematic diagram of an implementation of a clock divider according to an embodiment of the present application.

[0028] FIG5 is a schematic diagram showing an implementation of a processing module of a clock divider according to an embodiment of the present application.

[0029] FIG6 is a schematic diagram showing an implementation of a circuit for performing asynchronous processing of a clock divider according to an embodiment of the present application.

[0030] FIG7 is a schematic diagram showing another implementation of a circuit for performing asynchronous processing of a clock divider according to an embodiment of the present application.

[0031] FIG8 shows a flow chart of a clock frequency division method according to an embodiment of the present application.

[0032] Note that in the embodiments described below, the same reference numerals are sometimes used in common across different drawings to denote the same parts or parts having the same functions, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items. Therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0033] To facilitate understanding, the positions, sizes, and ranges of various structures shown in the drawings and the like may not always represent actual positions, sizes, and ranges. Therefore, the disclosed invention is not limited to the positions, sizes, and ranges disclosed in the drawings and the like. Furthermore, the drawings are not necessarily drawn to scale, and some features may be exaggerated to illustrate details of specific components. DETAILED DESCRIPTION

[0034] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangements of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless otherwise specifically stated.

[0035] The following description of at least one exemplary embodiment is merely illustrative and is not intended to limit the present disclosure, its application, or use. Specifically, the circuit structures described herein are provided as examples to illustrate various embodiments of the present disclosure and are not intended to be limiting. Those skilled in the art will appreciate that these examples are merely illustrative of exemplary methods that may be used to implement the present disclosure, and are not intended to be exhaustive.

[0036] Technologies, methods and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, such technologies, methods and equipment should be considered part of the authorization specification.

[0037] As mentioned earlier, clock circuits are crucial to the operation of chip systems. They typically provide multiple clock signals through clock division. Clock division involves converting the same clock signal into clock signals of varying frequencies through a specific circuit structure. For example, a divide-by-four function can be achieved by using a circuit structure that outputs a periodic signal every four cycles of the clock. For example, a counter can be triggered by a pulse clock, which resets the counter to zero and outputs a pulse every four counts.

[0038] The circuits used for clock division are closely related to the structure, scale, performance, and power consumption of the chip's internal circuitry. Generally speaking, while meeting circuit performance requirements, low-frequency clocks are used whenever possible to save power. Power consumption is crucial to circuit performance. In related art, when the clock signal is not needed during a certain time period, a gating signal is typically used at the output of the clock circuit to shut down the output clock signal. In this case, the input side of the clock division circuit still receives the driving clock signal, and the clock division circuit still processes the driving clock signal internally, but the target clock signal outputted at the output side is shut down. Therefore, the clock division circuit is still operating, which is disadvantageous from a power consumption perspective. Furthermore, as is common, when the clock circuit processes high-frequency signals, the power consumption of the clock circuit significantly increases the chip's standby power consumption, making this a topic of considerable concern.

[0039] On the other hand, dynamically adjusting the clock output frequency through software control or adaptive control as application requirements change is a common requirement for clock circuits. Related art clock circuits often generate glitches in the clock circuit's output signal when switching the frequency division ratio. These glitches in the clock signal can introduce noise into subsequent signals, causing abnormal chip operation. This is detrimental to the chip's stable operation.

[0040] The present application provides a clock divider, a clock division method, and a system-on-chip comprising the clock divider. The clock divider according to an embodiment of the present application can be implemented with an extremely low-cost circuit structure and can flexibly output a desired divided clock signal.

[0041] According to one embodiment of the present application, the clock divider can support dynamic gating. When the output clock signal is not needed, the driving clock of the entire divider is also turned off. This not only ensures that the circuit driven by the generated divided clock will not flip, but also ensures that the clock divider circuit itself will not flip, thereby reducing power consumption to an optimal level. When processing high-frequency clock signals, the power consumption of the clock circuit saved by the technical solution of one embodiment of the present application is very considerable.

[0042] According to an embodiment of the present application, the clock divider can support dynamic configuration of the frequency division ratio. When the frequency division ratio is switched dynamically, the output target clock signal will not be interrupted, and the desired clock signals of different frequencies can be switched without glitch through glitch-free processing. Through glitch-free processing, the clock divider according to an embodiment of the present application will not cause abnormalities in the effective pulse width of the output divided clock regardless of whether the frequency division ratio is switched or the gating signal is switched. In addition, according to an embodiment of the present application, the clock divider can support not only two or more frequency divisions, but also one frequency division, which enriches the function of the circuit and can meet the needs of one frequency division.

[0043] Various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0044] FIG1 shows a schematic diagram of a clock divider according to an embodiment of the present application. A clock divider 100 according to an embodiment of the present application may include a drive clock input 101 for receiving a drive clock signal. The drive clock signal may be a master clock signal of a chip system. The drive clock signal may have any suitable frequency. The clock divider 100 may also include a frequency division ratio input 102 for receiving a frequency division ratio signal. The frequency division ratio signal may be used to request even frequency division or odd frequency division. According to embodiments of the present application, one or more of a variety of frequency division methods may be implemented through different implementations.

[0045] The clock divider 100 may further include a gate input terminal 103 for receiving a gate signal, and a clock output terminal 104 for outputting a target clock signal.

[0046] As mentioned above, when the clock signal is not needed in a certain period of time, in order to save power consumption, the clock divider can be turned off by a gating signal. When the clock signal is needed, the clock divider can be turned on by a gating signal to provide a clock signal of the desired frequency through clock division processing.

[0047] The clock divider 100 may further include a first processing module 105 configured to, when the gating signal indicates that the clock divider circuit is enabled, process the driving clock signal according to the division ratio signal to generate a target clock signal corresponding to the division ratio signal for output at the clock output terminal 104. The clock divider 100 may further include a second processing module 106 configured to stop the operation of the first processing module 105 when the gating signal indicates that the clock divider circuit is disabled.

[0048] The first processing module 105 can be implemented in any suitable manner. One or more implementations of the first processing module 105 will be described in detail below with reference to the accompanying drawings. Those skilled in the art will appreciate that the first processing module 105 can be implemented in any suitable manner known in the art or that may emerge in the future, as needed. The specific implementations of the first processing module 105 described below are merely exemplary and are not intended to limit the scope of this disclosure.

[0049] In one embodiment of the present disclosure, when the output clock signal is no longer needed, the second processing module 106 stops the operation of the first processing module 105, rather than simply shutting off the generated target clock signal at the output. This at least reduces the power consumption required for the operation of the first processing module 105. When the processed drive clock signal is a high-frequency signal, the power consumption savings can be significant.

[0050] In one embodiment of the present disclosure, the second processing module 106 may be a module that implements the following functionality: processing a gating signal and a drive clock signal, such that when the gating signal indicates disabling the clock divider, the input of the first processing module 105 is switched to an inactive signal at the inactive level of the output target clock signal. For example, when a high-level signal or a rising edge is a valid signal, the input of the first processing module 105 may be switched to a low-level signal at the low level of the output target clock signal. The following description will assume that a high-level signal or a rising edge is a valid signal. In this embodiment, since the input of the first processing module 105 is switched to a low-level signal, the first processing module 105 no longer processes the drive clock signal based on the division ratio signal, for example, by inverting the drive clock signal to generate the desired target clock signal, thereby saving power. Furthermore, the switching of the input of the first processing module 105 to a low level occurs at the low level of the output target clock signal, preventing the target clock signal from being abnormally output at a high level and ensuring that the pulse width of the high level is consistent with the division ratio switching operation.

[0051] Those skilled in the art will appreciate that the function of stopping the operation of the first processing module may be achieved by any suitable means known in the art or that may appear in the future. The above is merely exemplary and is not intended to limit the scope of the present disclosure.

[0052] Returning to Figure 1, in one embodiment of the present disclosure, the clock divider may further include a third processing module 107. When the division ratio signal indicates a change from the first division ratio to the second division ratio, the first processing module 105 processes the drive clock signal according to the second division ratio signal to generate a target clock signal corresponding to the second division ratio. The third processing module 107 may process the division ratio signal and the drive clock signal so that the output target clock signal switches to the target clock signal corresponding to the second division ratio after the current signal cycle ends. This can effectively prevent abnormal effective pulse widths in the output target signal. This will be further explained below with reference to the signal timing diagram in Figure 3.

[0053] In one embodiment of the present disclosure, when the division ratio signal indicates that the division ratio changes to one, the target clock signal to be output is the driving clock signal, and the first processing module 105 is configured to send the driving clock signal to the third processing module 107. The third processing module 107 is configured to switch the output target clock signal to the driving clock signal after the current signal cycle ends.

[0054] Supporting a frequency division ratio of one can enrich the functionality of the clock divider. Furthermore, the third processing module implements a glitch-free switching between a driving clock signal corresponding to a frequency division ratio of one and a target clock signal corresponding to other frequency division ratios.

[0055] In one embodiment of the present disclosure, the maximum division ratio of the clock divider depends on the bit width of the first processing module, and the division ratio signal input through the division ratio input terminal is between 1 and the maximum division ratio.

[0056] In addition, the present application takes into account that the clock domain of the input signals of the clock divider, such as the division ratio signal and the gating signal, may be asynchronous with the clock domain of the driving clock signal of the clock divider, or the clock domain of the division ratio signal and the gating signal may be synchronous with the clock domain of the driving clock signal of the clock divider but at different frequencies. In the case of being asynchronous, the division ratio signal and the gating signal need to be processed asynchronously with the driving clock signal. For the case of being synchronous but at different frequencies, in order to facilitate subsequent processing, such as converging timing during layout and routing in subsequent processes, especially when the driving clock signal is at high frequency, for example, when the driving clock signal exceeds 1 GHz, asynchronous processing is also performed.

[0057] In one embodiment of the present disclosure, the clock divider may further include a fourth processing module 108 for asynchronously processing the drive clock signal and the frequency division ratio signal. In one embodiment of the present disclosure, the clock divider may further include a fifth processing module 109 for asynchronously processing the drive clock signal and the gating signal. The modules for asynchronous processing will be described in detail below with reference to Figures 6 and 7.

[0058] Those skilled in the art will appreciate that the third processing module 107, the fourth processing module 108, and the fifth processing module 109 described above may be optional. One or more embodiments of the present disclosure may include one or more of the third processing module 107, the fourth processing module 108, and the fifth processing module 109, or may not include one or more of the third processing module 107, the fourth processing module 108, and the fifth processing module 109.

[0059] In one embodiment of the present disclosure, a processing module or one or more functions of a processing module can be selected through parameter configuration. For example, two configuration parameters can be set: a gating support parameter GATE_TYPE and a frequency division ratio support parameter SUPPORT_DIV1. Through these two parameters, the following four frequency dividers can be configured: support gating and support 1-N frequency division ratio, support gating and support 2-N frequency division ratio, do not support gating and support 1-N frequency division ratio, do not support gating and support 2-N frequency division ratio, where N is the maximum frequency division ratio. The desired configuration can be achieved through parameters. The clock divider selected through parameter configuration can achieve gating and frequency division ratio control through the input signal to output the target clock signal without glitches.

[0060] One or more embodiments of the present disclosure will be described below in conjunction with specific circuit structures and signal timing diagrams. Those skilled in the art will understand that the described circuit structures are merely exemplary, and that one or more portions of the clock divider of the present disclosure may be implemented by any suitable means known in the art or that may emerge in the future.

[0061] FIG2 shows a schematic diagram of an implementation of a clock divider according to an embodiment of the present application. The circuit shown in FIG2 can be implemented by configuring the gating support parameter GATE_TYPE to 1 and the frequency division ratio support parameter SUPPORT_DIV1 to 0. The circuit shown in FIG2 supports gating and supports a 2-N frequency division ratio. The circuit includes an input terminal div_num for receiving a frequency division ratio signal. As previously mentioned, the frequency division input terminal div_num can have online software configurability and can dynamically change the frequency division ratio at any time. For example, the frequency division ratio can be dynamically input through software. The circuit shown in FIG2 also includes an input terminal clk for receiving a drive clock signal. The drive clock signal can come from the main clock signal of the circuit. The circuit shown in FIG2 also includes an input terminal clk_en for receiving a gating signal. The circuit shown in FIG2 also includes an input terminal rstn for performing a reset operation on the circuit.

[0062] The embodiment of Figure 2 may further include a module CK_Divn (n≥2). When the gating signal from the input terminal clk_en indicates that the clock frequency division circuit is enabled, the module CK_Divn (n≥2) processes the driving clock signal from the input terminal clk according to the division ratio signal from the input terminal div_num to generate a target clock signal corresponding to the division ratio signal for output at the clock output terminal clk_out. For example, when the gating signal is at a high level, it indicates that the clock frequency division circuit is enabled. In this example, according to the division ratio signal from the division ratio input terminal div_num, for example, the division ratio signal can indicate a four-way division, the driving clock signal is divided by four to obtain the target clock signal, which is output to the clock output terminal clk_out. Those skilled in the art will understand that the frequency division process can be performed in any suitable manner known in the art or that may appear in the future.

[0063] The embodiment of Figure 2 may also include a module Gen_GateEn and a module CK_GT. The module Gen_GateEn receives a gating signal from the input terminal clk_en and a driving clock signal from the input terminal clk. The module CK_GT receives the driving clock signal from the input terminal clk and the signal Gate_en processed by the module Gen_GateEn, and sends the gated_clk signal to the module CK_Divn (n≥2) after processing. When the gating signal indicates that the clock frequency division circuit is enabled, the gated_clk signal can be an enabled driving clock signal, and the module CK_Divn (n≥2) can be used to process the gated_clk signal according to the division ratio signal to generate a target clock signal corresponding to the division ratio signal. When the gating signal indicates that the clock frequency division circuit is disabled, the gated_clk signal can be a turned-off driving clock signal, for example, the driving clock signal is adjusted to a low-level signal, and the module CK_Divn (n≥2) will stop operating. That is, in the circuit structure of Figure 2, the modules Gen_GateEn and CK_GT implement the function of stopping processing the drive clock signal to generate the target clock signal when the gating signal indicates that the clock divider circuit is disabled. This implements dynamic gating. When the output clock signal is not needed, the drive clock of the entire clock divider circuit is turned off. This not only ensures that the circuit driven by the generated divided clock will not flip, but also ensures that the clock divider circuit itself will not flip, thereby reducing power consumption to an optimal level. In the case of a high-frequency drive clock signal, such as when the drive clock signal exceeds 1GHz, the power consumption saved will be considerable.

[0064] To prevent the output target clock signal from being abnormal, when the gating signal indicates disable, the module Gen_GateEn and the module CK_GT are processed and the input of the module CK_Divn (n ≥ 2), such as the gated_clk signal, is switched to a low-level signal when the output target clock signal clk_out is at a low level. This will prevent the gated_clk signal from being turned off when the output target clock signal clk_out is at a high level, causing the output target clock signal clk_out to be abnormally high.

[0065] The second processing module 106 in one embodiment of the present application shown in FIG1 can be implemented as the module Gen_GateEn and the module CK_GT in the embodiment shown in FIG3 . This will be further described below with reference to the timing diagram. While this description herein uses a high-level signal as an example of a valid signal, those skilled in the art will appreciate that the technical solutions to be protected by this application are also applicable to situations where a low-level signal or a falling-edge signal is a valid signal.

[0066] In one embodiment of the present disclosure, when the division ratio signal indicates a change from a first division ratio to a second division ratio, the module CK_Divn (n ≥ 2) processes the division ratio signal and the drive clock signal so that the output target clock signal switches to the target clock signal corresponding to the second division ratio after the current signal cycle ends. This can avoid glitches or abnormalities in the effective pulse width of the output target clock signal.

[0067] The first processing module 105 and the third processing module 107 in one embodiment of the present application shown in Figure 1 can be implemented as the module CK_Divn (n≥2) in the embodiment shown in Figure 3. Detailed description will be given below in conjunction with the signal timing diagram.

[0068] FIG3 shows a timing diagram of signals processed by a clock divider according to an embodiment of the present application. The diagram illustrates a division ratio signal, a gating signal, a drive clock signal, a processed drive clock signal, and a target clock signal. At time t1, the division ratio signal changes, for example, from a division by two before time t1 to a division by six after time t1. At time t1, the drive clock signal is high, and the output target clock signal is also high. If the target clock signal is switched at time t1, a pulse width anomaly will occur. To avoid glitches in the output clock signal, the division ratio signal and the drive clock signal can be processed, for example, by the third processing module 107 shown in FIG1 or a portion of the module CK_Divn (n≥2) shown in FIG2 , so that the output target clock signal switches to the target clock signal corresponding to the second division ratio after the current signal cycle ends. That is, the output target clock signal is not switched at time t1, but instead is switched to the target clock signal divided by six after the current signal cycle of the target clock signal ends, i.e., at t2.

[0069] At t3, the gating signal changes from an enabled state to a disabled state, and the target clock signal outputted is now at a high level. If the drive clock signal is turned off at t3, the target clock signal will remain high, resulting in a signal abnormality. To avoid abnormalities, the gating signal and the drive clock signal can be processed by, for example, the second processing module shown in FIG1 or, for example, the module Gen_GateEn and the module CK_GT shown in FIG2 , so that when the gating signal indicates disable, at the low level of the output target clock signal, as shown in FIG3 as t4, the input of, for example, the first processing module 105 shown in FIG1 or, for example, the input of the module CK_Divn (n≥2) shown in FIG2 , shown as gated_clk in FIG2 , is switched to a low-level signal, thereby causing the first processing module 105 shown in FIG1 or the module CK_Divn (n≥2) shown in FIG2 to stop processing operations, which causes the output target clock signal to remain low.

[0070] This process allows for dynamic gating of the clock divider circuit. When the output clock signal is not needed, the drive clock to the entire divider circuit is turned off. This means that rather than simply shutting off the generated target clock signal at the output to prevent the circuit driven by the divided clock from flipping, the drive clock to the divider circuit is shut off, ensuring that the clock divider circuit itself does not flip, thereby minimizing power consumption. Furthermore, the timing of the shutdown is chosen to prevent abnormalities in the output target clock signal.

[0071] Figure 4 shows a schematic diagram of an implementation of a clock divider according to an embodiment of the present application. For example, the circuit shown in Figure 4 can be implemented by configuring the gating support parameter GATE_TYPE to 1 and the one-division ratio support parameter SUPPORT_DIV1 to 1. The circuit shown in Figure 4 supports gating and a 1-N division ratio, where N is the maximum division ratio. The circuit shown in Figure 4 is similar to the circuit shown in Figure 2. To avoid duplication, only the differences are described here.

[0072] 2 , the circuit shown in FIG4 further includes a module CK_DIV1 and a module CK_SWITCH. Part of the first processing module 105 shown in FIG1 can be implemented as the module CK_DIV1, and part of the third processing module 107 shown in FIG1 can be implemented as the module CK_SWITCH.

[0073] When the frequency division ratio signal from the input terminal div_num indicates that the frequency division ratio has changed to one, the module CK_DIV1 sends the driving clock signal to the module CK_SWITCH. The module CK_SWITCH can perform a clock selection operation to seamlessly switch the currently output target clock signal to the driving clock signal. In one embodiment, when the frequency division ratio signal indicates that the frequency division ratio has changed to one, the module CK_DIV1 sends the driving clock signal to the module CK_SWITCH. The module CK_SWITCH causes the output target clock signal to switch to the driving clock signal after the current signal cycle ends.

[0074] When the division ratio signal from the input terminal div_num indicates that the division ratio changes from 1 to other division ratios, the module CK_Divn (n≥2) sends the clock signal corresponding to the current division ratio to the module CK_SWITCH. The module CK_SWITCH can perform a clock selection operation and switch the target clock signal to the clock signal corresponding to the current division ratio without glitch.

[0075] That is, the module CK_SWITCH performs clock selection between the driving clock signal and the divided clock signal, so that the circuit outputs the target clock signal corresponding to the current frequency division ratio signal without glitches.

[0076] FIG5 is a schematic diagram illustrating an implementation of a processing module of a clock divider according to an embodiment of the present application. For example, the module CK_SWITCH in FIG4 can be implemented as the circuit structure shown in FIG5 . In particular, clk_in0 and clk_in1 in the circuit of FIG5 can receive the output of the module CK_Divn (n≥2) and the output of the module CK_DIV1 in FIG4 , so as to select a clock between the output of the module CK_Divn (n≥2) and the output of the module CK_DIV1 when the division ratio signal from the input terminal div_num indicates that the division ratio has changed to one or from one to another division ratio, thereby enabling the target clock signal to be output without glitches.

[0077] Those skilled in the art will understand that the above are merely examples, and the clock signal may be selected by any suitable method known in the art or that may appear in the future to output the desired target clock signal without glitches.

[0078] As mentioned above, in order to facilitate subsequent processing, when the division ratio signal and the gating signal of the clock divider are asynchronous or synchronous but at different frequencies with the driving clock signal of the clock divider, the division ratio signal and the driving clock signal can be processed asynchronously, or the gating signal and the driving clock signal can be processed asynchronously.

[0079] Figure 6 illustrates a circuit for asynchronously processing a gating signal and a driving clock signal in a clock divider according to one embodiment of the present application. The circuit may include an input terminal clk_en_in for receiving the gating signal to be asynchronously processed. The circuit may also include an input terminal clk for receiving the driving clock signal. The circuit may also include a reset signal input terminal rst_n. After two or three levels of synchronization, the asynchronously processed gating signal is output at the output terminal clk_en.

[0080] Figure 7 shows a circuit for asynchronously processing a division ratio signal and a drive clock signal in a clock divider according to an embodiment of the present application. The circuit may include an input terminal div_num_en_in and an input terminal div_num_in for receiving the division ratio signal to be asynchronously processed. The circuit may also include an input terminal clk for receiving the drive clock signal. The circuit may also include a reset signal input terminal rst_n. The flip edge of the signal at the input terminal div_num_en_in indicates that the signal at the input terminal div_num_in has been updated and stabilized. Therefore, the asynchronous processing circuit first synchronizes the input terminal div_num_en_in signal with two or three levels, then performs an XOR judgment with the signal synchronized with the first level to generate an enable pulse. This enable pulse is used to latch the div_num_in signal, and the latched output is div_num.

[0081] Those skilled in the art will understand that when the gating signal, the frequency division ratio signal, and the driving clock signal of the frequency division circuit are in the same clock domain, asynchronous processing may not be performed. Those skilled in the art will understand that the above are merely examples, and the above-mentioned asynchronous processing may be performed by any suitable method known in the art or that may be developed in the future.

[0082] 8 shows a flow chart of a clock frequency division method according to an embodiment of the present application. One or more steps of the clock frequency division method can be implemented by the clock frequency divider or clock frequency division circuit described above.

[0083] As shown in Figure 8, in step 801, a drive clock signal is received. In step 802, a frequency division ratio signal is received. In step 803, a gating signal is received. In step 804, when the gating signal indicates enable, the drive clock signal is processed according to the frequency division ratio signal to output a target clock signal corresponding to the frequency division ratio signal; and when the gating signal indicates disable, processing of the drive clock signal is stopped. By stopping processing the drive clock signal, rather than shutting down the generated target clock signal, power consumption can be saved. This power saving can be significant when the processed drive clock signal is a high-frequency signal.

[0084] In one embodiment of the present application, stopping processing the driving clock signal includes processing a gating signal and the driving clock signal such that, when the gating signal indicates disable, the received driving clock signal is switched to an inactive level signal at an inactive level of the output target clock signal. This can prevent the target clock signal from abnormally maintaining a valid level, thereby causing a malfunction.

[0085] In one embodiment of the present application, the method may further include the following steps: when the frequency division ratio signal indicates a change from a first frequency division ratio to a second frequency division ratio, processing the frequency division ratio signal and the drive clock signal so that the output target clock signal switches to the target clock signal corresponding to the second frequency division ratio after the current signal cycle ends. In one embodiment of the present application, the method may further include the following steps: when the frequency division ratio signal indicates a change from a first frequency division ratio to a second frequency division ratio, switching the output target clock signal to the drive clock signal after the current signal cycle ends. This can avoid glitches or abnormal effective pulse widths in the target clock signal when the frequency division ratio switches.

[0086] In one embodiment of the present application, the method may further include the following steps: asynchronously processing the drive clock signal and the frequency division ratio signal. In one embodiment of the present application, the method may further include the following steps: asynchronously processing the drive clock signal and the gating signal. Asynchronously processing the drive clock signal and the frequency division ratio signal or the drive clock signal and the gating signal may facilitate timing convergence during layout and routing in subsequent processes, thereby optimizing circuit performance.

[0087] According to another aspect of the present application, a system on chip is provided, comprising the clock divider as described above.

[0088] The clock divider, clock division method, and system on chip disclosed herein are described above in conjunction with specific embodiments. However, it should be understood that any feature of any embodiment may be combined with and / or replaced with any other feature of any other embodiment.

[0089] Aspects of the present disclosure may be implemented in various electronic devices. Examples of electronic devices may include, but are not limited to, consumer electronic products, components of consumer electronic products, electronic test equipment, cellular communication infrastructure such as base stations, and the like. Examples of electronic devices may include, but are not limited to, mobile phones such as smartphones, wearable computing devices such as smart watches or headphones, phones, televisions, computer monitors, computers, modems, handheld computers, laptop computers, tablet computers, personal digital assistants (PDAs), microwave ovens, refrigerators, in-vehicle electronic systems such as automotive electronic systems, stereo systems, DVD players, CD players, digital music players such as MP3 players, radios, portable cameras, cameras such as digital cameras, portable memory chips, washing machines, dryers, washer / dryers, peripheral devices, clocks, and the like. In addition, electronic devices may include incomplete products.

[0090] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0091] It should also be understood that when the term “include / comprises” is used in this document, it indicates the presence of the specified features, integers, steps, operations, units and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, units and / or components and / or their combinations.

[0092] Although some specific embodiments of the present application have been shown in detail by way of example, it will be understood by those skilled in the art that the above examples are intended to be illustrative only and are not intended to limit the scope of the present application. It will be understood by those skilled in the art that the above embodiments may be modified without departing from the scope and essence of the present application. The scope of the present application is defined by the appended claims.

Claims

1. A clock divider, comprising: A driving clock input terminal, used for receiving a driving clock signal; A frequency division ratio input terminal, used for receiving a frequency division ratio signal; A gate input terminal, used for receiving a gate signal; A clock output terminal, used for outputting a target clock signal; A first processing module is configured to process the driving clock signal according to a frequency division ratio signal to generate a target clock signal corresponding to the frequency division ratio signal when a gating signal indicates to enable the clock divider; as well as The second processing module is configured to stop the operation of the first processing module when the gating signal indicates to disable the clock divider.

2. The clock divider of claim 1 , wherein the second processing module is configured to process a gating signal and a driving clock signal, so that when the gating signal indicates disabling the clock divider, the input of the first processing module is switched to an invalid level signal at an invalid level of the output target clock signal.

3. The clock divider as described in claim 1 further includes a third processing module. When the division ratio signal indicates a change from the first division ratio to the second division ratio, the third processing module is configured to switch the output target clock signal to the target clock signal corresponding to the second division ratio generated by the first processing module after the current signal cycle ends. 4 . The clock divider of claim 3 , wherein when the division ratio signal indicates that the division ratio is changed to 1, the third processing module is configured to switch the output target clock signal to the driving clock signal after a current signal cycle ends. 5 . The clock divider as claimed in claim 1 , further comprising a fourth processing module for asynchronously processing the driving clock signal and the frequency division ratio signal. 6 . The clock divider as claimed in claim 1 , further comprising a fifth processing module for asynchronously processing the driving clock signal and the gating signal. 7 . The clock divider of claim 1 , wherein a maximum division ratio of the clock divider depends on a bit width of the first processing module and a division ratio signal is between 1 and a maximum division ratio.

8. A clock frequency division method, comprising: receiving a driving clock signal; receiving a frequency division ratio signal; receiving a gating signal; When the gating signal indicates enabling, processing the driving clock signal according to the frequency division ratio signal to output a target clock signal corresponding to the frequency division ratio signal; as well as When the gating signal indicates disabling, the driving clock signal is stopped from being processed.

9. The clock frequency division method according to claim 8, wherein stopping processing the driving clock signal comprises: The gating signal and the driving clock signal are processed so that when the gating signal indicates disabling, the received driving clock signal is switched to an inactive level signal at an inactive level of the output target clock signal.

10. The clock frequency division method according to claim 8, further comprising: When the frequency division ratio signal indicates a change from the first frequency division ratio to the second frequency division ratio, the frequency division ratio signal and the driving clock signal are processed so that the output target clock signal is switched to the target clock signal corresponding to the second frequency division ratio after the current signal cycle ends.

11. The clock frequency division method according to claim 8, further comprising: When the frequency division ratio signal indicates that the frequency division ratio is changed to 1, the output target clock signal is switched to the driving clock signal after the current signal cycle ends.

12. The clock frequency division method according to claim 8, further comprising: The driving clock signal and the frequency division ratio signal are processed asynchronously.

13. The clock frequency division method according to claim 8, further comprising: The driving clock signal and the gating signal are processed asynchronously.

14. A system on chip comprising the clock divider as claimed in any one of claims 1 to 7.

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