Semiconductor device

Abstract

The present invention provides a semiconductor device in which the occurrence of destruction can be suppressed. A semiconductor device according to an embodiment of the present invention includes a first electrode, a semiconductor layer, a second electrode, a first insulating part, and a second insulating part. The semiconductor layer is provided on the first electrode. The second electrode is provided on the semiconductor layer and contains aluminum. The first insulating part includes a first portion and a second portion. The first portion is provided between the semiconductor layer and an outer peripheral part of the second electrode. The second portion is provided around the first portion along a first surface that is perpendicular to a first direction extending from the first electrode toward the semiconductor layer, and a protrusion is provided on the upper surface thereof. The second insulating part is provided on the outer peripheral part of the second electrode and the second portion.

Description

Semiconductor Devices

[0001] FIELD An embodiment of the present invention relates to a semiconductor device.

[0002] BACKGROUND Semiconductor devices such as diodes, metal-oxide-semiconductor field effect transistors (MOSFETs), and insulated gate bipolar transistors (IGBTs) are used for applications such as power conversion. It is desirable for semiconductor devices to be resistant to breakdown.

[0003] Japanese Patent Application Publication No. 2-30130

[0004] The problem to be solved by the present invention is to provide a semiconductor device that can suppress the occurrence of breakdown.

[0005] The semiconductor device according to the embodiment includes a first electrode, a semiconductor layer, a second electrode, a first insulating portion, and a second insulating portion. The semiconductor layer is provided on the first electrode. The second electrode is provided on the semiconductor layer and includes aluminum. The first insulating portion includes a first portion and a second portion. The first portion is provided between the semiconductor layer and an outer periphery of the second electrode. The second portion is provided around the first portion along a first surface perpendicular to a first direction from the first electrode toward the semiconductor layer, and has a convex portion on its upper surface. The second insulating portion is provided on the outer periphery and the second portion of the second electrode.

[0006] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line A1-A2 of FIG. 1. FIG. 3 is a cross-sectional view showing a semiconductor device according to a reference example. FIGS. 4A and 4B are schematic diagrams for explaining problems with the semiconductor device according to the reference example. FIGS. 5A to 5D are plan views showing the layout of convex portions provided in first insulating portions. FIG. 6 is a cross-sectional view showing a portion of a semiconductor device according to a first modification of the first embodiment. FIG. 7 is a cross-sectional view showing a portion of a semiconductor device according to a second modification of the first embodiment. FIG. 8 is a cross-sectional view showing a portion of a semiconductor device according to a third modification of the first embodiment. FIG. 9 is a cross-sectional view showing a portion of a semiconductor device according to a fourth modification of the first embodiment. FIG. 10 is a cross-sectional view showing a portion of a semiconductor device according to a fifth modification of the first embodiment. FIG. 11 is a cross-sectional view showing a portion of a semiconductor device according to a second embodiment. FIG. 12 is a cross-sectional view showing a portion of a semiconductor device according to a third embodiment. FIG. 13 is a cross-sectional view showing a portion of a semiconductor device according to a fourth embodiment.

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as the actual ones. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In this specification and each drawing, elements similar to those already explained are given the same reference numerals, and detailed explanations will be omitted as appropriate. In the following description, n ＋ , n, n － and p ＋ , p indicates the relative level of impurity concentration in each conductivity type. ＋ has a relatively higher n-type impurity concentration than n, － indicates that the n-type impurity concentration is relatively lower than that of n. ＋ indicates that the p-type impurity concentration is relatively higher than that of p. Each embodiment described below may be implemented by reversing the p-type and n-type of each semiconductor region.

[0008] First Embodiment FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along A1-A2 in FIG. 1. The semiconductor device according to the first embodiment is a diode. As shown in FIGS. 1 and 2, the semiconductor device 1 according to the first embodiment includes a semiconductor layer 10, a lower electrode 21 (first electrode), an upper electrode 22 (second electrode), a first insulating portion 31, and a second insulating portion 32. Note that the second insulating portion 32 is omitted from FIG. 1.

[0009] Here, the direction from the lower electrode 21 toward the semiconductor layer 10 is referred to as the Z direction (first direction). A direction perpendicular to the Z direction is referred to as the X direction. A direction perpendicular to the X and Z directions is referred to as the Y direction. For the sake of explanation, the direction from the lower electrode 21 toward the semiconductor layer 10 is referred to as "up" and the opposite direction is referred to as "down." These directions are based on the relative positional relationship between the lower electrode 21 and the semiconductor layer 10 and are unrelated to the direction of gravity.

[0010] 1, an upper electrode 22 and a first insulating portion 31 are provided on the upper surface of the semiconductor device 1. The upper electrode 22 is provided in the center of the XY plane (first surface) of the semiconductor device 1, and the first insulating portion 31 is provided in the outer periphery of the semiconductor device 1.

[0011] 2, a lower electrode 21 is provided on the lower surface of the semiconductor device 1. The semiconductor layer 10 is provided on the lower electrode 21. The upper electrode 22 is located on the semiconductor layer 10.

[0012] The first insulating portion 31 includes a first portion 31a and a second portion 31b. The first portion 31a is located between the semiconductor layer 10 and the outer periphery of the upper electrode 22 in the Z direction. The second portion 31b is provided around the first portion 31a along the XY plane. A protrusion P1 is provided on the top surface of the second portion 31b.

[0013] 1 and 2, multiple protrusions P1 are provided in the radial direction (second direction) from the first portion 31a to the second portion 31b. The radial direction is perpendicular to the Z direction. Each protrusion P1 surrounds the upper electrode 22 along the XY plane.

[0014] 2, the position in the Z direction of at least a part of the protrusion P1 is the same as the position in the Z direction of at least a part of the upper electrode 22. For example, the top surface of the protrusion P1 is aligned with a part of the upper electrode 22 in the radial direction.

[0015] The second insulating portion 32 is provided on the outer periphery of the upper electrode 22 and on the second portion 31b. The lower surface of the second insulating portion 32 contacts the protrusion P1. Therefore, the lower surface of the second insulating portion 32 has one or more recesses formed therein corresponding to the one or more protrusions P1.

[0016] The semiconductor layer 10 is － type (first conductivity type) semiconductor region 11 (first semiconductor region), n ＋ a p-type contact region 11a, a p-type (second conductivity type) semiconductor region 12 (second semiconductor region), and a p-type ＋ contact regions 12a and n ＋ 1, the p-type semiconductor region 12 and the n-type semiconductor region 13 (third semiconductor region) are included. ＋ The semiconductor region 13 is shown in dashed lines.

[0017] n ＋ The contact region 11a is provided on the lower electrode 21 and is electrically connected to the lower electrode 21. － The semiconductor region 11 is ＋ The n-type contact region 11a is provided on the n-type contact region 11a. ＋ The n-type impurity concentration of the n-type contact region 11a is － The n-type impurity concentration of the n-type semiconductor region 11 is higher than that of the n-type semiconductor region 11 .

[0018] The p-type semiconductor region 12 is － The p-type semiconductor region 12 is located on the p-type semiconductor region 11. The p-type semiconductor region 12 is located in the center of the semiconductor layer 10 in the XY plane. ＋ The p-type contact region 12a is selectively provided on the p-type semiconductor region 12. ＋ The p-type impurity concentration of the p-type contact region 12 a is higher than the p-type impurity concentration of the p-type semiconductor region 12 .

[0019] The upper electrode 22 is connected to the p-type semiconductor region 12 and the p ＋The p-type semiconductor region 12 and the p-type contact region 12a are located on the p-type semiconductor region 12. ＋ The contact region 12 a is electrically connected to the upper electrode 22 .

[0020] n ＋ The n-type semiconductor region 13 is provided around the p-type semiconductor region 12 along the XY plane. ＋ The n-type semiconductor region 13 is located away from the p-type semiconductor region 12 and is located on the periphery of the semiconductor layer 10 in the XY plane. ＋ The n-type impurity concentration of the n-type semiconductor region 13 is － The n-type impurity concentration of the n-type semiconductor region 11 is higher than that of the n-type semiconductor region 11 .

[0021] An example of the material of each component will be described. The semiconductor layer 10 includes silicon, silicon carbide, gallium nitride, or gallium arsenide as the semiconductor material. For example, when silicon carbide is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as the n-type impurity. Boron can be used as the p-type impurity.

[0022] The lower electrode 21 and the upper electrode 22 contain aluminum. Each of the lower electrode 21 and the upper electrode 22 may have a stacked structure including multiple metal layers. For example, as shown in Fig. 2, the upper electrode 22 includes a first metal layer 22a containing titanium, a second metal layer 22b containing titanium nitride, and a third metal layer 22c containing aluminum.

[0023] The first insulating portion 31 includes silicon oxide. The second insulating portion 32 includes an insulating resin such as polyimide. After forming the first insulating portion 31 by chemical vapor deposition (CVD) or the like, a portion of the first insulating portion 31 is removed by photolithography and anisotropic etching to form the protrusion P1.

[0024] The operation of the semiconductor device 1 will be described. When a forward voltage (V Ｆ), a current flows from the upper electrode 22 to the lower electrode 21. This causes the semiconductor device 1 to be in an on state. When the voltage applied to the upper electrode 22 subsequently falls below the forward voltage, the current decreases and the semiconductor device 1 is in an off state. When a positive voltage is applied to the lower electrode 21 with respect to the upper electrode 22, n － A depletion layer spreads from the pn junction between the n-type semiconductor region 11 and the p-type semiconductor region 12. ＋ The potential in the vicinity of the semiconductor region 13 becomes substantially the same as the potential of the lower electrode 21 .

[0025] 3 is a cross-sectional view showing a semiconductor device according to a reference example. In the semiconductor device 1r shown in FIG. 3, the protrusion P1 is not provided on the upper surface of the first insulating portion 31. The upper surface of the first insulating portion 31 is flat. The other configurations of the semiconductor device 1r are the same as those of the semiconductor device 1.

[0026] 4(a) and 4(b) are schematic diagrams for explaining the problems with the semiconductor device according to the reference example. The semiconductor device may be used in a high-temperature and high-humidity environment. In this case, moisture easily penetrates into the second insulating portion 32. When the penetrated moisture reaches the upper electrode 22, electrolysis of the moisture occurs on the surface of the upper electrode 22 as follows. 2H ２ O + 2e － → H ２ +2OH －

[0027] The hydroxide ions cause the polarity around the upper electrode 22 to become alkaline, and aluminum complex ions are generated as follows: Al(OH) ３ +OH － → [Al(OH) ４ ] －

[0028] When the semiconductor device is in the off state, n ＋The potential near the semiconductor region 13 is substantially the same as the potential of the lower electrode 21. Therefore, an electric field is generated from the upper electrode 22 toward the outer periphery of the semiconductor layer 10. The interface between the first insulating portion 31 and the second insulating portion 32 is continuous with the interface between the upper electrode 22 and the first insulating portion 31 and the interface between the upper electrode 22 and the second insulating portion 32. Therefore, aluminum complex ions C generated in the upper electrode 22 move along the electric field at the interface between the first insulating portion 31 and the second insulating portion 32, as shown in FIG. 4( a).

[0029] Furthermore, in the upper electrode 22, as the complex ions move, oxides are formed as follows: 2[Al(OH) ４ ] － → Al ２ O ３ +3H ２ O + 2OH －

[0030] In addition, the transferred complex ion is n ＋ When the semiconductor region 13 is reached, the upper electrode 22 and the n ＋ A current begins to flow between the upper electrode 22 and the semiconductor region 13. This current flow promotes electrolysis and the generation of complex ions in the upper electrode 22. As aluminum oxide is formed, the stress applied to the second insulating portion 32 increases. Eventually, as shown in FIG. 4B, a crack is generated in the second insulating portion 32 by the oxide 22ox. A discharge occurs through the crack between the upper electrode 22 and the outer periphery of the semiconductor layer 10, destroying the semiconductor device 1r.

[0031] In the semiconductor device 1 according to the first embodiment, a protrusion P1 is provided on the upper surface of the first insulating portion 31. When the protrusion P1 is provided, the protrusion P1 prevents the movement of aluminum complex ions. By preventing the movement of the complex ions, the upper electrode 22 and the n ＋ This can prevent current from flowing between the upper electrode 22 and the second insulating region 13. This can prevent electrolysis and oxide formation in the upper electrode 22, thereby reducing the possibility of cracks occurring in the second insulating portion 32 due to oxides. As a result, the semiconductor device 1 is less likely to be damaged by cracks in the second insulating portion 32.

[0032] According to the first embodiment, even when used in a high-temperature and high-humidity environment, the occurrence of breakdown of the semiconductor device 1 can be suppressed, and the breakdown resistance of the semiconductor device 1 can be improved.

[0033] The above-mentioned problem is more likely to occur as the voltage applied to the semiconductor device increases. The higher the applied voltage, the more electrolysis of water occurs, and the more likely an oxide is formed on the upper electrode 22. For example, when the semiconductor layer 10 contains silicon carbide, the breakdown field strength of the semiconductor layer 10 can be made larger than when the semiconductor layer 10 contains single-crystal silicon. Because a larger voltage can be applied to the semiconductor device, electrolysis and oxide formation on the upper electrode 22 are more likely to occur.

[0034] According to the first embodiment, it is possible to suppress the formation of oxides in the upper electrode 22 even when a high voltage is applied to the semiconductor device 1. Therefore, the first embodiment of the present invention is more suitable for the semiconductor device 1 that uses silicon carbide.

[0035] As shown in FIG. 2, the position p1 of the protrusion P1 in the radial direction is the same as the position p2 of the p-type semiconductor region 12 in the radial direction. ＋ It is preferable that the position p1 of at least one of the protrusions P1 is between the position p2 and the position p3 of the semiconductor region 13. When the position p1 of at least one of the protrusions P1 is between the position p2 and the position p3, the movement of complex ions from the upper electrode 22 toward the outer periphery of the semiconductor layer 10 can be effectively suppressed.

[0036] 5(a) to 5(d) are plan views showing the layout of the protrusions provided on the first insulating portion. As shown in FIG. 1, an annular protrusion P1 may be provided, or as shown in FIG. 5(a), a linear protrusion P1 may be provided. In the example shown in FIG. 5(a), each protrusion P1 extends in the X direction or Y direction along the side of the semiconductor device 1. The protrusions P1 intersect with each other at the corners of the semiconductor device 1.

[0037] 5(b) and 5(c), more curved or linear protrusions P1 may be provided at the corners of the semiconductor device 1. Alternatively, as shown in FIG. 5(d), a plurality of protrusions P1 may be arranged along the outer periphery of the semiconductor device 1.

[0038] As shown in Figure 1 and Figures 5(a) to 5(d), the number and arrangement of the protrusions P1 are arbitrary. By providing at least one protrusion P1, the movement of complex ions can be inhibited. More preferably, the protrusions P1 surround the upper electrode 22 along the XY plane, as shown in Figure 2 and Figures 5(a) to 5(c). This allows the protrusions P1 to inhibit the movement of complex ions in any direction from the upper electrode 22 toward the outer periphery of the semiconductor layer 10.

[0039] (First Modification) Figure 6 is a cross-sectional view showing a portion of a semiconductor device according to a first modification of the first embodiment. In the semiconductor device 1a shown in Figure 6, the first insulating portion 31 and the protrusion P1 are made of different materials. For example, the first insulating portion 31 includes silicon oxide. The protrusion P1 includes silicon oxide or silicon nitride.

[0040] Unlike the semiconductor device 1a, the first insulating portion 31 and the protrusion P1 do not have to be an integral member. In the semiconductor device 1a, the first insulating portion 31 and the protrusion P1 are both made of an insulating material containing silicon. Complex ions are less likely to move at the interface between the protrusion P1 and the first insulating portion 31 than at the interface between the first insulating portion 31 and the second insulating portion 32, which contains resin. Therefore, according to the first modification, the breakdown resistance of the semiconductor device 1a can be improved compared to the semiconductor device 1r according to the reference example.

[0041] More preferably, the first insulating portion 31 and the protrusion P1 are integrally formed. For example, the first insulating portion 31 including the protrusion P1 is formed by processing a single insulating layer. In this case, the region between the first insulating portion 31 and the protrusion P1 is seamless, with no interface. This more reliably prevents the passage of complex ions between the first insulating portion 31 and the protrusion P1. By integrally forming the first insulating portion 31 and the protrusion P1, the breakdown resistance of the semiconductor device 1 can be further improved compared to the semiconductor device 1a.

[0042] 7 is a cross-sectional view showing a portion of a semiconductor device according to a second modification of the first embodiment. In the semiconductor device 1b shown in FIG. 7, the semiconductor layer 10 further includes a p-type RESURF region 14a (an example of a fourth semiconductor region), as compared to the semiconductor device 1. The p-type RESURF region 14a is provided around the p-type semiconductor region 12 along the XY plane.

[0043] The p-type resurf region 14a is in contact with the p-type semiconductor region 12. The lower surface of the p-type resurf region 14a is located higher than the lower surface of the p-type semiconductor region 12. The p-type impurity concentration of the p-type resurf region 14a may be the same as the p-type impurity concentration of the p-type semiconductor region 12, or may be lower than the p-type impurity concentration of the p-type semiconductor region 12. The end E in the radial direction of the p-type resurf region 14a is ＋ The semiconductor region 13 is spaced apart from the substrate.

[0044] By providing the p-type resurf region 14a, the electric field strength in the outer peripheral portion of the p-type semiconductor region 12 can be alleviated, and the breakdown voltage of the semiconductor device 1b can be improved.

[0045] In the semiconductor device 1b, the position p1 in the radial direction of the protrusion P1 is preferably between the position p2 in the radial direction of the p-type semiconductor region 12 and the position p4 in the radial direction of the end E of the p-type RESURF region 14a. The electric field strength is higher near the end E than in other parts. When the complex ions move to the region directly above the end E, the complex ions are accelerated by the electric field. As a result, the complex ions are accelerated by the ＋ Position p1 is located between positions p2 and p4, which makes it easier for the complex ions to reach the semiconductor region 13. Since position p1 is located between positions p2 and p4, the complex ions can be prevented from migrating to the region directly above the end E. This further improves the breakdown resistance of the semiconductor device 1b.

[0046] 8 is a cross-sectional view showing a part of a semiconductor device according to a third modification of the first embodiment. In the semiconductor device 1c shown in FIG. 8, the semiconductor layer 10 further includes a p-type guard ring region 14b (another example of the fourth semiconductor region) compared to the semiconductor device 1. The p-type guard ring region 14b is formed between the p-type semiconductor region 12 and the n-type semiconductor region 13. ＋A plurality of p-type guard ring regions 14b are provided in the radial direction and spaced apart from the p-type semiconductor region 13. The p-type guard ring regions 14b are spaced apart from each other and surround the p-type semiconductor region 12 in the XY plane.

[0047] The thickness of the p-type guard ring region 14b in the Z direction may be the same as the thickness of the p-type semiconductor region 12 in the Z direction, or may be smaller than the thickness of the p-type semiconductor region 12. The p-type impurity concentration of the p-type guard ring region 14b may be the same as the p-type impurity concentration of the p-type semiconductor region 12, or may be lower than the p-type impurity concentration of the p-type semiconductor region 12. The p-type impurity concentrations of the p-type guard ring regions 14b are the same as each other. The p-type impurity concentration of the p-type guard ring region 14b may decrease as it is positioned further outward from the semiconductor device 1c.

[0048] In the semiconductor device 1c, the position p1 of the protrusion P1 is preferably between the position p2 of the p-type semiconductor region 12 and the position p5 of the outermost p-type guard ring region 14b in the radial direction. The electric field strength is higher near the outermost p-type guard ring region 14b than in other areas. When the complex ions move to the region directly above the outermost p-type guard ring region 14b, the complex ions are accelerated by the electric field. As a result, the complex ions are transported to the n ＋ The position p1 is located between the positions p2 and p5, which makes it easier for the complex ions to reach the semiconductor region 13. The position p1 is located between the positions p2 and p5, which makes it possible to prevent the complex ions from migrating to a region of high electric field strength. This further improves the breakdown voltage of the semiconductor device 1c.

[0049] (Fourth Modification) Figure 9 is a cross-sectional view showing a portion of a semiconductor device according to a fourth modification of the first embodiment. A semiconductor device 1d shown in Figure 9 differs from the semiconductor device 1 in that it is provided with a protrusion P0 and a protrusion P2. The protrusion P0 is provided on the upper surface of the semiconductor layer 10. The protrusion P2 is provided on the upper surface of the second insulating portion 32. The position of the protrusion P0 in the X-Y plane, the position of the protrusion P1 in the X-Y plane, and the position of the protrusion P2 in the X-Y plane are all the same.

[0050] After forming the semiconductor layer 10, other portions of the semiconductor layer 10 are removed so that a portion corresponding to the protrusion P0 remains. As a result, the protrusion P0 is formed on the upper surface of the semiconductor layer 10. Thereafter, a first insulating portion 31 is formed on the semiconductor layer 10, thereby forming a protrusion P1 according to the position and size of the protrusion P0. A second insulating portion 32 is formed on the first insulating portion 31, thereby forming a protrusion P2 according to the position and size of the protrusion P1.

[0051] Furthermore, the semiconductor device 1d may be molded with resin. By providing the protrusion P2 on the upper surface of the second insulating portion 32, the contact area between the second insulating portion 32 and the molded resin can be increased, and the adhesion between the second insulating portion 32 and the molded resin can be improved.

[0052] (Fifth Modification) Figure 10 is a cross-sectional view showing a portion of a semiconductor device according to a fifth modification of the first embodiment. A semiconductor device 1e shown in Figure 10 differs from the semiconductor device 1 in that it further includes a third insulating portion 33. The third insulating portion 33 is provided on the second insulating portion 32. In the semiconductor device 1e, the second insulating portion 32 contains silicon oxide or silicon nitride. The third insulating portion 33 contains polyimide.

[0053] As in semiconductor device 1e, an insulating portion other than first insulating portion 31 and second insulating portion 32 may be further provided. Furthermore, in semiconductor device 1e, as in semiconductor device 1d, second insulating portion 32 may be provided with protrusion P2. In this case, protrusion P3 is provided on the upper surface of third insulating portion 33. By providing protrusion P3, when semiconductor device 1e is molded with resin, it is possible to improve adhesion between third insulating portion 33 and molding resin.

[0054] Second Embodiment Fig. 11 is a cross-sectional view showing a part of a semiconductor device according to a second embodiment. The semiconductor device according to the second embodiment is a MOSFET. A semiconductor device 2 shown in Fig. 11 further includes a gate electrode 25 compared to the semiconductor device 1. Furthermore, the semiconductor layer 10 in the semiconductor device 2 has an n ＋ The semiconductor region 15 (fifth semiconductor region) is further included.

[0055] The gate electrode 25 faces the p-type semiconductor region 12 via a gate insulating layer 25a. ＋ contact regions 12a and n ＋ The p-type semiconductor region 15 is provided on the p-type semiconductor region 12. ＋ contact regions 12a and n ＋ The semiconductor region 15 is electrically connected to the upper electrode 22 .

[0056] For example, the p-type semiconductor region 12, p ＋ Contact regions 12a,n ＋ A plurality of p-type semiconductor regions 15 and a plurality of gate electrodes 25 are provided in the X direction. ＋ shaped contact region 12a, each n ＋ The semiconductor region 15 and each gate electrode 25 extend in the Y direction.

[0057] The operation of the semiconductor device 2 will now be described. With a positive voltage applied to the lower electrode 21 relative to the upper electrode 22, a voltage equal to or greater than the threshold is applied to the gate electrode 25. This forms a channel (inversion layer) in the p-type semiconductor region 12, turning the semiconductor device 2 on. Electrons flow through the channel from the upper electrode 22 to the lower electrode 21. When the voltage applied to the gate electrode 25 becomes lower than the threshold, the channel in the p-type semiconductor region 12 disappears, turning the semiconductor device 2 off.

[0058] When the semiconductor device 2 is in an off state, an electric field is generated from the upper electrode 22 toward the outer periphery of the semiconductor layer 10, similar to the semiconductor device 1. By providing the protrusion P1 on the upper surface of the first insulating portion 31, the breakdown voltage of the semiconductor device 2 can be improved, similar to the first embodiment.

[0059] 11 is a trench-gate MOSFET, and the gate electrode 25 faces the p-type semiconductor region 12 in the X direction. The semiconductor device according to the second embodiment may be a planar-gate MOSFET. In that case, the gate electrode 25 faces the p-type semiconductor region 12 in the Z direction.

[0060] 12 is a cross-sectional view showing a part of a semiconductor device according to a third embodiment. The semiconductor device according to the third embodiment is an IGBT. In the semiconductor device 3 shown in FIG. 12, the semiconductor layer 10 is n-type, as compared with the semiconductor device 2. ＋ Instead of the contact region 11a, ＋ The semiconductor layer 10 further includes an n-type semiconductor region 11b.

[0061] p ＋ The semiconductor region 16 is connected to the lower electrode 21 and － The n-type semiconductor region 11b is electrically connected to the lower electrode 21. ＋ The semiconductor region 16 and the n － The n-type impurity concentration of the n-type semiconductor region 11b is n － The n-type impurity concentration of the n-type semiconductor region 11 is higher than that of the n-type semiconductor region 11 .

[0062] With a positive voltage applied to the lower electrode 21 relative to the upper electrode 22, a voltage equal to or greater than the threshold is applied to the gate electrode 25. This forms a channel (inversion layer) in the p-type semiconductor region 12. Electrons pass through the channel and ＋ Semiconductor regions 15 to n － The holes flow into the semiconductor region 11, ＋ Semiconductor regions 16 to n － flow into the semiconductor region 11. － Conductivity modulation occurs in the p-type semiconductor region 11, greatly reducing the electrical resistance of the semiconductor device 3. A large current flows through the semiconductor device 3, turning the semiconductor device 3 on. Thereafter, when the voltage applied to the gate electrode 25 becomes lower than the threshold, the channel in the p-type semiconductor region 12 disappears, turning the semiconductor device 3 off.

[0063] When the semiconductor device 3 is in an off state, an electric field is generated from the upper electrode 22 toward the outer periphery of the semiconductor layer 10, similar to the semiconductor device 1. By providing the protrusion P1 on the upper surface of the first insulating portion 31, the breakdown voltage of the semiconductor device 3 can be improved, similar to the first embodiment.

[0064] The structures according to the modifications of the first embodiment can also be applied to the semiconductor device according to the second or third embodiment. For example, the semiconductor device 2 or the semiconductor device 3 may be provided with a p-type resurf region 14a or a p-type guard ring region 14b. The semiconductor device 2 or the semiconductor device 3 may be provided with a protrusion P0 and a protrusion P2. The semiconductor device 2 or the semiconductor device 3 may be provided with a third insulating portion 33.

[0065] 13 is a cross-sectional view showing a portion of a semiconductor device according to a fourth embodiment. In the semiconductor device 4 shown in FIG. 13, a recess R1 is provided on the upper surface of the first insulating portion 31 instead of the protrusion P1. For example, a plurality of recesses R1 are provided in the radial direction. Each recess R1 surrounds the upper electrode 22 along the XY plane. A portion of the second insulating portion 32 is located inside the recess R1. Therefore, a protrusion is provided on the lower surface of the second insulating portion 32.

[0066] Similarly to the case where the protrusion P1 is provided, when the recess R1 is provided on the upper surface of the first insulating portion 31, it is possible to inhibit the movement of complex ions from the upper electrode 22 toward the outer periphery of the semiconductor layer 10. Therefore, according to the fourth embodiment, like the first embodiment, it is possible to improve the breakdown resistance of the semiconductor device 4.

[0067] However, in the semiconductor device 4, the thickness of the first insulating portion 31 where the recess R1 is provided is smaller than the thickness of the other portions of the first insulating portion 31. Therefore, the electric field strength is higher at the bottom of the recess R1 than in other portions. If ions remain at the bottom of the recess R1 due to the strong electric field, the expansion of the depletion layer in the radial direction in the semiconductor layer 10 is affected. As a result, the breakdown voltage of the semiconductor device 4 may fluctuate.

[0068] Providing the protrusion P1 can suppress a partial increase in electric field strength at the interface between the first insulating portion 31 and the second insulating portion 32, thereby making it possible to further stabilize the breakdown voltage of the semiconductor device. For this reason, when comparing the recess R1 and the protrusion P1, providing the protrusion P1 is more preferable.

[0069] Embodiments of the present invention include the following features. (Structure 1) A semiconductor device comprising: a first electrode; a semiconductor layer provided on the first electrode; a second electrode provided on the semiconductor layer and containing aluminum; a first insulating portion including: a first portion provided between the semiconductor layer and an outer periphery of the second electrode; and a second portion provided around the first portion along a first surface perpendicular to a first direction from the first electrode to the semiconductor layer, the second portion having a convex portion on its upper surface; and a second insulating portion provided on the outer periphery and the second portion of the second electrode. (Structure 2) The semiconductor device according to Structure 1, wherein the convex portion surrounds the second electrode along the first surface. (Structure 3) The semiconductor device according to Structure 2, wherein a plurality of the convex portions are provided in a second direction from the first portion to the second portion. (Structure 4) The semiconductor device according to any one of Structures 1 to 3, wherein the second portion and the convex portion are integrally provided. (Structure 5) The semiconductor device according to any one of Structures 1 to 4, wherein the semiconductor layer includes: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on the first semiconductor region; and a third semiconductor region of the first conductivity type provided around the second semiconductor region along the first surface, spaced apart from the second semiconductor region, and having a higher impurity concentration of the first conductivity type than the first semiconductor region, the second electrode being provided on the second semiconductor region, and a position of the convex portion in a second direction from the first portion to the second portion being between a position of the second semiconductor region in the second direction and a position of the third semiconductor region in the second direction. (Structure 6) The semiconductor device according to Structure 5, wherein the semiconductor layer further includes a fourth semiconductor region of the second conductivity type provided between the second semiconductor region and the third semiconductor region, an end of the fourth semiconductor region in the second direction is spaced apart from the third semiconductor region, and a position of the convex portion in the second direction is between a position of the second semiconductor region in the second direction and a position of the end in the second direction.(Structure 7) The semiconductor device according to Structure 5 or 6, further comprising a gate electrode facing the second semiconductor region via a gate insulating layer, wherein the semiconductor layer further includes a fifth semiconductor region of the first conductivity type provided on the second semiconductor region. (Structure 8) The semiconductor device according to any one of Structures 1 to 7, wherein the semiconductor layer includes silicon carbide.

[0070] In each of the embodiments described above, the relative level of the impurity concentration between each semiconductor region can be confirmed using, for example, a scanning capacitance microscope (SCM). The carrier concentration in each semiconductor region can be considered to be equal to the concentration of activated impurities in each semiconductor region. Therefore, the relative level of the carrier concentration between each semiconductor region can also be confirmed using SCM. Furthermore, the impurity concentration in each semiconductor region can be measured using, for example, secondary ion mass spectrometry (SIMS).

[0071] Although several embodiments of the present invention have been described above, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other.

[0072] 1, 1a to 1e, 1r, 2 to 4: semiconductor device, 10: semiconductor layer, 11: n － Semiconductor region, 11a:n ＋ n-type contact region, 11b: n-type semiconductor region, 12: p-type semiconductor region, 12a: p ＋ Shape contact area, 13:n ＋ p-type semiconductor region, 14a: p-type RESURF region, 14b: p-type guard ring region, 15: n ＋ Shape semiconductor region, 16:p ＋shaped semiconductor region, 21: lower electrode, 22: upper electrode, 22a: first metal layer, 22b: second metal layer, 22c: third metal layer, 22ox: oxide, 25: gate electrode, 25a: gate insulating layer, 31: first insulating portion, 31a: first portion, 31b: second portion, 32: second insulating portion, 33: third insulating portion, E1: end portion, P0 to P3: convex portions, R1: concave portion

Claims

1. A semiconductor device comprising: a first electrode; a semiconductor layer provided on the first electrode; a second electrode provided on the semiconductor layer and including aluminum; a first insulating portion including a first portion provided between the semiconductor layer and an outer periphery of the second electrode and a second portion provided around the first portion along a first plane perpendicular to a first direction from the first electrode to the semiconductor layer and having a convex portion on an upper surface; and a second insulating portion provided on the outer periphery and the second portion of the second electrode.

2. The semiconductor device according to claim 1, wherein said protrusion surrounds said second electrode along said first surface.

3. The semiconductor device according to claim 2, wherein the protruding portion is provided in a plurality of portions in a second direction from the first portion toward the second portion.

4. The semiconductor device according to any one of claims 1 to 3, wherein the second portion and the protruding portion are integrally formed.

5. The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor layer includes: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on the first semiconductor region; and a third semiconductor region of the first conductivity type provided around the second semiconductor region along the first surface, spaced apart from the second semiconductor region, and having a higher impurity concentration of the first conductivity type than the first semiconductor region; the second electrode is provided on the second semiconductor region; and the position of the convex portion in a second direction from the first portion to the second portion is between the position of the second semiconductor region in the second direction and the position of the third semiconductor region in the second direction.

6. The semiconductor device described in claim 5, wherein the semiconductor layer further includes a fourth semiconductor region of a second conductivity type provided between the second semiconductor region and the third semiconductor region, an end of the fourth semiconductor region in the second direction is separated from the third semiconductor region, and a position of the convex portion in the second direction is between a position of the second semiconductor region in the second direction and a position of the end in the second direction.

7. The semiconductor device according to claim 5, further comprising a gate electrode facing the second semiconductor region via a gate insulating layer, the semiconductor layer further including a fifth semiconductor region of the first conductivity type provided on the second semiconductor region.

8. The semiconductor device according to claim 1, wherein the semiconductor layer includes silicon carbide.

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