Bus monitoring and control method, electronic device, chip and storage medium

Abstract

The present application relates to a bus monitoring and control method, an electronic device, a chip and a storage medium. The method is applied to an integrated circuit device. The method comprises: an integrated circuit device monitoring communication data between masters and slaves in an SPMI bus; if it is determined on the basis of the communication data that the operating state of the integrated circuit device is a first operating state, and the SPMI bus is in an idle state, simulating for the masters the slaves to perform bus arbitration, simulating for the slaves the masters to perform bus arbitration, and controlling a switch module to perform switching, such that the integrated circuit device is connected to the masters and the slaves; and when it is determined that the masters preempt the SPMI bus using the highest priority, sending resent data to the slaves. After the masters and the slaves are all subjected to bus arbitration, the integrated circuit device switches the switch module, such that burrs generated during the process of switching the switch module can be prevented from affecting the operation of the SPMI bus, and an external integrated circuit device controls data of the slaves.

Description

Bus monitoring and control method, electronic device, chip and storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to a Chinese patent application filed with the Chinese Patent Office on August 8, 2023, with application number 202310992708.9 and application name “Bus monitoring and control method, electronic device, chip and storage medium”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to the field of bus communication technology, and in particular to bus monitoring and control methods, electronic equipment, chips and storage media. Background Art

[0004] The existing System Power Management Interface (SPMI) is a two-wire serial interface, commonly used as a power management interface, connecting a host and a slave device. For example, the host can be a system-on-a-chip (SOC), and the slave device can be a power management IC (PMIC). The SPMI bus accurately monitors and controls the processor performance level required for a given workload or application on the associated devices, and dynamically controls the power supply voltage in real time based on this performance level. However, data in a master-slave system based on the SPMI bus must be controlled by the host, making it impossible to stably control the data in the master-slave system through external devices.

[0005] Summary of the Invention

[0006] In view of the above, it is necessary to provide a bus monitoring and control method, electronic device, chip and storage medium to solve the problem that data in a master-slave system based on the SPMI bus cannot be stably controlled by external devices.

[0007] In a first aspect, an embodiment of the present application provides a bus monitoring and control method, which is applied to an integrated circuit device, wherein the integrated circuit device is connected to a host, and the host, the integrated circuit device, and the slave are respectively connected to a switch module through a system power management interface SPMI bus. The method includes: monitoring the communication data between the host and the slave in the SPMI bus; if it is determined according to the communication data that the working state of the integrated circuit device is a first working state, sending preset reissued data to the slave; wherein, sending the preset reissued data to the slave includes: if it is monitored that the SPMI bus is in an idle state, simulating the slave to perform bus arbitration on the host, and simulating the host to perform bus arbitration on the slave; controlling the switch module to switch so that the integrated circuit device is connected to the host and the slave, respectively; and when it is determined that the host preempts the SPMI bus with the highest priority, sending the reissued data to the slave. In the above technical solution, when the integrated circuit device is in the first working state, it detects whether the SPMI bus is idle. When the SPMI bus is idle, the integrated circuit device first simulates the slave to perform bus arbitration on the host, and simulates the host to perform bus arbitration on the slave. When both the host and the slave perform bus arbitration, the switch module is switched. This can avoid the burrs generated during the switching of the switch module from affecting the correct operation of the SPMI bus, and at the same time ensure that no other host or slave will preempt the bus at the same time when the switch module is switched, thereby realizing stable control of the slave data by the external integrated circuit device.

[0008] In one embodiment of the present application, the method further includes: if the operating state of the integrated circuit device is determined to be the second operating state based on the communication data, controlling the switch module to switch so that the host and the slave are connected. In the above solution, the host establishes a communication channel with the slave through the switch module and transmits the communication data directly to the slave through the switch module.

[0009] In one embodiment of the present application, determining the operating state of the integrated circuit device based on the communication data includes: if it is determined that the communication data includes a preset instruction, determining the operating state of the integrated circuit device to be the first operating state; or if it is determined that the communication data does not include the preset instruction, determining the operating state of the integrated circuit device to be the second operating state. In the above technical solution, the operating state of the integrated circuit device can be determined based on the preset instruction included in the communication data.

[0010] In one embodiment of the present application, the bus arbitration of simulating the slave to the host and the bus arbitration of simulating the master to the slave include: simulating the slave to perform bus arbitration by pulling up a data signal line of the SPMI bus connected to the upper port of the integrated circuit device, wherein the upper port is connected to the host via the SPMI bus; and simulating the slave to perform bus arbitration by pulling up a data signal line of the SPMI bus connected to the lower port of the integrated circuit device, wherein the lower port is connected to the slave via the SPMI bus. In the above technical solution, the integrated circuit device simulates the slave to pull up a data signal line to initiate bus arbitration for the host, and simulates the slave to pull up a bus arbitration for the host. After both sides are pulled up, the switch module is switched. This can prevent the glitches generated during the switching process of the switch from affecting the operation of the SPMI bus.

[0011] In one embodiment of the present application, when determining that the master preempts the SPMI bus with the highest priority, sending the retransmitted data to the slave includes: writing the retransmitted data value to the slave via an external register write instruction. In the above technical solution, the integrated circuit device can write the retransmitted data from a non-master into the slave via an external register write instruction.

[0012] In one embodiment of the present application, after the master simulates the slave for bus arbitration, the method further includes: if the SPMI bus instruction cycle of the slave performing bus arbitration reaches the stage where the slave preempts the SPMI bus with the highest priority, sending a preset slave address to the master. In the above technical solution, when the master simulates the slave for bus arbitration, if the SPMI bus instruction cycle reaches the stage where the slave preempts the SPMI bus with the highest priority, sending the preset slave address to the master to ensure the correct execution of the SPMI bus instruction cycle.

[0013] In one embodiment of the present application, after sending a preset slave address to the master, the method further includes: if the SPMI bus instruction cycle of the slave performing bus arbitration reaches the frame sequence stage, writing preset data to the master with the preset master address. In the above technical solution, when the master simulates the slave performing bus arbitration, if the SPMI bus instruction cycle reaches the frame sequence stage, writing preset data to the master with the preset master address further ensures the correct operation of the SPMI bus instruction cycle.

[0014] In one embodiment of the present application, writing the preset data to the host having the preset host address includes: writing the preset data to a register of the host having the preset host address using a master write instruction. In the above technical solution, the integrated circuit device can transmit the preset data to the host having the preset host address using the master write instruction.

[0015] In one embodiment of the present application, the retransmitted data is data determined according to the type of the slave.

[0016] On the second aspect, some embodiments of the present application provide an electronic device, which includes a memory and a processor: wherein the memory is used to store program instructions; the processor is used to read and execute the program instructions stored in the memory, and when the program instructions are executed by the processor, the electronic device executes the above-mentioned bus monitoring and control method.

[0017] On the third aspect, some embodiments of the present application provide a chip comprising a processor and a memory; wherein the processor is connected to the memory; the memory is used to store program instructions; and the processor is used to read the program instructions stored in the memory to implement the above-mentioned bus monitoring and control method.

[0018] In a fourth aspect, some embodiments of the present application provide a computer storage medium storing program instructions. When the program instructions are executed on an electronic device, the electronic device executes the above-mentioned bus monitoring and control method.

[0019] In addition, the technical effects brought about by the second to fourth aspects can be found in the descriptions of the methods of each design in the above method section, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] FIG1 is a schematic diagram of the architecture of the SPMI bus in the related art.

[0021] FIG. 2 is a schematic diagram of an instruction cycle of an SPMI bus in an embodiment of the present application.

[0022] FIG3 is a schematic diagram of the architecture of the SPMI bus in one embodiment of the present application.

[0023] FIG4 is a functional module diagram of an integrated circuit device in an embodiment of the present application.

[0024] FIG5 is a schematic diagram showing the connection between an integrated circuit device and a host and a slave in an embodiment of the present application.

[0025] FIG6 is a schematic diagram showing the connection between an integrated circuit device and a host and a slave in another embodiment of the present application.

[0026] FIG7 is a flow chart of a bus monitoring and control method according to an embodiment of the present application.

[0027] FIG8 is a schematic diagram showing the connection between an integrated circuit device and a host and a slave in another embodiment of the present application.

[0028] FIG9 is a flow chart of a method for monitoring an SPMI bus in an embodiment of the present application.

[0029] FIG10 is a flow chart of a bus monitoring and control method in another embodiment of the present application.

[0030] FIG11 is a schematic diagram of the hardware structure of an electronic device in an embodiment of the present application. DETAILED DESCRIPTION

[0031] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of such features. In the description of some embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "for example" in some embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete way.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs. The terms used in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. It should be understood that, unless otherwise specified in this application, " / " means or. For example, A / B can mean A or B. "And / or" in some embodiments of this application is merely a way to describe the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. "At least one" means one or more. "Multiple" means two or more than two. For example, at least one of a, b or c can mean: a, b, c, a and b, a and c, b and c, a, b and c.

[0033] Referring to FIG1 , there is shown a schematic diagram of the architecture of a System Power Management Interface (SPMI) bus in the related art. The SPMI bus is an asynchronous bus that can connect multiple hosts 11 and multiple slaves 12. Multiple hosts 11 and multiple slaves 12 exchange data via the SPMI bus. In one embodiment of the present application, the host 11 and the slave 12 perform bus preemption through arbitration to resolve conflicts. When the bus is in an idle state, multiple hosts 11 or slaves 12 can access the bus through bus arbitration requests. The bus host 11 monitors the bus arbitration request and grants the bus to a requester.

[0034] When the bus is in an idle state, multiple hosts 11 or slaves 12 can access the bus through bus arbitration requests. A host 11 of the bus (the host is the current owner of the bus) monitors the bus arbitration request and grants the bus to a requester. Generally, the SPMI bus may include a clock signal line and a data signal line. The clock signal line is used to transmit the clock signal SCLK (Serial Clock) and the data signal line is used to transmit the data signal SDATA (Serial Data). The SPMI bus can support the simultaneous connection of 4 hosts 11 and the access of 16 slaves 12. For example, the SPMI bus can be connected to one or more hosts 11 on a system-on-a-chip (SOC), or to one or more slaves 12 on a power management chip (PMIC).

[0035] The architecture shown in FIG1 is for illustrative purposes only and is not limited thereto in practical applications.

[0036] FIG2 is a schematic diagram illustrating an SPMI bus instruction cycle in accordance with one embodiment of the present application. In one embodiment of the present application, the SPMI bus instruction cycle includes the following phases: bus arbitration, sequence start, frame sequence, and bus stop cycle. During the bus arbitration phase, when the data signal line of the SPMI bus is pulled high, the host 11 currently occupying the SPMI bus releases the clock signal SCLK via the clock signal line. The host 11 or slave 12 connected to the SPMI bus pulls the data signal line high in response to the corresponding clock signal SCLK to declare its priority. If a device with a higher priority requests to occupy the SPMI bus, the host 11 currently occupying the SPMI bus releases the bus to the higher-priority device based on its priority. After the host 11 or slave 12 preempts the SPMI bus and becomes the controller of the SPMI bus, it gains control of the SPMI bus clock signal SCLK and provides the SPMI bus clock signal SCLK. After completing bus arbitration, the SPMI bus enters the sequence start phase. The sequence start phase can be a bus buffer phase. During the sequence start phase, the device that wins the bus preemption pulls the clock signal SCLK low and simultaneously controls the data signal line to first pull the data signal SDATA high and then pull it low, generating a sequence start condition (SSC). After detecting the start condition, a slave device 12 on the SPMI bus, such as a power management chip, prepares to receive the subsequent frame sequence.

[0037] In one embodiment of the present application, a frame sequence is used to execute a data transmission instruction. The data transmission instruction includes information such as a transmission command, a transmission address, and transmission data. In one embodiment of the present application, the types of transmission commands include, but are not limited to: the host 11 reads the register of the slave 12, the host 11 writes the register of the slave 12, and the slave 12 writes the register of the host 11. In one embodiment of the present application, the transmission address includes the address of the slave 12 and the address of the register of the slave 12. For example, a specific data transmission instruction may be a command for the host to write data 01 to the 0011 register of the slave with address 0001. After the data transmission instruction is completed in the frame sequence, the SPMI bus enters a bus stop cycle.

[0038] In one embodiment of the present application, the bus stop cycle phase of the SPMI bus is a process in which the bus is stopped, during which the SPMI bus is in an idle state. When the SPMI bus is in the bus stop cycle phase, the clock signal SCLK and the transmission data signal SDATA of the SPMI bus are both pulled low, for example, the clock signal SCLK and the transmission data signal SDATA of the SPMI bus are pulled low to a low level.

[0039] However, in the related art, data interaction between the host 11 and the slave 12 on the SPMI bus shown in Figure 1 is controlled by the host 11 and cannot be controlled by external devices. To address the problem that data interaction between the host 11 and the slave 12 on the SPMI bus cannot be controlled by external devices, an embodiment of the present application provides another SPMI bus architecture. Referring to Figure 3, a schematic diagram of the SPMI bus architecture in one embodiment of the present application is shown. In this embodiment of the present application, multiple hosts 11 are connected to an integrated circuit (IC) device 13. For example, multiple hosts 11 are connected to the IC device 13 via the SPMI bus. Multiple hosts 11, multiple slaves 12, and the IC device 13 are each connected to a switch module 14 via the SPMI bus. The IC device 13 can control the switch module 14 to switch between a first channel and a second channel. When the switch module 14 switches to the first channel, the host 11 and the slave 12 are each connected to the IC device 13 via the SPMI bus. When the switch module 14 switches to the second channel, the host 11 is directly connected to the slave 12 via the SPMI bus.

[0040] In one embodiment of the present application, the switch module 14 includes a first switch 141 and a second switch 142. The first switch 141 and the second switch 142 are dual-channel high-speed switches. The first channel of the first switch 141 and the first channel of the second switch 142 are both connected to the integrated circuit device 13, and the second channel of the first switch 141 is connected to the second channel of the second switch 142. Thus, when both the first switch 141 and the second switch 142 are switched to the first channel, the integrated circuit device 13 is connected to the master 11 and the slave 12 respectively via the SPMI bus. When both the first switch 141 and the second switch 142 are switched to the second channel, the master 11 is directly connected to the slave 12 via the SPMI bus.

[0041] In one embodiment of the present application, the operating state of the integrated circuit device 13 includes a first operating state and a second operating state. The first operating state indicates that the integrated circuit device 13 sends data from a non-master device to the slave device 12, that is, the integrated circuit device 13 retransmits data to the slave device 12. In various embodiments of the present application, data from the non-master device 11 is used as retransmitted data and is sent to the slave device 12. The second operating state indicates that the integrated circuit device 13 controls the master device 11 to directly exchange data with the slave device 12.

[0042] FIG4 shows a functional block diagram of an integrated circuit device 13 according to an embodiment of the present application. The integrated circuit device 13 includes a bus monitoring module 131, a data retransmission module 132, and a switch control module 133. FIG5 shows a schematic diagram of the connection between the integrated circuit device and a host and a slave according to an embodiment of the present application. In one embodiment of the present application, when the integrated circuit device 13 is operating in a first operating state, the first switch 141 is switched to the first channel, and the second switch 142 is switched to the first channel. Thus, the host 11 communicates with the integrated circuit device 13 via the first channel of the first switch 141, and the slave 12 communicates with the integrated circuit device 13 via the first channel of the second switch 142. FIG6 shows a schematic diagram of the connection between the integrated circuit device and a host and a slave according to another embodiment of the present application. In one embodiment of the present application, when the integrated circuit device 13 is operating in a second operating state, the first switch 141 is switched to the second channel, and the second switch 142 is switched to the second channel. The host 11 directly exchanges data with the slave 12 via the second channel of the second switch 142 via the second channel of the first switch 141.

[0043] In one embodiment of the present application, the bus monitoring module 131 is connected to the data retransmission module 132 and the switch control module 133, respectively. The switch control module 133 is connected to the first switch 141 and the second switch 142, and is configured to control the switching between the first channel and the second channel of the first switch 141 and the second switch 142. The data retransmission module 132 is connected to the first channel of the first switch 141 and the first channel of the second switch 142, respectively. The bus monitoring module 131 is configured to monitor the communication data between the host 11 and the slave 12 and determine the operating state of the integrated circuit device 13 based on the monitored communication data. If it is determined that the communication data between the host 11 and the slave 12 includes a preset instruction, the operating state of the integrated circuit device 13 is determined to be the first operating state. If it is determined that the communication data between the host 11 and the slave 12 does not include the preset instruction, the operating state of the integrated circuit device 13 is determined to be the second operating state. Preset instructions include, but are not limited to, instructions for the host 11 to read from the slave 12, instructions for the host 11 to write to the slave 12, and instructions for the slave 12 to write to the host 11. When the bus monitoring module 131 determines that the operating state of the integrated circuit device 13 is the second operating state, it determines a switching time and notifies the switch control module 133 of the switching time. The switch control module 133 controls the first switch 141 and the second switch 142 to switch on and off based on the switching time, thereby switching the channel to be switched on. For example, when the integrated circuit device 13 is operating in the second operating state, the switch control module 133 controls the first switch 141 and the second switch 142 to switch to the second channel based on the switching time. When the integrated circuit device 13 is operating in the first operating state, the switch control module 133 controls the first switch 141 and the second switch 142 to switch to the first channel based on the switching time. When the bus monitoring module 131 determines that the operating state of the integrated circuit device 13 is the first operating state, it sends a data retransmission notification to the data retransmission module 132. The data retransmission module 132 determines retransmission data based on the data retransmission notification and sends the retransmission data to the slave 12. The retransmission data is data pre-set based on the type of the slave 12. For example, if the slave device 12 is a power management chip, the retransmitted data is voltage or current data.

[0044] In an embodiment of the present application, the integrated circuit device 13 monitors the communication data between the host 11 and the slave 12 on the SPMI bus. When the working state of the integrated circuit device 13 is determined to be the second working state based on the monitored communication data, the first switch 141 and the second switch 142 are switched to the second channel, so that the host 11 and the slave 12 can communicate directly, thereby ensuring the interaction of original data between the host 11 and the slave 12; when the working state of the integrated circuit device 13 is determined to be the first working state based on the monitored communication data, the reissued data is determined and sent to the slave 12, thereby realizing the control of the data of the slave 12 by the integrated circuit device 13.

[0045] 7 is a flow chart of a bus monitoring and control method according to an embodiment of the present application. The bus monitoring and control method is applied to an integrated circuit device 13. The method specifically includes the following steps.

[0046] Step S701: pre-set a predetermined instruction.

[0047] In one embodiment of the present application, the bus monitoring module 131 pre-sets a predetermined instruction. For example, the predetermined instruction may be at least one of an instruction for the host 11 to read from the slave 12, an instruction for the host 11 to write to the slave 12, and an instruction for the slave 12 to write to the host 11. The above is merely an example and is not limited to this in actual application. For example, the predetermined instruction may be an instruction for the host 11 with a source address of 0001 to write the value "01" to the slave 12 with a destination address of 1111.

[0048] Step S702 : monitoring the communication data on the SPMI bus and determining whether the working state of the integrated circuit device 13 is the first working state.

[0049] In one embodiment of the present application, the bus monitoring module 131 monitors communication data on the SPMI bus, such as communication data sent from the master 11 to the slave 12, and determines whether the communication data includes a predetermined instruction. If it is determined that the communication data does not include the predetermined instruction, the bus monitoring module 131 determines that the integrated circuit device 13 is in the second operating state and executes step S703. If it is determined that the communication data includes the predetermined instruction, the monitoring module 133 determines that the integrated circuit device 13 is in the first operating state and executes step S704. If the bus monitoring module 131 determines that the communication data includes the predetermined instruction, it continues to monitor the SPMI bus to ensure that the subsequent data retransmission module 132 successfully seizes the bus.

[0050] In step S703 , the control host sends the communication data directly to the slave 12 .

[0051] In one embodiment of the present application, when the integrated circuit device 13 operates in the second operating state, the switch control module 133 controls the first switch 141 and the second switch 142 to switch to the second channel. In this way, the host 11 establishes a communication channel with the slave 12 through the first switch 141 and the second switch 142, and transmits the communication data directly to the slave through the first switch 141 and the second switch 142.

[0052] Step S704: determining resending data according to the communication data.

[0053] In one embodiment of the present application, when the bus monitoring module 131 determines that the operating state of the integrated circuit device 13 is the first operating state based on predetermined instructions in the communication data, it sends a data retransmission notification to the data retransmission module 132. The data retransmission module 132 determines retransmission data based on the data retransmission notification. The retransmission data is data pre-set based on the type of the slave device 12. For example, if the slave device 12 is a power management chip, the retransmission data is voltage or current data.

[0054] Step S705: monitor whether the SPMI bus is in an idle state.

[0055] In one embodiment of the present application, if the bus monitoring module 131 monitors that both the clock signal line and the data signal line of the SPMI bus are in a high-impedance state, the SPMI bus is determined to be in an idle state. If the SPMI bus is in an idle state, steps S706 and S707 may be executed synchronously. In one embodiment of the present application, synchronous execution means executing at the same time point. If the SPMI bus is not in an idle state, step S705 is repeated until the SPMI bus is monitored to enter an idle state.

[0056] Step S706: Perform bus arbitration on the master simulating the slave.

[0057] Referring to FIG8 , there is shown a schematic diagram of the connection between the integrated circuit device and the host and slave in another embodiment of the present application. The upper port of the integrated circuit device 13 is connected to the host 11 via the SPMI bus, and the lower port of the integrated circuit device 13 is connected to the slave 11 via the SPMI bus. The data retransmission module 132 simulates the bus arbitration of the slave 12 for the host 11 by pulling up the data signal line of the SPMI bus connected to the upper port. Pulling up the data signal line of the SPMI bus connected to the upper port indicates that the data signal line of the SPMI bus connected to the upper port is set to a high potential, such as a potential of 1.5V or above. The data retransmission module 132 simulates the bus arbitration of the slave 12 for the host 11, which can ensure that the integrated circuit device 13 will not be interfered with by the bus operation of the host 11 when performing data retransmission.

[0058] Step S707: Perform bus arbitration on the slave device by simulating the master device.

[0059] In one embodiment of the present application, the data retransmission module 132 simulates the master 11 and performs bus arbitration on the slave 12 by pulling up the data signal line of the SPMI bus connected to the lower port. Pulling up the data signal line of the SPMI bus connected to the lower port indicates that the data signal line of the SPMI bus connected to the lower port is set to a high potential.

[0060] Step S708: Control the integrated circuit device to connect to the host and the slave respectively.

[0061] In one embodiment of the present application, the switch control module 133 controls the first switch 141 and the second switch 142 to switch to the first channel. Thus, the integrated circuit device 13 establishes a communication channel with the host 11 and the slave 12 through the first switch 141 and the second switch 142. After step S708 is executed, the process continues to step S709 and step S713.

[0062] Step S709 , determining whether the SPMI bus instruction cycle of the slave performing bus arbitration has reached the stage where the slave preempts the SPMI bus with the highest priority.

[0063] In one embodiment of the present application, if the SPMI bus instruction cycle of the slave performing bus arbitration reaches the stage where the slave preempts the SPMI bus with the highest priority, step S710 is executed; if the SPMI bus instruction cycle of the slave performing bus arbitration has not reached the stage where the slave preempts the SPMI bus with the highest priority, step S709 is repeated until the stage where the slave preempts the SPMI bus with the highest priority arrives, and the process executes step S710.

[0064] Step S710: When the slave seizes the SPMI bus with the highest priority, it sends a preset slave address to the host.

[0065] In one embodiment of the present application, the preset slave address is different from the addresses of all slaves 12 connected to the integrated circuit device 13. For example, the addresses of all slaves 12 connected to the SPMI bus include Address0 to Address15. The data retransmission module 132 sends the preset slave address Address16, which is different from Address0 to Address15, to the host 11.

[0066] Step S711: determining whether the SPMI bus instruction cycle of the slave device performing bus arbitration has reached the frame sequence stage.

[0067] In one embodiment of the present application, if the SPMI bus instruction cycle for bus arbitration of the slave machine reaches the frame sequence stage, step S712 is executed; if the SPMI bus instruction cycle for bus arbitration of the slave machine does not reach the frame sequence stage, step S712 is repeated until the frame sequence stage arrives.

[0068] Step S712: write preset data to the host with the preset host address.

[0069] In one embodiment of the present application, the data re-issuing module 132 writes preset data, such as 00, to a register of a host having a preset host address through a master write instruction. In one embodiment of the present application, the preset host address is different from the addresses of all hosts 12 connected to the integrated circuit device 13. For example, the addresses of all hosts 12 connected on the SPMI bus include address 0 to address 3. The data re-issuing module 132 writes the preset data to the host 11 having a preset host address address 4, which is different from address 0 to address 3.

[0070] Step S713: determining whether the SPMI bus instruction cycle in which the host performs bus arbitration has reached a stage where the host preempts the SPMI bus with the highest priority.

[0071] In one embodiment of the present application, if the SPMI bus instruction cycle of the host performing bus arbitration reaches the stage where the host preempts the SPMI bus with the highest priority, step S714 is executed; if the SPMI bus instruction cycle of the host performing bus arbitration does not reach the stage where the host preempts the SPMI bus with the highest priority, step S713 is repeated until the stage where the host preempts the SPMI bus with the highest priority arrives.

[0072] Step S714: When the host seizes the SPMI bus with the highest priority, the retransmitted data is sent to the slave.

[0073] In one embodiment of the present application, the data retransmission module 132 sends the retransmission data to any one or more slaves 12 connected to the SPMI bus. In one embodiment of the present application, the data retransmission module 132 writes the retransmission data value to the target slave via an external register write instruction.

[0074] In one embodiment of the present application, after the retransmitted data is sent to the target slave, the switch control module 133 controls the first switch 141 and the second switch 142 to switch from the first channel to the second channel. In this way, the host 11 re-establishes a communication channel with the slave 12 through the first switch 141 and the second switch 142, and transmits the communication data directly to the slave 12 through the first switch 141 and the second switch 142.

[0075] To maintain stable operation of the SPMI bus when the integrated circuit device 13 switches between the first and second operating states, the integrated circuit device 13 in the embodiment of the present application detects the need for data retransmission (i.e., the integrated circuit device 13 is in the first operating state). When the SPMI bus is idle, the integrated circuit device 13 simulates a slave pulling up the data signal line to initiate bus arbitration for the master, and simulates a master pulling up the data signal line to initiate bus arbitration for the slave. After both sides are pulled up, the first switch 141 and the second switch 142 are switched to the first channel. This prevents glitches during the switching of the first and second switches 141, 142 from affecting the correct operation of the SPMI bus, and ensures that no other master or slave simultaneously attempts to seize the bus when the first and second switches 141, 142 are switched, causing anomalies. During the data retransmission process for the slave, the integrated circuit device 13 simultaneously preempts the SPMI bus with the highest priority for the master, ensuring that no master performs bus operations during the data retransmission period.

[0076] In an embodiment of the present application, the integrated circuit device 13 monitors the communication data of the SPMI bus, and after detecting that there is a predetermined instruction in the communication data and the SPMI bus is idle, the integrated circuit device 13 first simulates the host to pull up the data signal line of the slave to initiate bus arbitration, simulates the host to pull up the integrated circuit device 13 to initiate bus arbitration, and writes the re-sent data value into the target slave, thereby realizing the external integrated circuit device 13 to stably transmit data from the slave 12.

[0077] In one embodiment of the present application, when integrated circuit device 13 operates in a first operating state, integrated circuit device 13 can accurately identify the current state of the SPMI bus, thereby ensuring that SPMI can pull up the data signal line with the highest priority to preempt the bus at the rising edge of the clock signal line of host 11. When integrated circuit device 13 operates in a second operating state, integrated circuit device 13 can identify and store communication data between the master and slave devices, and identify whether the communication data contains predetermined instructions requiring data retransmission.

[0078] 9 is a flow chart of a method for monitoring an SPMI bus according to an embodiment of the present application. The method for monitoring an SPMI bus is applied during the bus arbitration phase of an SPMI bus instruction cycle. The method includes the following steps.

[0079] Step S901: monitoring the bus start condition.

[0080] In one embodiment of the present application, if it is detected that the data signal line of the SPMI bus is pulled high and the clock signal line remains at a low level, it is determined that the bus start condition is detected.

[0081] Step S902: monitor the status of the BUS Park of the SPMI bus.

[0082] In one embodiment of the present application, BUS Park represents a bus park period.

[0083] Step S903: monitor whether the slave machine preempts the SPMI bus with the secondary priority. If the slave machine preempts the SPMI bus with the secondary priority, execute step S904; if the slave machine does not preempt the SPMI bus with the secondary priority, execute step S905.

[0084] Step S904: Execute a bus connection sequence.

[0085] In one embodiment of the present application, the bus connection sequence represents that other hosts 11 access the SPMI bus.

[0086] Step S905: monitor whether the slave has seized the SPMI bus with the highest priority. If the slave has seized the SPMI bus with the highest priority, execute step S906; if the slave has not seized the SPMI bus with the highest priority, execute step S907.

[0087] Step S906: Identify the slave address sent by the slave. After step S906 is completed, the process goes to step S917.

[0088] Step S907: monitor whether the host preempts the SPMI bus with the highest priority. If the host does not preempt the SPMI bus with the highest priority, execute step S908; if the host preempts the SPMI bus with the highest priority, execute step S917.

[0089] Step S908: Monitor whether the host preempts the SPMI bus with the first priority. If the host does not preempt the SPMI bus with the first priority, execute step S909. If the host preempts the SPMI bus with the first priority, execute step S917. The first priority level is lower than the highest priority level.

[0090] Step S909 monitors whether the host preempts the SPMI bus with the second priority. If the host does not preempt the SPMI bus with the second priority, step S910 is executed. If the host preempts the SPMI bus with the second priority, step S917 is executed. The second priority is lower than the first priority.

[0091] Step S910 monitors whether the host preempts the SPMI bus with a third priority. If the host does not preempt the SPMI bus with the third priority, step S911 is executed. If the host preempts the SPMI bus with the third priority, step S917 is executed. The third priority is lower than the second priority.

[0092] Step S911, monitoring whether the slave machine preempts the SPMI bus with the second-second priority; if the slave machine preempts the SPMI bus with the second-second priority, executing step S906; if the slave machine does not preempt the SPMI bus with the second-second priority, executing step S912.

[0093] Step S912: monitor whether the host preempts the SPMI bus with the highest priority. If the host does not preempt the SPMI bus with the highest priority, execute step S913; if the host preempts the SPMI bus with the highest priority, execute step S917.

[0094] Step S913: monitor whether the host preempts the SPMI bus with the first priority. If the host does not preempt the SPMI bus with the first priority, execute step S914; if the host preempts the SPMI bus with the first priority, execute step S917.

[0095] Step S914: monitor whether the host preempts the SPMI bus with the second priority. If the host does not preempt the SPMI bus with the second priority, execute step S915; if the host preempts the SPMI bus with the second priority, execute step S917.

[0096] Step S915: monitor whether the host preempts the SPMI bus with the third priority. If the host does not preempt the SPMI bus with the third priority, execute step S916; if the host preempts the SPMI bus with the third priority, execute step S917.

[0097] Step S916: It is determined that no device has seized the SPMI bus, and the SPMI bus enters an idle state.

[0098] Step S917: The bus arbitration phase ends and the SPMI bus enters the SSC phase.

[0099] In an embodiment of the present application, the integrated circuit device 13 adopts a sampling method triggered by the falling edge of the clock to monitor and identify the stage of the SPMI bus instruction cycle in which the SPMI bus is currently located, so that the delay in sending the monitoring result and the communication data of the host is within a preset time range, for example, within 5ns.

[0100] 10 is a flow chart of a bus monitoring and control method according to another embodiment of the present application, which includes the following steps.

[0101] Step S1001: monitoring the communication data between the master and slave in the SPMI bus.

[0102] In one embodiment of the present application, the specific implementation steps of step S1001 refer to step S702 of FIG7 , and will not be repeated here.

[0103] Step S1002: If it is determined according to the communication data that the working state of the integrated circuit device is the first working state, the retransmission data is sent to the slave device.

[0104] In one embodiment of the present application, if it is monitored that the SPMI bus is in an idle state, the host 11 simulates the slave 12 to perform bus arbitration, and the slave 12 simulates the host 11 to perform bus arbitration; the control switch module 14 is switched so that the integrated circuit device 13 is connected to the host 11 and the slave 12 respectively; when it is determined that the host 11 preempts the SPMI bus with the highest priority, the retransmitted data is sent to the slave 12, thereby realizing the control of the external integrated circuit device 13 over the data of the slave 12.

[0105] 11 is a schematic diagram of the hardware structure of an electronic device 100 according to an embodiment of the present application. The electronic device 100 may include a processor 110, an integrated circuit device 13, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone jack 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display 194, and a subscriber identification module (SIM) card interface 195. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc.

[0106] It should be understood that the structure illustrated in the embodiments of the present invention does not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may include more or fewer components than shown, or may combine or separate certain components, or arrange the components differently. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0107] The processor 110 may include one or more processing units. For example, the processor 110 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU). The different processing units may be independent devices or integrated into one or more processors.

[0108] The controller can generate operation control signals according to the instruction operation code and timing signal to complete the control of instruction fetching and execution.

[0109] Processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in processor 110 is a cache memory. This memory can store instructions or data that have just been used or are being recycled by processor 110. If processor 110 needs to use the same instruction or data again, it can directly access the memory. This avoids duplicate accesses, reduces processor 110 latency, and thus improves system efficiency.

[0110] In some embodiments, the processor 110 may include one or more interfaces. The interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface.

[0111] The I2C interface is a bidirectional synchronous serial bus that includes a serial data line (SDA) and a serial clock line (SCL). In some embodiments, the processor 110 may include multiple I2C bus lines. The processor 110 may be coupled to the touch sensor 180K, the charger, the flash, the camera 193, and the like via different I2C bus interfaces. For example, the processor 110 may be coupled to the touch sensor 180K via the I2C interface, enabling communication between the processor 110 and the touch sensor 180K via the I2C bus interface, thereby implementing the touch function of the electronic device 100.

[0112] The I2S interface can be used for audio communication. In some embodiments, the processor 110 can include multiple I2S buses. The processor 110 can be coupled to the audio module 170 via the I2S bus to enable communication between the processor 110 and the audio module 170. In some embodiments, the audio module 170 can transmit audio signals to the wireless communication module 160 via the I2S interface, enabling the function of answering calls through a Bluetooth headset.

[0113] The PCM interface can also be used for audio communication, sampling, quantizing, and encoding analog signals. In some embodiments, the audio module 170 and the wireless communication module 160 can be coupled via a PCM bus interface. In some embodiments, the audio module 170 can also transmit audio signals to the wireless communication module 160 via the PCM interface, enabling the function of answering calls via a Bluetooth headset. Both the I2S interface and the PCM interface can be used for audio communication.

[0114] The UART interface is a universal serial data bus used for asynchronous communication. This bus can be a bidirectional communication bus. It converts the data to be transmitted between serial communication and parallel communication. In some embodiments, the UART interface is typically used to connect the processor 110 and the wireless communication module 160. For example, the processor 110 communicates with the Bluetooth module in the wireless communication module 160 via the UART interface to implement Bluetooth functionality. In some embodiments, the audio module 170 can transmit audio signals to the wireless communication module 160 via the UART interface, enabling the function of playing music through Bluetooth headphones.

[0115] The MIPI interface can be used to connect the processor 110 to peripheral devices such as the display 194 and the camera 193. MIPI interfaces include the camera serial interface (CSI) and the display serial interface (DSI). In some embodiments, the processor 110 and the camera 193 communicate via the CSI interface to implement the camera function of the electronic device 100. The processor 110 and the display 194 communicate via the DSI interface to implement the display function of the electronic device 100.

[0116] The GPIO interface can be configured via software. The GPIO interface can be configured as either a control signal or a data signal. In some embodiments, the GPIO interface can be used to connect the processor 110 to the camera 193, display 194, wireless communication module 160, audio module 170, sensor module 180, etc. The GPIO interface can also be configured as an I2C interface, an I2S interface, a UART interface, a MIPI interface, etc.

[0117] The USB interface 130 is an interface that complies with USB standards and may be a Mini USB interface, a Micro USB interface, a USB Type-C interface, or the like. The USB interface 130 can be used to connect a charger to charge the electronic device 100, or to transfer data between the electronic device 100 and peripheral devices. It can also be used to connect headphones to play audio. This interface can also be used to connect other electronic devices 100, such as AR devices.

[0118] It is understood that the interface connection relationship between the modules illustrated in the embodiment of the present invention is merely an illustrative illustration and does not constitute a structural limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may also adopt different interface connection methods from the above embodiments, or a combination of multiple interface connection methods.

[0119] The charging management module 140 is configured to receive charging input from a charger. The charger can be either a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 140 can receive charging input from the wired charger via the USB interface 130. In some wireless charging embodiments, the charging management module 140 can receive wireless charging input via the wireless charging coil of the electronic device 100. While charging the battery 142, the charging management module 140 can also provide power to the electronic device 100 via the power management module 141.

[0120] The power management module 141 is used to connect the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140, and provides power to the processor 110, the internal memory 121, the display 194, the camera 193, and the wireless communication module 160. The power management module 141 can also be used to monitor parameters such as battery capacity, battery cycle count, and battery health status (leakage, impedance). In some other embodiments, the power management module 141 can also be set in the processor 110. In other embodiments, the power management module 141 and the charging management module 140 can also be set in the same device.

[0121] The wireless communication function of the electronic device 100 can be implemented through the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, the modem processor and the baseband processor.

[0122] Antenna 1 and Antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in electronic device 100 can be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve antenna utilization. For example, antenna 1 can be reused as a diversity antenna for a wireless local area network. In other embodiments, the antennas can be used in conjunction with a tuning switch.

[0123] The mobile communication module 150 can provide solutions for wireless communications including 2G / 3G / 4G / 5G applied to the electronic device 100. The mobile communication module 150 may include at least one filter, a switch, a power amplifier, a low noise amplifier (LNA), etc. The mobile communication module 150 can receive electromagnetic waves from the antenna 1, and filter, amplify, and process the received electromagnetic waves, and transmit them to the modulation and demodulation processor for demodulation. The mobile communication module 150 can also amplify the signal modulated by the modulation and demodulation processor, and convert it into electromagnetic waves for radiation through the antenna 1. In some embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the processor 110. In some embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the same device as at least some of the modules of the processor 110.

[0124] The modem processor may include a modulator and a demodulator. The modulator is used to modulate the low-frequency baseband signal to be transmitted into a medium-high frequency signal. The demodulator is used to demodulate the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After being processed by the baseband processor, the low-frequency baseband signal is passed to the application processor. The application processor outputs a sound signal through an audio device (not limited to the speaker 170A, the receiver 170B, etc.) or displays an image or video through the display screen 194. In some embodiments, the modem processor may be an independent device. In other embodiments, the modem processor may be independent of the processor 110 and be set in the same device as the mobile communication module 150 or other functional modules.

[0125] The wireless communication module 160 can provide wireless communication solutions including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR), etc., which are applied to the electronic device 100. The wireless communication module 160 can be one or more devices that integrate at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via the antenna 2, frequency modulates and filters the electromagnetic wave signals, and sends the processed signals to the processor 110. The wireless communication module 160 can also receive the signal to be sent from the processor 110, frequency modulate it, amplify it, and convert it into electromagnetic waves for radiation through the antenna 2.

[0126] In some embodiments, the antenna 1 of the electronic device 100 is coupled to the mobile communication module 150, and the antenna 2 is coupled to the wireless communication module 160, so that the electronic device 100 can communicate with a network and other devices through wireless communication technologies. The wireless communication technologies may include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code division multiple access (WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (LTE), BT, GNSS, WLAN, NFC, FM, and / or IR technology. The GNSS may include a global positioning system (GPS), a global navigation satellite system (GLONASS), a Beidou navigation satellite system (BDS), a quasi-zenith satellite system (QZSS) and / or a satellite based augmentation system (SBAS).

[0127] Electronic device 100 implements display functionality through a GPU, display screen 194, and an application processor. A GPU is a microprocessor for image processing that connects display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. Processor 110 may include one or more GPUs that execute program instructions to generate or modify display information.

[0128] Display screen 194 is used to display images, videos, and the like. Display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a MiniLED, a MicroLED, a Micro-oLed, or a quantum dot light-emitting diode (QLED). In some embodiments, electronic device 100 may include one or N display screens 194, where N is a positive integer greater than one.

[0129] The electronic device 100 can implement a shooting function through an ISP, a camera 193, a video codec, a GPU, a display screen 194, and an application processor.

[0130] The ISP processes data fed back by camera 193. For example, when taking a photo, the shutter is opened, and light is transmitted through the lens to the camera's photosensitive element. The light signal is converted into an electrical signal, which is then passed to the ISP for processing and converted into a visible image. The ISP can also perform algorithmic optimization on image noise, brightness, and skin tone. It can also optimize parameters such as exposure and color temperature of the captured scene. In some embodiments, the ISP can be located within camera 193.

[0131] The camera 193 is used to capture still images or videos. The object generates an optical image through the lens and projects it onto the photosensitive element. The photosensitive element can be a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the light signal into an electrical signal, and then passes the electrical signal to the ISP for conversion into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in a standard RGB, YUV or other format. In some embodiments, the electronic device 100 may include 1 or N cameras 193, where N is a positive integer greater than 1.

[0132] The digital signal processor is used to process digital signals. In addition to processing digital image signals, it can also process other digital signals. For example, when the electronic device 100 selects a frequency point, the digital signal processor is used to perform Fourier transform on the frequency point energy.

[0133] Video codecs are used to compress or decompress digital video. Electronic device 100 may support one or more video codecs. This allows electronic device 100 to play or record videos in various encoding formats, such as Moving Picture Experts Group (MPEG) 1, MPEG2, MPEG3, and MPEG4.

[0134] The NPU is a neural network (NN) computing processor. Drawing on the structure of biological neural networks, such as the transmission patterns between neurons in the human brain, it rapidly processes input information and can continuously self-learn. The NPU can enable intelligent cognitive applications in electronic device 100, such as image recognition, face recognition, speech recognition, and text comprehension.

[0135] The internal memory 121 may include one or more random access memories (RAM) and one or more non-volatile memories (NVM).

[0136] Random access memory may include static random-access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM, for example, the fifth generation DDR SDRAM is generally referred to as DDR5 SDRAM), etc.; non-volatile memory may include disk storage devices and flash memory.

[0137] Flash memory can be divided into NOR FLASH, NAND FLASH, 3D NAND FLASH, etc. according to the operating principle; single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC), etc. according to the storage cell potential level; universal flash storage (UFS) and embedded multi media card (eMMC) can be divided into UFS and eMMC according to the storage specification.

[0138] The random access memory can be directly read and written by the processor 110, and can be used to store executable programs (such as machine instructions) of the operating system or other running programs, and can also be used to store user and application data.

[0139] The non-volatile memory may also store executable programs and user and application data, etc., and may be loaded into the random access memory in advance for direct reading and writing by the processor 110 .

[0140] The external memory interface 120 can be used to connect to an external non-volatile memory to expand the storage capacity of the electronic device 100. The external non-volatile memory communicates with the processor 110 via the external memory interface 120 to implement data storage. For example, files such as music and videos can be stored in the external non-volatile memory.

[0141] The internal memory 121 or the external memory interface 120 is used to store one or more computer programs. The one or more computer programs are configured to be executed by the processor 110. The one or more computer programs include multiple instructions. When the multiple instructions are executed by the processor 110, the bus monitoring and control method executed on the electronic device 100 in the above embodiment can be implemented to realize the bus monitoring and control functions of the electronic device 100.

[0142] The electronic device 100 can implement audio functions such as music playback and recording through the audio module 170, the speaker 170A, the receiver 170B, the microphone 170C, the headphone jack 170D, and the application processor.

[0143] The audio module 170 is used to convert digital audio information into analog audio signal output, and is also used to convert analog audio input into digital audio signals. The audio module 170 can also be used to encode and decode audio signals. In some embodiments, the audio module 170 can be provided in the processor 110, or some functional modules of the audio module 170 can be provided in the processor 110.

[0144] The speaker 170A, also called a "speaker", is used to convert audio electrical signals into sound signals. The electronic device 100 can listen to music or listen to hands-free calls through the speaker 170A.

[0145] The receiver 170B, also called a "handset", is used to convert audio electrical signals into sound signals. When the electronic device 100 receives a call or a voice message, the user can place the receiver 170B close to the ear to hear the voice.

[0146] Microphone 170C, also known as "microphone" or "microphone", is used to convert sound signals into electrical signals. When making a call or sending a voice message, the user can speak by putting their mouth close to the microphone 170C to input the sound signal into the microphone 170C. The electronic device 100 can be provided with at least one microphone 170C. In other embodiments, the electronic device 100 can be provided with two microphones 170C, which can not only collect sound signals but also realize noise reduction function. In other embodiments, the electronic device 100 can also be provided with three, four or more microphones 170C to collect sound signals, reduce noise, identify the source of sound, realize directional recording function, etc.

[0147] The headphone jack 170D is used to connect a wired headphone and can be a USB interface 130 or a 3.5mm open mobile terminal platform (OMTP) standard interface or a cellular telecommunications industry association of the USA (CTIA) standard interface.

[0148] Pressure sensor 180A is used to sense pressure signals and convert them into electrical signals. In some embodiments, pressure sensor 180A can be located on display screen 194. There are many types of pressure sensors 180A, such as resistive, inductive, and capacitive. A capacitive pressure sensor can include at least two parallel plates made of conductive material. When force acts on pressure sensor 180A, the capacitance between the electrodes changes. Electronic device 100 determines the intensity of the pressure based on this change in capacitance. When a touch operation is applied to display screen 194, electronic device 100 detects the touch intensity based on pressure sensor 180A. Electronic device 100 can also calculate the touch location based on the detection signal from pressure sensor 180A. In some embodiments, touch operations applied to the same touch location but with different touch intensities can correspond to different operation instructions. For example, when a touch operation with an intensity less than a first pressure threshold is applied to a short message application icon, a command to view short messages is executed. When a touch operation with an intensity greater than or equal to the first pressure threshold is applied to a short message application icon, a command to create a new short message is executed.

[0149] The gyroscope sensor 180B can be used to determine the motion posture of the electronic device 100. In some embodiments, the angular velocity of the electronic device 100 around three axes (i.e., x, y, and z axes) can be determined by the gyroscope sensor 180B. The gyroscope sensor 180B can be used for anti-shake shooting. For example, when the shutter is pressed, the gyroscope sensor 180B detects the angle of the electronic device 100 shaking, calculates the distance that the lens module needs to compensate based on the angle, and allows the lens to offset the shaking of the electronic device 100 through reverse movement to achieve anti-shake. The gyroscope sensor 180B can also be used for navigation and somatosensory game scenes.

[0150] The pressure sensor 180C is used to measure air pressure. In some embodiments, the electronic device 100 calculates the altitude through the air pressure value measured by the pressure sensor 180C to assist in positioning and navigation. The magnetic sensor 180D includes a Hall sensor. The electronic device 100 can use the magnetic sensor 180D to detect the opening and closing of the flip leather case. In some embodiments, when the electronic device 100 is a flip phone, the electronic device 100 can detect the opening and closing of the flip cover based on the magnetic sensor 180D. Then, based on the detected opening and closing state of the leather case or the opening and closing state of the flip cover, features such as automatic unlocking of the flip cover can be set. The acceleration sensor 180E can detect the magnitude of the acceleration of the electronic device 100 in various directions (generally three axes). When the electronic device 100 is stationary, the magnitude and direction of gravity can be detected. It can also be used to identify the posture of the electronic device 100, and is applied to applications such as horizontal and vertical screen switching, pedometers, etc. The distance sensor 180F is used to measure distance. The electronic device 100 can measure distance through infrared or laser. In some embodiments, when shooting a scene, the electronic device 100 may use the distance sensor 180F to measure distance to achieve fast focusing.

[0151] The proximity light sensor 180G may include, for example, a light emitting diode (LED) and a light detector, such as a photodiode. The light emitting diode may be an infrared light emitting diode. The electronic device 100 emits infrared light outward through the light emitting diode. The electronic device 100 uses a photodiode to detect infrared reflected light from nearby objects. When sufficient reflected light is detected, it can be determined that there is an object near the electronic device 100. When insufficient reflected light is detected, the electronic device 100 can determine that there is no object near the electronic device 100. The electronic device 100 can use the proximity light sensor 180G to detect that the user is holding the electronic device 100 close to the ear to talk, so as to automatically turn off the screen to save power. The proximity light sensor 180G can also be used in leather case mode and pocket mode to automatically unlock and lock the screen.

[0152] Ambient light sensor 180L is used to sense ambient light brightness. Electronic device 100 can adaptively adjust the brightness of display screen 194 based on the perceived ambient light. Ambient light sensor 180L can also be used to automatically adjust white balance when taking photos. Ambient light sensor 180L can also work with proximity light sensor 180G to detect whether electronic device 100 is in a pocket to prevent accidental touches.

[0153] The fingerprint sensor 180H is used to collect fingerprints. The electronic device 100 can use the collected fingerprint characteristics to implement fingerprint unlocking, access application locks, fingerprint photography, fingerprint call answering, etc.

[0154] The temperature sensor 180J is used to detect temperature. In some embodiments, the electronic device 100 uses the temperature detected by the temperature sensor 180J to execute a temperature processing strategy. For example, when the temperature reported by the temperature sensor 180J exceeds a threshold, the electronic device 100 reduces the performance of the processor located near the temperature sensor 180J to reduce power consumption and implement thermal protection. In other embodiments, when the temperature is lower than another threshold, the electronic device 100 heats the battery 142 to prevent the electronic device 100 from shutting down abnormally due to low temperature. In other embodiments, when the temperature is lower than another threshold, the electronic device 100 boosts the output voltage of the battery 142 to prevent abnormal shutdown due to low temperature.

[0155] The touch sensor 180K is also called a "touch-sensitive device." The touch sensor 180K can be disposed on the display screen 194. The touch sensor 180K and the display screen 194 form a touch screen, also called a "touch screen." The touch sensor 180K is used to detect touch operations applied thereto or in the vicinity thereof. The touch sensor can transmit the detected touch operations to the application processor to determine the type of touch event. Visual output related to the touch operations can be provided via the display screen 194. In other embodiments, the touch sensor 180K can also be disposed on the surface of the electronic device 100, at a location different from that of the display screen 194.

[0156] The bone conduction sensor 180M can obtain vibration signals. In some embodiments, the bone conduction sensor 180M can obtain vibration signals from the vibrating bones of the human body. The bone conduction sensor 180M can also contact the human pulse to receive blood pressure pulse signals. In some embodiments, the bone conduction sensor 180M can also be set in headphones to form bone conduction headphones. The audio module 170 can parse out voice signals based on the vibration signals of the vibrating bones of the human body obtained by the bone conduction sensor 180M to implement voice functions. The application processor can parse heart rate information based on the blood pressure pulse signals obtained by the bone conduction sensor 180M to implement heart rate detection functions.

[0157] The buttons 190 include a power button, a volume button, and the like. The buttons 190 may be mechanical buttons or touch buttons. The electronic device 100 may receive key inputs and generate key signal inputs related to user settings and function control of the electronic device 100.

[0158] Motor 191 can generate vibration prompts. Motor 191 can be used for incoming call vibration prompts, and can also be used for touch vibration feedback. For example, touch operations acting on different applications (such as taking pictures, audio playback, etc.) can correspond to different vibration feedback effects. For touch operations acting on different areas of the display screen 194, motor 191 can also correspond to different vibration feedback effects. Different application scenarios (for example: time reminders, receiving messages, alarm clocks, games, etc.) can also correspond to different vibration feedback effects. The touch vibration feedback effect can also support customization.

[0159] The indicator 192 may be an indicator light, which may be used to indicate the charging status, power level changes, messages, missed calls, notifications, etc.

[0160] The SIM card interface 195 is used to connect a SIM card. The SIM card can be connected to and disconnected from the electronic device 100 by inserting it into or removing it from the SIM card interface 195. The electronic device 100 can support 1 or N SIM card interfaces, where N is a positive integer greater than 1. The SIM card interface 195 can support Nano SIM cards, Micro SIM cards, SIM cards, and the like. Multiple cards can be inserted into the same SIM card interface 195 at the same time. The types of the multiple cards can be the same or different. The SIM card interface 195 can also be compatible with different types of SIM cards. The SIM card interface 195 can also be compatible with external memory cards. The electronic device 100 interacts with the network through the SIM card to implement functions such as calls and data communications. In some embodiments, the electronic device 100 uses an eSIM, i.e., an embedded SIM card. The eSIM card can be embedded in the electronic device 100.

[0161] This embodiment further provides a computer program product. When the computer program product is run on a computer, the computer is caused to execute the above-mentioned related steps to implement the bus monitoring and control method in the above-mentioned embodiment.

[0162] In addition, some embodiments of the present application also provide a device, which can specifically be a chip, component or module, and the device may include a connected processor and memory; wherein the memory is used to store computer-executable instructions, and when the device is running, the processor can execute the computer-executable instructions stored in the memory to enable the chip to execute the bus monitoring and control methods in the above-mentioned method embodiments.

[0163] Among them, the electronic device, computer storage medium, computer program product or chip provided in this embodiment is used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method provided above, and will not be repeated here.

[0164] Through the description of the above implementation methods, technical personnel in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0165] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interface, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0166] The unit described as a separate component may or may not be physically separated, and the component displayed as a unit may be one physical unit or multiple physical units, that is, it may be located in one place, or it may be distributed in multiple different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, the various functional units in the various embodiments of the present application may be integrated into a processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0167] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of some embodiments of the present application are essentially or partly contributed to the prior art or all or part of the technical solutions can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a device (which can be a single-chip microcomputer, chip, etc.) or a processor to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0168] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of some embodiments of the present application and are not limiting. Although some embodiments of the present application are described in detail with reference to the preferred embodiments, ordinary technicians in this field should understand that the technical solutions of some implementation examples of the present application can be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of some embodiments of the present application.

Claims

1. A bus monitoring and control method, applied to an integrated circuit device, characterized in that: The integrated circuit device is connected to a host, and the host, the integrated circuit device, and the slave are respectively connected to a switch module via a system power management interface SPMI bus, and the method includes: Monitoring the communication data between the host and the slave in the SPMI bus; If it is determined according to the communication data that the working state of the integrated circuit device is the first working state, sending the preset retransmission data to the slave; Wherein, sending the preset resending data to the slave device comprises: If it is monitored that the SPMI bus is in an idle state, the host simulates the slave to perform bus arbitration, and the slave simulates the host to perform bus arbitration; Controlling the switch module to switch so that the integrated circuit device is connected to the host and the slave respectively; When it is determined that the host preempts the SPMI bus with the highest priority, the retransmitted data is sent to the slave.

2. The bus monitoring and control method according to claim 1, characterized in that: The method further comprises: If it is determined according to the communication data that the working state of the integrated circuit device is the second working state, the switch module is controlled to switch so that the host is connected to the slave.

3. The bus monitoring and control method according to claim 1 or 2, characterized in that: Determining the working state of the integrated circuit device according to the communication data comprises: If it is determined that the communication data includes a preset instruction, determining that the working state of the integrated circuit device is the first working state; or If it is determined that the communication data does not include a preset instruction, the working state of the integrated circuit device is determined to be the second working state.

4. The bus monitoring and control method according to claim 1, characterized in that: The step of simulating the slave to perform bus arbitration on the host and simulating the host to perform bus arbitration on the slave comprises: By pulling up a data signal line of an SPMI bus connected to an upper port of the integrated circuit device, simulating the slave to perform bus arbitration on the host, wherein the upper port is connected to the host through the SPMI bus; The slave simulates the host to perform bus arbitration by pulling up a data signal line of the SPMI bus connected to the lower port of the integrated circuit device, wherein the lower port is connected to the slave through the SPMI bus.

5. The bus monitoring and control method according to claim 1, characterized in that: When it is determined that the host preempts the SPMI bus with the highest priority, sending the retransmitted data to the slave comprises: The reissued data value is written into the slave device through an external register write instruction.

6. The bus monitoring and control method according to claim 1, characterized in that: After the host simulates the slave to perform bus arbitration, the method further includes: If the slave performs bus arbitration in the SPMI bus instruction cycle and the slave performs the bus arbitration in the highest priority During the SPMI bus preemption phase, a preset slave address is sent to the host.

7. The bus monitoring and control method according to claim 6, characterized in that: After sending the preset slave address to the host, the method further includes: If the SPMI bus instruction cycle of the slave performing bus arbitration reaches the frame sequence stage, the preset data is written to the host with the preset host address.

8. The bus monitoring and control method according to claim 7, characterized in that: Writing preset data to a host having a preset host address comprises: The preset data is written into the register of the host having the preset host address through the master write instruction.

9. The bus monitoring and control method according to claim 1, characterized in that: The reissued data is data determined according to the type of the slave.

10. An electronic device, characterized in that: The electronic device comprises a memory and a processor: The memory is used to store program instructions; The processor is used to read and execute the program instructions stored in the memory. When the program instructions are executed by the processor, the electronic device executes the bus monitoring and control method as described in any one of claims 1 to 9.

11. A chip, characterized in that: It includes a processor and a memory; wherein the processor is connected to the memory; The memory is used to store program instructions; The processor is used to read the program instructions stored in the memory to implement the bus monitoring and control method according to any one of claims 1 to 9.

12. A computer storage medium, characterized in that: The computer storage medium stores program instructions, and when the program instructions are executed on an electronic device, the electronic device executes the bus monitoring and control method according to any one of claims 1 to 9.

13. The bus monitoring and control method according to claim 2, characterized in that: Determining the working state of the integrated circuit device according to the communication data comprises: If it is determined that the communication data includes a preset instruction, determining that the working state of the integrated circuit device is the first working state; or If it is determined that the communication data does not include a preset instruction, the working state of the integrated circuit device is determined to be the second working state.

14. The bus monitoring and control method according to claim 1, characterized in that: The step of simulating the slave to perform bus arbitration on the host and simulating the host to perform bus arbitration on the slave comprises: By pulling up the data signal line of the SPMI bus connected to the upper port of the integrated circuit device, the host is simulated The slave performs bus arbitration, wherein the upper port is connected to the host through the SPMI bus, and a data signal line of the SPMI bus connected to the upper port of the integrated circuit device is pulled high to indicate that the data signal line of the SPMI bus connected to the upper port is set to a high potential; By pulling up the data signal line of the SPMI bus connected to the lower port of the integrated circuit device, the slave simulates the host to perform bus arbitration, wherein the lower port is connected to the slave through the SPMI bus, and pulling up the data signal line of the SPMI bus connected to the lower port of the integrated circuit device represents setting the data signal line of the SPMI bus connected to the lower port to a high potential.

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