Semiconductor device, display device, and method for manufacturing semiconductor device

Abstract

The present invention provides a highly integrated semiconductor device with minute transistors. The semiconductor device has two vertical transistors and an insulating layer. The insulating layer is provided with a line-shaped aperture formed by an exposure device, and the two vertical transistors are provided opposite each other, with the opposing sidewalls of the aperture oriented in the channel length direction. The two vertical transistors share one of either the source electrode or the drain electrode, above which the gate electrode and the other of either the source electrode or the drain electrode of each transistor are superimposed in different areas. Gate insulating layers of the two transistors are each provided in contact with the sidewalls of the aperture. A semiconductor layer is provided along the sidewalls and bottom of the aperture, with the gate insulating layers interposed. The semiconductor layer is shared by the two vertical transistors.

Description

Semiconductor device, display device, and method for manufacturing the semiconductor device

[0001] 1. An embodiment of the present invention relates to a transistor. 2. An embodiment of the present invention relates to a semiconductor device including a transistor. 3. An embodiment of the present invention relates to a display device including a transistor. 4. An embodiment of the present invention relates to a manufacturing method of a semiconductor device including a transistor.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, lighting devices, input devices, input / output devices, electronic devices including these devices, and driving methods or manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

[0003] One type of display device is a liquid crystal display device that uses liquid crystal elements as display elements. For example, active matrix liquid crystal display devices, in which pixel electrodes are arranged in a matrix and switching elements are connected to each pixel electrode, are used in a variety of devices such as smartphones, tablet terminals, monitors, televisions, and digital signage.

[0004] There are two types of LCD devices known, broadly classified as transmissive and reflective. The larger the effective display area ratio (also called aperture ratio) of a pixel in an LCD device, the brighter the display will be and the lower the power consumption will be. Therefore, there is a demand for improving the aperture ratio.

[0005] For example, an active matrix liquid crystal display device is known that uses transistors with metal oxides in their channel formation regions as switching elements connected to pixel electrodes. Patent Document 1 discloses a liquid crystal display device that employs transistors with metal oxides in their channel formation regions to increase the aperture ratio.

[0006] JP 2018-189938 A

[0007] In order to further increase the aperture ratio of a liquid crystal display device and achieve higher resolution, further miniaturization of a transistor used in a pixel circuit is required. Therefore, an object of one embodiment of the present invention is to provide a transistor that can be miniaturized, or to provide a transistor with favorable electrical characteristics, or to provide a transistor with a short channel length, or to provide a transistor that occupies a small area.

[0008] Another object of one embodiment of the present invention is to provide a small-sized semiconductor device including miniaturized transistors, or to provide a highly integrated semiconductor device including miniaturized transistors.

[0009] Another object of one embodiment of the present invention is to provide a liquid crystal display device with a high aperture ratio, a high-resolution liquid crystal display device, a liquid crystal display device with low power consumption, a liquid crystal display device that can be driven at high speed, or a display device with high display quality.

[0010] Another object of one embodiment of the present invention is to provide a transistor, a semiconductor device, a display device, an electronic device, and a manufacturing method thereof, each having a novel structure.Another object of one embodiment of the present invention is to provide a highly reliable transistor, a semiconductor device, a display device, an electronic device, and a manufacturing method thereof.An object of one embodiment of the present invention is to alleviate at least one of the problems of the prior art.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description in the specification, drawings, claims, etc.

[0012] One embodiment of the present invention provides a transistor including a first transistor, a second transistor, a first insulating layer, and a second insulating layer. The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a third insulating layer, a fourth insulating layer, and a semiconductor layer. The second transistor includes a first conductive layer, a fifth conductive layer, a sixth conductive layer, a fourth conductive layer, a fifth insulating layer, a fourth insulating layer, and a semiconductor layer. The first insulating layer includes a first region and a second region separated from the first region. the first conductive layer has a fifth region and a sixth region spaced apart from the third region, the first region, the second conductive layer, the third region, and the third conductive layer are provided on the fifth region in a superimposed manner in this order, the second region, the fifth conductive layer, the fourth region, and the sixth conductive layer are provided on the sixth region in a superimposed manner in this order, and the third insulating layer is provided in contact with a side surface of the first region, a side surface of the second conductive layer, a side surface of the third region, and a side surface of the third conductive layer; The fifth insulating layer is provided in contact with a side surface of the second region, a side surface of the fifth conductive layer, a side surface of the fourth region, and a side surface of the sixth conductive layer; the semiconductor layer is provided in contact with an upper surface of the first conductive layer between the fifth region and the sixth region, a side surface of the third insulating layer, a side surface of the fifth insulating layer, an upper surface of the third conductive layer, and an upper surface of the sixth conductive layer; the fourth insulating layer is provided in contact with an upper surface and a side surface of the semiconductor layer, an upper surface and a side surface of the first conductive layer, an upper surface and a side surface of the third conductive layer, and an upper surface and a side surface of the sixth conductive layer; The layer is provided in contact with an upper surface of the fourth insulating layer, and in the first transistor, one surface of the part of the semiconductor layer faces a part of the fourth conductive layer via a part of the fourth insulating layer, and the other surface of the part of the semiconductor layer faces the second conductive layer via a third insulating layer. In the second transistor, one surface of the other part of the semiconductor layer faces the other part of the fourth conductive layer via a part of the fourth insulating layer, and the other surface of the other part of the semiconductor layer faces the fifth conductive layer via a fifth insulating layer.

[0013] In the above, it is preferable that the semiconductor layer contains a metal oxide, and the first insulating layer, the second insulating layer, the third insulating layer, and the fifth insulating layer each contain one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide.

[0014] Furthermore, in the above, it is preferable that the first insulating layer has a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer, the second insulating layer has a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer, and that the sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer each have one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide, and that the seventh insulating layer and the tenth insulating layer each have one or both of silicon oxide and silicon oxynitride.

[0015] Another embodiment of the present invention is a display device including the above semiconductor device, a first liquid crystal element, and a second liquid crystal element. The first liquid crystal element includes a third conductive layer, a liquid crystal, and a seventh conductive layer. The second liquid crystal element includes a sixth conductive layer, a liquid crystal, and the seventh conductive layer. The liquid crystal is provided over the third conductive layer or the sixth conductive layer, and the seventh conductive layer is provided over the liquid crystal.

[0016] Another embodiment of the present invention includes a first transistor, a second transistor, a first insulating layer, and a second insulating layer. The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a third insulating layer, a fourth insulating layer, and a semiconductor layer. The second transistor includes a first conductive layer, a fourth conductive layer, a third conductive layer, a fifth insulating layer, a fourth insulating layer, and a semiconductor layer. The first insulating layer includes a first region and a second region separated from the first region. the second insulating layer has a third region and a fourth region spaced apart from the third region; the first conductive layer has a fifth region and a sixth region spaced apart from the fifth region; the first region, the second conductive layer, and the third region are provided on the fifth region in a superimposed manner in this order; the second region, the fourth conductive layer, and the fourth region are provided on the sixth region in a superimposed manner in this order; and the third insulating layer has a side surface of the first region, a side surface of the second conductive layer, and a side surface of the third region. the fifth insulating layer is provided in contact with a side surface of the second region, a side surface of the fourth conductive layer, and a side surface of the fourth region; the semiconductor layer is provided in contact with a top surface of the first conductive layer, a side surface of the third insulating layer, a side surface of the fifth insulating layer, a top surface of a portion of the second insulating layer, and a top surface of another portion of the second insulating layer between the fifth region and the sixth region; the fourth insulating layer is provided in contact with a top surface of the semiconductor layer; and the third conductive layer is provided in contact with a top surface of the fourth insulating layer; in the first transistor, one surface of the portion of the semiconductor layer faces a portion of the third conductive layer via a portion of the fourth insulating layer, and the other surface of the portion of the semiconductor layer faces the second conductive layer via the third insulating layer; and in the second transistor, one surface of the other portion of the semiconductor layer faces the other portion of the third conductive layer via the other portion of the fourth insulating layer, and the other surface of the other portion of the semiconductor layer faces the fourth conductive layer via the fifth insulating layer.

[0017] In the above, it is preferable that the semiconductor layer contains a metal oxide, and the first insulating layer, the second insulating layer, the third insulating layer, and the fifth insulating layer each contain one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide.

[0018] Furthermore, in the above, it is preferable that the first insulating layer has a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer, the second insulating layer has a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer, and that the sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer each have one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide, and that the seventh insulating layer and the tenth insulating layer each have one or both of silicon oxide and silicon oxynitride.

[0019] Another embodiment of the present invention is a display device including the above semiconductor device and a liquid crystal element, in which the liquid crystal element includes a semiconductor layer, a liquid crystal, and a fifth conductive layer, in which the liquid crystal is provided over the semiconductor layer and the fifth conductive layer is provided over the liquid crystal.

[0020] Another embodiment of the present invention is a method for forming a first conductive layer, forming a first insulating film and a first conductive film in this order over the first conductive layer, processing the first conductive film to form a second conductive layer in a region overlapping with the first conductive layer, forming a second insulating film and a second conductive film in this order over the first insulating film and the second conductive layer, processing the second conductive film to form a third conductive layer having a region overlapping with the first conductive layer and the second conductive layer, and forming a third conductive layer including the first insulating film, the second conductive layer, the second insulating film, and the third conductive layer. A portion of each conductive layer is removed to form an opening reaching the first conductive layer, and a first insulating layer is formed from the first insulating film, a fourth conductive layer and a fifth conductive layer are formed from the second conductive layer, a second insulating layer is formed from the second insulating film, and a sixth conductive layer and a seventh conductive layer are formed from the third conductive layer, and a top surface and side surfaces of the first conductive layer in the opening, a side surface of the first insulating layer in the opening, a side surface of the second insulating layer in the opening, a side surface of the fourth conductive layer in the opening, and a top surface and side surfaces of the first conductive layer in the opening a third insulating film in contact with a side surface of the fifth conductive layer in the opening, a side surface of the sixth conductive layer in the opening, a side surface of the seventh conductive layer in the opening, a top surface of the sixth conductive layer, and a top surface of the seventh conductive layer; a part of the third insulating film is removed; a third insulating layer in contact with one side surface of the first insulating layer in the opening, a side surface of the fourth conductive layer in the opening, one side surface of the second insulating layer in the opening, and a side surface of the sixth conductive layer in the opening; and a fourth insulating layer in contact with the other side surface of the first insulating layer in the opening, the side surface of the fifth conductive layer in the opening, the other side surface of the second insulating layer in the opening, and a side surface of the seventh conductive layer in the opening; and a semiconductor layer in contact with the top surface and side surface of the first conductive layer in the opening, the side surface of the third insulating layer in the opening, the side surface of the fourth insulating layer in the opening, the top surface and side surface of the sixth conductive layer, the top surface and side surface of the seventh conductive layer, and the top surface of the second insulating layer.

[0021] According to one embodiment of the present invention, a transistor that can be miniaturized, a transistor with favorable electrical characteristics, a transistor with a short channel length, or a transistor with a small occupation area can be provided.

[0022] According to one embodiment of the present invention, a small-sized semiconductor device including a miniaturized transistor or a highly integrated semiconductor device including a miniaturized transistor can be provided.

[0023] According to one embodiment of the present invention, a liquid crystal display device with a high aperture ratio, a high-resolution liquid crystal display device, a liquid crystal display device with low power consumption, a liquid crystal display device capable of high-speed operation, or a display device with high display quality can be provided.

[0024] According to one embodiment of the present invention, a transistor, a semiconductor device, a display device, an electronic device, and a manufacturing method thereof each having a novel structure can be provided. According to one embodiment of the present invention, a highly reliable transistor, a semiconductor device, a display device, an electronic device, and a manufacturing method thereof can be provided. According to one embodiment of the present invention, at least one of the problems of the prior art can be alleviated.

[0025] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0026] FIG. 1A is a plan view illustrating an example of a semiconductor device. FIG. 1B is a cross-sectional view illustrating an example of a semiconductor device. FIGS. 2A and 2B are cross-sectional views illustrating an example of a semiconductor device. FIG. 2C is a circuit diagram illustrating a semiconductor device. FIGS. 3A and 3B are plan views illustrating an example of a semiconductor device. FIGS. 4A and 4B are plan views illustrating an example of a semiconductor device. FIGS. 5A and 5B are cross-sectional views illustrating an example of a semiconductor device. FIGS. 6A and 6B are cross-sectional views illustrating an example of a semiconductor device. FIGS. 7A and 7B are cross-sectional views illustrating an example of a semiconductor device. FIGS. 8A and 8B are cross-sectional views illustrating an example of a semiconductor device. FIG. 9A is a plan view illustrating an example of a display device. FIG. 9B is a cross-sectional view illustrating an example of a display device. FIG. 10A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 10B to 10D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 11A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 11B to 11D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 12A is a plan view illustrating an example of a method for manufacturing a semiconductor device. 12B to 12D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 13A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 13B to 13D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 14A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 14B to 14D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 15A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 15B to 15D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 16A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 16B to 16D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 17A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 17B to 17D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 18A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 18B to 18D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 19 shows a structural example of a display device. FIG. 20 shows a structural example of a display device. Fig. 21A is a block diagram of a display device, and Fig. 21B and Fig. 21C are circuit diagrams of the display device.Figures 22A, 22C, and 22D are circuit diagrams of a display device. Figure 22B is a timing chart. Figure 23 is a block diagram of a touch panel module. Figures 24A to 24C are configuration examples of a touch panel module. Figures 25A to 25F are configuration examples of an electronic device.

[0027] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0028] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0029] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0030] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0031] In addition, in this specification, "connection" includes "electrical connection."

[0032] "A and B are electrically connected" means that, among the cases where A and B are connected without an insulator (where A and B are connected via a conductor or semiconductor, or where A and B are in contact), there is a time when exchange of electrical signals or interaction of potentials occurs between A and B during circuit operation. In other words, even if there is a time when exchange of electrical signals or interaction of potentials does not occur between A and B during circuit operation, it can be said that "A and B are electrically connected" as long as there is a time when exchange of electrical signals or interaction of potentials occurs between A and B.

[0033] An "electrical connection" includes a connection (direct connection) that does not involve a circuit element (for example, a transistor, but excluding wiring), and a connection (indirect connection) that involves one or more circuit elements.

[0034] Examples of "A and B being electrically connected" include when A and B are connected without a circuit element, or when A and B are connected via the source and drain of one or more transistors. However, this is premised on the fact that there is a timing when an electrical signal is exchanged or an interaction of potential occurs between A and B.

[0035] An example in which it cannot be said that "A and B are electrically connected" because A and B are connected via an insulator is when a dielectric of a capacitive element, a gate insulating film of a transistor, etc. is interposed between A and B.

[0036] Examples of cases where A and B are connected without an insulator between them, but there is no timing at which an electrical signal is exchanged or there is no potential interaction between A and B, and therefore it cannot be said that "A and B are electrically connected" include a case where a potential V is supplied to the path from A to B from a power supply, signal source, etc. (however, this does not include a case where the potential V is supplied via a circuit element), or a case where A and C are connected via the source and drain of a transistor TrP and B and C are connected via the source and drain of a transistor TrQ, but there is no timing at which both the transistor TrP and the transistor TrQ are turned on simultaneously.

[0037] In this specification, the phrase "top surface shapes generally match" refers to the overlap of at least a portion of the contours between stacked layers. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" may also be used.

[0038] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. The plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0039] In the following description, expressions indicating directions such as "upper" and "lower" are basically used in accordance with the directions in the drawings. However, for purposes such as facilitating explanation, the directions indicated by "upper" or "lower" in the specification may not match those in the drawings. For example, when describing the stacking order (or formation order) of a laminate, etc., even if the surface on which the laminate is provided (such as a surface to be formed, a support surface, an adhesive surface, or a flat surface) is located above the laminate in the drawings, the surface to be formed may be expressed as being below, and the laminate may be expressed as being above.

[0040] Furthermore, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the terms "conductive layer" and "insulating layer" may be interchangeable with the terms "conductive film" and "insulating film."

[0041] In this specification and the like, a display panel, which is one aspect of a display device, has a function of displaying (outputting) an image or the like on a display surface, and therefore the display panel is one aspect of an output device.

[0042] Furthermore, in this specification and the like, a display panel having a connector such as an FPC (Flexible Printed Circuit) or a TCP (Tape Carrier Package) attached to the substrate, or a substrate having an IC mounted on it using a COG (Chip On Glass) method or the like, may be referred to as a display panel module, a display module, or simply a display panel.

[0043] In this specification and the like, a touch panel, which is one aspect of a display device, has a function of displaying an image or the like on a display surface and a function as a touch sensor that detects that a detectable object such as a finger or a stylus touches, presses, or approaches the display surface. Thus, the touch panel is one aspect of an input / output device.

[0044] A touch panel can also be called, for example, a display panel (or display device) with a touch sensor or a display panel (or display device) with a touch sensor function. A touch panel can have a configuration including a display panel and a touch sensor panel. Alternatively, the touch panel can have a touch sensor function inside or on the surface of the display panel.

[0045] In addition, in this specification and the like, a touch panel substrate on which a connector or an IC is mounted may be referred to as a touch panel module, a display module, or simply a touch panel.

[0046] Embodiment 1 In this embodiment, a transistor of one embodiment of the present invention, a semiconductor device including the transistor, a display device to which the transistor is applied, a manufacturing method of the semiconductor device including the transistor, and the like will be described.

[0047] A semiconductor device according to one embodiment of the present invention includes a first transistor, a second transistor, a first insulating layer, and a second insulating layer.

[0048] The first transistor and the second transistor are vertical transistors in which a source electrode and a drain electrode are provided overlapping each other at different heights relative to the substrate surface, and a drain current flows in a direction substantially perpendicular to the substrate surface.

[0049] The gate electrode of the first transistor (first gate electrode) and the gate electrode of the second transistor (first gate electrode) overlap with and are provided between the source electrode and the drain electrode, respectively. That is, the first transistor and the second transistor each have a structure in which one of the source electrode or the drain electrode, the gate electrode, and the other of the source electrode or the drain electrode are provided overlapping in this order.

[0050] A first insulating layer is provided between the gate electrode and one of the source electrode or the drain electrode of each of the first transistor and the second transistor, and a second insulating layer is provided between the gate electrode and the other of the source electrode or the drain electrode.

[0051] The first transistor and the second transistor share a conductive layer that serves as one of a source electrode and a drain electrode. Other components of the first transistor (such as a gate electrode and the other of the source electrode and drain electrode) are provided on a first region of the conductive layer, and other components of the second transistor (such as a gate electrode and the other of the source electrode and drain electrode) are provided on a second region separated from the first region. The first insulating layer has a third region overlapping with the first region and a fourth region separated from the third region and overlapping with the second region. The second insulating layer has a fifth region overlapping with the first region and a sixth region separated from the fifth region and overlapping with the second region.

[0052] In a semiconductor device according to one embodiment of the present invention, a third region, a gate electrode of the first transistor, a fifth region, and the other of the source and drain electrodes of the first transistor are provided over a first region to overlap with each other, and a fourth region, a gate electrode of the second transistor, a sixth region, and the other of the source and drain electrodes of the second transistor are provided over a second region to overlap with each other. The first region functions as one of the source and drain electrodes of the first transistor, and the second region functions as one of the source and drain electrodes of the second transistor. The first transistor and the second transistor are opposed to each other with respect to an axis that is a midpoint between the first and second regions.

[0053] The third region, the gate electrode of the first transistor, the fifth region, and a side surface (first side surface) of the other of the source electrode or drain electrode of the first transistor on the first region, facing the second transistor, are generally aligned. Similarly, the fourth region, the gate electrode of the second transistor, the sixth region, and a side surface (second side surface) of the other of the source electrode or drain electrode of the second transistor on the second region, facing the first transistor, are generally aligned.

[0054] The gate insulating layer (first gate insulating layer) of the first transistor is provided in contact with the first side surface. The gate insulating layer (first gate insulating layer) of the second transistor is provided in contact with the second side surface. Note that the gate insulating layer of the first transistor and the gate insulating layer of the second transistor may be a single continuous film.

[0055] The first transistor and the second transistor share a semiconductor layer having their respective channel formation regions. The semiconductor layer is provided so as to cover a conductive layer that serves as one of a source electrode or a drain electrode of each transistor, a gate insulating layer of each transistor, and the other of the source electrode or the drain electrode of each transistor. The semiconductor layer is in contact with a top surface of the conductive layer that serves as one of the source electrode or the drain electrode of each transistor (the top surface in a region between the first region and the second region), a side surface of the gate insulating layer of each transistor, and a top surface of the other of the source electrode or the drain electrode of each transistor.

[0056] The semiconductor layer has a region facing the gate electrode of the first transistor with the gate insulating layer of the first transistor interposed therebetween and a region facing the gate electrode of the second transistor with the gate insulating layer of the second transistor interposed therebetween. The former functions as a channel formation region of the first transistor, and the latter functions as a channel formation region of the second transistor. In addition, in the semiconductor layer, the region in contact with the source electrode or drain electrode of the first transistor functions as the source region and drain region of the first transistor, and the region in contact with the source electrode or drain electrode of the second transistor functions as the source region and drain region of the second transistor.

[0057] That is, the first transistor and the second transistor have a structure in which the source electrode and the drain electrode are provided at different heights relative to the substrate surface, and a drain current flows vertically (in a direction substantially perpendicular to the substrate surface) through a channel formation region located between the electrodes. Therefore, the area occupied by the transistor in the substrate surface can be reduced compared to, for example, a planar transistor.

[0058] The first transistor and the second transistor may each have a back-gate insulating layer (second gate insulating layer) and a back gate electrode (second gate electrode). The insulating layer that becomes the back-gate insulating layer and the conductive layer that becomes the back gate electrode are provided in this order to cover the semiconductor layer. The insulating layer that becomes the back-gate insulating layer has a region that contacts the top surface and side surface of the semiconductor layer and the top surface of the other of the source electrode or drain electrode of each transistor. Of the region of the insulating layer that overlaps with the semiconductor layer, a portion located on the first side surface functions as the back-gate insulating layer of the first transistor, and a portion located on the second side surface functions as the back-gate insulating layer of the second transistor. Furthermore, the conductive layer that becomes the back gate electrode contacts the top surface of the insulating layer that becomes the back-gate insulating layer. Of the region of the conductive layer that overlaps with the semiconductor layer, a portion located on the first side surface functions as the back gate electrode of the first transistor, and a portion located on the second side surface functions as the back gate electrode of the second transistor.

[0059] When the first transistor and the second transistor have two gate electrodes, the potential of the back gate electrode can be set to ground potential or any other potential, thereby fixing the potential of the region of the semiconductor layer on the back gate electrode side. Therefore, the threshold voltage of the transistor can be made normally off, compared to a structure having only one gate electrode. Furthermore, variation in the electrical characteristics of the transistor can be suppressed.

[0060] As described above, the semiconductor device of one embodiment of the present invention includes two vertical transistors (a first transistor and a second transistor), each of which has a common component (a source electrode or a drain electrode, a semiconductor layer) sandwiched between other components (a gate electrode, the other of the source electrode or the drain electrode, and a gate insulating layer) facing each other. Therefore, by narrowing the gap between the two opposing vertical transistors, high integration of the transistors within a substrate can be achieved. Furthermore, in the semiconductor device of one embodiment of the present invention, the two opposing transistors share a conductive layer serving as one of the source electrode or the drain electrode. This allows the semiconductor device to be smaller overall than when each transistor individually has the conductive layer. For example, consider a case where a line-shaped opening is formed in a layer stacked on a conductive layer (e.g., three layers: an insulating layer, a conductive layer, and an insulating layer) using a conventional exposure apparatus (minimum line width: approximately 1.5 μm or 1.25 μm) for mass production of flat panel displays, and a vertical transistor is formed using the sidewall depth direction of the opening as the channel length direction. In this case, when two transistors each having separate components are formed, two openings must be formed in the layer stacked on the conductive layer that serves as one of the source and drain electrodes of the two transistors. In contrast, in a semiconductor device according to one embodiment of the present invention, when two transistors share a conductive layer that serves as one of the source and drain electrodes, two vertical transistors can be formed with a channel length direction aligned along the depth direction of opposing sidewalls of the opening simply by forming one opening in the layer stacked on the conductive layer. Therefore, the distance between the two vertical transistors can be made extremely narrow. For example, a display device can achieve a resolution of 2000 ppi or higher by using a semiconductor device including the two vertical transistors.

[0061] Below, a more specific structural example of a semiconductor device of one embodiment of the present invention will be described with reference to the drawings.

[0062] <Configuration Example 1 of Semiconductor Device> Fig. 1A shows a plan view (also referred to as a top view) of a semiconductor device 100. Fig. 1B shows a cross-sectional view taken along dashed dotted line A1-A2 shown in Fig. 1A. Fig. 2A shows a cross-sectional view taken along dashed dotted line B1-B2 shown in Fig. 1A. Fig. 2B shows a cross-sectional view taken along dashed dotted line C1-C2 shown in Fig. 1A. Fig. 2C shows an equivalent circuit diagram of the semiconductor device 100. Note that some of the components of the semiconductor device 100 (insulating layers, etc.) are omitted in Fig. 1A. As with Fig. 1A, some of the components may be omitted in plan views of semiconductor devices in the following drawings.

[0063] The semiconductor device 100 includes a transistor 10_1, a transistor 10_2, an insulating layer 110a, and an insulating layer 110b. The semiconductor device 100 is provided over a substrate 102. The transistors 10_1 and 10_2 share some components and are provided opposite each other on the substrate 102. The transistors 10_1 and 10_2 can be said to have the same structure. The transistors 10_1 and 10_2 can be formed simultaneously using the same material and through the same process.

[0064] The transistor 10_1 includes a conductive layer 112a, a conductive layer 112b1, a conductive layer 116_1, an insulating layer 110s1, a semiconductor layer 108, an insulating layer 106, and a conductive layer 104. In the transistor 10_1, a part of the conductive layer 112a functions as one of a source electrode and a drain electrode. The conductive layer 112b1 functions as the other of the source electrode and the drain electrode. The conductive layer 116_1 functions as a gate electrode (first gate electrode). The insulating layer 110s1 functions as a gate insulating layer (first gate insulating layer). A part of the semiconductor layer 108 functions as a channel formation region. A part of the insulating layer 106 functions as a back-gate insulating layer (second gate insulating layer). A part of the conductive layer 104 functions as a back-gate electrode (second gate electrode).

[0065] The transistor 10_2 includes a conductive layer 112a, a conductive layer 112b2, a conductive layer 116_2, an insulating layer 110s2, a semiconductor layer 108, an insulating layer 106, and a conductive layer 104. In the transistor 10_2, another part of the conductive layer 112a functions as one of a source electrode and a drain electrode. The conductive layer 112b2 functions as the other of the source electrode and the drain electrode. The conductive layer 116_2 functions as a gate electrode (first gate electrode). The insulating layer 110s2 functions as a gate insulating layer (first gate insulating layer). Another part of the semiconductor layer 108 functions as a channel formation region. Another part of the insulating layer 106 functions as a back-gate insulating layer (second gate insulating layer). Another part of the conductive layer 104 functions as a back-gate electrode (second gate electrode).

[0066] Each of the layers constituting the transistor 10_1 and the transistor 10_2 can have a single-layer structure or a stacked-layer structure.

[0067] The transistor 10_1 and the transistor 10_2 share, among their components, a conductive layer (conductive layer 112a) that functions as one of a source electrode or a drain electrode, a semiconductor layer (semiconductor layer 108) that has a channel formation region, an insulating layer (insulating layer 106) that functions as a back-gate insulating layer, and a conductive layer (conductive layer 104) that functions as a back-gate electrode. The other components are provided separately for the transistor 10_1 and the transistor 10_2.

[0068] Note that the transistor 10_1 and the transistor 10_2 may have a structure without a back gate electrode and a back gate insulating layer.

[0069] An insulating layer 195 is provided to cover the transistor 10_1 and the transistor 10_2. The insulating layer 195 functions as a protective layer for the transistor 10_1 and the transistor 10_2.

[0070] The structures of the transistors 10_1 and 10_2 will be described. The conductive layer 112a is provided over the substrate 102. FIG. 3A is a plan view illustrating only the conductive layer 112a. The conductive layer 112a extends in a direction parallel to the dashed-dotted line A1-A2 in a plan view. A part of the conductive layer 112a protrudes toward the B1 side. In FIGS. 1A and 3A, the intersection of the dashed-dotted line A1-A2 and the dashed-dotted line B1-B2 is shown to be located at the center of the protrusion.

[0071] The protruding portions of the conductive layer 112a overlap with the channel formation regions of the transistors 10_1 and 10_2. That is, the conductive layers 112b1 and 112b2 are provided to overlap the protruding portions.

[0072] A portion of the insulating layer 110a is provided on the region on the A1 side of the protrusion, and another portion of the insulating layer 110a is provided on the region on the A2 side of the protrusion. The insulating layer 110a has a three-layer structure consisting of an insulating layer 110a1, an insulating layer 110a2 on the insulating layer 110a1, and an insulating layer 110a3 on the insulating layer 110a2. The insulating layer 110a has a region in contact with the upper surface and side surfaces of the conductive layer 112a and the upper surface of the substrate 102. It can also be said that the insulating layer 110a is provided so as to cover the upper surface and side surfaces of the conductive layer 112a.

[0073] A conductive layer 116_1 is provided over a portion of the insulating layer 110a, and a conductive layer 116_2 is provided over another portion of the insulating layer 110a. Figure 3B shows a plan view of the conductive layer 116_1 and the conductive layer 116_2 superimposed on the conductive layer 112a. The conductive layer 116_1 extends in a direction parallel to the dashed-dotted line B1-B2 and overlaps with a region of the conductive layer 112a on the A1 side of the protrusion. The conductive layer 116_1 has a region that overlaps with a portion of the conductive layer 112a with the insulating layer 110a interposed therebetween. The conductive layer 116_2 extends in a direction parallel to the dashed-dotted line B1-B2 and overlaps with a region of the conductive layer 112a on the A2 side of the protrusion. The conductive layer 116_2 has a region that overlaps with another portion of the conductive layer 112a with the insulating layer 110a interposed therebetween.

[0074] A part of the insulating layer 110b is provided over a part of the insulating layer 110a and the conductive layer 116_1, and another part of the insulating layer 110b is provided over another part of the insulating layer 110a and the conductive layer 116_2. The insulating layer 110b has a three-layer structure including an insulating layer 110b3, an insulating layer 110b2 over the insulating layer 110b3, and an insulating layer 110b1 over the insulating layer 110b2. A part of the insulating layer 110b has a region in contact with the top surface and side surfaces of the conductive layer 116_1 and the top surface of a part of the insulating layer 110a. It can also be said that the part of the insulating layer 110b is provided so as to cover the top surface and side surfaces of the conductive layer 116_1. It can also be said that the conductive layer 116_1 is sandwiched between a part of the insulating layer 110a and a part of the insulating layer 110b. Similarly, another part of the insulating layer 110b has a region in contact with the top surface and side surfaces of the conductive layer 116_2 and the top surface of another part of the insulating layer 110a. It can also be said that the other part of the insulating layer 110b is provided so as to cover the top surface and side surfaces of the conductive layer 116_2. It can also be said that the conductive layer 116_2 is sandwiched between the other part of the insulating layer 110a and the other part of the insulating layer 110b.

[0075] In this specification and the like, the insulating layer 110a and the insulating layer 110b may be collectively referred to as the insulating layer 110.

[0076] A conductive layer 112b1 is provided on a part of the insulating layer 110b, and a conductive layer 112b2 is provided on another part of the insulating layer 110b. Fig. 4A shows a plan view in which the conductive layer 112b1 and the conductive layer 112b2 are superimposed on the plan view shown in Fig. 3B.

[0077] The conductive layer 112b1 extends toward the A1 side in a direction parallel to the dashed-dotted line A1-A2 direction and has a region overlapping with a part of the conductive layer 112a and the conductive layer 116_1. The end of the conductive layer 112b1 on the dashed-dotted line B1-B2 side roughly coincides with the end of the conductive layer 116_1 on the dashed-dotted line B1-B2 side. The conductive layer 112b1 has a region overlapping with the conductive layer 116_1 through a part of the insulating layer 110b. The conductive layer 112b1 also has a region overlapping with a part of the conductive layer 112a through a part of the insulating layer 110 and the conductive layer 116_1. It can also be said that the part of the insulating layer 110 and the conductive layer 116_1 have regions sandwiched between a part of the conductive layer 112a and the conductive layer 112b1. The side surfaces (hereinafter also referred to as first side surfaces) of part of the insulating layer 110, the conductive layer 116_1, and the conductive layer 112b1 on the dashed-dotted line B1-B2 side are generally aligned with each other.

[0078] The conductive layer 112b2 extends toward the A2 side in the direction parallel to the dashed-dotted line A1-A2 and has a region overlapping with another portion of the conductive layer 112a and the conductive layer 116_2. The end of the conductive layer 112b2 on the dashed-dotted line B1-B2 side roughly coincides with the end of the conductive layer 116_2 on the dashed-dotted line B1-B2 side. The conductive layer 112b2 has a region overlapping with the conductive layer 116_2 via another portion of the insulating layer 110b. The conductive layer 112b2 also has a region overlapping with another portion of the conductive layer 112a via another portion of the insulating layer 110 and the conductive layer 116_2. It can also be said that the other portion of the insulating layer 110 and the conductive layer 116_2 have regions sandwiched between the other portion of the conductive layer 112a and the conductive layer 112b2. The side surfaces (hereinafter also referred to as second side surfaces) of the other part of the insulating layer 110, the conductive layer 116_2, and the conductive layer 112b2 on the dashed dotted line B1-B2 side are generally aligned.

[0079] Here, the conductive layer 112b1 is preferably disposed relative to the conductive layer 112a so as to overlap only the protruding portion thereof. That is, the conductive layer 112b1 preferably does not overlap with regions other than the protruding portion (regions extending in the direction of the dashed dotted line A1-A2 of the conductive layer 112a). Because the insulating layer 110 is provided between the conductive layer 112a and the conductive layer 112b1, the region sandwiched between the conductive layer 112a and the conductive layer 112b1 can function as parasitic capacitance of the semiconductor device 100. Therefore, it is preferable that the area of ​​this region be as small as possible. By configuring the conductive layer 112b1 so as to overlap only the protruding portion of the conductive layer 112a, the aforementioned parasitic capacitance can be reduced. The same applies to the arrangement of the conductive layer 112b2 relative to the conductive layer 112a.

[0080] Note that the first side surface and the second side surface can also be said to correspond to the side walls of the opening 143 provided to reach the conductive layer 112a with respect to the insulating layer 110, the conductive layer that becomes the conductive layer 116_1 and the conductive layer 116_2, and the conductive layer that becomes the conductive layer 112b1 and the conductive layer 112b2, as shown in FIG. 1B.

[0081] The insulating layer 110s1 is provided in contact with the first side surface. The insulating layer 110s1 has a region in contact with a portion of the side surface of the insulating layer 110, the side surface of the conductive layer 116_1, and the side surface of the conductive layer 112b1. The insulating layer 110s2 is provided in contact with the second side surface. The insulating layer 110s2 has a region in contact with another portion of the side surface of the insulating layer 110, the side surface of the conductive layer 116_2, and the side surface of the conductive layer 112b2. In a cross-sectional view ( FIG. 1B ), the upper ends of the insulating layer 110s1 and the insulating layer 110s2 have a curved shape. The insulating layer 110s1 and the insulating layer 110s2 may be referred to as a sidewall, a sidewall insulating layer, a sidewall protective layer, or the like. In some cases, the insulating layer 110s1 and the insulating layer 110s2 can be considered as a single insulating layer.

[0082] The semiconductor layer 108 is provided to cover the opening 143 with the insulating layers 110s1 and 110s2 interposed therebetween. FIG. 4B shows a plan view in which the semiconductor layer 108 is superimposed on the plan view shown in FIG. 4A . A portion of the semiconductor layer 108 overlaps with a portion of the conductive layer 112a, the conductive layer 116_1, and the conductive layer 112b1, and another portion of the semiconductor layer 108 overlaps with another portion of the conductive layer 112a, the conductive layer 116_2, and the conductive layer 112b2. Furthermore, within the opening 143, the semiconductor layer 108 has regions in contact with the top surface of the conductive layer 112a, the side surface of the insulating layer 110s1, the curved portion of the insulating layer 110s1, the side surface of the insulating layer 110s2, and the curved portion of the insulating layer 110s2. Outside the opening 143, the semiconductor layer 108 has regions in contact with the top surface of the conductive layer 112b1 and the top surface of the conductive layer 112b2. The semiconductor layer 108 has a shape that follows the shapes of the upper surface of the conductive layer 112b1, the curved portion of the insulating layer 110s1, the side surface of the insulating layer 110s1, the upper surface of the conductive layer 112a, the side surface of the insulating layer 110s2, the curved portion of the insulating layer 110s2, and the upper surface of the conductive layer 112b2.

[0083] A part of the semiconductor layer 108 overlaps with a part of the conductive layer 112a through the conductive layer 112b1, the conductive layer 116_1, and parts of the insulating layer 110. It can also be said that the part of the semiconductor layer 108 faces, in the opening 143, side surfaces of part of the insulating layer 110, the side surfaces of the conductive layer 116_1, and the side surfaces of the conductive layer 112b1, with the insulating layer 110s1 interposed therebetween. Another part of the semiconductor layer 108 overlaps with another part of the conductive layer 112a through the conductive layer 112b2, the conductive layer 116_2, and another part of the insulating layer 110. It can also be said that the other part of the semiconductor layer 108 faces, in the opening 143, side surfaces of the other part of the insulating layer 110, the side surfaces of the conductive layer 116_2, and the side surfaces of the conductive layer 112b2, with the insulating layer 110s2 interposed therebetween.

[0084] The semiconductor layer 108 has a region in contact with the conductive layer 112a, a region in contact with the conductive layer 112b1, and a region in contact with the conductive layer 112b2. The region of the semiconductor layer 108 in contact with the conductive layer 112a functions as one of the source region and the drain region of the transistor 10_1 and the transistor 10_2. The region of the semiconductor layer 108 in contact with the conductive layer 112b1 functions as the other of the source region and the drain region of the transistor 10_1. The region of the semiconductor layer 108 in contact with the conductive layer 112b2 functions as the other of the source region and the drain region of the transistor 10_2.

[0085] In the semiconductor device 100, the semiconductor layer having the channel formation region of the transistor 10_1 and the semiconductor layer having the channel formation region of the transistor 10_2 share the same semiconductor layer (semiconductor layer 108). Furthermore, the conductive layer functioning as one of the source electrode and drain electrode of the transistor 10_1 and the conductive layer functioning as one of the source electrode and drain electrode of the transistor 10_2 share the same conductive layer (conductive layer 112a). Therefore, it can be said that one of the source region and drain region of the transistor 10_1 is connected to one of the source region and drain region of the transistor 10_2. In the semiconductor layer 108, the channel formation regions of the transistors 10_1 and 10_2 are provided between the source and drain regions of the transistors 10_1 and 10_2.

[0086] The insulating layer 106 is provided to cover the opening 143 with the insulating layer 110s1, the insulating layer 110s2, and the semiconductor layer 108 interposed therebetween. The insulating layer 106 has a region in contact with the top surface and side surfaces of the semiconductor layer 108, the top surface and side surfaces of the conductive layer 112b1, the top surface and side surfaces of the conductive layer 112b2, the top surface and side surfaces of the conductive layer 112a, the top surface of the insulating layer 110, and the top surface of the substrate 102. The insulating layer 106 has a shape that follows the shapes of the top surface and side surfaces of the semiconductor layer 108, the top surface and side surfaces of the conductive layer 112b1, the top surface and side surfaces of the conductive layer 112b2, the top surface and side surfaces of the conductive layer 112a, the top surface of the insulating layer 110, and the top surface of the substrate 102.

[0087] The conductive layer 104 is provided over the insulating layer 106 and has a region in contact with the top surface of the insulating layer 106. The conductive layer 104 has a region overlapping with the semiconductor layer 108 with the insulating layer 106 interposed therebetween. The conductive layer 104 also has a region facing the semiconductor layer 108 with the insulating layer 106 interposed therebetween in the opening 143. FIG. 1B and other figures show an example in which the conductive layer 104 has a shape that follows the shape of the top surface of the insulating layer 106. The conductive layer 104 may be provided so that a part of it is embedded in the opening 143.

[0088] In the transistors 10_1 and 10_2, the source and drain electrodes are located at different heights with respect to the surface of the substrate 102, which is a surface where the transistors are formed, and drain currents flow in a direction perpendicular to or approximately perpendicular to the surface of the substrate 102. It can also be said that the drain currents flow in the vertical direction or approximately vertically in the transistors 10_1 and 10_2. Therefore, the transistor of one embodiment of the present invention can be called a vertical transistor, a vertical channel transistor, or a vertical field effect transistor (VFET).

[0089] The channel length of the transistor 10_1 can be controlled by the thicknesses of the conductive layer 116_1 and the insulating layer 110 provided between the conductive layer 112a and the conductive layer 112b1. Similarly, the channel length of the transistor 10_2 can be controlled by the thicknesses of the conductive layer 116_2 and the insulating layer 110 provided between the conductive layer 112a and the conductive layer 112b2. Therefore, a transistor having a channel length smaller than the minimum dimension of an exposure apparatus used for manufacturing the transistor can be manufactured with high accuracy. This also reduces the characteristic variation among multiple transistors included in the semiconductor device. Therefore, the operation of the semiconductor device including the transistor can be stabilized and the reliability can be improved. Furthermore, the reduced characteristic variation among multiple transistors increases the degree of freedom in circuit design, and the operating voltage of the semiconductor device can be reduced. Therefore, the power consumption of the semiconductor device can be reduced.

[0090] In the transistor 10_1 and the transistor 10_2, the source electrode, the layer having the channel formation region, and the drain electrode can be provided in an overlapping manner, respectively, and therefore the occupied area can be significantly reduced compared to a so-called planar transistor in which the layer having the channel formation region is arranged in a planar shape.

[0091] The conductive layer 112a, the conductive layer 112b1, the conductive layer 112b2, the conductive layer 116_1, the conductive layer 116_2, and the conductive layer 104 can each function as a wiring, and the transistor 10_1 and the transistor 10_2 can be provided in a region where these wirings overlap. That is, in a circuit including the transistor 10_1, the transistor 10_2, and the wiring, the area occupied by the transistor 10_1, the transistor 10_2, and the wiring can be reduced. Therefore, the area occupied by the circuit can be reduced, and a small-sized semiconductor device can be obtained.

[0092] In the opening 143 of the transistor 10_1, one surface of a part of the semiconductor layer 108 faces a part of the conductive layer 104 with a part of the insulating layer 106 interposed therebetween, and the other surface of the part of the semiconductor layer 108 faces a part of the conductive layer 116_1 with the insulating layer 110s1 interposed therebetween. As described above, in the transistor 10_1, the part of the conductive layer 104 functions as a back gate electrode, and the conductive layer 116_1 functions as a gate electrode. Similarly, in the transistor 10_2, one surface of the other part of the semiconductor layer 108 faces a part of the conductive layer 104 with the other part of the insulating layer 106 interposed therebetween, and the other surface of the other part of the semiconductor layer 108 faces a conductive layer 116_2 with the insulating layer 110s2 interposed therebetween. As described above, in the transistor 10_2, the other part of the conductive layer 104 functions as a back gate electrode, and the conductive layer 116_2 functions as a gate electrode.

[0093] In the semiconductor device 100, the same conductive layer (conductive layer 104) is used for the conductive layer that functions as the back gate electrode of the transistor 10_1 and the conductive layer that functions as the back gate electrode of the transistor 10_2. As described above, the same conductive layer (conductive layer 112a) is used for the conductive layer that functions as one of the source electrode and drain electrode of the transistor 10_1 and the conductive layer that functions as one of the source electrode and drain electrode of the transistor 10_2. Therefore, as shown in FIG. 2C , the semiconductor device 100 can be said to include the transistors 10_1 and 10_2 in which one of the source electrode and drain electrode (conductive layer 112a) is connected to each other and the back gate electrodes (conductive layer 104) are also connected to each other.

[0094] The potential of the back gate electrode can be ground potential or any other potential. This allows the potential of the region of the semiconductor layer 108 facing the back gate electrode to be fixed, so that the threshold voltages of the transistors 10_1 and 10_2 can be normally-off. Furthermore, variation in the electrical characteristics of the transistors 10_1 and 10_2 can be suppressed.

[0095] Note that in the case where the potential of the back gate electrode is set to the ground potential or any potential, a common wiring may be provided to connect the back gate electrodes of the plurality of transistors 10_1 and 10_2, and the potential may be applied to the common wiring.

[0096] As described above, the transistors 10_1 and 10_2 can be transistors with extremely short channel lengths. Therefore, it can be said that these transistors are transistors in which defects such as a short-channel effect are likely to become apparent. The transistors 10_1 and 10_2 each have a backgate electrode, which makes it easier to control the threshold voltage than when the transistors 10_1 and 10_2 do not have a backgate electrode, thereby preventing the short-channel effect from becoming apparent.

[0097] Furthermore, by providing a back gate electrode, it may be possible to reduce variations in characteristics among a plurality of transistors included in the semiconductor device 100. For example, it may be possible to reduce variations in threshold voltage among a plurality of transistors.

[0098] When the semiconductor device 100 is applied to a display device such as a liquid crystal display device, the back gate electrodes of the transistors 10_1 and 10_2 can also function as, for example, capacitor electrodes, etc. In this case, since there is no need to separately form a capacitor electrode, the number of steps required for manufacturing the display device can be reduced.

[0099] Furthermore, in the semiconductor device 100, the transistors 10_1 and 10_2 are provided facing each other across an opening 143. Therefore, by narrowing the width of the opening 143 in the direction of the dashed dotted line A1-A2 in a plan view (corresponding to the width D143 shown in FIG. 1A ), the distance between the transistors 10_1 and 10_2 can be shortened. For example, using a conventional exposure apparatus (minimum line width: approximately 1.5 μm or 1.25 μm) for mass production of flat panel displays, the opening 143 having the minimum line width D143 of the exposure apparatus is formed in the layers stacked on the conductive layer 112a (specifically, the stacked structure of the insulating layer 110a, the conductive layers that become the conductive layers 116_1 and 116_2, and the insulating layer 110b). The transistors 10_1 and 10_2 having the above-described configuration are provided in the opening, thereby realizing an extremely small and highly integrated semiconductor device 100. By applying the semiconductor device 100 to a display device, for example, a resolution of 2000 ppi or more can be achieved.

[0100] The detailed structures of the transistor 10_1 and the transistor 10_2 will be described below.

[0101] The semiconductor material used for the semiconductor layer 108 is not particularly limited. For example, a semiconductor made of a single element or a compound semiconductor can be used. Examples of semiconductors made of a single element include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS: Oxide Semiconductor). Note that these semiconductor materials may contain impurities as dopants.

[0102] The crystallinity of the semiconductor material used for the semiconductor layer 108 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) can be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because deterioration of transistor characteristics can be suppressed.

[0103] Silicon can be used for the semiconductor layer 108. Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS). A transistor using amorphous silicon for a channel formation region can be formed on a large glass substrate and manufactured at low cost. A transistor using polycrystalline silicon for a channel formation region has high field-effect mobility and can operate at high speed. Furthermore, a transistor using microcrystalline silicon for a channel formation region has higher field-effect mobility and can operate at high speed than a transistor using amorphous silicon.

[0104] The semiconductor layer 108 preferably includes a metal oxide (also referred to as an oxide semiconductor) that exhibits semiconductor characteristics.

[0105] The band gap of the metal oxide used for the semiconductor layer 108 is preferably 2.0 eV or more, more preferably 2.5 eV or more.

[0106] The band gap of a metal oxide can be evaluated by optical evaluation using a spectrophotometer, spectroscopic ellipsometry, photoluminescence, X-ray photoelectron spectroscopy (XPS: X-ray photoelectron spectrometry or ESCA: Electron spectrometry for chemical analysis), or X-ray absorption fine structure (XAFS: X-ray absorption fine structure). Furthermore, a combination of these techniques can be used for analysis. The electron affinity or the bottom of the conduction band can be determined from the ionization potential, which is the difference in energy between the vacuum level and the top of the valence band, and the band gap. The ionization potential can be evaluated by, for example, ultraviolet photoelectron spectroscopy (UPS).

[0107] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has extremely high field-effect mobility compared to a transistor using amorphous silicon. Furthermore, an OS transistor has an extremely low off-state current and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device.

[0108] The insulating layer 110 can be an inorganic insulating layer, an organic insulating layer, or both. Examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin. The insulating layer 110 preferably includes one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxynitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride. Examples of nitride oxides include silicon nitride oxide and aluminum nitride oxide.

[0109] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0110] The insulating layer 110 preferably has a laminated structure. Figure 1B and other figures show an example in which the insulating layer 110 includes an insulating layer 110a1, an insulating layer 110a2 on the insulating layer 110a1, an insulating layer 110a3 on the insulating layer 110a2, an insulating layer 110b3 on the insulating layer 110a3, an insulating layer 110b2 on the insulating layer 110b3, and an insulating layer 110b1 on the insulating layer 110b2. These insulating layers may each be made of a material that can be used for the insulating layer 110.

[0111] The insulating layers 110a1, 110a2, 110a3, 110b1, 110b2, and 110b3 can be formed by, for example, sputtering or plasma-enhanced chemical vapor deposition (PECVD). It is preferable that the flow rate of a hydrogen-containing gas (e.g., hydrogen gas and ammonia gas) relative to the total deposition gas used in the formation of these layers is low, or that the partial pressure of the gas in the processing chamber of the deposition apparatus is low. This can reduce the amount of hydrogen contained in the insulating layers 110a1, 110a2, 110a3, 110b1, 110b2, and 110b3. Furthermore, by forming these layers by a method that does not use a hydrogen-containing gas, the amount of hydrogen contained in these layers can be significantly reduced. The insulating layers 110a1, 110a2, 110a3, 110b1, 110b2, and 110b3 can be formed by a sputtering method. By reducing the amount of hydrogen contained in the insulating layers 110a1, 110a2, 110a3, 110b1, 110b2, and 110b3, hydrogen can be prevented from being supplied to the channel formation region of the semiconductor layer 108, and the electrical characteristics of the transistors 10_1 and 10_2 can be stabilized.

[0112] The insulating layer 110s1 and the insulating layer 110s2 have regions in contact with the semiconductor layer 108. In the semiconductor layer 108, the region in contact with the insulating layer 110s1 can function as a channel formation region of the transistor 10_1, and the region in contact with the insulating layer 110s2 can function as a channel formation region of the transistor 10_2. Therefore, when a metal oxide is used for the semiconductor layer 108, the insulating layer 110s1 and the insulating layer 110s2 preferably contain oxygen. This can improve the interface characteristics between the semiconductor layer 108 and the insulating layer 110s1 and between the semiconductor layer 108 and the insulating layer 110s2. Furthermore, the insulating layer 110s1 and the insulating layer 110s2 are preferably films that release oxygen when heated. The insulating layer 110s1 and the insulating layer 110s2 release oxygen due to heat applied during the manufacturing process of the transistors 10_1 and 10_2, thereby supplying oxygen to the semiconductor layer 108. By supplying oxygen from the insulating layer 110s1 and the insulating layer 110s2 to the semiconductor layer 108, particularly to the channel formation region, oxygen vacancies (V Ｏ The oxygen vacancy (V) is repaired and the oxygen vacancy (V Ｏ ) can be reduced. Therefore, the transistors 10_1 and 10_2 can have favorable electrical characteristics and high reliability. For the insulating layers 110s1 and 110s2, for example, one or more of an oxide and an oxynitride that can be used for the insulating layer 110 can be preferably used. Specifically, the insulating layers 110s1 and 110s2 preferably contain silicon and oxygen, and one or both of silicon oxide and silicon oxynitride can be preferably used.

[0113] Of the insulating layers 110, the insulating layer 110a2 sandwiched between the insulating layers 110a1 and 110a3 and the insulating layer 110b2 sandwiched between the insulating layers 110b1 and 110b3 preferably contain oxygen. Furthermore, it is more preferable to use films that release oxygen when heated for the insulating layers 110a2 and 110b2. That is, it is preferable to use the same material for the insulating layers 110a2 and 110b2 as for the insulating layers 110s1 and 110s2. This allows oxygen contained in the insulating layers 110a2 and 110b2 to be supplied to the channel formation region of the semiconductor layer 108 through the insulating layer 110s1 or 110s2. Furthermore, both the oxygen contained in the insulating layer 110s1 or 110s2 and the oxygen contained in the insulating layer 110a2 and the insulating layer 110b2 can be supplied to the channel formation region of the semiconductor layer 108, which can further improve the reliability of the transistors 10_1 and 10_2.

[0114] For example, oxygen can be supplied to the insulating layer 110s1, the insulating layer 110s2, the insulating layer 110a2, or the insulating layer 110b2 by heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the insulating layer 110a2 or the insulating layer 110b2 by forming an oxide film on the top surface of the insulating layer 110a2 or the insulating layer 110b2 by a sputtering method in an oxygen-containing atmosphere. The oxide film may then be removed.

[0115] It is preferable that substances (e.g., atoms, molecules, and ions) diffuse easily in the insulating layer 110s1, the insulating layer 110s2, the insulating layer 110a2, and the insulating layer 110b2. It can also be said that it is preferable that the diffusion coefficient of substances in the insulating layer 110s1, the insulating layer 110s2, the insulating layer 110a2, and the insulating layer 110b2 is large. In particular, it is preferable that oxygen diffuses easily in the insulating layer 110s1, the insulating layer 110s2, the insulating layer 110a2, and the insulating layer 110b2. In other words, it is preferable that the diffusion coefficient of oxygen in the insulating layer 110s1, the insulating layer 110s2, the insulating layer 110a2, and the insulating layer 110b2 is large. The oxygen contained in the insulating layer 110s1 diffuses through the insulating layer 110s1 and is supplied to the semiconductor layer 108 via the interface between the insulating layer 110s1 and the semiconductor layer 108. Similarly, oxygen contained in the insulating layer 110s2 diffuses through the insulating layer 110s2 and is supplied to the semiconductor layer 108 via the interface between the insulating layer 110s2 and the semiconductor layer 108. Furthermore, oxygen contained in the insulating layer 110a2 diffuses through the insulating layer 110a2 and is supplied to the insulating layer 110s1 and the insulating layer 110s2, and is supplied to the semiconductor layer 108 via the interface between the insulating layer 110s1 and the semiconductor layer 108 and the interface between the insulating layer 110s2 and the semiconductor layer 108. Similarly, oxygen contained in the insulating layer 110b2 diffuses through the insulating layer 110b2 and is supplied to the insulating layer 110s1 and the insulating layer 110s2, and is supplied to the semiconductor layer 108 via the interface between the insulating layer 110s1 and the semiconductor layer 108 and the interface between the insulating layer 110s2 and the semiconductor layer 108. In this way, by forming the insulating layer 110s1, the insulating layer 110s2, the insulating layer 110a2, and the insulating layer 110b2 into which oxygen easily diffuses, the oxygen contained in the insulating layers can be efficiently supplied to the semiconductor layer 108 (particularly, the channel formation region).

[0116] A region of the semiconductor layer 108 in contact with the conductive layer 112a functions as one of the source and drain regions of the transistor 10_1 and the transistor 10_2, a region of the semiconductor layer 108 in contact with the conductive layer 112b1 functions as the other of the source and drain regions of the transistor 10_1, and a region of the semiconductor layer 108 in contact with the conductive layer 112b2 functions as the other of the source and drain regions of the transistor 10_2. The source and drain regions have lower electrical resistance than the channel formation region. The source and drain regions can also be referred to as regions with a higher carrier concentration and a higher oxygen defect density than the channel formation region.

[0117] Of the insulating layers 110, the insulating layer 110a1 is provided between the conductive layer 112a and the insulating layer 110a2. The insulating layer 110a3 is provided between the insulating layer 110a2 and the conductive layer 116_1 and between the insulating layer 110a2 and the conductive layer 116_2. The insulating layer 110b3 is provided between the conductive layer 116_1 and the insulating layer 110b2 and between the conductive layer 116_2 and the insulating layer 110b2. The insulating layer 110b1 is provided between the insulating layer 110b2 and the conductive layer 112b1 and between the insulating layer 110b2 and the conductive layer 112b2. It is preferable that the insulating layer 110a1, the insulating layer 110a3, the insulating layer 110b1, and the insulating layer 110b3 each release a small amount of impurities (e.g., hydrogen and water). Furthermore, the insulating layer 110a1, the insulating layer 110a3, the insulating layer 110b1, and the insulating layer 110b3 preferably have a high impermeability to substances. It can also be said that the insulating layer 110a1, the insulating layer 110a3, the insulating layer 110b1, and the insulating layer 110b3 function as barrier films. Specifically, the insulating layer 110a1, the insulating layer 110a3, the insulating layer 110b1, and the insulating layer 110b3 preferably have a high impermeability to impurities. This can prevent impurities contained in the insulating layer 110a1, the insulating layer 110a3, the insulating layer 110b1, and the insulating layer 110b3 from diffusing into the channel formation region of the semiconductor layer 108. Therefore, the transistors 10_1 and 10_2 can have favorable electrical characteristics and high reliability.

[0118] It is preferable that the insulating layers 110a1, 110a3, 110b1, and 110b3 are made of a material that is difficult for oxygen to permeate. This can prevent oxygen contained in the insulating layer 110a2 and oxygen contained in the insulating layer 110b2 from diffusing to the conductive layer 112a side through the insulating layer 110a1 and the insulating layer 110b3, respectively. Similarly, it can prevent oxygen contained in the insulating layer 110a2 and oxygen contained in the insulating layer 110b2 from diffusing to the conductive layer 112b1 side and the conductive layer 112b2 side through the insulating layer 110a3 and the insulating layer 110b1, respectively. This increases the amount of oxygen supplied from the insulating layer 110a2 and the insulating layer 110b2 to the channel formation region of the semiconductor layer 108, and reduces oxygen vacancies (V Ｏ ), and defects in which hydrogen enters oxygen vacancies (hereinafter referred to as V Ｏ H) can be reduced. Therefore, the transistors 10_1 and 10_2 can have favorable electrical characteristics and high reliability. Furthermore, the conductive layer 112a can be prevented from being oxidized by oxygen contained in the insulating layer 110a2 and oxygen contained in the insulating layer 110b2, which can prevent the electrical resistance of the conductive layer 112a from increasing. Similarly, the conductive layer 112b1 or the conductive layer 112b2 can be prevented from being oxidized by oxygen contained in the insulating layer 110a2 and oxygen contained in the insulating layer 110b2, which can prevent the electrical resistance of the conductive layer 112b1 or the conductive layer 112b2 from increasing. Therefore, the transistors 10_1 and 10_2 can have high on-state current.

[0119] In this specification and the like, a barrier film refers to a film having barrier properties. The barrier properties refer to one or both of a function of suppressing the diffusion of a target substance (also referred to as low permeability) and a function of capturing or fixing the substance (also referred to as gettering). For example, an insulating layer having barrier properties can be referred to as a barrier insulating layer.

[0120] The insulating layers 110a1, 110a3, 110b1, and 110b3, which function as barrier films, can each be made of, for example, one or more of an oxide containing one or both of aluminum and hafnium, an oxide containing magnesium, an oxide containing gallium, a nitride containing silicon, and a nitride oxide containing silicon. Specifically, the insulating layers 110a1, 110a3, 110b1, and 110b3 can each be made of, for example, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. The insulating layers 110a1, 110a3, 110b1, and 110b3 can each be made of the same material. Using the same material allows the insulating layers to be formed using the same equipment, thereby improving productivity and reducing manufacturing costs. Alternatively, different materials may be used for the insulating layer 110a1, the insulating layer 110a3, the insulating layer 110b1, and the insulating layer 110b3.

[0121] In this specification and the like, different materials refer to materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0122] The insulating layers 110a1, 110a3, 110b1, and 110b3 are preferably formed by a method that does not use a gas containing hydrogen. For example, sputtering can be suitably used to form the insulating layers 110a1, 110a3, 110b1, and 110b3. For the insulating layers 110a1, 110a3, 110b1, and 110b3, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, and gallium zinc oxide can be particularly suitably used, respectively.

[0123] The insulating layer 110a3 over the insulating layer 110a2 and the insulating layer 110b1 over the insulating layer 110b2 are preferably formed in an atmosphere containing oxygen. This allows oxygen to be supplied to the insulating layer 110a2 when the insulating layer 110a3 is formed. Similarly, oxygen can be supplied to the insulating layer 110b2 when the insulating layer 110b1 is formed. Materials containing oxygen are particularly suitable for use for the insulating layers 110a3 and 110b1. The higher the ratio of the flow rate of oxygen gas to the total film formation gas used to form the insulating layer 110a3 (hereinafter also referred to as the oxygen flow ratio) or the oxygen partial pressure in the treatment chamber of the film formation apparatus, the more efficiently oxygen can be supplied to the insulating layer 110a2. By treating the insulating layer 110b1 in the same manner as above, oxygen can be efficiently supplied to the insulating layer 110b2.

[0124] The thickness of each of the insulating layer 110a1 and the insulating layer 110b3 (film thickness relative to the surface on which it is formed) is preferably 3 nm or more and 500 nm or less, more preferably 5 nm or more and 400 nm or less, even more preferably 10 nm or more and 300 nm or less, even more preferably 20 nm or more and 300 nm or less, even more preferably 50 nm or more and 300 nm or less, even more preferably 100 nm or more and 300 nm or less, even more preferably 100 nm or more and 250 nm or less, even more preferably 150 nm or more and 250 nm or less.

[0125] If the insulating layer 110a1 is thin, oxygen contained in the insulating layer 110a2 may diffuse toward the conductive layer 112a through the insulating layer 110a1, thereby reducing the amount of oxygen supplied to the channel formation region of the semiconductor layer 108. Similarly, if the insulating layer 110b3 is thin, oxygen contained in the insulating layer 110b2 may diffuse toward the conductive layer 112a through the insulating layer 110b3, thereby reducing the amount of oxygen supplied to the channel formation region of the semiconductor layer 108. On the other hand, if the insulating layer 110a1 is thick, the amount of impurities released from the insulating layer 110a1 may increase, resulting in a larger amount of impurities diffusing into the channel formation region of the semiconductor layer 108. Similarly, if the insulating layer 110b3 is thick, the amount of impurities released from the insulating layer 110b3 may increase, resulting in a larger amount of impurities diffusing into the channel formation region of the semiconductor layer 108. By setting the thickness of each of the insulating layers 110a1 and 110b3 within the above-described range, the amount of oxygen supplied to the channel formation region of the semiconductor layer 108 can be increased, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. In addition, it is possible to prevent the conductive layer 112a from being oxidized by oxygen contained in the insulating layer 110a2 and the insulating layer 110b2, which would otherwise increase the electrical resistance of the conductive layer 112a. Note that the thicknesses of the insulating layer 110a1 and the insulating layer 110b3 are not limited to the above-described ranges.

[0126] The thickness of each of the insulating layer 110a3 and the insulating layer 110b1 (film thickness relative to the surface on which it is formed) is preferably 3 nm or more and 500 nm or less, more preferably 5 nm or more and 400 nm or less, even more preferably 10 nm or more and 300 nm or less, even more preferably 20 nm or more and 300 nm or less, even more preferably 20 nm or more and 200 nm or less, even more preferably 30 nm or more and 200 nm or less, even more preferably 50 nm or more and 200 nm or less, even more preferably 50 nm or more and 150 nm or less.

[0127] When the insulating layer 110a3 is thick, the amount of impurities released from the insulating layer 110a3 increases, which may increase the amount of impurities diffusing into the channel formation region of the semiconductor layer 108. Similarly, when the insulating layer 110b1 is thick, the amount of impurities released from the insulating layer 110b1 increases, which may increase the amount of impurities diffusing into the channel formation region of the semiconductor layer 108. On the other hand, when the insulating layer 110a3 is thin, oxygen contained in the insulating layer 110a2 may diffuse to the conductive layer 112b1 side and the conductive layer 112b2 side through the insulating layer 110a3, which may decrease the amount of oxygen supplied to the channel formation region of the semiconductor layer 108. Similarly, when the insulating layer 110b1 is thin, oxygen contained in the insulating layer 110b2 may diffuse to the conductive layer 112b1 side and the conductive layer 112b2 side through the insulating layer 110b1, which may decrease the amount of oxygen supplied to the channel formation region of the semiconductor layer 108. By setting the thickness of each of the insulating layers 110a3 and 110b1 within the above-mentioned ranges, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. In addition, it is possible to prevent the conductive layer 112b1 or the conductive layer 112b2 from being oxidized by oxygen contained in the insulating layer 110a2 or the insulating layer 110b2, and to prevent the electrical resistance of the conductive layer 112b1 or the conductive layer 112b2 from increasing. Note that the thicknesses of the insulating layer 110a3 and the insulating layer 110b1 are not limited to the above-described ranges.

[0128] Note that when the channel lengths of the transistors 10_1 and 10_2 are short, impurities diffusing into the channel formation regions have a greater effect on the electrical characteristics of the respective transistors. Therefore, it is preferable to use materials that release less impurities (especially hydrogen) from the insulating layers 110a1, 110a3, 110b1, and 110b3. Furthermore, it is more preferable that the insulating layers 110a1, 110a3, 110b1, and 110b3 be thin. This reduces the amount of impurities diffusing into the channel formation regions, enabling the transistors 10_1 and 10_2 to have good electrical characteristics and high reliability even when the channel lengths are short. For example, when the channel length is 500 nm or less, the thickness of each of the insulating layer 110a1, the insulating layer 110a3, the insulating layer 110b1, and the insulating layer 110b3 is preferably 3 nm or more and 100 nm or less, more preferably 3 nm or more and 50 nm or less, even more preferably 3 nm or more and 30 nm or less, even more preferably 3 nm or more and 20 nm or less, even more preferably 3 nm or more and 10 nm or less, and even more preferably 5 nm or more and 10 nm or less.

[0129] Note that although the insulating layer 110 has a six-layer structure here, one embodiment of the present invention is not limited to this. The insulating layer 110 can also have a single layer, a two-layer structure, a three-layer structure, a four-layer structure, a five-layer structure, or a seven or more layer structure.

[0130] 1A and 1B, the channel lengths and channel widths of the transistors 10_1 and 10_2 are described. Here, an example is described in which a region of the semiconductor layer 108 in contact with the insulating layer 110s1 functions as a channel formation region of the transistor 10_1, and a region of the semiconductor layer 108 in contact with the insulating layer 110s2 functions as a channel formation region of the transistor 10_2.

[0131] 1B , the channel length L10_1 of the transistor 10_1 and the channel length L10_2 of the transistor 10_2 are indicated by dashed double arrows. Note that although the channel length L10_1 of the transistor 10_1 will be described below, the channel length L10_1 can also be applied to the channel length L10_2 of the transistor 10_2 by replacing the conductive layer 112b1 with the conductive layer 112b2, the insulating layer 110s1 with the insulating layer 110s2, and the conductive layer 116_1 with the conductive layer 116_2. The channel length L10_1 of the transistor 10_1 corresponds to the distance along the insulating layer 110s1 between the top surface of the conductive layer 112a and the top surface of the conductive layer 112b1 in the semiconductor layer 108.

[0132] Note that the channel length L10_1 of the transistor 10_1 may be a sum of the thicknesses of the insulating layers 110a1, 110a2, 110a3, 116_1, 110b3, 110b2, and 110b1 in the semiconductor layer 108, which are located between the top surface of the conductive layer 112a and the bottom surface of the conductive layer 112b1 (in FIG. 1B , the thickness T110 is indicated by a double-headed dashed arrow). Alternatively, the channel length L10_1 of the transistor 10_1 may be a sum of the thickness T110 and the thickness of the conductive layer 112b1.

[0133] The channel length L10_1 is determined by the thickness T110, the thickness of the conductive layer 112b1, and the angle (angle θ110) between the surface on which the insulating layer 110s1 is to be formed (here, the side surfaces of the insulating layer 110a1, the insulating layer 110a2, the insulating layer 110a3, the conductive layer 116_1, the insulating layer 110b3, the insulating layer 110b2, the insulating layer 110b1, and the conductive layer 112b1) and the surface on which the insulating layer 110a1 is to be formed (here, the top surface of the conductive layer 112a1). This is not affected by the performance of the exposure equipment used to fabricate the transistor. Therefore, the channel length L10_1 can be made smaller than the minimum dimension of the exposure equipment, thereby enabling the realization of a fine-sized transistor. Specifically, a transistor with an extremely short channel length, which could not be realized with conventional exposure equipment for mass production of flat panel displays (e.g., a minimum dimension of approximately 1.5 μm or 1.25 μm), can be realized. Furthermore, it is possible to realize a transistor with a channel length of less than 10 nm without using the extremely expensive exposure equipment used in cutting-edge LSI technology.

[0134] The channel length L10_1 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and 2.5 μm or less, 10 nm or more and 2 μm or less, 10 nm or more and 1.5 μm or less, 10 nm or more and 1.2 μm or less, 10 nm or more and 1 μm or less, 10 nm or more and 500 nm or less, 10 nm or more and 300 nm or less, 10 nm or more and 200 nm or less, 10 nm or more and 100 nm or less, 10 nm or more and 50 nm or less, 10 nm or more and 30 nm or less, or 10 nm or more and 20 nm or less. For example, the channel length L10_1 can be 100 nm or more and 1 μm or less.

[0135] By shortening the channel length L10_1, the on-state current of the transistor 10_1 can be increased. By using the transistor 10_1, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a small-sized semiconductor device can be obtained. For example, when the semiconductor device of one embodiment of the present invention is applied to a large display device or a high-resolution display device, even if the number of wirings is increased, signal delay in each wiring can be reduced, and display unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.

[0136] The channel length L10_1 can be controlled by adjusting the thickness T110, the angle θ110, and the like.

[0137] The thickness T110 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and 2.5 μm or less, 10 nm or more and 2 μm or less, 10 nm or more and 1.5 μm or less, 10 nm or more and 1.2 μm or less, 10 nm or more and 1 μm or less, 10 nm or more and 500 nm or less, 10 nm or more and 300 nm or less, 10 nm or more and 200 nm or less, 10 nm or more and 100 nm or less, 10 nm or more and 50 nm or less, 10 nm or more and 30 nm or less, or 10 nm or more and 20 nm or less.

[0138] The side surface of the insulating layer 110 on the opening 143 side is preferably tapered. The angle θ110 is preferably less than 90 degrees. By reducing the angle θ110, the coverage of a layer (e.g., the semiconductor layer 108) formed on the insulating layer 110 can be improved. Furthermore, the smaller the angle θ110, the longer the channel length L10_1 can be, and the larger the angle θ110, the shorter the channel length L10_1 can be.

[0139] The angle θ110 can be, for example, 30 degrees or more and 90 degrees or less, 35 degrees or more and 85 degrees or less, 40 degrees or more and 80 degrees or less, 45 degrees or more and 80 degrees or less, 50 degrees or more and 80 degrees or less, 55 degrees or more and 80 degrees or less, 60 degrees or more and 80 degrees or less, 65 degrees or more and 80 degrees or less, or 70 degrees or more and 80 degrees or less.

[0140] 1B and the like, the angle θ110 is shown as being less than 90 degrees; however, this is not limited to this embodiment of the present invention. The angle θ110 can also be set to 90 degrees or approximately 90 degrees. This can shorten the channel length L10_1 of the transistor 10_1.

[0141] 1B and the like shows an example in which the sidewalls of the opening 143 (the side surfaces of the insulating layer 110a1, the side surfaces of the insulating layer 110a2, the side surfaces of the insulating layer 110a3, the side surfaces of the conductive layer 116_1, the side surfaces of the insulating layer 110b3, the side surfaces of the insulating layer 110b2, the side surfaces of the insulating layer 110b1, and the side surfaces of the conductive layer 112b1) are formed in a straight line; however, one embodiment of the present invention is not limited to this. For example, the angle formed between the side surfaces of insulating layer 110a1, insulating layer 110a2, and insulating layer 110a3 and the upper surface of conductive layer 112a, the angle formed between the side surface of conductive layer 116_1 and the upper surface of insulating layer 110a3, the angle formed between the side surfaces of insulating layer 110b3, insulating layer 110b2, and insulating layer 110b1 and the upper surface of conductive layer 116_1, and the angle formed between the side surface of conductive layer 112b1 and the upper surface of insulating layer 110b1 may be configured to be different from each other.

[0142] In FIG. 1A , the channel width W10_1 of the transistor 10_1 and the channel width W10_2 of the transistor 10_2 are indicated by solid double-headed arrows. The channel width W10_1 corresponds to the length of a region where the end of the conductive layer 116_1 on the opening 143 side overlaps with the semiconductor layer 108 in a plan view. This length also corresponds to the length of a region where the semiconductor layer 108 overlaps with at least one of the conductive layer 112a (one of the source electrode and drain electrode of the transistor 10_1) and the conductive layer 112b1 (the other of the source electrode and drain electrode of the transistor 10_1). Therefore, this length can be considered to be the length of a region through which the drain current of the transistor 10_1 can flow in a plan view. Furthermore, this length direction is also approximately perpendicular to the channel length L10_1 of the transistor 10_1. Therefore, this length can be considered to be the channel width W10_1 of the transistor 10_1. The above can also be applied to the channel width W10_2 of the transistor 10_2 by replacing the conductive layer 116_1 with the conductive layer 116_2 and the conductive layer 112b1 with the conductive layer 112b2.

[0143] Note that the channel width W10_1 of the transistor 10_1 may refer to the length of a region where the semiconductor layer 108 overlaps with both the conductive layer 112a (one of the source electrode or drain electrode of the transistor 10_1) and the conductive layer 112b1 (the other of the source electrode or drain electrode of the transistor 10_1). Similarly, the channel width W10_2 of the transistor 10_2 may refer to the length of a region where the semiconductor layer 108 overlaps with both the conductive layer 112a (one of the source electrode or drain electrode of the transistor 10_2) and the conductive layer 112b2 (the other of the source electrode or drain electrode of the transistor 10_2).

[0144] 5A shows a cross-sectional view of a structure in which only the transistor 10_2 side is cut out from the semiconductor device 100 shown in FIG. 1B. In FIG. 5A, the cross section of the structure is shown as an XZ plane. In FIG. 5B, a view of the structure shown in FIG. 5A seen from the YZ plane side is shown. For ease of viewing, only the conductive layer 112a, the conductive layer 112b2, the conductive layer 116_2, and the semiconductor layer 108 are shown in FIG. 5B.

[0145] 5B, when the channel width W10_2 of the transistor 10_2 is the length of the region where the semiconductor layer 108 overlaps with at least one of the conductive layer 112a and the conductive layer 112b2, the channel width W10_2 corresponds to the width W10_2A shown in FIG. 5B. On the other hand, when the channel width W10_2 of the transistor 10_2 is the length of the region where the semiconductor layer 108 overlaps with both the conductive layer 112a and the conductive layer 112b2, the channel width W10_2 corresponds to the width W10_2B shown in FIG. 5B.

[0146] The width D143 of the opening 143 may vary in the depth direction. For example, the width D143 of the opening 143 may be an average value of the diameter at the highest point, the diameter at the lowest point, and the diameter at the midpoint between these points in a cross-sectional view.

[0147] When the opening 143 is formed using photolithography, the width D143 of the opening 143 is equal to or larger than the minimum dimension of the exposure device. The width D143 can be, for example, 200 nm to less than 5 μm, 300 nm to 4.5 μm, 400 nm to 4 μm, 500 nm to 3.5 μm, 500 nm to 3 μm, 500 nm to 2.5 μm, 500 nm to 2 μm, 500 nm to 1.5 μm, or 500 nm to 1 μm.

[0148] [Semiconductor Layer 108] Metal oxides that can be used for the semiconductor layer 108 will be specifically described. Examples of metal oxides include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium or zinc. The metal oxide preferably contains one or more elements selected from indium, element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements are more preferred because they have a high bond energy with oxygen and an ionic radius similar to that of indium or zinc. Furthermore, tin is more preferred because it is tetravalent and can increase carrier mobility. In this specification, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification may also include metalloid elements.

[0149] The semiconductor layer 108 may be formed of, for example, indium zinc oxide (In—Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In—Sn oxide, also referred to as ITO), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium tungsten oxide (In—W oxide, also referred to as IWO), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide), or the like. Examples of usable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as AZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO, IGZAO, or IAGZO). Alternatively, examples of usable materials include indium tin oxide containing silicon (ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0150] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide. Therefore, the presence of a metal element having a higher period number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0151] The metal oxide may contain one or more nonmetallic elements. The presence of a nonmetallic element in the metal oxide may increase the carrier concentration or narrow the band gap, thereby increasing the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0152] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased, and a transistor with a large on-state current can be realized.

[0153] In this specification and the like, the ratio of the number of indium atoms to the sum of the numbers of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements. When a plurality of elements are contained as the element M, the sum of the ratios of the number of atoms of the element M to the sum of the numbers of atoms of all contained metal elements can be referred to as the content of the element M.

[0154] By increasing the zinc content in the metal oxide, the metal oxide can be made highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0155] By increasing the content of element M in the metal oxide, it is possible to obtain a metal oxide with a large band gap. Ｏ ) is suppressed, the formation of oxygen vacancies (V Ｏ ) can be suppressed, and a shift in the threshold voltage of the transistor can be suppressed. As a result, the cutoff current can be reduced, and the transistor can be a normally-off transistor. In addition, the transistor can have a small off-state current. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0156] The electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used in the semiconductor layer 108. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0157] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:1, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In: Examples of the composition include In:M:Zn = 5:1:9, In:M:Zn = 6:1:6, In:M:Zn = 10:1:1, In:M:Zn = 10:1:3, In:M:Zn = 10:1:4, In:M:Zn = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, In:M:Zn = 5:2:5, In:M:Zn = 10:1:10, In:M:Zn = 20:1:10, In:M:Zn = 40:1:10, and compositions in the vicinity thereof. Note that a composition in the vicinity includes a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in the metal oxide can increase the on-state current or field-effect mobility of the transistor.

[0158] The atomic ratio of In in the In-M-Zn oxide can be less than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxide include In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, In:M:Zn=1:3:6, and compositions close to these. By increasing the ratio of the number of M atoms in the metal oxide, oxygen deficiency (V Ｏ ) can be suppressed.

[0159] By using a material with a high indium content for the semiconductor layer 108, the on-state current or the field-effect mobility of the transistor can be increased. Ｏ) can be suppressed. The content of element M (the ratio of the number of atoms of element M to the sum of the number of atoms of all contained metal elements) is preferably 0.1% to 25%, more preferably 0.1% to 20%, even more preferably 0.1% to 10%, even more preferably 0.1% to 8%, even more preferably 0.1% to 6%, and even more preferably 0.1% to 4%. This allows for a transistor with excellent electrical characteristics. For example, it is preferable to use a metal oxide having a ratio of In:M:Zn=40:1:10 or a metal oxide having a similar ratio. The element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, metal oxides having a ratio of In:Sn:Zn=40:1:10 or a metal oxide having a similar ratio can be suitably used. Alternatively, metal oxides having a ratio of In:Al:Zn=40:1:10 or a metal oxide having a similar ratio can be suitably used.

[0160] Here, when a polycrystalline metal oxide is used for the semiconductor layer 108, crystal grain boundaries become recombination centers, and carriers are captured, which may reduce the on-state current of the transistor. Furthermore, when a polycrystalline metal oxide is used for the semiconductor layer 108, the surface of the semiconductor layer 108 may become uneven. This increases the step on the surface where a layer (e.g., the insulating layer 106) formed on the semiconductor layer 108 is to be formed, which may cause defects such as discontinuities or voids in the layer. When a metal oxide having a composition that easily results in a polycrystalline structure is used for the semiconductor layer 108, it is preferable to include an element that inhibits crystallization. This prevents the semiconductor layer 108 from becoming polycrystalline, resulting in a transistor with a large on-state current. Furthermore, the coverage of a layer (e.g., the insulating layer 106) formed on the semiconductor layer 108 can be improved, which may prevent defects such as discontinuities or voids in the layer.

[0161] For example, compared with indium tin oxide (ITO), indium tin oxide (ITSO) containing silicon is less likely to form a polycrystalline structure and is therefore suitable for use in the semiconductor layer 108. When ITSO is used, the silicon content (the ratio of the number of silicon atoms to the sum of the numbers of atoms of all metal elements contained) is preferably 1% or more and 20% or less, more preferably 3% or more and 20% or less, even more preferably 3% or more and 15% or less, and even more preferably 5% or more and 15% or less. Specifically, metal oxides of In:Sn:Si=45:5:4, In:Sn:Si=95:5:8, and metal oxides in the vicinity thereof can be suitably used. When indium tin oxide (ITSO) containing silicon is used for the semiconductor layer 108, it is preferable that ITSO have crystallinity. Note that the semiconductor layer 108 may have an amorphous region or may be amorphous.

[0162] A metal oxide not containing element M can be used for the semiconductor layer 108. When the metal oxide is an In-Zn oxide, the atomic ratio of the metal elements can be, for example, In:Zn = 1:1, In:Zn = 2:1, In:Zn = 1:2, In:Zn = 3:1, In:Zn = 3:2, In:Zn = 2:3, In:Zn = 4:1, In:Zn = 4:3, In:Zn = 5:1, In:Zn = 5:2, In:Zn = 5:3, In:Zn = 5:4, In:Zn = 5:6, In:Zn = 5:7, In:Zn = 5:8, In:Zn = 5:9, In:Zn = 7:1, In:Zn = 10:1, In:Zn = 10:3, In:Zn = 10:7, and compositions in the vicinity thereof. Furthermore, it is more preferable that the atomic ratio of In is equal to or greater than the atomic ratio of Zn. By increasing the atomic ratio of indium in the metal oxide, the on-state current or field-effect mobility of the transistor can be increased.

[0163] The composition of the semiconductor layer 108 can be analyzed using, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectroscopy (XPS or ESCA), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Furthermore, a combination of these techniques can be used for analysis. It is preferable to separate peaks in the spectrum obtained by the analysis and identify and quantify the elements. For elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, may be difficult to quantify, or may be below the detection limit.

[0164] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). When the metal oxide is formed by sputtering, the composition of the formed metal oxide may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide may be reduced to about 50% of that in the sputtering target.

[0165] It is preferable to use a crystalline metal oxide for the semiconductor layer 108. Examples of the structure of a crystalline metal oxide include a CAAC (C-Axis Aligned Crystal) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc: nano-crystal) structure. By using a crystalline metal oxide, the defect level density in the semiconductor layer 108 can be reduced, and a highly reliable semiconductor device can be realized. Note that the CAAC structure is a crystal structure in which multiple microcrystals (typically, multiple IGZO microcrystals) have a c-axis orientation and are connected without being oriented in the a-b plane. The CAAC structure has fewer crystal grain boundaries and grains in the a-b plane than a polycrystalline structure, and therefore a highly reliable semiconductor device can be realized.

[0166] The semiconductor layer 108 is preferably formed using a CAAC-OS or an nc-OS.

[0167] The CAAC-OS has multiple layered crystals. The c-axes of the crystals are oriented in the normal direction to the surface where the semiconductor layer 108 is formed. The semiconductor layer 108 preferably has layered crystals that are parallel or approximately parallel to the surface where the semiconductor layer 108 is formed. For example, the semiconductor layer 108 preferably has layered crystals that are parallel or approximately parallel to the top surface of the conductive layer 112b1 and the top surface of the conductive layer 112b2 in regions in contact with the top surfaces of the conductive layer 112b1 and the conductive layer 112b2, and layered crystals that are parallel or approximately parallel to the side surfaces of the insulating layer 110s1 and the insulating layer 110s2 in regions in contact with the side surfaces of the insulating layer 110s1 and the insulating layer 110s2. In particular, the semiconductor layer 108 preferably has layered crystals that are parallel or approximately parallel to the side surfaces of the insulating layer 110s1 and the insulating layer 110s2, which are the surfaces where the semiconductor layer 108 is formed, in the opening 143. With this structure, the layered crystals of the semiconductor layer 108 are formed approximately parallel to the channel length direction of the transistor 10_1 and the channel length direction of the transistor 10_2, and therefore the transistors 10_1 and 10_2 can have large on-state current.

[0168] By using a metal oxide with high crystallinity for the channel formation region, the density of defect states in the channel formation region can be reduced, while by using a metal oxide with low crystallinity, a transistor capable of passing a large current can be realized.

[0169] The higher the substrate temperature during metal oxide formation, the higher the crystallinity of the resulting metal oxide. The substrate temperature during formation can be adjusted, for example, by the temperature of the stage on which the substrate is placed during formation. Furthermore, the higher the oxygen flow rate ratio of the deposition gas used for formation or the oxygen partial pressure in the processing chamber, the higher the crystallinity of the resulting metal oxide.

[0170] The crystallinity of the semiconductor layer 108 can be analyzed by, for example, X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). Furthermore, the analysis can be performed by combining a plurality of these techniques.

[0171] When a metal oxide is used for the semiconductor layer 108, V Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. Ｏ To obtain a metal oxide with a sufficiently reduced amount of H, it is necessary to remove impurities such as water and hydrogen from the metal oxide (sometimes referred to as dehydration or dehydrogenation treatment), and to supply oxygen to the metal oxide to eliminate oxygen deficiency (V Ｏ It is important to repair the Ｏ By using a metal oxide in which defects such as H are sufficiently reduced in a channel formation region of a transistor, stable electrical characteristics can be obtained. Ｏ ) is sometimes referred to as oxygenation treatment.

[0172] When a metal oxide is used for the semiconductor layer 108, the carrier concentration in the channel formation region is 1×10 １８ cm −３ Preferably, it is 1×10 or less. １７ cm−３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３ It is more preferable that the carrier concentration in the channel formation region is less than 1×10. −９ cm −３ It can be said that:

[0173] OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0174] The semiconductor layer 108 may include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0175] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as the channel formation region of a transistor include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0176] The semiconductor layer 108 can have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 108 can have the same or substantially the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. When the two or more metal oxide layers included in the semiconductor layer 108 have the same or substantially the same composition, the boundary (interface) between these metal oxide layers may not be clearly identified.

[0177] [Conductive Layer 112a, Conductive Layer 112b1, Conductive Layer 112b2, Conductive Layer 116_1, Conductive Layer 116_2, and Conductive Layer 104] The conductive layer 112a, the conductive layer 112b1, the conductive layer 112b2, the conductive layer 116_1, the conductive layer 116_2, and the conductive layer 104 can each have a single-layer structure or a stacked-layer structure. Examples of materials that can be used for the conductive layer 112a, the conductive layer 112b1, the conductive layer 112b2, the conductive layer 116_1, the conductive layer 116_2, and the conductive layer 104 include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, and alloys containing one or more of the above-mentioned metals. A conductive material with low electrical resistivity, including one or more of copper, silver, gold, and aluminum, can be preferably used for each of the conductive layers 112a, 112b1, 112b2, 116_1, 116_2, and 104. Copper or aluminum is particularly preferable because of its excellent mass productivity.

[0178] A conductive metal oxide (oxide conductor) can be used for each of the conductive layer 112a, the conductive layer 112b1, the conductive layer 112b2, the conductive layer 116_1, the conductive layer 116_2, and the conductive layer 104. Examples of oxide conductors (OC) include indium oxide, zinc oxide, In—Sn oxide (ITO), In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide (also referred to as ITO containing silicon, or ITSO), zinc oxide to which gallium is added, and In—Ga—Zn oxide. In particular, an oxide conductor containing indium is preferable because of its high conductivity.

[0179] Oxygen deficiency (V) in metal oxides with semiconducting properties Ｏ ) and the oxygen vacancy (V Ｏ When hydrogen is added to a metal oxide, a donor level is formed near the conduction band. As a result, the metal oxide becomes electrically conductive. A metal oxide that has become electrically conductive can be called an oxide conductor.

[0180] The conductive layer 112a, the conductive layer 112b1, the conductive layer 112b2, the conductive layer 116_1, the conductive layer 116_2, and the conductive layer 104 can each have a stacked structure of a conductive film containing the above-described oxide conductor and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced.

[0181] A Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can be used for each of the conductive layer 112a, the conductive layer 112b1, the conductive layer 112b2, the conductive layer 116_1, the conductive layer 116_2, and the conductive layer 104. By using a Cu-X alloy film, it is possible to process the film by wet etching, thereby reducing manufacturing costs.

[0182] Note that the conductive layer 112a, the conductive layer 112b1, the conductive layer 112b2, the conductive layer 116_1, the conductive layer 116_2, and the conductive layer 104 can be formed using the same material, or different materials can be used for some or all of them.

[0183] The conductive layer 112a, the conductive layer 112b1, and the conductive layer 112b2 have a region in contact with the semiconductor layer 108. When a metal oxide is used for the semiconductor layer 108, if a metal that is easily oxidized (e.g., aluminum) is used for the conductive layer 112a, the conductive layer 112b1, and the conductive layer 112b2, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 112a and the semiconductor layer 108, between the conductive layer 112b1 and the semiconductor layer 108, and between the conductive layer 112b2 and the semiconductor layer 108, which may hinder conduction therebetween. Therefore, for the conductive layer 112a, the conductive layer 112b1, and the conductive layer 112b2, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material.

[0184] For the conductive layer 112a, the conductive layer 112b1, and the conductive layer 112b2, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel, which are conductive materials that are difficult to oxidize or materials that maintain low electrical resistance even when oxidized, and are therefore preferable.

[0185] The conductive layer 112a, the conductive layer 112b1, and the conductive layer 112b2 can each be formed using the above-described oxide conductors. Specifically, metal oxides such as indium oxide, zinc oxide, ITO, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn oxide containing silicon, and zinc oxide doped with gallium can be used.

[0186] The conductive layer 112a, the conductive layer 112b1, and the conductive layer 112b2 may each include a nitride conductor, such as tantalum nitride or titanium nitride.

[0187] The conductive layer 112a, the conductive layer 112b1, the conductive layer 112b2, the conductive layer 116_1, the conductive layer 116_2, and the conductive layer 104 can each have a stacked structure. When the conductive layer 112a has a stacked structure, a conductive material that is not easily oxidized is preferably used for at least a layer in contact with the semiconductor layer 108. The same applies to the conductive layer 112b1 and the conductive layer 112b2.

[0188] [Insulating Layer 106] The insulating layer 106 preferably includes one or more inorganic insulating layers. The insulating layer 106 can be made of the same material as that used for the insulating layer 110, the insulating layer 110s1, and the insulating layer 110s2.

[0189] The insulating layer 106 has a region in contact with the semiconductor layer 108, the conductive layer 112b1, the conductive layer 112b2, the conductive layer 104, and the insulating layer 110. When a metal oxide is used for the semiconductor layer 108, any of the above-described oxides and oxynitrides is preferably used for at least a film that is in contact with the semiconductor layer 108 among the films that constitute the insulating layer 106. When the insulating layer 106 has a single-layer structure, silicon oxide, silicon oxynitride, or aluminum oxide can be preferably used for the insulating layer 106.

[0190] In a miniaturized transistor, a thin gate insulating layer may result in a large leakage current. By using a material with a high relative dielectric constant (also referred to as a high-k material) for the gate insulating layer, a low voltage can be achieved during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. Furthermore, a material that can have ferroelectricity can be used for the gate insulating layer. Examples of materials that can have ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ (X is a real number greater than 0). Examples of materials that can have ferroelectricity include materials in which an element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide. For example, the ratio of the number of hafnium atoms to the number of element J1 atoms may be 1:1 or close to that. Examples of materials that can have ferroelectricity include materials in which element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide. For example, the ratio of the number of zirconium atoms to the number of element J2 ... lead titanate (PbTiOＸ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, can be used.

[0191] 1B and the like, the insulating layer 106 has a single-layer structure, but one embodiment of the present invention is not limited to this. The insulating layer 106 can have a stacked-layer structure.

[0192] [Insulating Layer 195] The insulating layer 195, which functions as a protective layer, is preferably made of a material through which impurities do not easily diffuse. Providing the insulating layer 195 can effectively prevent impurities from diffusing from the outside into the transistors 10_1 and 10_2, thereby improving the reliability of the semiconductor device 100. Examples of impurities include water and hydrogen.

[0193] The insulating layer 195 can be an insulating layer containing an inorganic material or an insulating layer containing an organic material. For example, an inorganic material such as oxide, oxynitride, nitride oxide, or nitride can be suitably used for the insulating layer 195. More specifically, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. For example, one or more of acrylic resin and polyimide resin can be used as the organic material. A photosensitive material can be used as the organic material. Two or more of the above insulating films can be stacked. The insulating layer 195 can have a stacked structure of an insulating layer containing an inorganic material and an insulating layer containing an organic material.

[0194] [Substrate 102] There are no significant limitations on the material of the substrate 102, but it is necessary that the material has at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate can be used as the substrate 102. Furthermore, the substrate 102 may be configured to include a semiconductor element. Note that the shape of the semiconductor substrate and the insulating substrate may be circular or rectangular.

[0195] A flexible substrate can be used as the substrate 102, and the semiconductor device 100 and the like can be formed directly on the flexible substrate. Alternatively, a peeling layer can be provided between the substrate 102 and the semiconductor device 100 and the like. By providing the peeling layer, after a part or the whole of the semiconductor device is completed thereon, it can be separated from the substrate 102 and transferred to another substrate. In this case, the semiconductor device 100 and the like can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0196] 6A illustrates a cross-sectional view of the semiconductor device 100A taken along dashed line A1-A2 in the plan view of the semiconductor device 100 illustrated in FIG.

[0197] The semiconductor device 100A includes a transistor 10A_1, a transistor 10A_2, an insulating layer 110a, and an insulating layer 110b. The semiconductor device 100A differs from the semiconductor device 100 shown in FIG. 1B in that the semiconductor device 100A includes a transistor 10A_1 instead of the transistor 10_1 and a transistor 10A_2 instead of the transistor 10_2.

[0198] The transistor 10A_1 differs from the transistor 10_1 in that the insulating layer 110s1 has a stacked structure of an insulating layer 110s1a and an insulating layer 110s1b over the insulating layer 110s1a. The insulating layer 110s1a is provided in contact with the top surface of the conductive layer 112a, the side surface of the insulating layer 110, the side surface of the conductive layer 116_1, and the side surface of the conductive layer 112b1. The insulating layer 110s1b is provided to face the top surface of the conductive layer 112a, the side surface of the insulating layer 110, the side surface of the conductive layer 116_1, and the side surface of the conductive layer 112b1 with the insulating layer 110s1a interposed therebetween.

[0199] The transistor 10A_2 differs from the transistor 10_2 in that the insulating layer 110s2 has a stacked structure of an insulating layer 110s2a and an insulating layer 110s2b over the insulating layer 110s2a. The insulating layer 110s2a is provided in contact with the top surface of the conductive layer 112a, the side surface of the insulating layer 110, the side surface of the conductive layer 116_2, and the side surface of the conductive layer 112b2. The insulating layer 110s2b is provided to face the top surface of the conductive layer 112a, the side surface of the insulating layer 110, the side surface of the conductive layer 116_2, and the side surface of the conductive layer 112b2 with the insulating layer 110s2a interposed therebetween.

[0200] For example, the materials, manufacturing methods, etc. used for the insulating layers 110a1, 110a3, 110b1, and 110b3 can be applied to the insulating layers 110s1a and 110s2a. For example, the materials, manufacturing methods, etc. used for the insulating layers 110a2 and 110b2 can be applied to the insulating layers 110s1b and 110s2b. That is, the insulating layers 110s1a and 110s2a are made of a material that is difficult for oxygen to permeate, and the insulating layers 110s1b and 110s2b are made of a material that contains oxygen and releases oxygen when heated.

[0201] In a structure in which the insulating layer 110s1 that releases oxygen is in contact with the conductive layer 112a and the conductive layer 112b1, as in the transistor 10_1, there is a concern that the conductive layer 112a and the conductive layer 112b1 are oxidized by oxygen released from the insulating layer 110s1, thereby reducing the amount of oxygen supplied from the insulating layer 110s1 to the semiconductor layer 108. By forming the insulating layer 110s1 into a stacked structure of the insulating layer 110s1a and the insulating layer 110s1b, as in the transistor 10A_1, the insulating layer 110s1b that releases oxygen can be prevented from being in contact with the conductive layer 112a and the conductive layer 112b1. This can prevent the conductive layer 112a and the conductive layer 112b1 from being oxidized by oxygen released from the insulating layer 110s1b. Furthermore, a reduction in the amount of oxygen supplied from the insulating layer 110s1b to the semiconductor layer 108 can be suppressed.

[0202] Similarly, in a structure in which the insulating layer 110s2 that releases oxygen is in contact with the conductive layer 112a and the conductive layer 112b2, as in the transistor 10_2, there is a concern that the conductive layer 112a and the conductive layer 112b2 may be oxidized by the oxygen released from the insulating layer 110s2, thereby reducing the amount of oxygen supplied from the insulating layer 110s2 to the semiconductor layer 108. By forming the insulating layer 110s2 as a stacked structure of the insulating layer 110s2a and the insulating layer 110s2b as in the transistor 10A_2, the insulating layer 110s2b that releases oxygen can be prevented from being in contact with the conductive layer 112a and the conductive layer 112b2. This can prevent the conductive layer 112a and the conductive layer 112b2 from being oxidized by the oxygen released from the insulating layer 110s2b. Furthermore, a reduction in the amount of oxygen supplied from the insulating layer 110s2b to the semiconductor layer 108 can be suppressed.

[0203] With respect to the semiconductor device 100A, the contents described for the semiconductor device 100 can be referred to for other matters.

[0204] 6B is a cross-sectional view of the semiconductor device 100B taken along the dashed-dotted line A1-A2 in the plan view of the semiconductor device 100 shown in FIG.

[0205] The semiconductor device 100B includes a transistor 10B_1, a transistor 10B_2, an insulating layer 110a, and an insulating layer 110b. The semiconductor device 100B differs from the semiconductor device 100 shown in FIG. 1B in that the semiconductor device 100B includes a transistor 10B_1 instead of the transistor 10_1 and a transistor 10B_2 instead of the transistor 10_2.

[0206] The transistor 10B_1 differs from the transistor 10_1 in that an insulating layer 110g1 is provided between the conductive layer 116_1 and the insulating layer 110s1. The transistor 10B_2 differs from the transistor 10_2 in that an insulating layer 110g2 is provided between the conductive layer 116_2 and the insulating layer 110s2.

[0207] The insulating layers 110g1 and 110g2 contain, for example, oxides of the elements contained in the conductive layers 116_1 and 116_2, respectively. When the conductive layers 116_1 and 116_2 are made of a metal, the insulating layers 110g1 and 110g2 are, for example, oxides of the metal. When the conductive layers 116_1 and 116_2 are made of silicon, the insulating layers 110g1 and 110g2 are, for example, silicon oxide. The insulating layers 110g1 and 110g2 can be made of a metal oxide such as aluminum oxide or tantalum oxide, and aluminum oxide is particularly preferred.

[0208] The insulating layer 110g1 can function as a gate insulating layer of the transistor 10B_1. In the configuration shown in FIG. 6B , for example, a stacked structure of the insulating layer 110s1 and the insulating layer 110g1 functions as a gate insulating layer of the transistor 10B_1. Similarly, the insulating layer 110g2 can function as a gate insulating layer of the transistor 10B_2. In the configuration shown in FIG. 6B , for example, a stacked structure of the insulating layer 110s2 and the insulating layer 110g2 functions as a gate insulating layer of the transistor 10B_2.

[0209] In the transistor 10B_1, since the gate insulating layer includes the insulating layer 110s1 and the insulating layer 110g1, even if the insulating property of the insulating layer 110g1 is lower than that of the insulating layer 110s1, the electrical characteristics and reliability of the transistor 10B_1 can be sufficiently ensured when sufficient insulating property is obtained by stacking the insulating layer 110s1 and the insulating layer 110s1. Similarly, in the transistor 10B_2, since the gate insulating layer includes the insulating layer 110s2 and the insulating layer 110g2, even if the insulating property of the insulating layer 110g2 is lower than that of the insulating layer 110s2, the electrical characteristics and reliability of the transistor 10B_2 can be sufficiently ensured when sufficient insulating property is obtained by stacking the insulating layer 110s2 and the insulating layer 110g2.

[0210] The transistor 10B_1 includes the insulating layer 110g1, which may allow the thickness of the insulating layer 110s1 to be thin. The thinning of the insulating layer 110s1 may strengthen the effect of the electric field applied from the gate electrode (conductive layer 116_1) of the transistor 10B_1 to the semiconductor layer 108. Similarly, the transistor 10B_2 includes the insulating layer 110g2, which may allow the thickness of the insulating layer 110s2 to be thin. The thinning of the insulating layer 110s2 may strengthen the effect of the electric field applied from the gate electrode (conductive layer 116_2) of the transistor 10B_2 to the semiconductor layer 108. For example, a material having a higher dielectric constant than the material used for the insulating layers 110s1 and 110s2 can be preferably used for the insulating layers 110g1 and 110g2.

[0211] The insulating layer 110g1 can be formed in a self-aligned manner, for example, by depositing a layer capable of supplying oxygen in contact with the surface of the conductive layer 116_1 and oxidizing the surface of the conductive layer 116_1 with oxygen supplied from the insulating layers 110a2 and 110b2 through the layer. If the height of the upper end of the insulating layer 110s1 becomes lower than the height of the upper surface of the conductive layer 116_1 during etching during the formation of the insulating layer 110s1, or if the height of the upper end of the insulating layer 110s1 is higher than the height of the upper surface of the conductive layer 116_1 but the difference is small, leakage current may flow between the semiconductor layer 108 and the conductive layer 116_1, potentially degrading the electrical characteristics of the transistor 10B_1. Even in such a case, the transistor 10B_1 can suppress leakage between the semiconductor layer 108 and the conductive layer 116_1 by including the insulating layer 110g1.

[0212] Similarly, the insulating layer 110g2 can be formed in a self-aligned manner, for example, by depositing a layer capable of supplying oxygen in contact with the surface of the conductive layer 116_2 and oxidizing the surface of the conductive layer 116_2 with oxygen supplied from the insulating layers 110a2 and 110b2 through the layer. If the height of the upper end of the insulating layer 110s2 becomes lower than the height of the upper surface of the conductive layer 116_2 during etching during the formation of the insulating layer 110s2, or if the height of the upper end of the insulating layer 110s2 is higher than the height of the upper surface of the conductive layer 116_2 but the difference is small, leakage current may flow between the semiconductor layer 108 and the conductive layer 116_2, potentially degrading the electrical characteristics of the transistor 10B_2. Even in such a case, the transistor 10B_2 can suppress leakage between the semiconductor layer 108 and the conductive layer 116_2 by including the insulating layer 110g2.

[0213] With regard to the semiconductor device 100B, the contents described in connection with the semiconductor device 100 can be referred to for other matters than those described above.

[0214] 7A illustrates a cross-sectional view of the semiconductor device 100C taken along the dashed-dotted line A1-A2 in the plan view of the semiconductor device 100 illustrated in FIG.

[0215] The semiconductor device 100C includes a transistor 10C_1, a transistor 10C_2, an insulating layer 110a, and an insulating layer 110b. The semiconductor device 100C differs from the semiconductor device 100 illustrated in FIG. 1B in that the semiconductor device 100C includes a transistor 10C_1 instead of the transistor 10_1 and a transistor 10C_2 instead of the transistor 10_2.

[0216] The transistor 10C_1 differs from the transistor 10_1 in the configuration of an insulating layer 110s1, and the transistor 10C_2 differs from the transistor 10_2 in the configuration of an insulating layer 110s2.

[0217] Specifically, in the transistor 10C_1, the bottom surface of the insulating layer 110s1 is in contact with the top surface of the insulating layer 110a1, and the side surface of the insulating layer 110a1 is in contact with the semiconductor layer 108. That is, in the transistor 10C_1, the insulating layer 110s1 is not in contact with the conductive layer 112a. Similarly, in the transistor 10C_2, the bottom surface of the insulating layer 110s2 is in contact with the top surface of the insulating layer 110a1, and the side surface of the insulating layer 110a1 is in contact with the semiconductor layer 108. That is, in the transistor 10C_2, the insulating layer 110s2 is not in contact with the conductive layer 112a.

[0218] As described above, the insulating layers 110s1 and 110s2, together with the insulating layers 110a2 and 110b2, can have the function of supplying oxygen to the semiconductor layer 108. Therefore, in a structure in which the bottom surfaces of the insulating layers 110s1 and 110s2 are in contact with the conductive layer 112a, as in the transistors 10_1 and 10_2, oxygen diffused from the insulating layers 110s1 and 110s2 may oxidize part of the top surface of the conductive layer 112a, increasing its resistance and causing a problem of reducing the on-state current of the transistor. In contrast, by using a structure in which the insulating layer 110s1 and the conductive layer 112a and the insulating layer 110s2 are not in contact with each other, as in the transistors 10C_1 and 10C_2, the risk of causing the above problem can be reduced.

[0219] With respect to the semiconductor device 100C, the contents described in connection with the semiconductor device 100 can be referred to for other aspects than those described above.

[0220] 7B is a cross-sectional view of the semiconductor device 100D taken along the dashed-dotted line A1-A2 in the plan view of the semiconductor device 100 shown in FIG.

[0221] The semiconductor device 100D includes a transistor 10D_1, a transistor 10D_2, and insulating layers 110a and 110b. The same description as for the transistors 10A_1 and 10A_2 can be applied to the transistors 10D_1 and 10D_2, respectively. The semiconductor device 100D differs from the semiconductor device 100 shown in FIG. 1B in the configuration of the insulating layer 110.

[0222] Specifically, the semiconductor device 100D differs from the semiconductor device 100 in that the insulating layer 110a and the insulating layer 110b each have a single-layer structure. For the single-layer insulating layer 110a and the insulating layer 110b, it is preferable to use a material that can be used for the insulating layer 110a1, the insulating layer 110a3, the insulating layer 110b1, and the insulating layer 110b3, respectively. That is, it is preferable to use a material that has high blocking properties against oxygen and hydrogen. This can prevent the conductive layer 116_1 and the conductive layer 116_2 from being oxidized due to oxygen diffusion from the outside of the insulating layer 110a and the insulating layer 110b. Furthermore, oxygen in the semiconductor layer 108 diffuses toward the insulating layer 110a and the insulating layer 110b, causing oxygen vacancies (V Ｏ ) can be suppressed from being formed. As described above, since the insulating layers 110s1 and 110s2 have the function of releasing oxygen, even if the insulating layer 110 has the above-described configuration, oxygen can be supplied to the semiconductor layer 108. In the semiconductor device 100D, the number of insulating layers constituting the insulating layer 110 can be significantly reduced, and therefore the number of steps involved in forming the insulating layer 110 can be reduced compared to the semiconductor device 100, etc.

[0223] With respect to the semiconductor device 100D, the contents described in connection with the semiconductor device 100 can be referred to for other aspects than those described above.

[0224] 8A is a cross-sectional view of the semiconductor device 100E taken along dashed dotted line A1-A2 in the plan view of the semiconductor device 100 shown in FIG.

[0225] The semiconductor device 100E includes a transistor 10E_1, a transistor 10E_2, an insulating layer 110a, and an insulating layer 110b. The semiconductor device 100E differs from the semiconductor device 100 illustrated in FIG. 1B in that the semiconductor device 100E includes a transistor 10E_1 instead of the transistor 10E_1 and a transistor 10E_2 instead of the transistor 10E_2.

[0226] The transistor 10E_1 differs from the transistor 10_1 in that the transistor 10E_1 does not include the conductive layer 112b1 and the end of the semiconductor layer 108 on the A1 side extends to the outside of the conductive layer 116_1 and the conductive layer 112a. The transistor 10E_2 differs from the transistor 10_2 in that the transistor 10E_2 does not include the conductive layer 112b2 and the end of the semiconductor layer 108 on the A2 side extends to the outside of the conductive layer 116_2 and the conductive layer 112a.

[0227] In the transistor 10E_1, the semiconductor layer 108 has a region in contact with the top surface of the conductive layer 112a, the side surface of the insulating layer 110s1, the curved portion of the insulating layer 110s1, and the top surface of the insulating layer 110. In the transistor 10E_1, the semiconductor layer 108 can function as a semiconductor layer having a channel formation region and also as the other of the source and drain electrodes. For example, a region of the semiconductor layer 108 that overlaps with the insulating layer 110s1 can function as the channel formation region. A region located outside the opening 143 can function as the other of the source and drain electrodes.

[0228] In the transistor 10E_2, the semiconductor layer 108 has a region in contact with the top surface of the conductive layer 112a, the side surface of the insulating layer 110s2, the curved portion of the insulating layer 110s2, and the top surface of the insulating layer 110. In the transistor 10E_2, the semiconductor layer 108 can function as a semiconductor layer having a channel formation region and also as the other of the source and drain electrodes. For example, a region of the semiconductor layer 108 that overlaps with the insulating layer 110s2 can function as the channel formation region. A region located outside the opening 143 can function as the other of the source and drain electrodes.

[0229] For example, the resistance of the semiconductor layer 108 can be reduced by supplying impurities such as boron to the semiconductor layer 108 from a direction perpendicular to the substrate surface by ion implantation, ion doping, plasma immersion ion implantation, plasma treatment, or the like. Alternatively, when an oxide semiconductor is used for the semiconductor layer 108, a silicon nitride film or the like can be formed on a region of the semiconductor layer 108 that does not overlap with the opening 143 to make the region an oxide conductor (OC), thereby forming a low-resistance region in the semiconductor layer 108. In this manner, the resistance of the regions corresponding to the source and drain regions of the semiconductor layer 108 can be made lower than that of the channel formation region. Therefore, the channel formation region and the source and drain regions having lower resistance than the channel formation region can be separately formed in the semiconductor layer 108. As a result, in the transistors 10E_1 and 10E_2, regions corresponding to the source and drain electrodes can be formed in the semiconductor layer 108 without providing the conductive layers 112b1 and 112b2, respectively. Therefore, the number of steps required for manufacturing the transistors 10E_1 and 10E_2 can be reduced by the absence of the conductive layers 112b1 and 112b2, respectively.

[0230] With regard to the semiconductor device 100E, the contents described in connection with the semiconductor device 100 can be referred to for other aspects than those described above.

[0231] 8B is a cross-sectional view of the semiconductor device 100F taken along dashed dotted line A1-A2 in the plan view of the semiconductor device 100 shown in FIG.

[0232] The semiconductor device 100F includes a transistor 10F_1, a transistor 10F_2, an insulating layer 110a, and an insulating layer 110b. The semiconductor device 100F differs from the semiconductor device 100 shown in FIG. 1B in that the semiconductor device 100F includes a transistor 10F_1 instead of the transistor 10_1 and a transistor 10F_2 instead of the transistor 10_2.

[0233] The transistors 10F_1 and 10F_2 differ from the transistors 10_1 and 10_2, respectively, in that they do not include the conductive layer 104 that functions as a back gate electrode. That is, the transistor 10F_1 can be said to be a transistor that includes only one conductive layer (conductive layer 116_1) that functions as a gate electrode. Similarly, the transistor 10F_2 can be said to be a transistor that includes only one conductive layer (conductive layer 116_2) that functions as a gate electrode. Therefore, since the conductive layer 104 is not provided in the transistors 10F_1 and 10F_2, the number of steps required for manufacturing the transistors can be reduced.

[0234] With respect to the semiconductor device 100F, the contents described in the semiconductor device 100 can be referred to for other aspects than those described above.

[0235] As described above, the semiconductor device of one embodiment of the present invention can be applied to a display device. For example, the semiconductor device can be applied to a liquid crystal display device. A specific structural example in which the semiconductor device 100 illustrated in FIGS. 1A and 1B is applied to a liquid crystal display device will be described below. Note that a structural example in which the semiconductor device of one embodiment of the present invention is applied to a display device will also be described in detail in Embodiment 2.

[0236] Fig. 9A shows a plan view of a portion of a pixel of a display device. Fig. 9B shows a cross-sectional view taken along dashed line P1-P2 shown in Fig. 9A. Note that Fig. 9A omits some of the components of the display device (insulating layers, etc.).

[0237] The display device of one embodiment of the present invention is a liquid crystal display device including the semiconductor device 100 and the liquid crystal element 30 between the substrate 102 and the substrate 12 .

[0238] 9A , part of the semiconductor device 100 overlaps with an intersection between the conductive layer 116_1 and the conductive layer 112a, and another part of the semiconductor device 100 has a region overlapping with an intersection between the conductive layer 116_2 and the conductive layer 112a. The conductive layer 116_1, which functions as the gate electrode of the transistor 10_1, and the conductive layer 116_2, which functions as the gate electrode of the transistor 10_2, each function as a scan line. The conductive layer 112a, which functions as one of the source electrode or drain electrode of the transistor 10_1 and the transistor 10_2, functions as a signal line.

[0239] Note that the above-described contents can be referred to for details of the transistor 10_1, the transistor 10_2, the insulating layer 110a (insulating layer 110a1, insulating layer 110a2, and insulating layer 110a3), and the insulating layer 110b (insulating layer 110b1, insulating layer 110b2, and insulating layer 110b3) included in the semiconductor device 100. Since the above-described contents can be referred to for a description of the configuration of the semiconductor device 100, a description thereof will be omitted below in some cases.

[0240] The liquid crystal element 30 includes one of the conductive layers 112b1 and 112b2 (each of which also functions as the other of the source electrode and the drain electrode of the transistor 10_1 and the transistor 10_2) functioning as a pixel electrode, a conductive layer 32 functioning as a common electrode, a conductive layer 104 (which also functions as the back gate electrode of the transistor 10_1 and the transistor 10_2) functioning as a capacitor electrode, and a liquid crystal 33. The liquid crystal element 30 shown in FIG. 9B is a VA-mode liquid crystal element.

[0241] 9B shows only the liquid crystal element 30 including the conductive layer 112b2, the liquid crystal 33, and the conductive layer 32, but since the semiconductor device 100 has two transistors, it is possible to have two liquid crystal elements for one semiconductor device 100. That is, in addition to the above-described liquid crystal element, it is possible to have a liquid crystal element (not shown) including the conductive layer 112b1, the liquid crystal 33, and the conductive layer 32.

[0242] An insulating layer 46 functioning as a spacer is provided on a region of the insulating layer 195 that overlaps with the semiconductor device 100. A photosensitive resin can be used as the insulating layer 46. For example, the insulating layer 46 can be formed by forming a photosensitive resin on the insulating layer 195, exposing it to light, and developing it. The photosensitive resin can be a resin having either negative or positive photosensitivity.

[0243] The insulating layer 46 has a function of controlling the distance between the substrate 102 and the substrate 12 and controlling the thickness of the liquid crystal 33. Furthermore, the insulating layer 46 is preferably provided so as to fill a depression on the upper surface of the insulating layer 195 caused by the opening 143. By providing the insulating layer 46 so as to overlap the semiconductor device 100, a decrease in the aperture ratio due to the provision of the insulating layer 46 can be prevented.

[0244] Here, since the area of ​​the semiconductor device 100 in plan view can be made extremely small, the area of ​​the insulating layer 46 disposed in the region overlapping with the semiconductor device 100 also becomes small. Therefore, if the strength as a spacer is insufficient, it is preferable to dispose the insulating layer 46 in all sub-pixels. This ensures sufficient strength even for an insulating layer 46 with a small area.

[0245] Although the insulating layer 46 is provided on the substrate 102 side in this example, it may be provided on the substrate 12 side. In this case, the alignment film 41 may be provided in contact with the portion of the insulating layer 195 that overlaps with the semiconductor device 100. The insulating layer 46 may also be provided on both the substrate 102 side and the substrate 12 side.

[0246] The conductive layer 104, which functions as a capacitor electrode, has a region that overlaps with the conductive layer 112b1 or the conductive layer 112b2 with the insulating layer 106 interposed therebetween. The region where the conductive layer 104, the insulating layer 106, and the conductive layer 112b1 (or the conductive layer 112b2) are stacked functions as a storage capacitor of the pixel. In this case, the conductive layer 104 and the conductive layer 112b1 (or the conductive layer 112b2) function as a pair of electrodes of the capacitor, and the insulating layer 106 functions as a dielectric of the capacitor.

[0247] An alignment film 41 is provided to cover the insulating layer 46 and the insulating layer 195 .

[0248] In one embodiment of the present invention, the conductive layer 104 of the semiconductor device 100 functions as a back-gate electrode of the transistor 10_1 and the transistor 10_2 and as a capacitor electrode of the liquid crystal element 30. The insulating layer 106 of the semiconductor device 100 functions as a back-gate insulating layer of the transistor 10_1 and the transistor 10_2 and as a dielectric of the capacitor of the liquid crystal element 30. With this structure, the manufacturing process can be significantly simplified and manufacturing costs can be reduced compared to when these layers are formed separately. Furthermore, the number of required interlayer insulating films can be reduced, which can reduce scattering of light from a backlight, improve power efficiency, and reduce power consumption.

[0249] Here, the pixel electrode of the liquid crystal element 30 is required to have light-transmitting properties. Therefore, it is preferable to use a conductor that transmits visible light for the conductive layer 112b1 and the conductive layer 112b2 of the semiconductor device 100. For example, conductive oxides such as indium oxide, zinc oxide, In—Sn oxide, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn oxide containing silicon, and zinc oxide doped with gallium can be used. In particular, conductive oxides containing indium are preferable because of their high conductivity.

[0250] In addition, a capacitor electrode having a region overlapping with the pixel electrode is also required to have light-transmitting properties. Therefore, a conductor that transmits visible light is preferably used for the conductive layer 104 of the semiconductor device 100. For example, the light-transmitting conductive material that can be used for the conductive layer 112b1 and the conductive layer 112b2 described above can be used.

[0251] A colored layer 43, a light-shielding layer 44, an insulating layer 45, a conductive layer 32, and an alignment film 42 are provided on the surface of the substrate 12 facing the substrate 102. The alignment film 42 may have a portion that contacts the alignment film 41 in a portion that overlaps with the insulating layer 46. Note that either or both of the alignment films 41 and 42 may not be provided if they are not required.

[0252] The portion where the light-shielding layer 44 is provided becomes a non-light-emitting region. In one embodiment of the present invention, the light-shielding layer 44 can be provided in a region that covers the semiconductor device 100. In one embodiment of the present invention, there are no contact holes that connect the pixel electrode and the transistors (transistors 10_1 and 10_2) included in the semiconductor device 100, and therefore the area of ​​the non-light-emitting region where the light-shielding layer 44 is provided can be significantly reduced compared to conventional cases.

[0253] The colored layer 43 can also be called a color filter, and converts light from a light source such as a backlight into light exhibiting a specific color. For example, by applying colored layers 43 corresponding to red, green, and blue to each pixel (sub-pixel) as a colored layer, a full-color display can be achieved. Note that providing pixels (sub-pixels) corresponding to colors such as yellow and white in addition to these three colors is preferable because it reduces power consumption. In the case of white pixels, a configuration in which a color filter is not provided for the pixel may be adopted.

[0254] Alternatively, blue or purple light may be used as the light source, and a color conversion material that converts the blue or purple light into another color (e.g., red, green, etc.) may be applied to the colored layer 43. The color conversion material may be a fluorescent material, a phosphorescent material, or a resin material in which quantum dots are dispersed. In this case, it is preferable that the colored layer 43 has a laminated structure of a color conversion material and a color filter from the backlight side so as to absorb light that has passed through the color conversion material.

[0255] The insulating layer 45 functions as an overcoat that prevents components contained in the colored layer 43 and the like from diffusing into the liquid crystal 33. The insulating layer 45 also functions as a planarizing film. The insulating layer 45 can be formed using a light-transmitting organic resin.

[0256] The conductive layer 32 functioning as a common electrode is required to have a light-transmitting property. For example, the conductive layer 32 can be made of any of the light-transmitting conductive materials that can be used for the conductive layer 112b1, the conductive layer 112b2, and the conductive layer 104.

[0257] The substrate 102 and the substrate 12 are bonded together by an adhesive layer (not shown) provided outside the display section. The distance between the substrate 102 and the substrate 12 is controlled by an insulating layer 46 that functions as a spacer.

[0258] Here, the liquid crystal element 30 is shown to have pixel electrodes disposed on the substrate 102 side, and an electric field applied to the liquid crystal 33 in a direction perpendicular to the thickness direction. However, the electrode arrangement method is not limited to this, and a method of applying an electric field to the liquid crystal 33 in a direction parallel to the thickness direction may also be used.

[0259] The liquid crystal element 30 may be of various configurations. Typical examples include a VA (Vertical Alignment) mode, an FFS (Fringe Field Switching) mode, and an IPS (In-Plane Switching) mode. By applying the liquid crystal element to a display device, a transmissive liquid crystal display device can be formed. Furthermore, the liquid crystal display device may be not only a transmissive type but also a reflective type or a semi-transmissive type.

[0260] Examples of VA modes that can be used in the liquid crystal element 30 include a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, and an advanced super view (ASV) mode.

[0261] In addition to the above, liquid crystal elements employing various modes may be used for the liquid crystal element 30. For example, liquid crystal elements employing a twisted nematic (TN) mode, an axially symmetric aligned micro-cell (ASM) mode, an optically compensated birefringence (OCB) mode, a ferroelectric liquid crystal (FLC) mode, an antiferroelectric liquid crystal (AFLC) mode, an electrically controlled birefringence (ECB) mode, a guest-host mode, etc. may be used.

[0262] Here, a liquid crystal display device is a display device that controls the transmission or non-transmission of light by utilizing the optical modulation effect of polarized light and liquid crystals. The optical modulation effect of liquid crystals is controlled by an electric field (including a horizontal electric field, a vertical electric field, or an oblique electric field) applied to the liquid crystal. Liquid crystals that can be used in liquid crystal elements include thermotropic liquid crystals, low-molecular-weight liquid crystals, polymer liquid crystals, polymer-dispersed liquid crystals (PDLC), polymer network liquid crystals (PNLC), ferroelectric liquid crystals, and antiferroelectric liquid crystals. These liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, and the like, depending on the conditions. Furthermore, either positive or negative liquid crystals may be used as the liquid crystal material, and the optimal liquid crystal material may be used depending on the mode or design to be applied.

[0263] 9B, in the case of a transmissive liquid crystal display, a polarizing plate is provided on each of the outer surfaces of the substrate 102 and the substrate 12. Furthermore, a backlight is provided outside the substrate 102. In this case, the substrate 12 side becomes the display surface side.

[0264] Here, by using a light-blocking conductive material for either the conductive layer 112a or the conductive layer 104, light reaching the channel formation regions of the transistors (transistors 10_1 and 10_2) included in the semiconductor device 100 can be blocked, thereby improving the reliability of the transistors. In particular, fluctuations in threshold voltage in an NBTIS test can be reduced. Of the conductive layer 112a and the conductive layer 104, at least the conductive layer on the backlight side is preferably formed using a light-blocking conductive material.

[0265] With such a structure, the display device of one embodiment of the present invention can be a liquid crystal display device with an extremely high aperture ratio.

[0266] The transistors 10_1 and 10_2 included in the semiconductor device 100 can be applied to transistors connected to pixel electrodes of pixels. The transistors 10_1 and 10_2 included in the semiconductor device 100 can also be applied to a scan line driver circuit, a signal line driver circuit, a protection circuit, and other circuits other than pixel circuits.

[0267] As described above, the semiconductor device according to one embodiment of the present invention can be applied to, for example, a display device. The semiconductor device according to one embodiment of the present invention has a configuration in which two vertical transistors that share some of their components (such as one of a source electrode or a drain electrode, a semiconductor layer, etc.) are provided facing each other. Therefore, by narrowing the gap between the transistors, higher integration of the transistors within a substrate surface can be achieved compared to forming multiple vertical transistors each having individual components. For example, by using a conventional exposure apparatus (minimum line width of approximately 1.5 μm or 1.25 μm) for mass production of flat panel displays, linear openings can be formed in layers stacked on a conductive layer (e.g., three layers: an insulating layer, a conductive layer, and an insulating layer), and two vertical transistors can be formed using the depth direction of opposing sidewalls of the openings as the channel length direction. This can significantly narrow the gap between the two vertical transistors. This allows for a very small and highly integrated semiconductor device. Therefore, by applying a semiconductor device having the two vertical transistors to a display device, a resolution of, for example, 2000 ppi or higher can be achieved.

[0268] <Example of Manufacturing Method of Semiconductor Device> A method for manufacturing a semiconductor device according to one embodiment of the present invention will be described below with reference to the drawings. Here, the semiconductor device 100 shown in FIGS. 1A to 2B is used as an example.

[0269] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0270] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used when depositing insulating films, while DC sputtering is mainly used when depositing metal conductive films. Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, or carbides using reactive sputtering.

[0271] CVD methods can be classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, photo-CVD (photo-CVD) methods that utilize light, etc. Furthermore, CVD methods can be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0272] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can reduce plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, or elements included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0273] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0274] The CVD and ALD methods differ from sputtering methods in that particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio, for example. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0275] Furthermore, the CVD method allows deposition of a film of any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film whose composition changes continuously by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0276] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0277] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by methods such as spin coating, dipping, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife coating, slit coating, roll coating, curtain coating, and knife coating.

[0278] When processing a thin film that constitutes a semiconductor device, it can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0279] There are two typical photolithography methods: one is a method in which a resist mask is formed on a thin film to be processed, the thin film is processed by etching or the like, and the resist mask is then removed; the other is a method in which a photosensitive thin film is formed, and then the thin film is exposed to light and developed to be processed into a desired shape.

[0280] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0281] For etching the thin film, for example, dry etching, wet etching, or sandblasting can be used.

[0282] 10A to 18D are diagrams illustrating a method for manufacturing the semiconductor device 100. A in each figure shows a plan view corresponding to FIG. 1A. B in each figure shows a cross-sectional view taken along dashed line A1-A2 in the plan view shown in FIG. 1A. C in each figure shows a cross-sectional view taken along dashed line B1-B2 in the plan view shown in FIG. 1A. D in each figure shows a cross-sectional view taken along dashed line C1-C2 in the plan view shown in FIG. 1A.

[0283] First, a conductive film that will become the conductive layer 112a is formed over the substrate 102, and then part of the conductive film is removed to form the conductive layer 112a (FIGS. 10A to 10D). The conductive film can be formed by, for example, a sputtering method. The conductive film can be processed by one or both of a wet etching method and a dry etching method.

[0284] Subsequently, an insulating film 110a1f is formed on the conductive layer 112a and the substrate 102, an insulating film 110a2f is formed on the insulating film 110a1f, and an insulating film 110a3f is formed on the insulating film 110a2f.

[0285] The insulating films 110a1f and 110a3f can be formed using any of the materials that can be used for the insulating layers 110a1 and 110a3 described above.

[0286] For the insulating film 110a1f and the insulating film 110a3f, for example, silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, or the like can be suitably used.

[0287] Specifically, the insulating films 110a1f and 110a3f can be formed by, for example, a silicon nitride film by a sputtering method, a PEALD method, or an aluminum oxide film by a sputtering method.

[0288] Alternatively, for example, a structure in which aluminum oxide and silicon nitride are stacked can be used, for example, a structure in which aluminum oxide formed by sputtering and silicon nitride formed by PEALD are stacked.

[0289] The insulating film 110a2f can be formed using any of the materials that can be used for the insulating layer 110a2 described above.

[0290] For example, silicon oxide, silicon oxynitride, or the like can be suitably used as the insulating film 110a2f.

[0291] Specifically, the insulating film 110a2f can be formed by, for example, a silicon oxide film by a sputtering method, a silicon oxide film by a PECVD method, or a silicon oxynitride film by a PECVD method.

[0292] Alternatively, for example, a silicon oxide film formed by sputtering and a silicon oxide or silicon oxynitride film formed by PECVD can be stacked and used.

[0293] After the insulating film 110a2f is formed, heat treatment may be performed. By performing the heat treatment, water and hydrogen can be released from the surface and the interior of the insulating film 110a2f.

[0294] The temperature of the heat treatment is preferably 150° C. or higher and lower than the strain point of the substrate, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, and further preferably 350° C. or higher and 400° C. or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA: Clean Dry Air) may be used. Note that the atmosphere preferably contains as little hydrogen, water, or the like as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower. Using an atmosphere containing as little hydrogen, water, or the like as possible can prevent hydrogen, water, or the like from being taken into the insulating film 110a2f as much as possible. For the heat treatment, for example, an oven or a rapid thermal annealing (RTA) device can be used. By using an RTA device, the heat treatment time can be shortened.

[0295] After the heat treatment, a step of supplying oxygen to the insulating film 110a2f may be performed. For example, after the insulating film 110a2f is formed, a metal oxide layer may be formed on the insulating film 110a2f to supply oxygen to the insulating film 110a2f. Alternatively, heat treatment may be performed after the metal oxide layer is formed. By performing heat treatment after the metal oxide layer is formed, oxygen can be effectively supplied from the metal oxide layer to the insulating film 110a2f, and oxygen can be contained in the insulating film 110a2f. In a later step, the oxygen supplied to the insulating film 110a2f is supplied to the semiconductor layer 108, thereby forming oxygen vacancies (VＯ ) and V Ｏ H can be reduced.

[0296] After the metal oxide layer is formed or after the heat treatment, oxygen may be supplied to the insulating film 110a2f through the metal oxide layer. Examples of a method for supplying oxygen include ion implantation, ion doping, plasma immersion ion implantation, and plasma treatment. For the plasma treatment, an apparatus that converts oxygen gas into plasma using high-frequency power can be preferably used. Examples of apparatus that convert gas into plasma using high-frequency power include a plasma etching apparatus and a plasma ashing apparatus.

[0297] The metal oxide layer may be an insulating layer or a conductive layer, and may be, for example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO).

[0298] For the metal oxide layer, it is preferable to use an oxide material containing one or more elements that are the same as those of the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material that can be used for the semiconductor layer 108.

[0299] When a metal oxide material containing indium and gallium is used for the metal oxide layer, a material having a higher gallium content than the semiconductor layer 108 can be used. By using a material having a higher gallium content for the metal oxide layer, the blocking property against oxygen can be further improved. This is preferable because oxygen supplied to the insulating film 110a2f can be prevented from being released to the outside through the metal oxide layer.

[0300] The metal oxide layer is preferably formed in an atmosphere containing oxygen, for example. In particular, it is preferably formed by a sputtering method in an atmosphere containing oxygen. This allows oxygen to be suitably supplied to the insulating film 110a2f during the formation of the metal oxide layer.

[0301] Subsequently, the metal oxide layer is removed, for example, by wet etching.

[0302] The process of supplying oxygen to the insulating film 110a2f is not limited to the above-described method. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, or the like may be supplied to the insulating film 110a2f by ion doping, ion implantation, plasma treatment, or the like. Alternatively, a film that suppresses oxygen desorption may be formed over the insulating film 110a2f, and then oxygen may be supplied to the insulating film 110a2f through the film. The film is preferably removed after supplying oxygen. The film that suppresses oxygen desorption may be a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungsten.

[0303] Next, a conductive film 116f is formed over the insulating film 110a3f (FIGS. 11A to 11D). The conductive film 116f can be formed by, for example, a sputtering method.

[0304] Next, the conductive film 116f is processed to form a conductive layer 116e over the insulating film 110a3f so as to have a region overlapping with the conductive layer 112a (FIGS. 12A to 12D). The conductive layer 116e can be formed by, for example, wet etching.

[0305] Subsequently, an insulating film 110b3f is formed on the insulating film 110a3f and the conductive layer 116e, an insulating film 110b2f is formed on the insulating film 110b3f, and an insulating film 110b1f is formed on the insulating film 110b2f.

[0306] The insulating film 110b2f can be formed using any of the materials that can be used for the insulating layer 110b2 described above. The insulating films 110b1f and 110b3f can be formed using any of the materials that can be used for the insulating layer 110b1 and the insulating layer 110b3 described above.

[0307] For materials that can be used for and a deposition method of the insulating film 110b2f, the description of the insulating film 110a2f can be referred to. For materials that can be used for and a deposition method of the insulating film 110b1f and the insulating film 110b3f, the descriptions of the insulating films 110a1f and 110a3f can be referred to.

[0308] Note that after the insulating film 110b2f is formed, a step of supplying oxygen to the insulating film 110b2f may be performed. For this step, the above description of the step of supplying oxygen to the insulating film 110a2f can be referred to.

[0309] Next, a conductive film 112bf is formed over the insulating film 110b1f (FIGS. 13A to 13D). The conductive film 112bf can be formed by, for example, a sputtering method. The conductive film 112bf can be formed using any of the materials that can be used for the conductive layer 112b1 and the conductive layer 112b2 described above.

[0310] Next, the conductive film 112bf is processed to form a conductive layer 112be (FIGS. 14A to 14D). The conductive layer 112be is formed to have a region overlapping with the conductive layer 116e and the conductive layer 112a. For example, wet etching can be suitably used to form the conductive layer 112be.

[0311] Next, portions of the conductive layer 112be, the insulating film 110b1f, the insulating film 110b2f, the insulating film 110b3f, the conductive layer 116e, the insulating film 110a3f, the insulating film 110a2f, and the insulating film 110a1f are removed to form an opening 143 that reaches the conductive layer 112a and the substrate 102 ( FIGS. 15A to 15D ). The opening 143 is formed in a line shape in a direction parallel to the dashed dotted line B1-B2 in plan view. As a result, the conductive layers 112b1 and 112b2 are formed from the conductive layer 112be, the insulating layer 110b1 is formed from the insulating film 110b1f, the insulating layer 110b2 is formed from the insulating film 110b2f, the insulating layer 110b1 is formed from the insulating film 110b1f, the conductive layers 116_1 and 116_2 are formed from the conductive layer 116e, the insulating layer 110a3 is formed from the insulating film 110a3f, the insulating layer 110a2 is formed from the insulating film 110a2f, and the insulating layer 110a1 is formed from the insulating film 110a1f. For example, dry etching can be suitably used to form the opening 143.

[0312] 1B and other drawings show an example in which the bottom of the opening 143 is flush with the top surface of the conductive layer 112a; however, this is not limited to this embodiment of the present invention. For example, the conductive layer 112a may have a recess in a region overlapping with the opening 143. This allows the semiconductor layer 108 and the conductive layer 104 to be provided even in the recess, thereby strengthening the electric field of the back gate electrode applied to the semiconductor layer 108 near the conductive layer 112a. This allows the on-state current of the transistors 10_1 and 10_2 to be increased. For example, when forming the opening 143, etching is performed so that part of the top surface of the conductive layer 112a is removed, thereby forming the conductive layer 112a having the recess.

[0313] Subsequently, an insulating film 110sf is formed so as to cover the opening 143 ( FIGS. 16A to 16D ). The insulating film 110sf is provided in contact with the top surface of the conductive layer 112b1, the top surface of the conductive layer 112b2, the side surface of the conductive layer 112b1 in the opening 143, the side surface of the conductive layer 112b2 in the opening 143, the side surface of the insulating layer 110 (insulating layer 110a and insulating layer 110b) in the opening 143, the side surface of the conductive layer 116_1 in the opening 143, the side surface of the conductive layer 116_2 in the opening 143, the top surface of the conductive layer 112a in the opening 143, the side surface of the conductive layer 112a in the opening 143, and the top surface of the substrate 102 in the opening 143.

[0314] The insulating film 110sf can be formed using any of the materials that can be used for the insulating layer 110s1 and the insulating layer 110s2 described above.

[0315] By forming the insulating film 110sf using a CVD method, an ALD method, or the like, the insulating film 110sf can be favorably coated on the sidewall of the opening 143, which is preferable.

[0316] Subsequently, a portion of the insulating film 110sf is removed by etching to form insulating layers 110s1 and 110s2 ( FIGS. 17A to 17D ). Specifically, the insulating film 110sf is etched away from the upper surface of the conductive layer 112a, the upper surface of the conductive layer 112b1, the upper surface of the conductive layer 112b2, and the upper surface of the substrate 102. This removes the insulating film 110sf from the upper surface of the substrate 102, thereby forming an insulating layer 110s1 that contacts the side surface of the conductive layer 112b1 in the opening 143, one side surface of the insulating layer 110 (the insulating layer 110a and the insulating layer 110b) in the opening 143, and the side surface of the conductive layer 116_1 in the opening 143, and an insulating layer 110s2 that contacts the side surface of the conductive layer 112b2 in the opening 143, the other side surface of the insulating layer 110 in the opening 143, and the side surface of the conductive layer 116_2 in the opening 143.

[0317] The insulating film 110sf can be etched by, for example, anisotropic etching. More specifically, the insulating layer 110s1 and the insulating layer 110s2 can be formed by, for example, performing highly anisotropic dry etching.

[0318] Although not shown, depending on the etching conditions for the insulating film 110sf, part of the insulating film 110sf may remain on the side surfaces of the steps of the conductive layers 112b1 and 112b2 outside the opening 143.

[0319] Subsequently, a semiconductor film to become the semiconductor layer 108 is formed so as to cover the opening 143. The semiconductor film is provided in contact with the upper surface and side surfaces of the conductive layer 112a in the opening 143, the upper surface of the substrate 102 in the opening 143, the side surfaces of the insulating layer 110s1 in the opening 143, the side surfaces of the insulating layer 110s2 in the opening 143, the curved portions of the insulating layer 110s1, the curved portions of the insulating layer 110s2, the upper surface and side surfaces of the conductive layer 112b1, the upper surface and side surfaces of the conductive layer 112b2, and the upper surface of the insulating layer 110.

[0320] The semiconductor film that becomes the semiconductor layer 108 is preferably formed by a sputtering method using a metal oxide target. Alternatively, the semiconductor film is preferably formed by an ALD method. The ALD method has high coverage and is therefore suitable for forming the semiconductor film that covers the opening 143. By using the ALD method, the semiconductor film can be formed with good coverage also on the side surfaces of the insulating layer 110s1 and the insulating layer 110s2. Furthermore, the ALD method allows for easy control of the film formation rate, making it possible to form a thin film with a high yield.

[0321] The semiconductor film to be the semiconductor layer 108 is preferably a dense film with as few defects as possible. Furthermore, the semiconductor film is preferably a high-purity film in which impurities including hydrogen elements are reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the semiconductor film.

[0322] Oxygen gas is preferably used when forming a semiconductor film to be the semiconductor layer 108. By using oxygen gas, oxygen can be suitably supplied to the insulating layers 110s1 and 110s2. For example, when oxide or oxynitride is used for the insulating layers 110s1 and 110s2, oxygen can be suitably supplied to the insulating layers 110s1 and 110s2.

[0323] By supplying oxygen to the insulating layer 110s1 and the insulating layer 110s2, oxygen is supplied to the channel formation region of the semiconductor layer 108 in a later step, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0324] When forming a semiconductor film to be the semiconductor layer 108, oxygen gas and an inert gas (e.g., helium gas, argon gas, xenon gas, or the like) can be mixed. Note that when a metal oxide film is used as the semiconductor film, the crystallinity of the metal oxide film can be improved as the oxygen flow rate ratio of the deposition gas or the oxygen partial pressure in the treatment chamber when forming the metal oxide film increases, and a highly reliable transistor can be realized. On the other hand, the crystallinity of the metal oxide film can be reduced as the oxygen flow rate ratio or the oxygen partial pressure decreases, and the metal oxide film can have high electrical conductivity, resulting in a transistor with high on-state current.

[0325] Here, if the oxygen flow rate ratio or oxygen partial pressure is high, the metal oxide film may become a polycrystalline structure. In the case of a polycrystalline metal oxide film, crystal grain boundaries become recombination centers, and carriers are captured, which may reduce the on-state current of the transistor. Therefore, it is preferable to adjust the oxygen flow rate ratio or oxygen partial pressure so that the semiconductor film to be the semiconductor layer 108 does not become a polycrystalline structure. Since the ease with which a metal oxide film becomes a polycrystalline structure varies depending on the composition of the metal oxide film, the oxygen flow rate ratio or oxygen partial pressure may be adjusted depending on the composition of the semiconductor film.

[0326] The higher the substrate temperature during formation of the metal oxide film, the higher the crystallinity and density of the resulting metal oxide film, whereas the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the resulting metal oxide film.

[0327] The substrate temperature during the formation of the semiconductor film to be the semiconductor layer 108 is preferably from room temperature to 250° C., more preferably from room temperature to 200° C., and further preferably from room temperature to 140° C. For example, it is preferable to set the substrate temperature to from room temperature to 140° C., as this increases productivity. Furthermore, by setting the substrate temperature to room temperature or forming the semiconductor film without heating the substrate, the crystallinity can be reduced.

[0328] If the substrate temperature is high, the metal oxide film may have a polycrystalline structure. It is preferable to adjust the substrate temperature so that the semiconductor film to be the semiconductor layer 108 does not have a polycrystalline structure. The substrate temperature may be adjusted depending on the composition applied to the semiconductor film.

[0329] When the ALD method is used, it is preferable to use a film formation method such as a thermal ALD method or a PEALD (Plasma Enhanced ALD) method. The thermal ALD method is preferable because it exhibits extremely high coverage. The PEALD method is preferable because it not only exhibits high coverage but also allows low-temperature film formation.

[0330] The metal oxide film can be formed by, for example, the ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0331] For example, when forming an In—Ga—Zn oxide, three precursors, an indium-containing precursor, a gallium-containing precursor, and a zinc-containing precursor, or two precursors, an indium-containing precursor, and a gallium- and zinc-containing precursor, can be used.

[0332] Examples of indium-containing precursors include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amido]-indium.

[0333] Gallium-containing precursors include, for example, trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, and diethylchlorogallium.

[0334] Precursors containing aluminum include, for example, aluminum chloride and trimethylaluminum.

[0335] Tin-containing precursors include, for example, tin(IV) chloride and tetrakis(dimethylamido)tin.

[0336] Precursors containing zinc include, for example, dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.

[0337] Oxidizing agents include, for example, ozone, oxygen, and water.

[0338] Methods for controlling the composition of the resulting film include adjusting one or more of the types of source gases, the flow rate ratio of the source gases, the time for which the source gases are flowed, and the order in which the source gases are flowed. By adjusting these, the composition of the semiconductor film that will become the semiconductor layer 108 can be controlled. Furthermore, by adjusting these, a film whose composition changes continuously can be formed. A configuration in which the composition of the semiconductor film changes continuously can also be achieved.

[0339] Before forming a semiconductor film to be the semiconductor layer 108, it is preferable to perform at least one of a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surfaces of the insulating layers 110s1 and 110s2 and a treatment for supplying oxygen to the insulating layers 110s1 and 110s2. For example, heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, plasma treatment can be performed in an atmosphere containing oxygen. Alternatively, dinitrogen monoxide (N ２By performing plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (NO), oxygen can be supplied to the insulating layers 110s1 and 110s2. By performing plasma treatment containing nitrous oxide gas, oxygen can be supplied to the insulating layers 110s1 and 110s2 while suitably removing organic substances from the surfaces of the insulating layers 110s1 and 110s2. After such treatment, it is preferable to continuously form a semiconductor film that becomes the semiconductor layer 108 without exposing the surfaces of the insulating layers 110s1 and 110s2 to the atmosphere.

[0340] When the semiconductor layer 108 has a stacked structure, it is preferable to deposit a semiconductor film first and then deposit a subsequent semiconductor film without exposing the surface of the first semiconductor film to the air.

[0341] When the semiconductor layer 108 has a stacked structure, all layers constituting the semiconductor layer 108 can be formed by the same film formation method (for example, sputtering or ALD). Alternatively, different film formation methods can be used for different layers. For example, the first semiconductor layer can be formed by sputtering, and the second semiconductor layer on the first semiconductor layer can be formed by ALD. Alternatively, for example, the first semiconductor layer can be formed by ALD, the second semiconductor layer on the first semiconductor layer can be formed by sputtering, and the third semiconductor layer on the second semiconductor layer can be formed by ALD.

[0342] Next, the semiconductor film that becomes the semiconductor layer 108 is processed into an island shape to form the semiconductor layer 108 ( FIGS. 18A to 18D ). The semiconductor layer 108 is formed to have regions that overlap with the conductive layers 112a, 112b1, and 112b2 within the opening 143. The semiconductor layer 108 is provided in contact with the top and side surfaces of the conductive layer 112a within the opening 143, the top surface of the substrate 102 within the opening 143, the side surfaces of the insulating layer 110s1 within the opening 143, the side surfaces of the insulating layer 110s2 within the opening 143, the curved portions of the insulating layer 110s1, the curved portions of the insulating layer 110s2, the top and side surfaces of the conductive layer 112b1, the top and side surfaces of the conductive layer 112b2, and the top surface of the insulating layer 110.

[0343] A wet etching method can be suitably used for forming the semiconductor layer 108. At this time, parts of the substrate 102, the insulating layer 110, the conductive layer 112b1, and the conductive layer 112b2 that do not overlap with the semiconductor layer 108 may be etched and become thin. Note that in etching the semiconductor film that becomes the semiconductor layer 108, using materials with high selectivity for the substrate 102, the insulating layer 110, the conductive layer 112b1, and the conductive layer 112b2 can prevent the thicknesses of these layers from becoming thin, which is preferable.

[0344] Heat treatment is preferably performed after the semiconductor film that becomes the semiconductor layer 108 is formed or after the semiconductor film is processed into the semiconductor layer 108. The heat treatment can remove hydrogen and water contained in the semiconductor film or the semiconductor layer 108 or adsorbed on the surface. Furthermore, the heat treatment may improve the film quality of the semiconductor film or the semiconductor layer 108 (for example, reduce defects or improve crystallinity).

[0345] By the heat treatment, oxygen can also be supplied from the insulating layer 110s1 and the insulating layer 110s2 to the semiconductor film to be the semiconductor layer 108 or to the semiconductor layer 108. As a result, oxygen vacancies (V Ｏ ) can be reduced. In this case, it is more preferable to perform heat treatment before processing the semiconductor film that will become the semiconductor layer 108 into the semiconductor layer 108. The above description can be referred to for the heat treatment, and detailed description thereof will be omitted. Note that oxygen may be supplied to the channel formation region in a step in which heat is applied after the formation of the semiconductor film that will become the semiconductor layer 108 (for example, a step in which the insulating layer 106 is formed).

[0346] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be combined with a heat treatment performed in a later step. Furthermore, a high-temperature treatment in a later step (e.g., a film formation step) may also serve as this heat treatment.

[0347] Subsequently, the insulating layer 106 is formed to cover the semiconductor layer 108, the conductive layer 112b1, the conductive layer 112b2, the insulating layer 110, the conductive layer 112a, and the substrate 102. The insulating layer 106 can be formed by, for example, a PECVD method or an ALD method.

[0348] When a metal oxide is used for the semiconductor layer 108, the insulating layer 106 preferably functions as a barrier film that suppresses oxygen diffusion. When the insulating layer 106 has a function of suppressing oxygen diffusion, oxygen contained in the semiconductor layer 108 is suppressed from diffusing above the insulating layer 106, and oxygen vacancies (V Ｏ As a result, the transistors 10_1 and 10_2 can be realized which have favorable electrical characteristics and high reliability.

[0349] By increasing the temperature during the formation of the insulating layer 106, the insulating layer 106 can be formed with fewer defects. However, if the temperature during the formation of the insulating layer 106 is high, oxygen is released from the semiconductor layer 108, and oxygen vacancies (V Ｏ ) and V Ｏ H may increase. The substrate temperature during the formation of the insulating layer 106 is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, and further preferably 300° C. or higher and 400° C. or lower. Setting the substrate temperature during the formation of the insulating layer 106 within the above range can reduce defects in the insulating layer 106 and suppress oxygen detachment from the semiconductor layer 108. Therefore, the transistors 10_1 and 10_2 exhibiting favorable electrical characteristics and high reliability can be realized.

[0350] Before forming the insulating layer 106, plasma treatment can be performed on the surface of the semiconductor layer 108. The plasma treatment can reduce impurities (e.g., water) adsorbed to the surface of the semiconductor layer 108. Therefore, impurities at the interface between the semiconductor layer 108 and the insulating layer 106 can be reduced, and highly reliable transistors 10_1 and 10_2 can be realized. This is particularly suitable for the case where the surface of the semiconductor layer 108 is exposed to the air between the formation of the semiconductor layer 108 and the formation of the insulating layer 106. The plasma treatment can be performed in an atmosphere containing, for example, oxygen, ozone, nitrogen, nitrous oxide, argon, or the like. The plasma treatment and the formation of the insulating layer 106 are preferably performed successively without exposure to the air.

[0351] Subsequently, a conductive film to be the conductive layer 104 is formed over the insulating layer 106. For example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method can be suitably used to form the conductive film. Here, the conductive film is preferably formed in the opening 143 so as to be in contact with the insulating layer 106 that faces the side surfaces of the insulating layer 110s1 and the insulating layer 110s2. Therefore, the conductive film is preferably formed using a film formation method that has good coverage or embedding properties, and more preferably using a CVD method, an ALD method, or the like.

[0352] Next, the conductive film to be the conductive layer 104 is processed to form the conductive layer 104. The conductive layer 104 is formed to have regions overlapping with the conductive layer 112a, the conductive layer 112b1, and the conductive layer 112b2. The conductive layer 104 may be formed by photolithography. The above processing can be performed by dry etching or wet etching. Dry etching is suitable for microfabrication.

[0353] Subsequently, an insulating layer 195 is formed to cover the conductive layer 104 and the insulating layer 106 (FIGS. 1A to 2B).

[0354] The insulating layer 195 can be formed, for example, using the same material and method as the insulating layers 110a1, 110a3, 110b1, and 110b3.

[0355] Through the above steps, the semiconductor device 100 can be manufactured.

[0356] As described above, in one embodiment of the present invention, the two transistors (the transistor 10_1 and the transistor 10_2) included in the semiconductor device 100 can be formed simultaneously using the same material and through the same process.

[0357] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0358] Embodiment 2 A semiconductor device according to one embodiment of the present invention can be applied to, for example, a display device. In this embodiment, a structural example of a display device according to one embodiment of the present invention will be described.

[0359] The display device of this embodiment can be a high-resolution display device or a large-sized display device. Therefore, the display device of this embodiment can be used in electronic devices having relatively large screens, such as television devices, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproducing devices.

[0360] The display device of the present embodiment can be a high-definition display device, and can therefore be used, for example, as a display unit for a wristwatch-type or bracelet-type information terminal (wearable device), as well as a display unit for a wearable device that can be worn on the head, such as a head-mounted display (HMD) for VR, or a glasses-type AR device.

[0361] The semiconductor device of one embodiment of the present invention can be used for a display device or a module including the display device. Examples of the module including the display device include a module in which a connector such as a flexible printed circuit board (hereinafter referred to as FPC) or a TCP is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a COG method, a COF (chip on film) method, or the like.

[0362] <Configuration Example of Display Device> FIG. 19 shows a perspective view of a display device 50 .

[0363] The display device 50 has a configuration in which a substrate 152 and a substrate 151 are bonded together. In Fig. 19, the substrate 152 is indicated by a dashed line.

[0364] The display device 50 has a display unit 162, a connection unit 140, a circuit unit 164, wiring 165, etc. Fig. 19 shows an example in which an IC 173 and an FPC 172 are mounted on the display device 50. Therefore, the configuration shown in Fig. 19 can also be said to be a display module having the display device 50, an IC, and an FPC.

[0365] The connection portion 140 is provided on the outside of the display portion 162. The connection portion 140 can be provided along one side or multiple sides of the display portion 162. The connection portion 140 may be singular or multiple. FIG. 19 shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion. The connection portion 140 connects the common electrode of the display element and the conductive layer, and can supply a potential to the common electrode. Note that the connection portion 140 does not have to be provided if it is not necessary, such as when the common electrode is provided on the substrate 151 side.

[0366] The circuit portion 164 includes, for example, a scan line driver circuit (also referred to as a gate driver). Alternatively, the circuit portion 164 may include both a scan line driver circuit and a signal line driver circuit (also referred to as a source driver).

[0367] The wiring 165 has a function of supplying signals and power to the display portion 162 and the circuit portion 164. The signals and power are input to the wiring 165 from the outside via the FPC 172 or input to the wiring 165 from the IC 173.

[0368] 19 shows an example in which an IC 173 is provided on a substrate 151 by a COG method, a COF method, or the like. For example, an IC having one or both of a scanning line driver circuit and a signal line driver circuit can be used as the IC 173. Note that the display device 50 and the display module may not include an IC. Alternatively, the IC may be mounted on an FPC by a COF method or the like.

[0369] The vertical transistor included in the semiconductor device of one embodiment of the present invention can be applied to, for example, one or both of the display portion 162 and the circuit portion 164 of the display device 50. The vertical transistor included in the semiconductor device of one embodiment of the present invention can also be applied to the IC 173. For example, the vertical transistor included in the semiconductor device of one embodiment of the present invention can be provided over a silicon wafer. In this case, it is preferable to form a circuit using two types of transistors, that is, a transistor using single crystal silicon for its semiconductor layer and a vertical transistor included in the semiconductor device of one embodiment of the present invention stacked thereover.

[0370] For example, when a vertical transistor included in a semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced compared to when a planar transistor is used, and a high-resolution display device can be obtained. Furthermore, when a vertical transistor included in a semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced compared to when a planar transistor is used, and a display device with a narrow frame can be obtained. Furthermore, since the vertical transistor included in the semiconductor device of one embodiment of the present invention has favorable electrical characteristics, the use of the vertical transistor in a display device can improve the reliability of the display device.

[0371] The display section 162 is an area in the display device 50 that displays an image, and has a plurality of periodically arranged pixels 210. Fig. 19 shows an enlarged view of one pixel 210.

[0372] The pixel arrangement in the display device of this embodiment is not particularly limited, and various methods can be applied, such as a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

[0373] 19 includes a sub-pixel 210R that emits red light, a sub-pixel 210G that emits green light, and a sub-pixel 210B that emits blue light. Each of the sub-pixels 210R, 210G, and 210B includes a display element and a circuit that controls the driving of the display element.

[0374] The display element may be, for example, a liquid crystal element, which may be, for example, a transmissive liquid crystal display device, a reflective liquid crystal display device, or a semi-transmissive liquid crystal display device.

[0375] In addition to liquid crystal elements, various elements (e.g., light-emitting elements) can be used as display elements. Examples of light-emitting elements include self-luminous light-emitting elements such as LEDs (light-emitting diodes), OLEDs (organic LEDs), and semiconductor lasers. Examples of LEDs that can be used include mini LEDs and micro LEDs.

[0376] Other examples include a shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) element, a display element that employs a microcapsule method, an electrophoresis method, an electrowetting method, or an electronic liquid powder (registered trademark) method, etc. Also, a QLED (Quantum-dot LED) that uses a light source and color conversion technology using quantum dot materials may be used.

[0377] Figure 20 shows an example of a cross section of the display device 50 when a portion of the area including the FPC 172, a portion of the circuit section 164, a portion of the display section 162, a portion of the connection section 140, and a portion of the area including the end section are cut away.

[0378] FIG. 20 is a schematic cross-sectional view of a case where a VA mode liquid crystal element is applied.

[0379] Substrate 151 and substrate 152 are bonded together by adhesive layer 141. Liquid crystal 122 is sealed in the area surrounded by substrate 151, substrate 152, and adhesive layer 141. A polarizing plate 130a is provided on the outer surface of substrate 152. A polarizing plate 130b is provided on the outer surface of substrate 151.

[0380] Although not shown, a backlight can be provided outside the polarizing plate 130a or outside the polarizing plate 130b.

[0381] The substrate 151 is provided with a semiconductor layer 108 functioning as a pixel electrode of the liquid crystal element 60, a semiconductor device 201, a plurality of semiconductor devices 202, a connection portion 204, a wiring 206, a spacer 124, and the like. The semiconductor device 100 described in the above embodiment can be applied to the semiconductor device 202. That is, the semiconductor device 202 is a semiconductor device including two vertical transistors. The semiconductor device 201 is provided in the circuit portion 164, and the semiconductor device 202 is provided in the display portion 162.

[0382] 20 illustrates a structure in which the semiconductor device 201 does not include the conductive layer 116_1 and the conductive layer 116_2 and includes a vertical transistor having a gate electrode that uses the conductive layer 104. However, the present invention is not limited to this. The semiconductor device 201 may also have a structure in which a vertical transistor having a back gate electrode formed of the same material as the conductive layer 116_1 and the conductive layer 116_2 is used.

[0383] 20 , the vertical transistor included in the semiconductor device 201 has a shorter channel length than the two vertical transistors included in the semiconductor device 202. Therefore, the vertical transistor included in the semiconductor device 201 can have a larger on-state current than the vertical transistor included in the semiconductor device 202, resulting in a display device capable of high-speed operation. Meanwhile, the vertical transistor included in the semiconductor device 201 has only one gate electrode (conductive layer 104), whereas the vertical transistor included in the semiconductor device 202 has two gate electrodes (conductive layer 116_1 and conductive layer 104, or conductive layer 116_2 and conductive layer 104). Therefore, the vertical transistor included in the semiconductor device 202 can fix the potential on the back gate electrode side of the semiconductor layer 108 more effectively than the vertical transistor included in the semiconductor device 201, thereby achieving a normally-off threshold voltage. Furthermore, variations in the electrical characteristics of the transistors included in the semiconductor device 202 can be suppressed.

[0384] The substrate 152 is provided with a colored layer 131, a light-shielding layer 132, an insulating layer 123, a common electrode 113, and the like.

[0385] Insulating layers such as insulating layer 110a1, insulating layer 110a2, insulating layer 110a3, insulating layer 110b3, insulating layer 110b2, insulating layer 110b1, insulating layer 106, and insulating layer 195 are provided over the substrate 151. The insulating layers 110a1, 110a2, 110a3, 110b3, 110b2, and 110b1 function as interlayer insulating layers (or spacers). A part of the insulating layer 106 functions as a gate insulating layer of a transistor included in the semiconductor device 201 or a transistor included in the semiconductor device 202. The insulating layer 195 functions as a protective layer for the semiconductor devices 201 and 202.

[0386] The semiconductor device 202 includes a conductive layer 112a, a conductive layer 112b1, a conductive layer 112b2, an insulating layer 110s1, an insulating layer 110s2, a conductive layer 116_1, a conductive layer 116_2, a semiconductor layer 108, part of the insulating layer 106, and a conductive layer 104. The conductive layer 112b2 of the semiconductor device 202 functions as part of a pixel electrode. The conductive layer 112a functions as one of a source electrode and a drain electrode of a transistor included in the semiconductor device 201 or a transistor included in the semiconductor device 202, and the conductive layer 112b1 and the conductive layer 112b2 function as the other of a source electrode and a drain electrode of a transistor included in the semiconductor device 201 or a transistor included in the semiconductor device 202. The insulating layer 110s1 and the insulating layer 110s2 function as gate insulating layers (first gate insulating layers) of the transistors included in the semiconductor device 202. The conductive layer 116_1 and the conductive layer 116_2 function as gate electrodes (first gate electrodes) of transistors included in the semiconductor device 202. As described above, part of the insulating layer 106 functions as a gate insulating layer (second gate insulating layer) of a transistor included in the semiconductor device 201 or a transistor included in the semiconductor device 202. The conductive layer 104 functions as a gate electrode (second gate electrode) of a transistor included in the semiconductor device 201 or a transistor included in the semiconductor device 202.

[0387] Here, the conductive layer 112a2 is provided on and in contact with the conductive layer 112a1. The conductive layer 112a2 contains a conductive material having higher conductivity than the conductive layer 112a1 and functions as an auxiliary wiring. When a conductive oxide is used for the conductive layer 112a1, the conductive layer 112a2 may have high resistance and be difficult to use as a wiring. In such a case, the conductivity of the conductive layer 112a1 can be enhanced by providing the conductive layer 112a2 having higher conductivity than the conductive layer 112a1. The stacked structure of the conductive layer 112a1 and the conductive layer 112a2 corresponds to the conductive layer 112a in the semiconductor device 100 or the like. Note that although the conductive layer 112a2 is provided on the conductive layer 112a1 here, the conductive layer 112a2 may be provided below the conductive layer 112a1. Although not shown here, similar conductive layers are preferably provided in contact with the conductive layers 112b1 and 112b2.

[0388] The liquid crystal element 60 includes a part of the conductive layer 112b2 that functions as a pixel electrode, a common electrode 113, and a liquid crystal 122 sandwiched between them.

[0389] 20 also shows cross sections of two subpixels as an example of the display unit 162. Each subpixel includes at least a semiconductor device 202, a liquid crystal element 60, and a colored layer 131. For example, a full-color display can be achieved by selectively forming the colored layer 131 to arrange subpixels that exhibit red, green, and blue. Here, a pixel circuit (subpixel circuit) is configured by the semiconductor device 202, a portion of the conductive layer 112b2 that functions as a pixel electrode, wiring, and the like.

[0390] As described above, the case where the semiconductor device 201 included in the circuit portion 164 and the semiconductor device 202 included in the display portion 162 have different structures has been described here, but they may have the same structure. Furthermore, the plurality of semiconductor devices included in the circuit portion 164 may all have the same structure, or semiconductor devices with different structures (for example, the semiconductor device 100 and any of the semiconductor devices 100A to 100F) may be used in combination.

[0391] The insulating layer 195 covering the semiconductor device 201 and the semiconductor device 202 is preferably made of a material that is difficult for impurities such as water or hydrogen to diffuse into. That is, the insulating layer 195 can function as a barrier film. With such a configuration, it is possible to effectively prevent impurities from diffusing from the outside into the semiconductor device 201 and the semiconductor device 202. Therefore, for example, when the display device 50 is applied to a touch panel, the touch panel can be made highly reliable.

[0392] On the substrate 152 side, an insulating layer 123 is provided to cover the colored layer 131 and the light-shielding layer 132. The insulating layer 123 may also function as a planarizing film. The insulating layer 123 can make the surface of the common electrode 113 approximately flat, thereby making it possible to make the alignment state of the liquid crystal 122 uniform.

[0393] Note that an alignment film for controlling the alignment of the liquid crystal 122 may be provided on the surfaces of the common electrode 113 , the insulating layer 195 , and the like that come into contact with the liquid crystal 122 .

[0394] In the liquid crystal element 60, the conductive layer 112b2 and the common electrode 113 have the function of transmitting visible light. With this configuration, a display device incorporating the liquid crystal element 60 can be a transmissive liquid crystal display device. For example, when a backlight is disposed on the substrate 152 side, light from the backlight polarized by the polarizer 130a passes through the substrate 152, the common electrode 113, the liquid crystal 122, the conductive layer 112b2, the substrate 151, and the like, and reaches the polarizer 130b. The orientation of the liquid crystal 122 can be controlled by applying a voltage between the conductive layer 112b2 and the common electrode 113, thereby controlling the optical modulation of the light. That is, the intensity of the light emitted via the polarizer 130b can be controlled. Furthermore, the colored layer 131 absorbs light outside a specific wavelength range of the incident light, so that the extracted light exhibits, for example, red light.

[0395] Here, a linear polarizer may be used as the polarizer 130b, but a circular polarizer can also be used. For example, a circular polarizer may be a laminate of a linear polarizer and a quarter-wave retardation plate. By using a circular polarizer as the polarizer 130b, it is possible to suppress reflection of external light.

[0396] When a circular polarizer is used as polarizer 130b, a circular polarizer or a normal linear polarizer may also be used as polarizer 130a. The desired contrast can be achieved by adjusting the cell gap, orientation, drive voltage, etc. of the liquid crystal element used in liquid crystal element 60 depending on the type of polarizer used for polarizers 130a and 130b.

[0397] The common electrode 113 is connected to a conductive layer provided on the substrate 151 side at the connection portion 140 by a connector 243. This allows a potential or a signal to be supplied to the common electrode 113 from an FPC or an IC arranged on the substrate 151 side.

[0398] For example, conductive particles can be used as the connectors 243. Examples of conductive particles include particles of organic resin or silica coated with a metal material. Nickel or gold is preferable as the metal material because it can reduce contact resistance. It is also preferable to use particles coated with layers of two or more metal materials, such as nickel further coated with gold. It is also preferable to use a material that undergoes elastic or plastic deformation as the connectors 243. In this case, the conductive particles may be crushed in the vertical direction, as shown in FIG. 20 . This increases the contact area between the connectors 243 and the conductive layer connected thereto, reducing contact resistance and preventing problems such as poor connection.

[0399] The connectors 243 are preferably arranged so as to be covered by the adhesive layer 141. For example, the connectors 243 may be dispersed in the adhesive layer 141 before hardening. By arranging the connectors 243 in the area where the adhesive layer 141 is provided, the connectors 243 can be similarly applied to any configuration in which the adhesive layer 141 is used in the periphery, such as a display device with a solid sealing structure or a hollow sealing structure.

[0400] A connection portion 204 is provided in a region near the end of the substrate 151. In the connection portion 204, a wiring 206 is connected to the FPC 172 through a connection layer 242. In the structure illustrated in FIG. 20 , the wiring 206 has a stacked structure similar to that of the conductive layers 112a1 and 112a2.

[0401] It is preferable to use a conductive oxide for the conductive layers 112b1 and 112b2. This makes it possible to achieve good connection characteristics with the semiconductor layer 108. Furthermore, it is preferable that the electrode connected to the connector 243 in the connection portion 140 and the electrode connected to the connection layer 242 in the connection portion 204 are formed in the same process using the same conductive film as the conductive layers 112b1 and 112b2. This makes it possible to prevent poor contact caused by the formation of an insulating coating due to oxidation of exposed portions of the connection portion 140 and the connection portion 204, and to realize a highly reliable display device.

[0402] The above is an explanation of the cross-sectional configuration example.

[0403] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0404] Embodiment 3 In this embodiment, a display device including a transistor of one embodiment of the present invention (for example, a transistor included in the semiconductor device 100 or any of the semiconductor devices 100A to 100F) will be described.

[0405] 21A includes a pixel portion 502, a driver circuit portion 504, a protective circuit 506, and a terminal portion 507. Note that the protective circuit 506 may not be provided.

[0406] The transistor of one embodiment of the present invention can be applied to the transistor included in one or both of the pixel portion 502 and the driver circuit portion 504. The transistor of one embodiment of the present invention may also be applied to the protection circuit 506.

[0407] The pixel portion 502 has a plurality of pixel circuits 501 arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more). Each pixel circuit 501 has a circuit for driving a display element.

[0408] The driver circuit portion 504 includes driver circuits such as a gate driver 504a that outputs scan signals to the gate lines GL_1 to GL_X and a source driver 504b that supplies data signals to the data lines DL_1 to DL_Y. The gate driver 504a may include at least a shift register. The source driver 504b may include a shift register, a digital-to-analog conversion circuit, a latch circuit, or the like.

[0409] The terminal section 507 is a portion provided with terminals for inputting power, control signals, image signals, etc. from an external circuit to the display device.

[0410] The protection circuit 506 is a circuit that, when a potential outside a certain range is applied to a wiring connected to the protection circuit 506, brings the wiring into a conductive state with another wiring. The protection circuit 506 shown in Fig. 21A is connected to various wirings such as a gate line GL and a data line DL. Note that in Fig. 21A, the protection circuit 506 is indicated by a hatched pattern in order to distinguish the protection circuit 506 from the pixel circuit 501.

[0411] The gate driver 504a and the source driver 504b may be provided on the same substrate as the pixel portion 502, or an IC on which a gate driver circuit or a source driver circuit is separately formed may be mounted by COG or the like on the substrate on which the pixel portion 502 is provided. Alternatively, an FPC on which an IC is mounted may be attached to the substrate by using ACF (Anisotropic Conductive Film) or the like.

[0412] In particular, the pixel portion 502 and the gate driver 504a are preferably fabricated over the same substrate and through the same process. In this case, the pixel portion 502 and the gate driver 504a are preferably provided with the transistor of one embodiment of the present invention. Furthermore, when an IC is used for the source driver 504b, it is preferable to provide a demultiplexer circuit on the substrate, because this reduces the number of terminals of the IC. In this case, the transistor of one embodiment of the present invention is preferably used for the demultiplexer circuit.

[0413] FIG. 21B shows an example of the configuration of a pixel circuit that can be applied to the pixel circuit 501.

[0414] 21B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The pixel circuit 501 is connected to a data line DL_n, a gate line GL_m, a potential supply line VL, and the like.

[0415] The vertical transistor of one embodiment of the present invention can be applied to the transistor 550. Note that FIG. 21B illustrates a structure in which the transistor 550 has two gates, one of which (the first gate) is connected to the gate line GL_m and the other of which (the second gate, back gate) is not explicitly connected. The first gate of the transistor 550 corresponds to the conductive layer 116_1 or the conductive layer 116_2 of the transistor 10_1 or the transistor 10_2 included in the semiconductor device 100 illustrated in FIG. 1B and the like, and the second gate corresponds to the conductive layer 104. Although not explicitly connected to the second gate of the transistor 550, a ground potential or any potential can be applied to the second gate as described in Embodiment 1. The second gate electrode of the transistor 550 can function as, for example, a capacitor electrode.

[0416] The potential of one of the pair of electrodes of the liquid crystal element 570 is set as appropriate according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set by written data. Note that a common potential may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Alternatively, a different potential may be applied to one of the pair of electrodes of the liquid crystal element 570 in the pixel circuit 501 in each row.

[0417] 21C includes a transistor 552, a transistor 554, a capacitor 562, and a light-emitting element 572. The pixel circuit 501 is connected to a data line DL_n, a gate line GL_m, a potential supply line VL_a, a potential supply line VL_b, and the like.

[0418] Note that a high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b, and a low power supply potential VSS is applied to the other. The current flowing through the light-emitting element 572 is controlled in accordance with the potential applied to the gate of the transistor 554, thereby controlling the luminance of light emitted from the light-emitting element 572.

[0419] The vertical transistor of one embodiment of the present invention can be applied to one or both of the transistor 552 and the transistor 554. Note that although the transistor 552 and the transistor 554 both have second gates in FIG. 21C , the connection destination of the second gates is not clearly shown. For the second gates of the transistor 552 and the transistor 554, the above description of the second gate of the transistor 550 can be referred to.

[0420] Next, a pixel circuit including a memory for correcting the gray scale displayed in the pixel and a display device having the same will be described.

[0421] 22A shows a circuit diagram of a pixel circuit 400. The pixel circuit 400 includes a transistor M1, a transistor M2, a capacitor C1, and a circuit 401. The pixel circuit 400 is connected to a wiring S1, a wiring S2, a wiring G1, and a wiring G2.

[0422] The vertical transistor of one embodiment of the present invention can be applied to the transistor M1 and the transistor M2. Note that although the transistor M1 and the transistor M2 each have a second gate in FIG. 22A , the connection destination of the second gate is not clearly shown. For the second gates of the transistor M1 and the transistor M2, the above description of the second gate of the transistor 550 can be referred to. The same applies to the transistors M1, M2, and M3 shown in FIGS. 22C and 22D .

[0423] The transistor M1 has a gate connected to the wiring G1, one of a source and a drain connected to the wiring S1, and the other connected to one electrode of the capacitor C1. The transistor M2 has a gate connected to the wiring G2, one of a source and a drain connected to the wiring S2, and the other connected to the other electrode of the capacitor C1 and the circuit 401.

[0424] The circuit 401 is a circuit including at least one display element, which is a liquid crystal element.

[0425] The node connecting the transistor M1 and the capacitor C1 is referred to as a node N1, and the node connecting the transistor M2 and the circuit 401 is referred to as a node N2.

[0426] In the pixel circuit 400, the potential of the node N1 can be maintained by turning off the transistor M1. In addition, the potential of the node N2 can be maintained by turning off the transistor M2. In addition, by writing a predetermined potential to the node N1 via the transistor M1 while the transistor M2 is in the off state, the potential of the node N2 can be changed in accordance with the change in the potential of the node N1 due to capacitive coupling via the capacitor C1.

[0427] Here, the transistor including an oxide semiconductor, as exemplified in Embodiment 1, can be used as one or both of the transistors M1 and M2. Therefore, the potential of the node N1 or the node N2 can be held for a long period of time due to an extremely low off-state current. Note that when the period for holding the potential of each node is short (specifically, when the frame frequency is 30 Hz or higher), a transistor including a semiconductor such as silicon may be used.

[0428] [Driving Method Example] Next, an example of an operating method of the pixel circuit 400 will be described with reference to Fig. 22B. Fig. 22B is a timing chart relating to the operation of the pixel circuit 400. Note that, for ease of explanation, the influence of various resistances such as wiring resistance, parasitic capacitance, transistor threshold voltage, and the like is not taken into consideration here.

[0429] 22B, one frame period is divided into a period T1 and a period T2. The period T1 is a period in which a potential is written to the node N2, and the period T2 is a period in which a potential is written to the node N1.

[0430] [Period T1] In the period T1, a potential that turns on the transistor is applied to both the wiring G1 and the wiring G2. In addition, a fixed potential V ｒｅｆ is supplied to the line S2, and the first data potential V ｗ supply.

[0431] The node N1 is connected to the wiring S1 via the transistor M1. ｒｅｆ The node N2 is supplied with a first data potential V ｗ Therefore, the potential difference V ｗ -V ｒｅｆ is maintained.

[0432] [Period T2] Subsequently, in period T2, a potential that turns on the transistor M1 is applied to the wiring G1, and a potential that turns off the transistor M2 is applied to the wiring G2. In addition, a second data potential V ｄａｔａ A predetermined constant potential may be applied to the wiring S2, or the wiring S2 may be in a floating state.

[0433] The node N1 receives a second data potential V ｄａｔａ At this time, the second data potential V ｄａｔａ In other words, the circuit 401 receives the first data potential V ｗ The potential obtained by adding the potential dV to the second data potential V is input. Note that although the potential dV is shown as a positive value in FIG. 22B, it may be a negative value. That is, the second data potential V ｄａｔａ is the potential V ｒｅｆ It may be lower.

[0434] Here, the potential dV is roughly determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 401. When the capacitance value of the capacitor C1 is sufficiently larger than the capacitance value of the circuit 401, the potential dV is equal to the second data potential V ｄａｔａ The potential is close to

[0435] In this way, the pixel circuit 400 can generate a potential to be supplied to the circuit 401 including a display element by combining two types of data signals, and therefore, it is possible to perform gradation correction within the pixel circuit 400.

[0436] The pixel circuit 400 can also generate a potential that exceeds the maximum potential that can be supplied by a source driver connected to the wirings S1 and S2. For example, when a light-emitting element is used, high dynamic range (HDR) display or the like can be performed. Furthermore, when a liquid crystal element is used, overdrive driving or the like can be realized.

[0437] 22C includes a circuit 401LC. The circuit 401LC includes a liquid crystal element LC and a capacitor C2.

[0438] The liquid crystal element LC has one electrode connected to the node N2 and one electrode of the capacitor C2, and the other electrode connected to the potential V ｃｏｍ２ The other electrode of the capacitor C2 is connected to a wiring to which a potential V ｃｏｍ１ Connect with the wiring given.

[0439] The capacitor C2 functions as a storage capacitor. Note that the capacitor C2 can be omitted if it is not required.

[0440] The pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, which makes it possible to, for example, realize high-speed display by overdriving, apply a liquid crystal material with a high driving voltage, etc. Furthermore, by supplying a correction signal to the wiring S1 or the wiring S2, it is possible to correct the gradation in accordance with the operating temperature, the deterioration state of the liquid crystal element LC, etc.

[0441] [Example Using a Light-Emitting Element] A pixel circuit 400EL shown in Fig. 22D includes a circuit 401EL. The circuit 401EL includes a light-emitting element EL, a transistor M3, and a capacitor C2.

[0442] The transistor M3 has a gate connected to the node N2 and one electrode of the capacitor C2, and a source or drain connected to the potential V Ｈ The other electrode of the capacitor C2 is connected to a wiring to which a potential V ｃｏｍ The other electrode of the light-emitting element EL is connected to a wiring to which a potential V Ｌ Connect with the wiring given.

[0443] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. The capacitor C2 functions as a storage capacitor. The capacitor C2 can be omitted if it is not necessary.

[0444] Although the anode side of the light-emitting element EL is connected to the transistor M3 in this example, the transistor M3 may be connected to the cathode side. Ｈ and potential V Ｌ The value of can be changed as appropriate.

[0445] In the pixel circuit 400EL, a large current can be passed through the light-emitting element EL by applying a high potential to the gate of the transistor M3, which makes it possible to realize, for example, HDR display, etc. Furthermore, by supplying a correction signal to the wiring S1 or the wiring S2, it is possible to correct variations in the electrical characteristics of the transistor M3, the light-emitting element EL, etc.

[0446] Note that the circuits are not limited to those illustrated in FIGS. 22C and 22D, and may be configured to include additional transistors, capacitors, and the like.

[0447] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0448] Embodiment 4 In this embodiment, a configuration example of a touch panel module including a touch panel to which the display device of one embodiment of the present invention can be applied and an IC will be described.

[0449] 23 shows a block diagram of the touch panel module 6500. The touch panel module 6500 includes a touch panel 6510 and an IC 6520.

[0450] The touch panel 6510 includes a display portion 6511, an input portion 6512, a scanning line driver circuit 6513, a sensor driver circuit 6503, and a detection circuit 6504. The display portion 6511 has a plurality of pixels, a plurality of signal lines, and a plurality of scan lines, and has a function of displaying an image. The input portion 6512 has a plurality of sensor elements that detect contact or proximity of a detectable object to the touch panel 6510, and functions as a touch sensor. The scanning line driver circuit 6513 has a function of outputting a scan signal to the scan line of the display portion 6511.

[0451] The sensor driver circuit 6503 has a function of outputting a signal for driving a sensor element included in the input portion 6512. The sensor driver circuit 6503 can be, for example, a combination of a shift register circuit and a buffer circuit.

[0452] The detection circuit 6504 has a function of amplifying an output signal from the sensor element of the input portion 6512 and outputting it to the AD conversion circuit 6507 .

[0453] Here, for ease of explanation, the configuration of the touch panel 6510 is shown as being separated into a display portion 6511 and an input portion 6512, but it may also be a so-called in-cell type touch panel that has both the function of displaying images and the function of acting as a touch sensor.

[0454] As a touch sensor type that can be used for the input unit 6512, for example, a capacitance type can be applied. The capacitance type includes a surface capacitance type, a projected capacitance type, and the like. The projected capacitance type includes a self-capacitance type, a mutual capacitance type, and the like. The mutual capacitance type is preferable because it enables simultaneous multi-point detection.

[0455] Note that, without being limited to this, various types of sensors that can detect the approach, contact, or pressure of a detection target such as a finger or a stylus can also be applied to the input portion 6512. For example, as the sensor type, in addition to the capacitance type, various types such as a resistive film type, a surface acoustic wave type, an infrared type, and an optical type can be used.

[0456] Representative in-cell touch panels include hybrid in-cell and full in-cell types. The hybrid in-cell type refers to a configuration in which electrodes constituting a touch sensor are provided on both the substrate supporting the display element and the opposing substrate, or on the opposing substrate. On the other hand, the full in-cell type refers to a configuration in which electrodes constituting a touch sensor are provided on the substrate supporting the display element. A full in-cell touch panel is preferred because it can simplify the configuration of the opposing substrate. In particular, a full in-cell type in which the electrodes constituting the display element also serve as the electrodes constituting the touch sensor is preferred because it can simplify the manufacturing process and reduce manufacturing costs.

[0457] The display unit 6511 preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels). A resolution of 4K, 8K, or higher is particularly preferable. Furthermore, the pixel density (resolution) of the pixels provided in the display unit 6511 is preferably 300 ppi or higher, preferably 500 ppi or higher, more preferably 800 ppi or higher, more preferably 1000 ppi or higher, and more preferably 1200 ppi or higher. The display unit 6511 having such high resolution and high resolution can enhance the sense of realism and depth.

[0458] The IC 6520 includes a circuit unit 6501, a signal line driver circuit 6502, and an AD conversion circuit 6507. The circuit unit 6501 includes a timing controller 6505, an image processing circuit 6506, and the like.

[0459] The signal line driver circuit 6502 has a function of outputting analog video signals to signal lines included in the display portion 6511. For example, the signal line driver circuit 6502 can have a combination of a shift register, a digital-analog converter (DAC), a latch circuit, a buffer circuit, and the like. The touch panel 6510 may also have a demultiplexer circuit connected to the signal lines.

[0460] The AD conversion circuit 6507 has a function of converting an analog signal input from the detection circuit 6504 into a digital signal and outputting the digital signal to the circuit unit 6501. For example, the AD conversion circuit 6507 can have a configuration including an amplifier circuit in addition to an analog-digital converter (ADC).

[0461] The image processing circuit 6506 of the circuit unit 6501 has the function of generating and outputting a signal that drives the display unit 6511 of the touch panel 6510, the function of generating and outputting a signal that drives the input unit 6512, and the function of analyzing the signal output from the input unit 6512 and outputting it to the CPU 6540.

[0462] As a more specific example, the image processing circuit 6506 has a function of generating a video signal in accordance with an instruction from the CPU 6540. The image processing circuit 6506 also has a function of performing signal processing on the video signal in accordance with the specifications of the display unit 6511, converting it into an analog video signal, and supplying it to the signal line driver circuit 6502. The image processing circuit 6506 also has a function of generating a drive signal to be output to the sensor driver circuit 6503 in accordance with an instruction from the CPU 6540. The image processing circuit 6506 also has a function of analyzing a signal input from the detection circuit 6504 via the AD conversion circuit 6507, and outputting it to the CPU 6540 as position information.

[0463] The timing controller 6505 has a function of generating and outputting signals (such as clock signals and start pulse signals) to be output to the scanning line driver circuit 6513 and the sensor driver circuit 6503 based on a synchronization signal included in a video signal processed by the image processing circuit 6506. The timing controller 6505 may also have a function of generating and outputting a signal that determines the timing at which the detection circuit 6504 outputs a signal. Here, the timing controller 6505 preferably outputs signals synchronized with the signals to be output to the scanning line driver circuit 6513 and the sensor driver circuit 6503. In particular, it is preferable to separate a period for rewriting pixel data in the display portion 6511 from a period for sensing in the input portion 6512. For example, one frame period can be divided into a period for rewriting pixel data and a period for sensing, thereby driving the touch panel 6510. Furthermore, for example, by providing two or more sensing periods in one frame period, detection sensitivity and detection accuracy can be improved.

[0464] The image processing circuit 6506 may have a configuration including, for example, a processor. For example, a microprocessor such as a DSP (Digital Signal Processor) or a GPU (Graphics Processing Unit) may be used. These microprocessors may also be configured as programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs) or field programmable analog arrays (FPAAs). The image processing circuit 6506 performs various data processing, program control, and the like by interpreting and executing instructions from various programs using the processor. Programs that can be executed by the processor may be stored in a memory area of ​​the processor or in a separately provided storage device.

[0465] Note that a transistor using an oxide semiconductor for a channel formation region and having extremely low off-state current is preferably used for one or more of the display portion 6511, the input portion 6512, the scanning line driver circuit 6513, the sensor driver circuit 6503, and the detection circuit 6504 included in the touch panel 6510. Since the off-state current of the transistor is extremely low, the transistor can be used as a switch for retaining charge (data) flowing into a capacitor functioning as a memory element, thereby ensuring a long data retention period. Furthermore, the transistor may be applied to the circuit unit 6501, the signal line driver circuit 6502, the AD conversion circuit 6507, the CPU 6540 provided externally, or the like included in the IC 6520. For example, by using this characteristic in the register, cache memory, etc. of the image processing circuit 6506, the image processing circuit 6506 is operated only when necessary, and at other times, the information from the previous processing is saved in the memory element, thereby enabling so-called normally-off computing, in which the power supply to the image processing circuit 6506 is cut off when not in use, thereby enabling low power consumption of the touch panel module 6500 and the electronic device in which it is implemented.

[0466] Note that, here, the circuit unit 6501 has a configuration including a timing controller 6505 and an image processing circuit 6506, but the image processing circuit 6506 itself or a circuit having part of the functions of the image processing circuit 6506 may be provided outside the IC 6520. Alternatively, the functions of the image processing circuit 6506 or part of the functions may be performed by the CPU 6540. For example, the circuit unit 6501 may have a configuration including a signal line driver circuit 6502, a timing controller 6505, and an AD conversion circuit 6507.

[0467] Although an example in which the IC 6520 includes the circuit unit 6501 has been shown here, the circuit unit 6501 may not be included in the IC 6520. In this case, the IC 6520 may include a signal line driver circuit 6502 and an AD conversion circuit 6507. For example, when a plurality of ICs are mounted on the touch panel module 6500, an IC including the circuit unit 6501 may be separately provided, and a plurality of ICs 6520 not including the circuit unit 6501 may be disposed, or the IC 6520 and an IC having only the signal line driver circuit 6502 may be combined and disposed.

[0468] In this way, by incorporating the function of driving the display portion 6511 of the touch panel 6510 and the function of driving the input portion 6512 into a single IC, the number of ICs implemented in the touch panel module 6500 can be reduced, thereby reducing costs.

[0469] 24A to 24C are schematic diagrams of a touch panel module 6500 incorporating an IC 6520.

[0470] 24A includes a substrate 6531, an opposing substrate 6532, a plurality of FPCs 6533, an IC 6520, an IC 6530, etc. A display unit 6511, an input unit 6512, a scanning line driver circuit 6513, a sensor driver circuit 6503, and a detection circuit 6504 are provided between the substrate 6531 and the opposing substrate 6532. The IC 6520 and the IC 6530 are mounted on the substrate 6531 by a mounting method such as a COG method.

[0471] The IC 6530 is an IC similar to the IC 6520 described above, which includes only the signal line driver circuit 6502 or the signal line driver circuit 6502 and the circuit unit 6501. A signal is supplied to the IC 6520 and the IC 6530 from the outside via an FPC 6533. Furthermore, a signal can be output from the IC 6520 or the IC 6530 to the outside via the FPC 6533.

[0472] 24A shows an example of a configuration in which two scanning line driver circuits 6513 are provided so as to sandwich the display portion 6511. Also shown is a configuration including an IC 6530 in addition to an IC 6520. Such a configuration can be suitably used when the display portion 6511 has extremely high resolution.

[0473] 24B shows an example in which one IC 6520 and one FPC 6533 are mounted. This is preferable because the number of components can be reduced by consolidating the functions into one IC 6520. Also, in FIG. 24B, the scanning line driver circuit 6513 is arranged along one of the two short sides of the display portion 6511 that is closer to the FPC 6533.

[0474] 24C shows an example of a configuration having a PCB (Printed Circuit Board) 6534 on which an image processing circuit 6506 and the like are mounted. An IC 6520 and an IC 6530 on a substrate 6531 are connected to the PCB 6534 by an FPC 6533. Here, a configuration not having the image processing circuit 6506 described above can be applied to the IC 6520.

[0475] 24A to 24C, the IC 6520 and the IC 6530 may be mounted on the FPC 6533 instead of the substrate 6531. For example, the IC 6520 and the IC 6530 may be mounted on the FPC 6533 by a mounting method such as the COF method or the TAB method.

[0476] 24A and 24B , a configuration in which an FPC 6533, an IC 6520 (and an IC 6530), and the like are arranged on the short side of the display portion 6511 allows for a narrower frame, and therefore can be suitably used in electronic devices such as smartphones, mobile phones, and tablet terminals. Furthermore, a configuration using a PCB 6534 as shown in Fig. 24C can be suitably used in television devices, monitor devices, tablet terminals, and notebook personal computers, for example.

[0477] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0478] Embodiment 5 In this embodiment, an electronic device according to one embodiment of the present invention will be described.

[0479] The electronic devices of this embodiment include the display device of one embodiment of the present invention in their display portions. The display device of one embodiment of the present invention can easily achieve high definition and high resolution. Therefore, the display device of one embodiment of the present invention can be used in the display portions of various electronic devices.

[0480] The semiconductor device of one embodiment of the present invention can be applied to portions other than the display portion of an electronic device. For example, the use of the semiconductor device of one embodiment of the present invention in a control portion of an electronic device is preferable because it enables low power consumption.

[0481] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0482] In particular, the display device of one embodiment of the present invention can be used in electronic devices having a relatively small display area because it can increase the resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), and head-mounted wearable devices such as VR devices (e.g., head-mounted displays), AR glasses-type devices, and MR devices.

[0483] The electronic device of this embodiment may have a sensor (including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0484] The electronic device of the present embodiment can have various functions, such as a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading out programs or data recorded on a recording medium, etc.

[0485] The electronic device 7000 shown in FIG. 25A is a portable information terminal that can be used as a smartphone.

[0486] The electronic device 7000 includes a housing 7001, a display portion 7002, a power button 7003, a button 7004, a speaker 7005, a microphone 7006, a camera 7007, and a light source 7008. The display portion 7002 has a touch panel function.

[0487] The display device of one embodiment of the present invention can be applied to the display portion 7002 .

[0488] FIG. 25B is a schematic cross-sectional view including the end of the housing 7001 on the microphone 7006 side.

[0489] A translucent protective member 7010 is provided on the display surface side of the housing 7001, and a display panel 7011, optical members 7012, a touch sensor panel 7013, a printed circuit board 7017, a battery 7018, etc. are arranged in the space surrounded by the housing 7001 and the protective member 7010.

[0490] A display panel 7011, an optical member 7012, and a touch sensor panel 7013 are fixed to the protective member 7010 by adhesive layers (not shown).

[0491] A part of the display panel 7011 is folded back in an area outside the display portion 7002, and an FPC 7015 is connected to the folded back part. An IC 7016 is mounted on the FPC 7015. The FPC 7015 is connected to a terminal provided on a printed circuit board 7017.

[0492] The display device of one embodiment of the present invention can be applied to the display panel 7011. Therefore, an extremely lightweight electronic device can be realized. Furthermore, since the display panel 7011 is extremely thin, the thickness of the electronic device can be reduced and a large-capacity battery 7018 can be mounted thereon. Furthermore, by folding back part of the display panel 7011 and arranging a connection portion with the FPC 7015 on the back side of the display portion 7002, an electronic device with a narrow frame can be realized.

[0493] 25C shows an example of a television set. A television set 7100 includes a display portion 7002 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0494] The display device of one embodiment of the present invention can be applied to the display portion 7002 .

[0495] 25C can be operated using operation switches provided on the housing 7101 and a separate remote control 7111. Alternatively, the display portion 7002 may be provided with a touch sensor, and the television set 7100 may be operated by touching the display portion 7002 with a finger or the like. The remote control 7111 may have a display portion that displays information output from the remote control 7111. Using operation keys or a touch panel provided on the remote control 7111, the channel and volume can be controlled, and an image displayed on the display portion 7002 can be controlled.

[0496] The television device 7100 is configured to include a receiver, a modem, and the like. Ordinary television broadcasts can be received using the receiver. Furthermore, by connecting to a wired or wireless communication network via the modem, it is also possible to perform one-way (from a sender to a receiver) or two-way (between a sender and a receiver, or between receivers, etc.) information communication.

[0497] 25D shows an example of a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, and an external connection port 7214. The housing 7211 includes a display portion 7002.

[0498] The display device of one embodiment of the present invention can be applied to the display portion 7002 .

[0499] 25E and 25F show an example of digital signage.

[0500] 25E includes a housing 7301, a display portion 7002, and a speaker 7303. The digital signage 7300 may further include an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0501] 25F shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7002 provided along the curved surface of the pillar 7401.

[0502] 25E and 25F, the display device of one embodiment of the present invention can be applied to the display portion 7002.

[0503] The larger the display portion 7002, the more information can be provided at one time. Also, the larger the display portion 7002, the more easily people can see it, which can improve the effectiveness of advertising, for example.

[0504] Applying a touch panel to the display portion 7002 is preferable because it not only displays images or videos on the display portion 7002 but also allows a user to intuitively operate it. Furthermore, when used to provide information such as route information or traffic information, usability can be improved by intuitive operation.

[0505] 25E and 25F , the digital signage 7300 or the digital signage 7400 is preferably capable of wirelessly linking with an information terminal 7311 or an information terminal 7411, such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7002 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. Furthermore, by operating the information terminal 7311 or the information terminal 7411, the display on the display unit 7002 can be switched.

[0506] The digital signage 7300 or the digital signage 7400 can also be made to run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller), thereby allowing an unspecified number of users to simultaneously participate in and enjoy the game.

[0507] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0508] 10_1: transistor, 10_2: transistor, 10A_1: transistor, 10A_2: transistor, 10B_1: transistor, 10B_2: transistor, 10C_1: transistor, 10C_2: transistor, 10D_1: transistor, 10D_2: transistor, 10E_1: transistor, 10E_2: transistor, 10F_1: transistor, 10F_2: transistor, 12: substrate, 30: liquid crystal element, 32: conductive layer, 33: liquid crystal, 41: alignment film, 42: alignment film, 43: colored layer, 44: light-shielding layer, 45: insulating layer, 46: insulating layer , 50: display device, 60: liquid crystal element, 100A: semiconductor device, 100B: semiconductor device, 100C: semiconductor device, 100D: semiconductor device, 100E: semiconductor device, 100F: semiconductor device, 100: semiconductor device, 102: substrate, 104: conductive layer, 106: insulating layer, 108: semiconductor layer, 110a: insulating layer, 110a1: insulating layer, 110a1f: insulating film, 110a2: insulating layer, 110a2f: insulating film, 110a3: insulating layer, 110a3f: insulating film, 110b: insulating layer, 110b1: insulating layer, 110b1f: insulating film, 110b2: insulating layer, 110b2f: insulating film, 110b3: insulating layer, 110b3f: insulating film, 110g1: insulating layer, 110g2: insulating layer, 110s1: insulating layer, 110s1a: insulating layer, 110s1b: insulating layer, 110s2: insulating layer, 110s2a: insulating layer, 110s2b: insulating layer, 110sf: insulating film, 110: insulating layer, 112a: conductive layer, 112a1: conductive layer, 112a2: conductive layer, 112b1: conductive layer, 112b2: conductive layer, 112be: conductive layer, 112bf: conductive film, 113: common electrode, 116_1: conductive layer, 116_2: conductive layer, 116e: conductive layer, 116f: conductive film, 122: liquid crystal, 12 3: insulating layer, 124: spacer, 130a: polarizing plate, 130b: polarizing plate, 131: colored layer, 132: light-shielding layer, 140: connecting portion, 141: adhesive layer, 143: opening, 151: substrate, 152: substrate, 162: display portion, 164: circuit portion, 165: wiring, 172: FPC, 173: IC, 195: insulating layer, 201: semiconductor device, 202: semiconductor device, 204: connecting portion, 206: wiring, 210B: subpixel, 210G: subpixel, 210R: subpixel, 210: pixel, 242: connecting layer, 243: connector, 400EL: pixel circuit, 400LC: pixel circuit, 400: pixel circuit,401EL: circuit, 401LC: circuit, 401: circuit, 501: pixel circuit, 502: pixel section, 504a: gate driver, 504b: source driver, 504: drive circuit section, 506: protection circuit, 507: terminal section, 550: transistor, 552: transistor, 554: transistor, 560: capacitance element, 562: capacitance element, 570: liquid crystal element, 572: light-emitting element, 6500: touch panel module 6501: circuit unit, 6502: signal line driver circuit, 6503: sensor driver circuit, 6504: detection circuit, 6505: timing controller, 6506: image processing circuit, 6507: AD conversion circuit, 6510: touch panel, 6511: display unit, 6512: input unit, 6513: scanning line driver circuit, 6520: IC, 6531: substrate, 6532: opposing substrate, 6533: FPC, 6534: PCB, 65 40: CPU, 7000: Electronic device, 7001: Housing, 7002: Display unit, 7003: Power button, 7004: Button, 7005: Speaker, 7006: Microphone, 7007: Camera, 7008: Light source, 7010: Protective member, 7011: Display panel, 7012: Optical member, 7013: Touch sensor panel, 7015: FPC, 7017: Printed circuit board, 7018: Battery, 7100: Television device Station, 7101: housing, 7103: stand, 7111: remote control device, 7200: notebook personal computer, 7211: housing, 7212: keyboard, 7213: pointing device, 7214: external connection port, 7300: digital signage, 7301: housing, 7303: speaker, 7311: information terminal device, 7400: digital signage, 7401: pillar, 7411: information terminal device,

Claims

a first transistor, a second transistor, a first insulating layer, and a second insulating layer; the first transistor has a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a third insulating layer, a fourth insulating layer, and a semiconductor layer; the second transistor includes the first conductive layer, a fifth conductive layer, a sixth conductive layer, the fourth conductive layer, a fifth insulating layer, the fourth insulating layer, and the semiconductor layer; the first insulating layer has a first region and a second region spaced apart from the first region; the second insulating layer has a third region and a fourth region spaced apart from the third region, the first conductive layer has a fifth region and a sixth region spaced apart from the fifth region, the first region, the second conductive layer, the third region, and the third conductive layer are provided on the fifth region in a superimposed manner in this order; the second region, the fifth conductive layer, the fourth region, and the sixth conductive layer are provided on the sixth region in a superimposed manner in this order; the third insulating layer is provided in contact with a side surface of the first region, a side surface of the second conductive layer, a side surface of the third region, and a side surface of the third conductive layer; the fifth insulating layer is provided in contact with a side surface of the second region, a side surface of the fifth conductive layer, a side surface of the fourth region, and a side surface of the sixth conductive layer; the semiconductor layer is provided in contact with an upper surface of the first conductive layer between the fifth region and the sixth region, a side surface of the third insulating layer, a side surface of the fifth insulating layer, an upper surface of the third conductive layer, and an upper surface of the sixth conductive layer; the fourth insulating layer is provided in contact with an upper surface and a side surface of the semiconductor layer, an upper surface and a side surface of the first conductive layer, an upper surface and a side surface of the third conductive layer, and an upper surface and a side surface of the sixth conductive layer; the fourth conductive layer is provided in contact with an upper surface of the fourth insulating layer, In the first transistor, one surface of the portion of the semiconductor layer faces a portion of the fourth conductive layer via a portion of the fourth insulating layer, and the other surface of the portion of the semiconductor layer faces the second conductive layer via the third insulating layer; In the second transistor, one surface of the other part of the semiconductor layer faces the other part of the fourth conductive layer via the other part of the fourth insulating layer, and the other surface of the other part of the semiconductor layer faces the fifth conductive layer via the fifth insulating layer. Semiconductor device. 　 In claim 1, the semiconductor layer comprises a metal oxide; the first insulating layer, the second insulating layer, the third insulating layer, and the fifth insulating layer each include one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide; Semiconductor device. 　 In claim 1 or 2, the first insulating layer includes a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer; the second insulating layer includes a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer; the sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer each include one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon oxynitride; The seventh insulating layer and the tenth insulating layer each include one or both of silicon oxide and silicon oxynitride. Semiconductor device. 　 A semiconductor device comprising: the semiconductor device according to claim 1; a first liquid crystal element; and a second liquid crystal element; the first liquid crystal element includes the third conductive layer, a liquid crystal, and a seventh conductive layer; the second liquid crystal element includes the sixth conductive layer, the liquid crystal, and the seventh conductive layer; the liquid crystal is provided on the third conductive layer or the sixth conductive layer, the seventh conductive layer is provided on the liquid crystal; Display device. 　 a first transistor, a second transistor, a first insulating layer, and a second insulating layer; the first transistor has a first conductive layer, a second conductive layer, a third conductive layer, a third insulating layer, a fourth insulating layer, and a semiconductor layer; the second transistor includes the first conductive layer, the fourth conductive layer, the third conductive layer, the fifth insulating layer, the fourth insulating layer, and the semiconductor layer; the first insulating layer has a first region and a second region spaced apart from the first region; the second insulating layer has a third region and a fourth region spaced apart from the third region, the first conductive layer has a fifth region and a sixth region spaced apart from the fifth region, the first region, the second conductive layer, and the third region are provided on the fifth region in this order and overlap each other; the second region, the fourth conductive layer, and the fourth region are provided on the sixth region in this order and overlap each other; the third insulating layer is provided in contact with a side surface of the first region, a side surface of the second conductive layer, and a side surface of the third region; the fifth insulating layer is provided in contact with a side surface of the second region, a side surface of the fourth conductive layer, and a side surface of the fourth region; the semiconductor layer is provided in contact with an upper surface of the first conductive layer between the fifth region and the sixth region, a side surface of the third insulating layer, a side surface of the fifth insulating layer, an upper surface of a portion of the second insulating layer, and an upper surface of another portion of the second insulating layer; the fourth insulating layer is provided in contact with an upper surface of the semiconductor layer, the third conductive layer is provided in contact with an upper surface of the fourth insulating layer, In the first transistor, one surface of the portion of the semiconductor layer faces a portion of the third conductive layer via a portion of the fourth insulating layer, and the other surface of the portion of the semiconductor layer faces the second conductive layer via the third insulating layer; In the second transistor, one surface of the other part of the semiconductor layer faces the other part of the third conductive layer via the other part of the fourth insulating layer, and the other surface of the other part of the semiconductor layer faces the fourth conductive layer via the fifth insulating layer. Semiconductor device. 　 In claim 5, the semiconductor layer comprises a metal oxide; the first insulating layer, the second insulating layer, the third insulating layer, and the fifth insulating layer each include one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide; Semiconductor device. 　 In claim 5 or 6, the first insulating layer includes a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer; the second insulating layer includes a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer; the sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer each include one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon oxynitride; The seventh insulating layer and the tenth insulating layer each include one or both of silicon oxide and silicon oxynitride. Semiconductor device. 　 A semiconductor device according to claim 5 or 6, and a liquid crystal element, the liquid crystal element includes the semiconductor layer, a liquid crystal, and a fifth conductive layer; The liquid crystal is provided on the semiconductor layer, the fifth conductive layer is provided on the liquid crystal; Display device. 　 forming a first conductive layer; forming a first insulating film and a first conductive film in this order on the first conductive layer; processing the first conductive film to form a second conductive layer in a region overlapping the first conductive layer; forming a second insulating film and a second conductive film in this order on the first insulating film and the second conductive layer; processing the second conductive film to form a third conductive layer having an area overlapping the first conductive layer and the second conductive layer; removing a portion of each of the first insulating film, the second conductive layer, the second insulating film, and the third conductive layer to form an opening reaching the first conductive layer, and forming a first insulating layer from the first insulating film, a fourth conductive layer and a fifth conductive layer from the second conductive layer, a second insulating layer from the second insulating film, and a sixth conductive layer and a seventh conductive layer from the third conductive layer; forming a third insulating film in contact with an upper surface and a side surface of the first conductive layer in the opening, a side surface of the first insulating layer in the opening, a side surface of the second insulating layer in the opening, a side surface of the fourth conductive layer in the opening, a side surface of the fifth conductive layer in the opening, a side surface of the sixth conductive layer in the opening, a side surface of the seventh conductive layer in the opening, an upper surface of the sixth conductive layer, and an upper surface of the seventh conductive layer; a portion of the third insulating film is removed to form a third insulating layer in contact with one side surface of the first insulating layer in the opening, a side surface of the fourth conductive layer in the opening, one side surface of the second insulating layer in the opening, and a side surface of the sixth conductive layer in the opening, and a fourth insulating layer in contact with the other side surface of the first insulating layer in the opening, the side surface of the fifth conductive layer in the opening, the other side surface of the second insulating layer in the opening, and a side surface of the seventh conductive layer in the opening; forming a semiconductor layer in contact with an upper surface and a side surface of the first conductive layer in the opening, a side surface of the third insulating layer in the opening, a side surface of the fourth insulating layer in the opening, an upper surface and a side surface of the sixth conductive layer, an upper surface and a side surface of the seventh conductive layer, and an upper surface of the second insulating layer; A method for manufacturing a semiconductor device.

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