HEMT structures grown on miscut substrates

Abstract

Transistor structures and devices grown on miscut substrates and methods for fabricating transistors on miscut substrates. In some examples, a semiconductor device includes a miscut substrate having steps extending along a high mobility direction. The semiconductor device includes a III-N transistor on the miscut substrate. The III-N transistor includes a gate contact, a source contact, and a drain contact. The III-N transistor is oriented with respect to the miscut substrate such that a direction between the source contact and the drain contact is substantially perpendicular to the high mobility direction of the miscut substrate.

Description

HEMT STRUCTURES GROWN ON MISCUT SUBSTRATES TECHNICAL FIELD

[0001] The current disclosure relates to transistor structures and devices, and in particular devices grown on miscut substrates. BACKGROUND

[0002] III-N HEMTs, or III-Nitride High Electron Mobility Transistors, are a type of electronic device based on materials from the III-Nitride family, which includes compounds such as Gallium Nitride (GaN). III-N HEMTs have gained significant attention and popularity in recent years due to their exceptional properties, making them highly suitable for high-frequency and high-power applications. The unique material properties of III-Nitrides, including their wide bandgap, high electron mobility, and excellent thermal stability, allow III-N HEMTs to achieve superior performance compared to traditional silicon-based transistors. These transistors are utilized in a range of applications such as power amplifiers, radio frequency (RF) switches, wireless communications, radar systems, and power electronics, where their high power density, high operating frequencies, and efficiency are critical. III-N HEMTs have emerged as a promising technology for next-generation electronic devices, driving advancements in various fields requiring high-performance solid-state devices.

[0003] A "miscut substrate" refers to a substrate that has intentionally been cut at a non-standard angle or orientation. It is done deliberately during the fabrication process to create specific crystallographic orientations or surface properties on the substrate. By intentionally miscutting the substrate, specific crystal facets or surface orientations can be obtained, which can influence the growth and performance of subsequent layers deposited on the substrate. SUMMARY

[0004] This document describes transistor structures and devices grown on miscut substrates and methods for fabricating transistors on miscut substrates. In some examples, a semiconductor device includes a miscut substrate having steps extending along a high mobility direction. The semiconductor device includes a III- N transistor on the miscut substrate. The III-N transistor includes a gate contact, asource contact, and a drain contact. The III-N transistor is oriented with respect to the miscut substrate such that a direction between the source contact and the drain contact is substantially perpendicular to the high mobility direction of the miscut substrate. DESCRIPTION OF DRAWINGS

[0005] Figure 1A is a cross-sectional view of an example III-N high electron mobility transistor (HEMT).

[0006] Figure 1B shows an atomic force microscopy image of an example Nitrogen-polar (N-polar) Gallium Nitride (GaN) HEMT.

[0007] Figure 2 illustrates the transistor formed at different orientations on the miscut substrate.

[0008] Figure 3 shows a plot of the sheet resistance.

[0009] Figure 4 shows transfer curves for the transistor in parallel and perpendicular orientations.

[0010] Figure 5 shows transconductance and gmderivatives from samples plotted against Vg.

[0011] Figure 6 shows transconductance and gmderivatives from samples plotted against Id.

[0012] Figures 7A – 7B show a comparison of open-channel IV curves determined using TLM.

[0013] Figures 8A – 8C show example transistors having caterpillar gates in the parallel orientation.

[0014] Figures 9A – 9B show example transistors having caterpillar gates in the perpendicular orientation.

[0015] Figure 10 shows an example configuration of the transistor with caterpillar gates.

[0016] Figure 11 illustrates the potential effect of channel thickness on the transistor.

[0017] Figure 12 is a flow diagram of an example method for fabricating one or more transistors on a miscut substrate.

[0018] Figure 13A is a block diagram of an example power amplifier.

[0019] Figure 13B is a block diagram of an example low noise amplifier.

[0020] Figure 14A shows a cross-sectional drawing of the transistor with a T- gate.

[0021] Figure 14B shows a cross section drawing of the transistor with an I-gate.

[0022] Figure 15A shows an example device combining transistors.

[0023] Figure 15B shows an example device using two devices of the same style.

[0024] Figure 16 shows a block diagram of an example transmit receive circuit. DETAILED DESCRIPTION

[0025] This document describes transistor structures and devices, and in particular devices grown on miscut substrates. This document also describes methods for fabricating these devices and circuits and systems for applications of these devices, such as power amplifiers.

[0026] Figure 1A is a cross-sectional view of an example III-N high electron mobility transistor (HEMT) 100. As used herein, the terms III-Nitride or III-N materials, layers, devices, etc., refer to a material or device comprised of a compound semiconductor material according to the stoichiometric formula ScvBwAlxInyGazNa(D)b, where v+w+x+y+z is about 1, 0 ≤ v ≤ 1, 0 ≤ w ≤ 1, 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1, a+b is about 1, 0.9 < a ≤ 1, 0 ≤ b < 0.1, and (D) is any group-V element other than nitrogen. In a III-Nitride or III-N device, such as a high electron mobility transistor (HEMT), the conductive channel can be partially or entirely contained within a III-N material layer.

[0027] The transistor 100 includes a III-N material structure, grown on a suitable substrate 102, which can for example be silicon, silicon carbide, sapphire, AlN, or GaN. The III-N material structure includes a first III-N layer 112 on the substrate 102, a III-N barrier layer 114 on the first III-N layer 112, and a III-N channel layer 116 on the III-N barrier layer 114. The first III-N layer 112 can, for example, be formed of or include GaN, and can serve as a buffer layer in order to enable the growth of high quality III-N active device layers thereover. The III-N barrier layer 114 can, for example, be formed of or include AlxGa1-xN. The bandgap of the III-N barrier layer 114 can be larger than that of the first III-N layer 112. The III-N channel layer 116 can, for example, be GaN. The III-N channel layer 116 has a different composition than the III-N barrier layer 114, the bandgap of the III-Nbarrier layer 114 is larger than that of the III-N channel layer 116, and the thicknesses of layers 114 and 116 are selected such that a two-dimensional electron gas (2DEG) channel 118 (indicated by the dashed line in Figure 1A) is induced in the III-N channel layer 116 adjacent to the interface between III-N barrier layer 114 and III-N channel layer 116.

[0028] The transistor 100 includes a source contact 124, a drain contact 126, and a gate contact 128, with the source and drain contacts 124 and 126, respectively, being electrically connected to the 2DEG channel 118. The source and drain contacts can, for example, be made of conductive materials such as highly n+doped GaN, Al, Ti, Au, or combinations of these or other materials. As used herein, two or more contacts or other items such as conductive layers or components are said to be “electrically connected” if they are connected by a material which is sufficiently conducting to ensure that the electric potential at each of the contacts or other items is intended to be the same, i.e., is about the same, at all times under any bias conditions. In operation drain current ID, which is the flow of electrons in the 2DEG channel 118 from the source 124 to the drain 126, is controlled.

[0029] In some examples, III-N layers 112, 114, and 116 are N-polar III-N layers, oriented in thedirection. Then, III-N channel layer 116 can be on an N-face of the III-N barrier layer 114, and the source, drain, and gate contacts 124, 126, and 128 are over the N-face of the III-N material structure and on an opposite side of the III-N channel layer 116 from the III-N barrier layer 114.

[0030] The gate contact 128 can be used to control the flow of electrons in the 2DEG channel 118. By applying a voltage to the gate contact 128, the electric field created modulates the electron density in the channel 118, allowing the control of current flow. The 2DEG channel 118 exhibits high electron mobility due to the polarization properties of the GaN material providing mobile carriers without the use of impurity doping. This high mobility enables the transistor to operate at high frequencies and handle high power levels efficiently.

[0031] Figure 1B shows an atomic force microscopy (AFM) image of an example Nitrogen-polar (N-polar) Gallium Nitride (GaN) high electron mobility transistor (HEMT) 100 on a 3.5º miscut substrate 102. The substrate miscut leads to stepped epitaxial growth. Electron mobility becomes anisotropic. Electronics moving along the steps have high mobility. Electrons moving across steps have areduced mobility. Figure 1B illustrates a high mobility direction 104, extending along the steps, and a low mobility direction 106, extending across the steps.

[0032] Figure 2 illustrates the transistor 100 formed at different orientations on the miscut substrate 102. The miscut substrate 102 has steps 108 resulting from stepped epitaxial growth.

[0033] As shown in Figure 2, a first transistor 100a is formed in a “parallel” orientation, where the transistor 100a is oriented with respect to the steps 108 of the miscut substrate 102 such that a direction 110a between the source contact and the drain contact is substantially parallel to the high mobility direction 104 of the miscut substrate 102. A second transistor 100b is formed in a “perpendicular” orientation, where the transistor 100b is oriented with respect to the steps 108 of the miscut substrate 102 such that a direction 110b between the source contact and the drain contact is substantially perpendicular to high mobility direction 104 of the miscut substrate 102.

[0034] As current flows directly between the source and drain, in the parallel direction, charge carriers travel parallel to the step edges. In the perpendicular direction, charge carriers travel across the step edges from source to drain, resulting in lower mobility. The transistors 100a and 100b shown in Figure 2 are shown in the parallel and perpendicular directions; however, in general, the transistors 100a and 100b can be oriented to any angle with respect to the steps 108 of the miscut substrate 102 as appropriate for a particular application.

[0035] Figures 3 – 7 illustrate various measurements taken from sample transistors formed at varying orientations with respect to a miscut substrate. The measurements demonstrate the potential utility in manufacturing transistors with varying orientations.

[0036] Figure 3 shows a plot of the sheet resistance Rshof the contact formed between the source and drain contacts and the semiconductor material of the transistor 100 in parallel and perpendicular orientations. Rsh is a parameter which is inversely related to mobility that affects the performance of the transistor 100, e.g., in terms of power handling and current spreading. Rshcan be extracted using the transfer length method (TLM) technique.

[0037] The TLM measurements taken in this example show a normal difference in parallel versus perpendicular orientations. The perpendicular orientation results in a 22% higher Rsh indicating an 18% reduction in mobility.

[0038] Figure 4 shows transfer curves for the transistor 100 in parallel and perpendicular orientations. The transfer curves show the relationship between an input voltage and an output current of the transistor 100. The transfer curves were measured for example on transistors having a 1 μm gate length LG.

[0039] As shown in the example of Figure 4, there is a stretch-out 402 and 404 in a sub-threshold region for parallel orientations and is not consistent, resulting in variability in process. When there is this stretch-out, the transconductance gmrises sooner 406 and 408, which is not just a shift in gm. The transconductance represents the transistor’s ability to amplify signals and can be calculated as the slope of the transfer curve.

[0040] Figure 5 shows transconductance and gmderivatives from samples plotted against Vg. The gmderivatives show more gradual second gmderivative gm” 0-crossings 502 for the parallel device with the stretch out. The gradual crossings indicate devices with better linearity, i.e., that devices in the parallel orientation may be better suited for applications where improved linearity is useful.

[0041] Figure 6 shows transconductance and gmderivatives from samples plotted against drain current Id. The transconductance gm 602 rises faster for the perpendicular device, which can be useful, for example, in applications for getting gain at low IDQ bias points, resulting in high amplifier efficiency.

[0042] Figures 7A – 7B show a comparison of parameters extracted from open- channel IV curves determined using TLM. Figure 7A shows on-resistance Ron versus the distance between the source and drain contacts for the parallel and perpendicular devices. Figure 7B shows the percentage difference of Ronbetween the parallel and perpendicular devices to total Ron vs the distance between the source and drain contacts. When the distance is 2 μm and below, the difference between the parallel and perpendicular devices has less impact on Ronand Imax.

[0043] To fabricate analog integrated circuits it can be desirable, for example to provide the lowest loss signal routing or to reduce total chip area, to allow for designs to incorporate transistors with different orientations on the same substrate.

[0044] Figures 8A – 8C, 9, and 10 illustrate example structures for applications of transistors with varying orientations with respect to the miscut substrate.

[0045] Figures 8A – 8C show example transistors having gates in the parallel orientation. Figure 8A shows an example multi-finger transistor 100c where the gate contact 128 is divided into multiple parallel sections or fingers 810, which increases the effective gate width. The fingers are the part of the gate 128 that actively controls the current. The individual fingers are connected by a connecting section 812. Four parallel fingers 810 are shown in Figure 8A, but the number of parallel fingers could be larger or smaller. By increasing the gate width, a multi-finger transistor can achieve higher current-carrying capabilities, improved gain, and reduced resistance compared to a single-finger transistor. The increased gate width allows for better control of the transistor's behavior and enhances its overall performance. Dividing the gate total gate width into smaller fingers reduces the gate resistance enhancing the gain of the transistor. In the example transistor 100c shown in Figure 8A, each of the gate fingers 810 crosses many steps, and each gate finger crosses roughly the same steps.

[0046] Figure 8B shows an alternative multi-finger transistor 100d with a caterpillar gate configuration where the gate fingers are distributed across the transistor 100d. The total gate periphery is the same between 100c and 100d. Through the use of a larger quantity of shorter gate fingers, each gate finger crosses fewer steps and fewer steps are crossed, leading to a lower chance of a gate finger crossing a critical defect. This configuration can be useful, e.g., to improve manufacturability of N-polar HEMTs.

[0047] The gate 128 includes a number of parallel manifolds 802 extending along the high mobility direction of the substrate 102. The parallel manifolds 802 are connected by at least one connecting section 804 extending along the low mobility direction and crossing multiple steps. Each of the parallel manifolds 802 includes a number of active gate fingers 806 extending perpendicularly outward from the manifold and opposite one another along the manifold. The active gate fingers 806 are the section of gate 128 that controls the current in the transistor. The source and drain contacts are similarly arranged around the gate fingers 806 and manifolds 802.

[0048] Figure 8C shows another multi-finger transistor 100e that is a representation of 100c using the gate finger width of 100d resulting in stretch-out in the x-direction. The multi-finger transistor 100e can achieve some of the same benefits obtained with the configuration 100e of Figure 8B; however, the transistor 100e may not be practical due to being stretched out, e.g. at high frequency electromagnetic delays can lead to a phase difference can arise between gate fingers at the center and edge for the transistor.

[0049] Figures 9A – 9B show example transistors having gates in the perpendicular orientation. Figure 9A shows an example multi-finger transistor 100f where the gate contact 128 is divided into multiple parallel sections or fingers 910. The fingers 910 are the part of the gate 128 that actively controls the current. The individual fingers are connected by a connecting section 912. In the example transistor 100f shown in Figure 9A, each of the gate fingers 910 crosses fewer steps compared to the transistor 100c shown in Figure 8A, but each of the gate fingers 910 crosses different steps, which can lead to asymmetry between gate fingers.

[0050] Figure 9B shows an alternative multi-finger transistor 100g with a caterpillar gate configuration where the gate fingers are distributed across the transistor 100g. The total gate periphery is the same between configuration 100f and 100g. Through the use of a larger quantity of shorter active gate fingers compared to the configuration 100f shown in Figure 9A, the potential asymmetry between gate fingers is minimized by increasing the number of steps crossed.

[0051] The gate 128 includes a number of parallel manifolds 902 extending along the low mobility direction of the substrate 102 and crossing multiple steps. The parallel manifolds 902 are connected by at least one connecting section 904 extending along the high mobility direction. Each of the parallel manifolds 902 includes a number of active fingers 906 extending perpendicularly outward from the manifold and opposite one another along the manifold. The active gate fingers 906 are the section of gate 128 that controls the current in the transistor. The source and drain contacts are similarly arranged around the gate fingers 906 and manifolds 902.

[0052] Figure 10 shows an example configuration 100h of the transistor with caterpillar gates. In this example, the order of sources and drains 1002 are flipped on opposite sides of a gate manifold. Heat dissipation is strongest closest to the drain contact. By spacing individual drains as far apart as possible, heat flux isincreased, allowing for the device to operate at a lower temperature. This configuration can be used with gate fingers that are in the parallel orientation or the perpendicular orientation or in any appropriate orientation with respect to the miscut substrate.

[0053] Figure 11 illustrates the potential effect of channel thickness on the transistor 100. At extremely thin channels the channel becomes a nanowire, so there can only be parallel transport. The precise thickness where this will happen will depend on the miscut angle – a greater miscut will lead to this phenomenon happening with a thicker channel. For N-polar HEMTs grown on sapphire substrates with a 4° miscut, the influence of the thin channel has been observed to occur for channel thicknesses less than 10 nm.

[0054] The top cross section 1102 illustrates the situation where the channel is thick enough to avoid this phenomenon. The bottom cross section 1104 illustrates the situation where the channel is too thin, such that the channel is broken in the direction 1106 indicated so perpendicular transport will not happen.

[0055] Figure 12 is a flow diagram of an example method 300 for fabricating one or more transistors on a miscut substrate, e.g., an N-polar GaN HEMT.

[0056] The method 300 includes preparing a substrate, which can be, e.g., a sapphire wafer or silicon carbide substrate (302). The substrate is cleaned and prepared for epitaxial growth. The substrate is a miscut substrate and the degree of miscut is selected for the particular application of the HEMT.

[0057] The method 300 includes selecting an orientation for each transistor specifying an orientation with respect to the steps of the miscut substrate (304). For example, a perpendicular orientation can be selected for manufacturing uniformity, a parallel orientation can be selected for linearity, or an angle between perpendicular and parallel can be selected to tune the transconductance performance.

[0058] The method 300 includes growing a buffer layer (306). This layer is typically made of AlGaN or GaN and is grown by, e.g., metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). It may be doped with impurities such as iron or carbon to render it insulating in some regions, and it may be doped with Si or other electron donor or acceptor impurities to balance charge elsewhere in the structure.

[0059] The method 300 includes growing a back barrier layer (308). A back barrier layer is grown on the buffer layer, e.g., to prevent electron leakage and increase the breakdown voltage of the device. This layer can be made of, e.g., AlGaN and can be grown by, e.g., MOCVD or MBE. This layer may, over a portion of its thickness, be doped with Si or other impurities.

[0060] The method 300 includes growing a channel layer (310). A channel layer is grown on top of the back barrier layer. The channel layer can be made of, e.g., GaN and can be grown by, e.g., MOCVD or MBE.

[0061] The method 300 includes forming source, drain, and gate contacts (312). Metal contacts are deposited to form the source and drain electrodes. These contacts are typically made of a combination of metals such as Ti, Al, Ni, Au, and can be patterned using photolithography and liftoff or etching. To form the gate contacts, a metal layer (e.g., Ti, Cr, Ru, Pt, or Pd) can be deposited, e.g., on top of a thin insulating layer. Photolithography and / or etching can be used to expose the channel region where the gates are deposited.

[0062] The method 300 includes testing and packaging the transistor(s) (314). The completed device is tested to ensure that it meets the desired specifications for electrical performance. Once testing is complete, the device is packaged for use in a specific application.

[0063] Figure 13A is a block diagram of an example power amplifier 700. The power amplifier includes a power supply 702, a matching network 704, and a biasing circuit 706. The power amplifier 700 includes a digital signal processing (DSP) block 708, a HEMT 710, and a cooling system 712.

[0064] The power supply 702 provides DC voltage and current to operate the amplifier circuit. It typically includes rectifiers, filters, and regulators to convert the AC power into the appropriate DC power levels. The matching network 704, often composed of passive components like inductors and capacitors or transmission lines, is used to match the impedance between the amplifier and the input / output signal sources or load. It ensures impedance matching for optimal performance. The biasing circuit 706 establishes the desired operating point for the active devices, such as the HEMT. It provides the appropriate DC bias voltage and current to ensure the amplifier achieves the desired output power and linearity.

[0065] The HEMT 710 is formed with a substantially perpendicular orientation to a miscut substrate. The DSP block 708 performs digital predistortion and employs algorithms and techniques to pre-compensate for nonlinearities that may arise within the amplifier itself or from the input signal source. By applying digital predistortion, the amplifier can counteract these nonlinearities and produce a more linear and faithful amplification of the input signal. This can be useful, e.g., so that the digital predistortion can counteract nonlinearities resulting from the HEMT 710 having a perpendicular orientation, while benefitting from the uniformity improvement and higher gmof the perpendicular orientation, which can lead to increased manufacturability.

[0066] Figure 13B is a block diagram of an example low noise amplifier 750. The low noise amplifier 750 includes a miscut substrate 752 with one or more perpendicular HEMTs 754 forming one or more initial amplifier stages and a parallel HEMT 756 forming a final amplifier stage. The low noise amplifier 750 benefits from the uniformity and gain advantages of the perpendicular orientation for the initial stages and the linearity benefit of the parallel orientation for the final stage.

[0067] In some examples, short gate fingers can be used to allow for “I” gate structures instead of T-gates, which can be easier to fabricate and more mechanically robust. Additionally, I-gates can have lower parasitic capacitance resulting in increased gain. Figure 14A shows a cross-sectional drawing of the transistor 100 with a T-gate 130. The T-gate 130 contains two parts, a first narrow stem 130a that defines the gate length of the transistor 100 based on the lateral dimension where the stem 130a touches the semiconductor channel and a head section 130b above the stem 130a. The head section 130b is wider than the stem 130a. For high frequency operation minimizing the gate length is desirable. The head section 130b creates capacitance between the gate 130 and the channel due to the larger width of the head 130b. Increasing the height of the stem 130a decreases capacitance but can increase resistance and decrease manufacturability.

[0068] Figure 14B shows a cross section drawing of the transistor 100 with an I- gate 128. The I-gate 128 lacks the head section 130b of the T-gate 130. For transistors with the same gate length, the cross-sectional area of the overall gate is larger for the T-gate 130 relative to the I-gate 128 resulting in lower gate resistancefor the T-gate 130. Lower gate resistance allows for gates of longer width to be fabricated. Conversely the higher resistance of the I-gate 128 limits the gate width of the transistor with an I-gate 128 relative to one with a T-gate 130.

[0069] To help accommodate the multiple orientations it may be desirable to use transistors of style 100f for the first stage and 100d for the second stage or 100g for the first stage and 100c for the second stage. Figure 15A shows an example of combining transistor 100g with 100c. Connected to 100g and 100c are interconnect metals 1502, 1504, 1506, and 1508 for the input signal into the transistor and output signal of the transistor. The output of 100g is connected to the input of 100c. In this arrangement the geometry allows for a direct connection of devices with opposite orientation.

[0070] Figure 15B shows how this connection is less direct when using two devices of the same style such as 100f and 100c where additional interconnect 1510 is needed to connect the two transistors accommodating the 90 degree bend in the signal path.

[0071] Figure 15A is shown using two common-source devices (i.e., FETs where the input terminal is gate, the output the drain, and the source is common); however, these transistors could each be either common-gate, common-drain, or common- source. An additional circuit that can benefit from the mix of parallel and perpendicular orientations is the Cascode amplifier. In a Cascode amplifier the first device is a common-source transistor while the second device is a common-gate transistor (i.e., the input is the source terminal, the output the drain terminal with the gate terminal grounded). The common-source device benefits from the improved pinch off characteristics of the perpendicular device and can additionally benefit from the reduced capacitance of an I-gate gate electrode. The common-gate device can benefit from the more negative threshold voltage of a parallel device.

[0072] In some circuits, it may be desirable to include 90 degree bends in the signal path. For instance, in a transmit / receive module containing a power amplifier and a low noise amplifier connected together by a switch. Figure 16 shows a block diagram of such a transmit receive circuit 1600. In such a circuit the switch 1606 routes an electronic signal to / from antenna 1608 from either the power amplifier 1602 or low-noise amplifier 1604. With the LNA and PA stacked above each other, signal routing can be used to reach the amplifier terminals. For manufacturabilityand performance, it is generally preferable to have a compact design. To create a more compact circuit, access to parallel and perpendicular oriented FETs as well as FETs with normal or caterpillar designs can provide flexibility in the circuit layout. There are devices, such as the FETs within an RF switch, where the differences between the parallel and perpendicular devices may matter less. For such a device, access to both parallel and perpendicular devices allow for a more optimal layout to be obtained.

[0073] Various devices and their material structures have been described above, along with methods of forming the devices and material structures. However, it should be understood that they have been presented by way of example only, and not limitation. The implementations have been particularly shown and described, but it will be understood that various changes in form and details may be made. For example, for any of the transistors described herein, a gate insulator or gate dielectric can be included between the gate metal and the underlying semiconductor material. Accordingly, other implementations are within the scope of the following claims.

Claims

CLAIMSWHAT IS CLAIMED IS:

1. A semiconductor device comprising: a miscut substrate having a plurality of steps extending along a high mobility direction; a III-N transistor on the miscut substrate, wherein the III-N transistor comprises a gate contact, a source contact, and a drain contact; wherein the III-N transistor is oriented with respect to the miscut substrate such that a direction between the source contact and the drain contact is substantially perpendicular to the high mobility direction of the miscut substrate; and wherein a length between the source contact and the drain contact is equal to or less than 2 μm.

2. The semiconductor device of claim 1, wherein the III-N transistor comprises an N-polar GaN high electron mobility transistor (HEMT).

3. The semiconductor device of claim 1, wherein the III-N transistor comprises: a III-N backbarrier layer; a III-N channel layer over the III-N backbarrier layer; and a 2DEG channel in the III-N channel layer; wherein the source contact and the drain contact are coupled to the III-N channel layer.

4. A power amplifier comprising: a semiconductor device; and a digital signal processing block configured for performing digital predistortion on an input signal to compensate for at least one nonlinearity of the semiconductor device and outputting a distorted output signal to the semiconductor device; wherein the semiconductor device comprises a miscut substrate having a plurality of steps extending along a high mobility direction and a III-N transistor onthe miscut substrate, wherein the III-N transistor comprises a gate contact, a source contact, and a drain contact; wherein the III-N transistor is oriented with respect to the miscut substrate such that a direction between the source contact and the drain contact is substantially perpendicular to the high mobility direction of the miscut substrate.

5. The power amplifier of claim 4, wherein a length between the source contact and the drain contact of the semiconductor device is equal to or less than 2 μm.

6. A method for forming a plurality of semiconductor devices, the method comprising: obtaining a plurality of miscut substrates; and forming, on each miscut substrate, a III-N transistor comprising a gate contact, a source contact, and a drain contact; wherein, on each miscut substrate, the III-N transistor is oriented with respect to the miscut substrate such that a direction between the source contact and the drain contact is substantially perpendicular to the high mobility direction of the miscut substrate.

7. The method of claim 6, wherein, on each miscut substrate, a length between the source contact and the drain contact of the III-N transistor is equal to or less than 2 μm.

8. The method of claim 6, wherein the III-N transistor comprises an N-polar GaN high electron mobility transistor (HEMT).

9. The method of claim 6, wherein the III-N transistor comprises: a III-N backbarrier layer; a III-N channel layer over the III-N backbarrier layer; and a 2DEG channel in the III-N channel layer; wherein the source contact and the drain contact are coupled to the III-N channel layer.

10. The method of claim 6, comprising, for each semiconductor device, forming a power amplifier by coupling the semiconductor device to a digital signal processing block configured for performing digital predistortion on an input signal to compensate for at least one nonlinearity of the semiconductor device and outputting a distorted output signal to the semiconductor device.

11. A semiconductor device comprising: a miscut substrate having a plurality of steps extending along a high mobility direction; at least one first III-N transistor on the miscut substrate, wherein the first III- N transistor comprises a first source contact and a first drain contact, wherein the first III-N transistor is oriented with respect to the miscut substrate such that a first direction between the first source contact and the first drain contact is substantially perpendicular to the high mobility direction of the miscut substrate; and at least one second III-N transistor on the miscut substrate, wherein the second III-N transistor comprises a second source contact and a second drain contact, wherein the second III-N transistor is oriented with respect to the miscut substrate such that a second direction between the second source contact and the second drain contact is substantially parallel to the high mobility direction of the miscut substrate.

12. The semiconductor device of claim 11 wherein an input or output terminal of the first III-N transistor is connected to either an input or output terminal of the second III-N transistor.

13. The semiconductor device of claim 11, wherein the first III-N transistor or the second III-N or both comprises an N-polar GaN high electron mobility transistor (HEMT).

14. The semiconductor device of claim 11, wherein a length between the source contact and the drain contact of the first III-N transistor is equal to or less than 2 μm.

15. A low noise amplifier comprising: a miscut substrate having a plurality of steps extending along a high mobility direction; one or more initial stages at least one first III-N transistor on the miscut substrate, wherein the first III-N transistor comprises a first source contact and a first drain contact, wherein the first III-N transistor is oriented with respect to the miscut substrate such that a first direction between the first source contact and the first drain contact is substantially perpendicular to the high mobility direction of the miscut substrate; and a final stage comprising at least one second III-N transistor on the miscut substrate, wherein the second III-N transistor comprises a second source contact and a second drain contact, wherein the second III-N transistor is oriented with respect to the miscut substrate such that a second direction between the second source contact and the second drain contact is substantially parallel to the high mobility direction of the miscut substrate 16. The low noise amplifier of claim 15, wherein the first III-N transistor or the second III-N or both comprises an N-polar GaN high electron mobility transistor (HEMT).

17. A semiconductor device comprising: a miscut substrate having a plurality of steps extending along a high mobility direction; a III-N transistor on the miscut substrate, wherein the III-N transistor comprises a gate contact, a source contact, and a drain contact; wherein the gate contact comprises a number of parallel manifolds connected by at least one connecting section; wherein each parallel manifold comprises a plurality of fingers extending outward from the parallel manifold.

18. The semiconductor device of claim 17, wherein the parallel manifolds extend along the high mobility direction.

19. The semiconductor device of claim 17, wherein the parallel manifolds extend along a low mobility direction perpendicular to the high mobility direction.

20. The semiconductor device of claim 17, wherein each of the plurality of fingers extends perpendicularly outward from the parallel manifold, wherein the plurality of fingers comprises a plurality of pairs of fingers opposite one another along at least one of the parallel manifolds.

21. The semiconductor device of claim 17, wherein the III-N transistor is an N-polar GaN transistor.

22. The semiconductor device of claim 17, wherein a length between the source contact and the drain contact of the first III-N transistor is equal to or less than 2 μm.

23. The semiconductor device of claim 17, wherein the source contact and the drain contact comprise a plurality of source and drain fingers arranged on opposite sides of at least one parallel manifold.

24. The semiconductor device of claim 17, wherein the gate electrode is an I-gate.

25. A semiconductor device comprising: a substrate; a first III-N transistor on the substrate, wherein: the first III-N transistor comprises a gate contact, a source contact, and a drain contact; the gate contact comprises a number of parallel manifolds connected by at least one connecting section; and each parallel manifold comprises a plurality of fingers extending outward from the parallel manifold; and a second III-N transistor on the substrate.

26. The semiconductor device of claim 25, wherein the wherein each of the plurality of fingers extends perpendicularly outward from the parallel manifold, wherein the plurality of fingers comprises a plurality of pairs of fingers opposite one another along at least one of the parallel manifolds.

Images