Accumulation computing device using plastic synapse elements and method thereof

Abstract

An accumulation computing device according to one embodiment comprises: a plurality of electrodes arranged in an array structure; and a plurality of plastic synapse elements which are symmetrically connected to at least one electrode among the plurality of electrodes, are connected to a plastic synapse element of another electrode through a node, and have impedance varying on the basis of at least one of enabling or disabling of an input signal to the at least one electrode, wherein an impedance of at least one of the plurality of plastic synapse elements changes, in response to the input signal being enabled to the at least one electrode, from a first impedance magnitude to a second impedance magnitude based on the enabled input signal, and can non-linearly decay from the second impedance magnitude toward the first impedance magnitude in response to the input signal being disabled.

Description

Accumulative computing device and method using plastic synaptic elements

[0001] The present invention relates to a plastic synaptic element and an accumulator computing device comprising such elements. Raw data, distinguished by information about order and position, is converted into input data (or input signals) in the form of electrical pulses and applied to the accumulator computing device, thereby generating unique weights for each data. A series of learning methods are included for training a machine learning model on data patterns based on the generated unique weights.

[0002] Neuromorphic systems, inspired by the brain, are a promising computing paradigm that surpasses the von Neumann architecture and have proven to be suitable for data-intensive processing, object detection, and object prediction. A representative hardware implementation for neuromorphic systems is the crossbar array, comprised of various memristors. Core hardware devices that electronically compute multi-state synaptic weights based on the crossbar array structure composed of various memristors have been developed. However, conventional crossbar arrays have limitations in expressing the spatiotemporal characteristics of interconnectivity between adjacent neurons, including synaptic plasticity. Furthermore, building neural networks inevitably requires a large number of synaptic elements. Therefore, to efficiently implement a brain-like computing architecture, one promising structural solution is an accumulative computing device with a short-term memory that exhibits nonlinear behavior over time, and a learning method utilizing this device.

[0003] Currently, methods are being developed to distinguish the temporal order of input data by exploiting the nonlinear impedance change characteristics of plastic synaptic elements, and cumulative computing methods that leverage the randomness of the elements themselves. However, research into efficiently configuring and standardizing cumulative computing devices remains limited.

[0004] An accumulative computing device according to one embodiment comprises a plurality of electrodes arranged in an array structure and

[0005] A plurality of plastic synaptic elements may be symmetrically connected to at least one of the plurality of electrodes, connected to a plastic synaptic element of another electrode through a node, and having an impedance that varies based on at least one of enabling or disabling an input signal to the at least one electrode, wherein the impedance of the at least one plastic synaptic element of the plurality of plastic synaptic elements may vary from a first impedance magnitude to a second impedance magnitude based on the applied input signal in response to enabling the input signal to the at least one electrode, and may nonlinearly decay from the second impedance magnitude toward the first impedance magnitude in response to disabling the input signal.

[0006] In an accumulative computing device according to one embodiment, a plurality of plastic synaptic elements symmetrically connected to at least one of the plurality of electrodes may have the same impedance change characteristics.

[0007] In an accumulative computing device according to one embodiment, an impedance change characteristic of at least one of a plurality of plastic synaptic elements symmetrically connected to at least one of a plurality of electrodes may be different from an impedance change characteristic of another plastic synaptic element.

[0008] In an accumulative computing device according to one embodiment, the plastic synaptic elements on the first axis may have the same impedance change characteristics, the plastic synaptic elements on the second axis may have the same impedance change characteristics, and the plastic synaptic elements on the first axis and the plastic synaptic elements on the second axis may have different impedance change characteristics.

[0009] In an accumulative computing device according to one embodiment, the plurality of plastic synaptic elements may be at least one of an anisotropic material, an element based on a polymer mixture and fine metal wires aligned in a predetermined direction, an element based on a charge trap mechanism, or an element based on a conductivity change due to lattice vacancies and ion migration.

[0010] An accumulative computing device according to one embodiment may further include a control unit that applies or does not apply an input signal that causes a nonlinear change in the impedance size of at least one plastic synaptic element among a plurality of plastic synaptic elements to at least one electrode, and reads a composite impedance value of the plurality of plastic synaptic elements based on a read target electrode based on applying a read bias signal to the read target electrode.

[0011] In an accumulative computing device according to one embodiment, the control unit can apply the input signal generated based on a result of merging data chopped from binarized input data to the at least one electrode.

[0012] In an accumulative computing device according to one embodiment, the control unit can individually apply first input signals among a plurality of input signals corresponding to input data to corresponding electrodes, individually apply second input signals among the plurality of input signals to corresponding electrodes, and apply the second input signals after applying the first input signals.

[0013] In an accumulative computing device according to one embodiment, the control unit can ground a plurality of nodes surrounding at least one electrode, between a plurality of plastic synaptic elements and plastic synaptic elements of other electrodes, and apply an input signal to at least one electrode while the plurality of nodes are grounded.

[0014] In an accumulative computing device according to one embodiment, the control unit can terminate grounding of a plurality of nodes when an input signal is not applied to at least one electrode.

[0015] In an accumulative computing device according to one embodiment, the control unit can read a composite impedance value of a plurality of plastic synaptic elements based on applying a read bias signal to the read electrode while grounding other electrodes surrounding the read target electrode and grounding other electrodes surrounding the read target electrode.

[0016] In an accumulative computing device according to one embodiment, when at least one electrode to which an input signal is applied and another electrode are spaced apart from each other by at least two nodes on an axis from the at least one electrode to which the input signal is applied to the other electrode, the control unit can individually sweep and read a composite impedance value of a plurality of plastic synaptic elements connected to each of the at least one electrode and the other electrode by individually applying a read bias signal to the at least one electrode and the other electrode.

[0017] A method performed by an accumulative computing device according to one embodiment may include: enabling an input signal to an input target electrode, wherein the input signal causes an impedance of at least one plastic synaptic element among a plurality of plastic synaptic elements symmetrically connected to an input target electrode among a plurality of electrodes arranged in an array structure to change from a first impedance magnitude to a second impedance magnitude; disabling the input signal to at least one electrode such that the impedance of the at least one plastic synaptic element nonlinearly decays from the second impedance magnitude toward the first impedance magnitude; and reading a composite impedance value of the plurality of plastic synaptic elements with respect to the read target electrode based on applying a read bias signal to the read target electrode.

[0018] In a method performed by an accumulation computing device according to one embodiment, the step of applying the input signal may include a step of applying the input signal generated based on a result of merging data chopped from binarized input data to the at least one electrode.

[0019] In a method performed by an accumulation computing device according to one embodiment, the step of applying the input signal may include the step of individually applying first input signals among a plurality of input signals corresponding to input data to corresponding electrodes, and the step of individually applying second input signals among the plurality of input signals to corresponding electrodes after applying the first input signals.

[0020] In a method performed by an accumulative computing device according to one embodiment, the step of applying the input signal may include the step of grounding a plurality of nodes surrounding the input target electrode between the plurality of plastic synaptic elements and plastic synaptic elements of other electrodes, and the step of applying the input signal to the input target electrode while the plurality of nodes are grounded.

[0021] In a method performed by an accumulative computing device according to one embodiment, the step of de-energizing the input signal may include the step of terminating grounding of the plurality of nodes.

[0022] In a method performed by an accumulation computing device according to one embodiment, the step of reading the composite impedance value may include the step of grounding other electrodes around the read target electrode among the plurality of electrodes, and the step of reading the composite impedance value of the plurality of plastic synaptic elements based on the read target electrode based on applying a read bias signal to the read target electrode while the other electrodes around the read target electrode are grounded.

[0023] In a method performed by an accumulative computing device according to one embodiment, the step of reading the composite impedance value may include the step of individually sweeping and reading the composite impedance value of a plurality of plastic synaptic elements connected to each of the at least one electrode and the other electrode by individually applying a read bias signal to the at least one electrode and the other electrode, when the at least one electrode to which the input signal is applied and the other electrode are spaced apart from each other by at least two nodes on an axis from the at least one electrode to which the input signal is applied to the other electrode.

[0024] FIG. 1 illustrates an accumulation computing device according to one embodiment.

[0025] Figure 2 shows the conductance change characteristics of a comparative example and the conductance change characteristics of a plastic synaptic element of the present invention according to the number of bias applications and whether conductance size decay is performed.

[0026] Figure 3a is a graph showing the change in current intensity according to the bias strength and number of bias applications applied to a plastic synaptic element according to one embodiment.

[0027] FIG. 3b is a graph showing the conductance change characteristics of a plastic synaptic element over time according to the bias strength applied to the plastic synaptic element according to one embodiment.

[0028] Figure 3c is a graph showing the conductance change characteristics of a plastic synaptic element according to a pulse signal applied to the plastic synaptic element according to one embodiment.

[0029] Figures 4a to 4d illustrate examples of plastic synaptic elements.

[0030] Figure 5 schematically illustrates an accumulation computing method according to the present invention.

[0031] Figure 6 is a flowchart of a method performed by an accumulation computing device.

[0032] FIG. 7 illustrates an accumulative computing device applying an input signal according to one embodiment.

[0033] FIG. 8A is a diagram showing an input signal being applied to a plurality of electrodes of an accumulative computing device according to one embodiment, and a diagram showing an input signal being applied to the plurality of electrodes at different times.

[0034] FIG. 8b illustrates an input signal based on input data including time information being applied to a plurality of electrodes of an accumulative computing device according to one embodiment.

[0035] FIG. 9 illustrates a synthetic impedance readout operation for a plurality of plastic synaptic elements of an accumulative computing device according to one embodiment.

[0036] FIG. 10 is a schematic diagram illustrating a method for reading a synthetic impedance value of a plastic synaptic element from input data by an accumulation computing device.

[0037] FIG. 11A illustrates an embodiment of at least one electrode having anisotropy along a connection direction and a plurality of plastic synaptic elements symmetrically connected to at least one electrode.

[0038] Figures 11b to 11d are graphs of the synthetic impedance values ​​of plastic synaptic elements according to the presence or absence of anisotropy for the same input signal.

[0039] Specific structural or functional descriptions of the embodiments are disclosed for illustrative purposes only and may be modified and implemented in various forms. Therefore, the actual implementation is not limited to the specific embodiments disclosed, and the scope of this specification includes modifications, equivalents, or alternatives within the technical concepts described in the embodiments.

[0040] Although terms such as "first" or "second" may be used to describe various components, these terms should be interpreted solely to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component.

[0041] When it is said that a component is "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but there may also be other components in between.

[0042] Singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, the terms "comprises" or "has" should be understood to indicate the presence of a described feature, number, step, operation, component, part, or combination thereof, but not to exclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0043] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art. Terms defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0044] Hereinafter, embodiments will be described in detail with reference to the attached drawings. In the description with reference to the attached drawings, identical components are assigned the same reference numerals regardless of the drawing numbers, and redundant descriptions thereof will be omitted.

[0045] FIG. 1 illustrates an accumulation computing device (100) according to one embodiment.

[0046] Referring to FIG. 1, the accumulation computing device (100) according to the present invention may include a plurality of electrodes (110, 111), a plurality of plastic synaptic elements (120), and a control unit (not shown).

[0047] A plurality of electrodes (110, 111) may be arranged in an array structure. The form in which the plurality of electrodes (110, 111) are arranged in an array structure may be a rectangular grid form or a triangular grid form. Hereinafter, the form in which the plurality of electrodes form a rectangular grid form will be mainly described, but the arrangement form of the plurality of electrodes (110, 111) is not limited thereto.

[0048] The plurality of electrodes (110, 111) can receive an input signal. In addition, the plurality of electrodes (110, 111) can receive a read bias signal to read the composite impedance of the plurality of plastic synaptic elements (120) connected to the plurality of electrodes (110, 111) after receiving the input signal. As will be described later, the plurality of electrodes (110, 111) can be grounded to read the composite impedance value of the plurality of plastic synaptic elements (120) connected to the plurality of electrodes (110, 111).

[0049] A plurality of plastic synaptic elements (120) may be connected to at least one electrode (110) among a plurality of electrodes (110, 111). More specifically, the plurality of plastic synaptic elements (120) may be symmetrically connected to at least one electrode (110) among a plurality of electrodes (110, 111) arranged in an array structure. For example, the plurality of plastic synaptic elements (120) connected to at least one electrode (110) may be positioned on a diagonal of a regular octagon inscribed in an imaginary circle formed with at least one electrode (110) as the center, thereby being symmetrically connected in eight directions with at least one electrode (110) as the center. For another example, a plurality of plastic synaptic elements (120) connected to at least one electrode (110) may be positioned on a diagonal of a regular hexagon inscribed in an imaginary circle formed with at least one electrode (110) as the center, thereby being symmetrically connected in six directions with at least one electrode (110) as the center. As illustrated in FIG. 1, a plurality of plastic synaptic elements (120) symmetrically connected to at least one electrode (110) may be connected in eight directions to form one unit cell (101), and different unit cells (101) may be connected through nodes (130) to form an array structure, thereby being standardized. The examples of the symmetrical connection of a plurality of plastic synaptic elements (120) described above are merely exemplary, and the direction of connection of a plurality of plastic synaptic elements (120) to at least one electrode (110) is not limited thereto.

[0050] A plurality of plastic synaptic elements (120) symmetrically connected to at least one electrode (110) among a plurality of electrodes (110, 111) may be connected to a plastic synaptic element connected to another electrode (111). More specifically, the plurality of plastic synaptic elements (120) may be connected to at least one electrode (110) among a plurality of electrodes arranged in an array structure at a first end, and may be connected to a plastic synaptic element connected to another electrode (111) at a second end. The plurality of plastic synaptic elements (120) may be connected to a plastic synaptic element of another electrode (111) through a node (130).

[0051] The plurality of plastic synaptic elements (120) may have an impedance that varies based on at least one of enabling or disabling an input signal to at least one electrode (110) to which the plurality of plastic synaptic elements (120) are connected.

[0052] The impedance of at least one plastic synaptic element among the plurality of plastic synaptic elements (120) may change in response to an input signal being applied (enabled) to at least one electrode (110). More specifically, the impedance of the plastic synaptic element may change from a first impedance magnitude to a second impedance magnitude based on the applied input signal. For example, the first impedance magnitude may correspond to an initial resistance value or an initial conductance value of the plastic synaptic element, and the second impedance magnitude may correspond to a resistance value or a conductance value formed according to a change in the internal structure of the plastic synaptic element (e.g., a phase change, channel formation, or filament formation, etc.) caused by an electrical pulse applied to an electrode connected to the plastic synaptic element.

[0053] In addition, the impedance of at least one of the plurality of plastic synaptic elements (120) may nonlinearly decay from a second impedance magnitude toward a first impedance magnitude in response to the input signal being disabled. When the impedance magnitude of the plurality of plastic synaptic elements (120) is nonlinearly decayed, the impedance magnitude of the plurality of plastic synaptic elements (120) may be maintained within a critical range even after a certain period of time has elapsed. Hereinafter, the nonlinear impedance magnitude decaying (or change) of the plurality of plastic synaptic elements (120) will be described in detail later with reference to FIGS. 2 to 4d.

[0054] The accumulative computing device (100) may include a control unit (not shown). The control unit may be connected to a plurality of electrodes (110, 111) and a node (130). The control unit may be connected to the plurality of electrodes (110, 111) and may perform at least one of applying or not applying an input signal to at least one electrode (110) among the plurality of electrodes (110, 111). In addition, when the control unit terminates the application of the input signal to at least one electrode (110) among the plurality of electrodes (110, 111), the control unit may read a composite impedance value of a plurality of plastic synaptic elements (120) symmetrically connected to at least one electrode (110). Additionally, the control unit may apply an input signal generated based on a result of merging data chopped from binarized input data to at least one electrode. Additionally, the control unit can determine whether to ground the node (130) to apply an input signal, and can determine whether to ground the electrode to read the composite impedance. A more specific operation method of the control unit is described in FIGS. 5 to 10.

[0055] Figure 2 shows the conductance change characteristics (201) of a comparative example and the conductance change characteristics (202) of a plastic synaptic element of the present invention according to the number of bias applications and whether conductance size decays.

[0056] The comparative embodiment may include a non-plastic element. In this specification, the comparative embodiment is described as an example of a non-volatile memristor. The conductance change characteristic (201) represents the change in conductance size according to the number of bias application times (210_1) for the comparative embodiment. The conductance size of the comparative embodiment increases in proportion to the number of bias application times (210_1), and the conductance size of the comparative embodiment to which the bias is applied does not decay. Each increased conductance size corresponds to a conductance state (220_1). As illustrated in FIG. 2, when the number of bias application times (210_1) is three, the comparative embodiment includes a total of four conductance states (220_1), including an initial conductance state corresponding to the conductance size before the bias is applied. When the number of times the bias is applied (210_1) is n, the comparative example may include a total of n+1 conductance states (220_1) including the initial conductance state before the bias is applied. The conductance state (220_1) may include multiple state vectors. The state vector may be expressed as a matrix including 0s and 1s, and the sum of all elements included in the state vector may represent the number of times the bias is applied (210_1). Each column of the state vector expressed as a matrix may sequentially correspond to a bias application time, and among the elements of the state vector, 0 may represent non-application of the bias, and 1 may represent application of the bias. For example, in the comparative example, a conductance state (220_1) in which a bias is applied 0 times may include a state vector of (0,0,0), and in the comparative example, a conductance state (220_1) in which a bias is applied once may include a state vector of (1,0,0), (0,1,0), or (0,0,1).Since the conductance magnitude of the comparative example is not decayed, regardless of when the bias is applied, the state vectors of (1,0,0), (0,1,0), or (0,0,1) represent the same conductance state, so the conductance magnitude is not distinguished.

[0057] The conductance change characteristic (202) is an example of a plastic synaptic element of the present invention, and represents a change in the conductance size according to the number of bias application times (210_2) of a volatile memristor. The conductance size of the volatile memristor increases according to the number of bias application times (210_2), and if no bias is additionally applied, the conductance size of the volatile memristor may nonlinearly decaerate. By the nonlinear decaerate of the conductance size, when the number of bias application times (210_2) is n, the volatile memristor is 2 nThe conductance state (220_2) may include a plurality of conductance states. After the conductance magnitude is nonlinearly decoded, the conductance magnitude may be maintained within a specific threshold range for a certain period of time, and each conductance magnitude maintained within the specific threshold range corresponds to a conductance state (220_2). The conductance state (220_2) may correspond one-to-one with a state vector. As described above, the state vector may be expressed as a matrix including 0s and 1s, and the sum of all elements included in the state vector may represent the number of bias application times (210_2). Each column of the state vector expressed as a matrix may sequentially correspond to a bias application time, and among the elements of the state vector, 0 may represent non-application of bias, and 1 may represent application of bias. For example, the conductance state (220_2) of a volatile memristor to which no bias is applied may include a state vector of (0,0,0). The conductance state (220_2) of a volatile memristor to which a bias is applied once may include a state vector of (1,0,0), (0,1,0) or (0,0,1), but each state vector corresponds to a different conductance state (220_2) due to the difference in the decay of the conductance magnitude depending on the time point at which the bias is applied. Since one state vector corresponds to one conductance magnitude, the volatile memristor has 2 n The dog can have distinct conductance states (220_2).

[0058] Figure 3a is a graph showing the change in current intensity according to the bias strength and number of bias applications applied to a plastic synaptic element according to one embodiment.

[0059] The x-axis of Fig. 3a corresponds to the bias strength (301), the y-axis corresponds to the number of bias applications (302), and the z-axis corresponds to the current strength (303). As illustrated in Fig. 3a, the bias strength (301) may correspond to the voltage applied to the plastic synaptic element. As the bias strength (301) increases, the current strength (303) flowing to the plastic synaptic element increases. In addition, as the number of bias applications (302) increases, the current strength (303) flowing to the plastic synaptic element also increases.

[0060] FIG. 3b is a graph showing the conductance change characteristics of a plastic synaptic element over time according to the bias strength applied to the plastic synaptic element according to one embodiment.

[0061] The x-axis of Fig. 3b corresponds to time, and the y-axis corresponds to conductance. According to Fig. 3b, a bias is applied to a plastic synaptic element at a specific section (310) on the time axis, and the voltage intensity (311) of the bias applied to the plastic synaptic element may be different. For example, the voltage intensity (311) of the bias may be 3 V, 6 V, 9 V, or 12 V, as illustrated in Fig. 3b. When a bias is applied to a plastic synaptic element at a specific section (310), the conductance of the plastic synaptic element may increase at the specific section (310). The greater the voltage intensity (311), the greater the conductance increase. If no additional bias is applied to the plastic synaptic element after the specific section (310), the conductance of the plastic synaptic element decreases.

[0062] Figure 3c is a graph showing the conductance change characteristics of a plastic synaptic element according to a pulse signal applied to the plastic synaptic element according to one embodiment.

[0063] FIG. 3c includes a set pulse (321_1), a reset pulse (321_2), and a read pulse applied to a plastic synaptic element in a specific time interval (330, 331). The specific time interval (330) represents a time interval in which the set pulse (321_1) and the read pulse are applied to the plastic synaptic element, and the specific time interval (331) represents a time interval in which the reset pulse (321_2) and the read pulse are applied to the plastic synaptic element. For example, the set pulse (321_1) applied to the plastic synaptic element in the specific time interval (330) corresponds to a voltage of 15 V, and the set pulse (321_1) is applied 50 times during the specific time interval (330). According to the conductance change characteristic (320), when the number of set pulses (321_1) applied to the plastic synaptic element increases during a specific section (330), the conductance value of the plastic synaptic element increases. After the specific section (330), the application of the set pulse (321_1) to the plastic synaptic element is terminated in a specific section (331), and a reset pulse (321_2) is applied. For example, the reset pulse (321_2) applied to the plastic synaptic element in the specific section (331) corresponds to a voltage of 0 V, and the reset pulse (321_2) is applied 50 times during the specific section (331). By the reset pulse (321_2) of 0 V voltage, the conductance of the plastic synaptic element is de-echoed during the specific section (331) and converges toward a constant conductance value.

[0064] Figures 4a to 4d illustrate examples of plastic synaptic elements.

[0065] The plastic synaptic elements may include elements comprising anisotropic materials such as alpha molybdenum trioxide (α-MoO3), elements based on a mixture of fine metal wires and polymers aligned in a predetermined direction, and elements based on a charge trap mechanism. For example, the plurality of plastic synaptic elements may include a conductive bridging RAM (CBRAM) (410), a diffusive memristor (420), and a charge-trap optical memristor (430) or charge-trap transistor (440).

[0066] In FIG. 4A, a CBRAM (410) according to one embodiment may have a structure (411) including PVP between device layers including silver (Ag). When a specific electric pulse (412) greater than a threshold value is applied to the CBRAM (410), the CBRAM (410) may form a conductive filament. For example, the conductive filament may be formed by positive silver (Ag) ions in a device layer including silver (Ag) at the (+) terminal. + ) can be formed by moving to the element layer including silver located at the (-) terminal and accumulating in the PVP. When a conductive filament is formed in the CBRAM (410), the conductance value (413) of the CBRAM (410) can increase. When another electrical pulse is disabled to the CBRAM (410) after the conductance value (413) of the CBRAM (410) increases, the CBRAM (410) can dissolve the formed conductive filament. When the conductive filament is dissolved, the conductance value (413) of the CBRAM (410) can decrease nonlinearly over time. The CBRAM (410) can have different conductance value decrease ranges depending on the manufacturing method and the ratio of materials forming the CBRAM (410).

[0067] In FIG. 4b, a diffusive memristor (420) according to one embodiment may have a structure in which titanium (Ti), titanium oxide (TiOx, TiOy), and platinum (Pt) are sequentially stacked. When an electrical signal (e.g., a voltage pulse) (422) greater than a threshold value is applied to the diffusive memristor (420), a change (423) in the current intensity flowing in the diffusive memristor may occur according to the movement of vacancies or ions in the diffusive memristor. The change in the current intensity flowing in the diffusive memristor (420) may decrease and converge to a specific current value in the absence of other electrical signals.

[0068] In FIG. 4C, a charge-trap optical memristor (430) according to one embodiment may include a specific material that reacts to light irradiation, and the specific material may change the internal charge state of the charge-trap optical memristor (430) by absorbing or emitting light energy. The charge-trap optical memristor (430) may store or release charges in a trap structure included in the charge-trap optical memristor (430) based on the intensity of light irradiation or the time of light irradiation. The resistance value of the charge-trap optical memristor (430) may change nonlinearly depending on the amount of charge stored in the trap structure. For example, when a voltage pulse (431) having a magnitude of about 4.5 V is applied to the charge-trap optical memristor (430) for 0.75 seconds, the current flowing in the charge-trap optical memristor (430) may decrease depending on the number of times the voltage pulse (431) is applied.

[0069] In FIG. 4D, according to one embodiment, a charge-trap transistor (440) may include silicon oxide (SiO2), molybdenum disulfide (MoS2), and silver (Ag). The charge-trap transistor maintains a state in which there is almost no charge in the trap structure before voltage is applied to the gate, and when voltage is applied to the gate, charge can be stored in the trap structure. The charge-trap transistor (440) changes the conductivity of the channel according to the amount and position of the stored charge, and thus the conductance (or resistance) can be changed. The charge-trap transistor (440) can maintain a resistance value by maintaining the charge stored in the trap structure even when the voltage application to the gate is terminated.

[0070] Figure 5 schematically illustrates an accumulation computing method according to the present invention.

[0071] An input signal (510) may be input to an accumulation computing device (511) according to the present invention. The input signal (510) may be a signal converted from digital to analog by a converter from digital input data. For example, the input signal (510) may be a voltage pulse signal converted by a converter based on digital input data.

[0072] The accumulation computing device (511) can apply an input signal (510) to at least one of a plurality of electrodes, thereby inducing a change in the impedance size of a plurality of plastic synaptic elements symmetrically connected to the at least one electrode. After the application of the input signal (510) is terminated, the accumulation computing device (511) can read a composite impedance value of a plurality of plastic synaptic elements connected to a reading target electrode among a plurality of electrodes arranged in an array structure. Based on the composite impedance value of the plurality of plastic synaptic elements symmetrically connected to each of the plurality of electrodes read by the accumulation computing device (511), a unique weight for each input signal (511) can be obtained. A weight included in a machine learning model (512) can be updated with the composite impedance value read by the accumulation computing device (511), and the input signal (511) can be classified based on the updated weight.

[0073] Figure 6 is a flowchart of an accumulation computing method performed by an accumulation computing device.

[0074] In step (601), the accumulating computing device can enable an input signal to be applied to the input target electrode, which causes an impedance change of at least one plastic synaptic element among a plurality of plastic synaptic elements symmetrically connected to the input target electrode among a plurality of electrodes arranged in an array structure, from a first impedance magnitude to a second impedance magnitude. Based on the input signal applied to the input target electrode, the specific impedance change characteristic of the at least one plastic synaptic element is as described above with reference to FIGS. 2 to 4d.

[0075] In step (602), the storage computing device can disable an input signal to at least one electrode so that the impedance of at least one plastic synaptic element nonlinearly decays from a second impedance magnitude toward a first impedance magnitude. The decay width of the impedance over time may vary depending on differences in the types or component ratios of each of the plurality of plastic synaptic elements connected to the at least one electrode. Due to the difference in the impedance decay width of each of the plurality of plastic synaptic elements, each of the plurality of plastic synaptic elements may converge to a different impedance magnitude.

[0076] In step (603), the accumulation computing device can read the composite impedance values ​​of the plurality of plastic synaptic elements based on the read target electrode based on applying a read bias signal to the read target electrode. The composite impedance values ​​of the plurality of plastic synaptic elements connected to the read target electrode can correspond to a unique weight value corresponding to an input signal applied to the read target electrode. The accumulation computing device can simultaneously read the composite impedance values ​​of the plurality of plastic synaptic elements based on the plurality of read target electrodes.

[0077] FIG. 7 illustrates an accumulator computing device applying an input signal according to one embodiment. The accumulator computing device can input the input signal to at least one electrode among a plurality of electrodes through a control unit (not shown). The input data (701) can be binarized through the control unit included in the accumulator computing device or another external processor (or device). The binarized input data (702) can include a value corresponding to a pixel unit of the input data (701). For example, a pixel portion having color information among the input data (701) can correspond to 1 among the values ​​of the binarized input data (702), and a pixel portion not including color information (e.g., null) can correspond to 0 among the values ​​of the binarized input data (702). The binarized input data (702) can be chopped (or split). For example, if the binarized input data (702) is configured as a matrix, the chopped data (703) may correspond to each row. The chopped data (703) may be mapped to each of a plurality of electrodes. For example, data corresponding to the first row of the chopped data (703) may be mapped to the 0th electrode (704). For example, data corresponding to the second row of the chopped data (703) may be mapped to the 1st electrode. The input signal may be a signal obtained by merging the chopped data (703). The storage computing device may input values ​​corresponding to each column of the input signal to the plurality of electrodes based on the result of the chopped data (703) being mapped to the plurality of electrodes.

[0078] FIG. 8A is a diagram showing an input signal being applied to a plurality of electrodes of an accumulative computing device according to one embodiment, and a diagram showing an input signal being applied to the plurality of electrodes at different times.

[0079] As illustrated in FIG. 8A, an accumulative computing device (800) according to one embodiment may include a plurality of electrodes (803) arranged in an array structure, a plurality of plastic synaptic elements symmetrically connected to at least one of the plurality of electrodes, and a control unit (801). The control unit (801) may be connected to the plurality of electrodes (803) as described above, and may be connected to a node (804) defined by the plurality of plastic synaptic elements connected to at least one electrode and the plastic synaptic elements connected to another electrode. An input signal (802) may be applied to at least one of the plurality of electrodes (803) by the control unit (801) connected to the plurality of electrodes (803). The control unit (801) may ground the node (804) prior to applying the input signal (802) to at least one of the plurality of electrodes (803). The control unit (801) can apply an input signal to an electrode among a plurality of electrodes to which an input signal is mapped at individual points in time (e.g., a first point in time (810), a second point in time (820)) according to a preset time interval.

[0080] The control unit (801) can individually apply first input signals among a plurality of input signals corresponding to input data to the corresponding electrodes at a first time point (810). For example, the first input signals can be applied to the electrodes (811, 813) at the first time point (810). When the first input signals are applied to the electrodes (811, 813), the impedance sizes of the plurality of plastic synaptic elements (812, 814) symmetrically connected to the electrodes (811, 813) can change. After applying the first input signals at the first time point (810), the second input signals can be applied at a second time point (820). The electrodes (811, 813) to which the first input signal is applied at the first time point (810) and the electrodes to which the second input signal is applied at the second time point (820) may be the same or different. The impedance size of the plurality of plastic synaptic elements (812) connected to the electrode (811) to which the first input signal is applied at the first time point (810) and to which the second input signal is also applied at the second time point (820) can change in proportion to the number of times the input signal is applied, as described above. The impedance value of the plurality of plastic synaptic elements (814) connected to the electrode (813) to which the first input signal is applied at the first time point (810) and to which the input signal is not applied at the second time point (820) can be nonlinearly decoded, as described above.

[0081] FIG. 8B illustrates that an input signal based on input data including time information is applied to at least one electrode among a plurality of electrodes of an accumulation computing device according to one embodiment. More specifically, the input signal based on the input data including time information may be obtained from data in which a series of still image frames (video frames) are continuously displayed over time, such as video or moving image data, but is not limited thereto. FIG. 8B illustrates that some of a series of still image frames included in the input signal are input by an accumulation computing device according to one embodiment. Each image frame (830, 840, 850) may be a set of pixels, and each pixel may form an array arrangement on each image frame (830, 840, 850) as illustrated in FIG. 8B. The accumulation computing device may match each of the plurality of electrodes with each of the pixels of the image frames (830, 840, 850). For example, FIG. 8B expresses the matching relationship between each of the plurality of electrodes and each of the pixels by writing the same number on the plurality of electrodes and pixels. An input signal corresponding to a pixel (831) among a plurality of pixels included in a first image frame (830) may be applied to an electrode (832) in a matching relationship. When the input signal is applied to the electrode (832), the impedance values ​​of a plurality of plastic synaptic elements surrounding the electrode (832) may change based on the input signal. The impedance value change characteristics of the plurality of plastic synaptic elements are as described above. After the application of the input signal corresponding to the pixel (831) included in the first image frame (830) to the electrode (832) is completed, an input signal corresponding to the pixel (841) included in the second image frame (840) may be applied to the electrode (842) in a matching relationship. When the input signal is applied to the electrode (842), the impedance values ​​of a plurality of plastic synaptic elements surrounding the electrode (842) may change based on the input signal.After the application of the input signal corresponding to the pixel (841) is completed, the input signal corresponding to the pixel (850) included in the third image frame (850) can be applied to the electrode (852) in a matching relationship, and the impedance values ​​of the plurality of plastic synaptic elements surrounding the electrode (852) can change based on the input signal. By sequentially applying the input signal corresponding to the pixel value included in each image frame (830, 840, 850) to at least one electrode among the plurality of electrodes of the accumulation computing device, a composite impedance value including the correlation between the image frames (830, 840, 850) can be read. More specifically, the relationship between the image frames (830, 840, 850) may include, for example, a positional relationship in which the value of a pixel (831) of the image frame (830) sequentially moves to a pixel (841) and a pixel (851) in each of the image frames (840) and (850), when the input data is a video.

[0082] FIG. 9 illustrates a synthetic impedance reading operation for a plurality of plastic synaptic elements of an accumulation computing device according to one embodiment. A control unit of the accumulation computing device may terminate the grounding of a plurality of nodes when an input signal is not applied to at least one electrode or when the application of an input signal is terminated. The control unit may terminate the grounding of all nodes included in the accumulation computing device, or may selectively terminate the grounding of only the nodes surrounding the read target electrodes (901, 902). When the grounding of the plurality of nodes is terminated, the control unit may ground other surrounding electrodes surrounding the read target electrodes (901, 902). The control unit may read the synthetic impedance values ​​of the plurality of plastic synaptic elements based on applying a read bias signal (910, 920) to the read target electrodes (901, 902) while other surrounding electrodes are grounded based on the read target electrodes (901, 902).

[0083] For example, when the control unit reads the composite impedance value of a plurality of plastic synaptic elements connected to a read target electrode (901) arranged at a corner of an array structure among a plurality of electrodes included in an accumulation computing device, as illustrated in FIG. 9, the control unit terminates the grounding of nodes adjacent in three directions (e.g., in the vertically downward direction, and in the counterclockwise direction at 45 degrees and 90 degrees with respect to the vertically downward direction) with respect to the read target electrode (901), grounds the electrodes (930) arranged in three directions surrounding the read target electrode (901), and while the electrodes (930) are grounded, applies a read bias signal (910) to the read target electrode (901), thereby reading the composite impedance value of a plurality of plastic synaptic elements positioned between the read target electrode (901) and the electrodes (930).

[0084] As another example, when the control unit reads the composite impedance value of a plurality of plastic synaptic elements connected to the read target electrode (902) in eight directions based on the read target electrode (902) among a plurality of electrodes, the control unit terminates the grounding of the nodes adjacent in the eight directions, grounds the electrodes (940) surrounding the read target electrode (902) and positioned in the eight directions, and then, while the electrodes (940) are grounded, applies a read bias signal (920) to the read target electrode (902), thereby reading the composite impedance value of a plurality of plastic synaptic elements located between the read target electrode (902) and the electrodes (940). The control unit can individually apply a read bias signal to at least one electrode and the other electrode, when the other electrode is spaced apart from at least one electrode to which the input signal is applied by at least two nodes on an axis from the other electrode to which the input signal is applied, and individually sweep and read the composite impedance values ​​of the plurality of plastic synaptic elements connected to the at least one electrode and the other electrode, respectively. For example, when the reading target electrode (901) and the other electrode (903) are spaced apart from the reading target electrode (901) by at least two nodes on an axis from the reading target electrode (901) to the other electrode (903) as illustrated in FIG. 9, the control unit can individually apply a read bias signal to the reading target electrode (901) and the other electrode (9030), and individually sweep and read the composite impedance values ​​of the plurality of plastic synaptic elements connected to the reading target electrode (901) and the other electrode (903).

[0085] FIG. 10 is a schematic diagram illustrating a method for reading a synthetic impedance value of a plastic synaptic element from input data by an accumulation computing device.

[0086] Sequence data (1005) may include partial data (1006) for each time point (or group) and may be generated (or determined) based on binarization (1002), chopping (1003), and merging (1004) of input data (1001). The partial data (1006) may include a set of input values ​​corresponding to any time point in the input data (1001). Assuming that the input data (1001) is a matrix, partial data (1006) corresponding to any time point (e.g., input values ​​arranged along the same column) may be input to the storage computing device at the same time point.

[0087] Partial data (1006) (e.g., column data) corresponding to any point in time in the sequence data (1005) may include input values ​​corresponding to multiple entries. If there are N entries, each partial data (1006) may include N input values. The multiple entries may be individually mapped to multiple electrodes of the device. In this specification, an example in which the number of entries and the number of electrodes are the same and are mapped one-to-one is mainly described, but the present invention is not limited thereto. For example, the value of the 1st entry of the partial data (1006) at any point in time may be applied to the 1st electrode, and the value of the nth entry may be applied to the nth electrode.

[0088] An accumulation computing device can sequentially receive partial data (1007, 1008) corresponding to a plurality of time points from sequence data (1005). The accumulation computing device can apply input signals corresponding to each of the sequentially acquired partial data (1007, 1008). The input signal can be a signal corresponding to an input value of a corresponding entry (e.g., a voltage signal having a voltage level corresponding to the input value). The accumulation computing device can apply input signals of the partial data of each time point to electrodes for each of the time points. For example, the accumulation computing device can individually and simultaneously apply input signals of the partial data (1007) corresponding to a first time point to the corresponding electrodes. The accumulation computing device can individually apply input signals of the partial data (1008) corresponding to a second time point subsequent to the first time point to the corresponding electrodes. The accumulation computing device can adjust an interval between the first time point and the second time point subsequent to the first time point. The time interval between the first time point and the second time point controlled by the accumulation computing device may correspond to the longest time among the decaying times of the impedance magnitudes of the plurality of plastic synaptic elements included in the accumulation computing device. The accumulation computing device may read the composite impedance value of the plurality of plastic synaptic elements at each time interval between the first time point and the second time point.

[0089] FIG. 11A illustrates an embodiment of at least one electrode having anisotropy along a connection direction and a plurality of plastic synaptic elements symmetrically connected to at least one electrode.

[0090] Among the plurality of electrodes included in the storage computing device, a plurality of plastic synaptic elements (1101, 1102, 1103) symmetrically connected to at least one electrode (1100) may have the same impedance change characteristics. Alternatively, the impedance change characteristics of at least one of the plurality of plastic synaptic elements (1101, 1102, 1103) symmetrically connected to at least one electrode (1100) may be different from the impedance change characteristics of other plastic synaptic elements. For example, when a plurality of plastic synaptic elements are connected to at least one electrode (1100) in eight directions, the impedance change characteristics of the plurality of plastic synaptic elements may all be different in each direction. The impedance change characteristics of the plurality of plastic synaptic elements may correspond to the amount of impedance increase or decrease of the plastic synaptic element when the same input signal is applied, or may include the impedance decay time when the input signal is not applied, but is not limited thereto. As illustrated in Fig. 11a, the plurality of plastic synaptic elements (1101, 1102, 1103) symmetrically connected to at least one electrode (1100) may have different impedance change characteristics depending on the position of each axis along which they are arranged. For example, the plastic synaptic elements (1101) on the first axis may have the same impedance change characteristics, the plastic synaptic elements (1102) on the second axis may have the same impedance change characteristics, and the plastic synaptic elements (1101) on the first axis and the plastic synaptic elements (1102) on the second axis may have different impedance change characteristics.

[0091] Figures 11b to 11d are graphs of the synthetic impedance values ​​of plastic synaptic elements according to the presence or absence of anisotropy for the same input signal.

[0092] For the same input data (1110a to 1110f), when a plurality of plastic synaptic elements symmetrically connected to at least one electrode all have the same impedance change characteristic (or there is no anisotropy), the graphs of the composite impedance values ​​(1120a to 1120f) of the plurality of plastic synaptic elements may include at most two and at least one composite impedance value. For example, for the input data (1110a), when the input nodes on the x-axis (e.g., electrodes to which the input signal is applied) are 0 and 1, the composite impedance values ​​corresponding to the y values ​​may represent the same value of 0.4. In addition, when the input nodes on the x-axis are 2 and 3, the composite impedance values ​​corresponding to the y values ​​may represent the same value of 0.2.

[0093] For the same input data (1110a to 1110f), when a plurality of plastic synaptic elements symmetrically connected to at least one electrode have different impedance change characteristics (or anisotropy) depending on the position of each axis along which the plurality of plastic synaptic elements (1101, 1102, 1103) symmetrically connected to at least one electrode (1100) are arranged, as illustrated in FIG. 11a, the composite impedance value graphs (1130a to 1130f) of the plurality of plastic synaptic elements may include at least two and at most four composite impedance values. For example, for the input data (1110a), in each case where the input nodes on the x-axis are 0, 1, 2, and 3, the composite impedance values ​​corresponding to the y values ​​may represent values ​​of 0.065, 0.08, 0.055, and 0.065, respectively. Comparing the synthetic impedance value graph (1120a) and the synthetic impedance value graph (1130a), it can be confirmed that the case where anisotropy is included can display more synthetic impedance values ​​than the case where it is not included.

[0094] In this document, each of the phrases "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" may include any one of the items listed together in that phrase, or all possible combinations thereof.

[0095] Although the embodiments described above have been described with limited drawings, those skilled in the art will appreciate that various technical modifications and variations can be applied based on the described embodiments. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

[0096] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

Claims

1. In an accumulation computing device, A plurality of electrodes arranged in an array structure; and A plurality of plastic synaptic elements symmetrically connected to at least one of the plurality of electrodes, connected to a plastic synaptic element of another electrode through a node, and having an impedance that varies based on at least one of enabling or disabling an input signal to the at least one electrode Including, The impedance of at least one plastic synaptic element among the plurality of plastic synaptic elements is, In response to an input signal being enabled to at least one of the electrodes, the first impedance size changes to a second impedance size based on the applied input signal, nonlinearly decaying from the second impedance magnitude toward the first impedance magnitude in response to the input signal being disabled; Accumulative computing device.

2. In paragraph 1, A plurality of plastic synaptic elements symmetrically connected to at least one of the plurality of electrodes have the same impedance change characteristics. Accumulative computing device.

3. In paragraph 1, The impedance change characteristic of at least one of the plurality of plastic synaptic elements symmetrically connected to at least one of the plurality of electrodes is different from the impedance change characteristic of the other plastic synaptic elements. Accumulative computing device.

4. In paragraph 1, The plastic synaptic elements on the first axis have identical impedance change characteristics. The plastic synaptic elements on the second axis have identical impedance change characteristics. The plastic synaptic elements on the first axis and the plastic synaptic elements on the second axis have different impedance change characteristics. Accumulative computing device.

5. In paragraph 1, The above multiple plastic synaptic elements are, At least one of an anisotropic material, a device based on a polymer mixture and fine metal wires aligned in a predetermined direction, a device based on a charge trap mechanism, or a device based on a change in conductivity due to lattice vacancies and ion movement. Accumulative computing device.

6. In paragraph 1, A control unit that applies or does not apply an input signal that causes a nonlinear change in the impedance size of at least one plastic synaptic element among the plurality of plastic synaptic elements to the at least one electrode, and reads a composite impedance value of the plurality of plastic synaptic elements based on the read target electrode by applying a read bias signal to the read target electrode. Including more Accumulative computing device.

7. In paragraph 6, The above control unit, Applying the input signal generated based on the result of merging the chopped data from the binarized input data to the at least one electrode. Accumulative computing device.

8. In paragraph 6, The above control unit, Among the plurality of input signals corresponding to the input data, the first input signals are individually applied to the corresponding electrodes, Among the above multiple input signals, the second input signals are individually applied to the corresponding electrodes, After applying the first input signals, the second input signals are applied. Accumulative computing device.

9. In paragraph 6, The above control unit, Grounding a plurality of nodes surrounding at least one electrode, between the plurality of plastic synaptic elements and the plastic synaptic elements of other electrodes, and applying an input signal to the at least one electrode while the plurality of nodes are grounded. Accumulative computing device.

10. In paragraph 6, The above control unit, If an input signal is not applied to at least one of the above electrodes, the grounding of multiple nodes is terminated. Accumulative computing device.

11. In paragraph 6, The above control unit, Grounding other surrounding electrodes surrounding the target electrode to be read, and reading the composite impedance value of a plurality of plastic synaptic elements based on applying a reading bias signal to the target electrode while the other surrounding electrodes are grounded based on the target electrode to be read. Accumulative computing device.

12. In paragraph 6, The above control unit, When at least one electrode to which the input signal is applied and the other electrode are spaced apart such that at least two or more nodes are included on an axis from the at least one electrode to which the input signal is applied to the other electrode, By individually applying a read bias signal to at least one electrode and the other electrode, the composite impedance value of a plurality of plastic synaptic elements connected to each of the at least one electrode and the other electrode is individually swept and read. Accumulative computing device.

13. In a method performed by an accumulation computing device, A step of enabling an input signal to at least one electrode, which causes a change in impedance of at least one plastic synaptic element among a plurality of plastic synaptic elements symmetrically connected to at least one electrode among a plurality of electrodes arranged in an array structure from a first impedance magnitude to a second impedance magnitude; disabling the input signal to the at least one electrode such that the impedance of the at least one plastic synaptic element nonlinearly decays from the second impedance magnitude toward the first impedance magnitude; and A step of reading the composite impedance value of a plurality of plastic synaptic elements based on the reading target electrode by applying a read bias signal to the reading target electrode. A method including:

14. In paragraph 13, The step of applying the above input signal is: A step of applying the input signal generated based on the result of merging the chopped data from the binarized input data to the at least one electrode. A method including:

15. In paragraph 13, The step of applying the above input signal is: A step of individually applying first input signals among a plurality of input signals corresponding to input data to corresponding electrodes; and A step of individually applying second input signals among the plurality of input signals to corresponding electrodes after applying the first input signals; A method including:

16. In paragraph 13, The step of applying the above input signal is: A step of grounding a plurality of nodes surrounding at least one electrode, between the plurality of plastic synaptic elements and the plastic synaptic elements of other electrodes; and A step of applying an input signal to at least one electrode while the above plurality of nodes are grounded. A method including:

17. In paragraph 13, The step of disabling the above input signal is: Step to terminate grounding of multiple nodes A method including:

18. In paragraph 13, The step of reading the above synthetic impedance value is: A step of grounding other electrodes around the electrode to be read among the plurality of electrodes; and A step of reading the composite impedance value of a plurality of plastic synaptic elements based on the read target electrode by applying a read bias signal to the read target electrode while other surrounding electrodes are grounded. A method including:

19. In paragraph 13, The step of reading the above synthetic impedance value is: At least one electrode to which the above input signal is applied and another electrode, If at least two nodes are spaced apart from at least one electrode to which the input signal is applied and are directed toward the other electrode, A step of individually sweeping and reading the composite impedance values ​​of a plurality of plastic synaptic elements connected to each of the at least one electrode and the other electrode by individually applying a read bias signal to the at least one electrode and the other electrode. A method including:

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