Semiconductor substrate, manufacturing method, and image sensor

Abstract

A semiconductor substrate, a manufacturing method, and an image sensor. The semiconductor substrate (1) comprises: a base (100), the base (100) having a first surface (101); a capture layer (200), the capture layer (200) being located on the side of the base (100) away from the first surface (101), and the capture layer (200) being used for capturing metal ions from the base (100) or capturing metal ions passing through the base (100); and a back sealing layer (300), the back sealing layer (300) being located on the side of the capture layer (200) away from the base (100). By providing the capture layer on one side of the base of the semiconductor substrate, the external gettering capability of the semiconductor substrate is improved. The semiconductor substrate is used as a substrate of an image sensor, reducing dark current and the number of white pixels of the image sensor.

Description

Semiconductor substrate, preparation method and image sensor

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on August 30, 2023, with application number 202311114955.5 and invention name “Semiconductor substrate, preparation method and image sensor”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application belongs to the field of semiconductor technology, and specifically relates to a substrate, an image sensor, and a method for manufacturing the same. Background Art

[0003] Semiconductor substrates are the basic materials used to manufacture semiconductor devices. Silicon substrates have good electrical properties, thermal stability and processability, and are commonly used semiconductor substrate materials. The quality of silicon substrates is crucial to the performance and manufacturing of semiconductor devices. Technical issues

[0004] Semiconductor substrates have low external gettering capabilities and are easily contaminated by metal ions, resulting in relatively low product yields. When used in devices, these substrates can produce high dark currents and a high number of white pixels, impacting chip quality. Technical Solutions

[0005] An embodiment of the present application provides a semiconductor substrate, comprising:

[0006] a substrate having a first surface;

[0007] a capture layer, the capture layer being located on a side of the substrate away from the first surface;

[0008] A back-sealing layer is located on a side of the capture layer away from the substrate.

[0009] In some embodiments, the capture layer is used to capture metal ions, including metal ions in the substrate and metal ions that pass through the first surface into the substrate.

[0010] In some embodiments, the capture layer has a thickness of

[0011] In some embodiments, the resistivity of the substrate is 0.010 ohm-cm to 0.020 ohm-cm.

[0012] Accordingly, an embodiment of the present application provides a method for preparing a semiconductor substrate, comprising:

[0013] providing a substrate having a first surface;

[0014] forming a capture layer, wherein the capture layer is located on a side of the substrate away from the first surface;

[0015] A back sealing layer is formed, and the back sealing layer is located on a side of the capture layer away from the substrate.

[0016] In some embodiments, the capture layer has a thickness of

[0017] In some embodiments, the step of forming the capture layer comprises:

[0018] forming a second polysilicon layer, wherein the second polysilicon layer is located on the first surface;

[0019] forming a first polysilicon layer, wherein the substrate has a second surface away from the first surface, and the second polysilicon layer is located on the second surface;

[0020] The second polysilicon layer is removed, and the first polysilicon layer is retained; the first polysilicon layer serves as the capture layer.

[0021] In some embodiments, the first polysilicon layer is prepared by the following method: using silicon-containing gas to deposit a polysilicon layer on the surface of the substrate; the consumption of the silicon-containing gas is

[0022] In some embodiments, the second polysilicon layer is prepared by the following method: using silicon-containing gas to deposit a polysilicon layer on the surface of the substrate; the consumption of the silicon-containing gas is

[0023] In some embodiments, in the step of forming the first polysilicon layer, the substrate is placed in an environment with a temperature ranging from 600° C. to 660° C.

[0024] In some embodiments, in the step of forming the second polysilicon layer, the substrate is placed in an environment with a temperature ranging from 600° C. to 660° C.

[0025] In some embodiments, the second polysilicon layer is removed by a chemical mechanical polishing method, and the chemical mechanical polishing method includes: grinding the second polysilicon layer to remove the second polysilicon layer.

[0026] In some embodiments, the first substrate is adsorbed on a polishing head having a chamber. Along the thickness direction of the semiconductor substrate, the chamber has a first thickness H1 μm, and the first substrate has a second thickness H2 μm, satisfying: 0

[0027] ​An embodiment of the present application provides an image sensor, which includes the above-mentioned semiconductor substrate; or, the image sensor includes a semiconductor substrate prepared by the above-mentioned method for preparing a semiconductor substrate; the semiconductor substrate serves as a base of the image sensor.

[0028] In some embodiments, the semiconductor substrate includes a P-type substrate. Beneficial effects

[0029] This application provides a semiconductor substrate, a preparation method, and an image sensor. The semiconductor substrate includes: a base having a first surface; a capture layer located on a side of the base away from the first surface, the capture layer being configured to capture metal ions from the base or metal ions that pass through the base; and a back-sealing layer located on a side of the capture layer away from the base. This application improves the external gettering capability of the semiconductor substrate by providing the capture layer on the base side of the semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0031] FIG1 is a flow chart of a manufacturing process of a semiconductor substrate in an embodiment of the present application;

[0032] FIG2 is a flow chart of a manufacturing process of a semiconductor substrate in an embodiment of the present application;

[0033] FIG3 is a flow chart of a manufacturing process of a semiconductor substrate in an embodiment of the present application;

[0034] FIG4 is a schematic structural diagram of a semiconductor substrate in an embodiment of the present application;

[0035] FIG5 is a schematic diagram of the structure of an image sensor according to an embodiment of the present application;

[0036] FIG6 is a schematic structural diagram of a grinding disk and a semiconductor substrate according to an embodiment of the present application;

[0037] FIG7 shows the geometric flatness test results of the semiconductor substrate prepared in the embodiment of the present application, wherein FIGA shows the maximum local flatness SFQR test result; FIGB shows the maximum edge flatness ESFQR test result; FIGC shows the maximum local flatness mean result; FIGD shows the maximum edge flatness mean result; and FIGE shows the maximum local flatness test result of the 95% distribution number;

[0038] FIG8 is a schematic structural diagram of an image sensor prepared in an embodiment of the present application;

[0039] FIG9 is a schematic structural diagram of a front-illuminated image sensor according to an embodiment of the present application;

[0040] FIG10 is a dark current test result of a semiconductor substrate used in an image sensor according to an embodiment of the present application;

[0041] FIG11 is a white pixel detection result of an image sensor in which a semiconductor substrate is applied in an embodiment of the present application;

[0042] Figure numerals: 1-semiconductor substrate, 100-base, 101-first surface, 102-second surface, 110-first substrate, 200-capture layer, 210-first polysilicon layer, 220-second polysilicon layer, 300 back sealing layer; 2-grinding disk, 3-polishing head, 300-chamber, 301-bottom surface.

[0043] Implementation Methods of the Application

[0044] The following will provide a clear and complete description of the technical solutions in the embodiments of the present application, in conjunction with the embodiments of the present application. It should be noted that the embodiments described are only a portion of the embodiments of the present application, and are not intended to be exhaustive. All other embodiments derived by persons skilled in the art based on the embodiments of the present application without inventive effort are intended to fall within the scope of protection of the present application. Furthermore, in the description of the present application, the term "including" means "including but not limited to." The terms "first," "second," and "third," etc., are used merely as designations and do not impose numerical requirements or establish an order. Various embodiments of the present application may be presented in the form of a range. It should be understood that describing in a range format is merely for convenience and brevity and should not be construed as a rigid limitation on the scope of the present application. Therefore, the range description should be considered to specifically disclose all possible subranges and individual numerical values ​​within the range. For example, a range description of 1 to 6 should be considered to specifically disclose subranges, such as 1 to 3, 1 to 4, 1 to 5, 2 to 4, 2 to 6, 3 to 6, etc., as well as individual numerical values ​​within the range, such as 1, 2, 3, 4, 5, and 6, regardless of the range. In addition, whenever a numerical range is indicated herein, it is intended to include any cited numeral (fractional or integer) within the indicated range. In this application, the X direction is the thickness direction, and the Y direction is the extending direction of the semiconductor substrate.

[0045] As shown in FIG4 , an embodiment of the present application provides a semiconductor substrate, comprising: a base 100 having a first surface 101; a capture layer 200 located on a side of the base 100 away from the first surface 101, the capture layer 200 being used to capture metal ions from the base 100 or metal ions that pass through the base 100; and a backing layer 300 located on a side of the capture layer 200 away from the base 100. The present application provides the capture layer 200 on one side of the base 100 to enhance the semiconductor substrate's external impurity gettering capability, effectively reduce metal ion contamination, and improve the product yield.

[0046] In some embodiments, the capture layer 200 has a thickness of For example, the thickness of the capture layer 200 The value of is any value among 1000, 2000, 3000, 4000, 5000, 6000, 7000, 8000 or a range consisting of any two values. For example, the thickness of the capture layer 200 is or, In this application, since the capture layer 200 may deteriorate the geometric flatness of the substrate, the thickness of the capture layer 200 in this application is Within this range, the external gettering function of the semiconductor substrate of the present application can be satisfied while the degradation degree of the device flatness caused by the setting of the capture layer 200 can be improved.

[0047] In some embodiments, the substrate 100 is a silicon substrate, and the resistivity of the substrate 100 is 0.010 ohm-cm to 0.020 ohm-cm. For example, the resistivity (ohm-cm) of the substrate 100 is any value selected from 0.01, 0.011, 0.012, 0.013, 0.014, 0.015, 0.016, 0.017, 0.018, 0.019, and 0.020, or a range consisting of any two values.

[0048] In some embodiments, the resistivity of substrate 100 is changed by methods such as ion doping of the silicon substrate, which may be performed by ion implantation. Alternatively, during the silicon substrate preparation process, doping elements of varying concentrations are added to the silicon material to change the resistivity of substrate 100.

[0049] In some embodiments, the capture layer 200 includes polycrystalline silicon, which serves as a gettering material for capturing metal ions from the epitaxial layer. When used in a device, the semiconductor substrate of the present application can capture metal ions in the device layer, reducing the device's dark current and the number of white pixels.

[0050] In some embodiments, the backing layer 300 is a silicon oxide layer, and the thickness of the backing layer 300 is For example, the thickness of the back cover layer 300 It is any value among 3000, 3100, 3200, 3300, 3400, 3500, 3600, 3700, 3800, 3900, 4000, or a range consisting of any two values.

[0051] In some embodiments, the backing layer 300 includes low temperature silicon oxide (LTO).

[0052] In some embodiments, the temperature for low-temperature silicon oxide deposition is 400° C. to 800° C., for example, the deposition temperature (° C.) is any value of 400, 450, 500, 550, 600, 650, 700, 750, 800, or a range consisting of any two values. In some embodiments, the preparation temperature of the backing layer 300 is 600° C. to 650° C.

[0053] In some embodiments, the backing layer 300 is prepared by chemical vapor deposition on the substrate 100 having the capture layer 200. In some embodiments, the oxygen flow rate (Standard Cubic Centimeters per Minute, sccm) ranges from 495 to 616. In some embodiments, the SiH4 flow rate (Standard Cubic Centimeters per Minute, sccm) ranges from 45 to 56.

[0054] In some embodiments, the present invention provides a method for preparing a semiconductor substrate, comprising:

[0055] As shown in FIG1 , a substrate 100 is provided, and the substrate 100 has a first surface 101 ;

[0056] A capture layer 200 is formed, and the capture layer 200 is located on the side of the substrate 100 away from the first surface 101 ; a backing layer 300 is formed, and the backing layer 300 is located on the side of the capture layer 200 away from the substrate 100 .

[0057] In some embodiments, the capture layer 200 has a thickness of

[0058] As shown in FIG2 , the steps of forming the capture layer 200 include:

[0059] forming a second polysilicon layer 220 , wherein the second polysilicon layer 220 is located on the first surface 101 ;

[0060] A first polysilicon layer 210 is formed, the substrate 100 has a second surface 102 away from the first surface 101 , and a second polysilicon layer 220 is located on the second surface 102 ;

[0061] As shown in FIG. 3 , the second polysilicon layer 220 is removed, and the first polysilicon layer 210 is retained; the first polysilicon layer 210 serves as the capture layer 200 .

[0062] In some embodiments, the first polysilicon layer 210 is prepared by the following method: using silicon-containing gas to deposit the first polysilicon layer 210 on the surface of the substrate 100; the consumption of the silicon-containing gas is Such as the consumption of silicon-containing gas The value of is any value selected from 2.0, 2.5, 3.0, 3.5, and 4.0, or a range consisting of any two values. The present application controls the thickness of the first polysilicon layer 210 by controlling the consumption of the silicon-containing gas, and also controls the deposition rate of the first polysilicon layer 210 on the surface of the substrate 100, thereby reducing the impact of the preparation of the polysilicon layer on the flatness of the semiconductor substrate 1.

[0063] In some embodiments, the second polysilicon layer 220 is prepared by the following method: using silicon-containing gas to deposit the second polysilicon layer 220 on the surface of the substrate 100; the consumption of the silicon-containing gas is Such as the consumption of silicon-containing gas The value of is any value among 2.0, 2.5, 3.0, 3.5, 4.0, or a range consisting of any two values. The present application controls the thickness of the second polysilicon layer 220 by controlling the consumption of the silicon-containing gas, and also controls the deposition rate of the second polysilicon layer 220 on the surface of the substrate 100, thereby improving the quality of the semiconductor substrate.

[0064] In some embodiments, during the step of forming the first polysilicon layer 210 , the substrate 100 is placed in an environment with a temperature ranging from 600° C. to 660° C.

[0065] In some embodiments, during the step of forming the second polysilicon layer 220 , the substrate 100 is placed in an environment with a temperature ranging from 600° C. to 660° C.

[0066] In some embodiments, the temperature (° C.) for forming the first polysilicon layer 210 is any value among 600, 610, 620, 630, 6405, 650, 660, or a range consisting of any two values.

[0067] In some embodiments, the temperature (° C.) for forming the second polysilicon layer 220 is any value among 600, 610, 620, 630, 6405, 650, 660, or a range consisting of any two values.

[0068] In some embodiments, polysilicon layers are simultaneously formed on both sides of the substrate 100, that is, a first polysilicon layer 210 and a second polysilicon layer 220 are simultaneously formed on both sides of the substrate 100, to obtain a first substrate 110. The first polysilicon layer 210 and the second polysilicon layer 220 are formed at a temperature in the range of 600° C. to 620° C., or in the range of 640° C. to 660° C.

[0069] When the polysilicon layer is prepared It can be prepared by the following methods:

[0070] In some embodiments, the first polysilicon layer 210 and the second polysilicon layer 220 are prepared by the following method: the first temperature range is 600° C. to 620° C., the silicon-containing gas is heated at a first flow rate of The polysilicon layer is prepared under the conditions of

[0071] In some embodiments, the second temperature range is 640°C to 660°C, and the silicon-containing gas at the second flow rate is The polysilicon layer is prepared under the conditions of

[0072] When the thickness of the prepared polysilicon layer is greater than It can be prepared by the following methods:

[0073] In some embodiments, the first polysilicon layer 210 and the second polysilicon layer 220 are prepared by the following method: the first temperature range is 600° C. to 620° C., the silicon-containing gas is heated at a third flow rate of The polysilicon layer is prepared under the conditions of

[0074] In some embodiments, the second temperature range is 640°C to 660°C, and the silicon-containing gas is at a fourth flow rate of The polysilicon layer is prepared under the conditions of

[0075] In some embodiments, the silicon-containing gas includes SiH 4 .

[0076] In some embodiments, the second polysilicon layer 220 is removed by a chemical mechanical polishing method.

[0077] As shown in FIG6 , the apparatus for performing the chemical mechanical polishing method includes a grinding disc 2 and a polishing head 3. The polishing head 3 has a chamber 300. During chemical mechanical polishing, a pressurized air bag is applied through an intermediate air pipe to adsorb the surface of the semiconductor substrate. That is, the first substrate 110 is closely attached to the polishing head 3 above by vacuum adsorption. A delivery pipe delivers a polishing liquid containing a corrosive liquid and abrasive particles. The polishing head 3 rotates at high speed to remove the second polysilicon layer 220.

[0078] In some embodiments, along the thickness direction (X direction) of the semiconductor substrate 1, the chamber 300 has a first thickness H1 μm, and the base has a second thickness H2 μm, satisfying: 0 1- -H2≤15μm, or 5μm≤H1-H2≤10μm, or 10μm≤H1-H2≤15μm.

[0079] In some embodiments, the distance between H1 and H2 refers to the distance S μm between the bottom surface 301 of the polishing head 3 and the top surface of the first substrate 110. In this application, the bottom surface or the top surface is described in relative directions and does not limit the specific structure of this application.

[0080] In some embodiments, the distance S between the bottom surface 301 of the polishing head 3 and the top surface of the first substrate 110 satisfies: 0<S≤20μm. For example, the value of S is any value among 5, 10, 15, 20, or a range consisting of any two values.

[0081] In some embodiments, the first thickness H1 of the chamber 300 is 780 μm to 790 μm, for example, the first thickness H1 is any value among 780, 785, 790, or a range consisting of any two values.

[0082] In some embodiments, the second thickness H2 of the first substrate 110 is 765 μm to 785 μm, such as any value of 765, 770, 775, 780, 785, or a range consisting of any two values.

[0083] When H1-H2 of the present application is greater than 20 μm, for example, the height of the chamber 300 is 800 μm, the thickness of the first substrate 110 is 775 μm, and the thickness of the prepared polysilicon layer is Within the range of , a geometric flatness test was performed on the obtained substrate, and it was found that the geometric flatness of the substrate was poor. However, when the distance between the lower surface of the chamber 300 and the first substrate 110 was reduced, the influence of the polysilicon layer prepared in this application on the deterioration of the geometric flatness of the substrate could be improved.

[0084] In some embodiments, the geometric flatness of the semiconductor substrate 1 in the present application can be characterized by maximum local flatness and maximum edge flatness.

[0085] In some embodiments, an optical microscope, a scanning electron microscope (SEM), or an atomic force microscope (AFM) is used as a flatness testing instrument in the present application.

[0086] ​As shown in Figures 5 and 7, an embodiment of the present application provides an image sensor (CIS, CMOS Image Sensor), which includes the above-mentioned semiconductor substrate 1, which serves as the base of the image sensor, wherein a device layer 400 is provided in the epitaxial layer of the semiconductor substrate 1.

[0087] As shown in FIG7 , in some embodiments, the semiconductor substrate of the present application is a P-type substrate, and the image sensor includes an NMOS transistor structure and a PMOS transistor structure. The image sensor shown in FIG7 of the present application is merely an example structure; the semiconductor substrate 1 of the present application may also be an N-type substrate, and the image sensor may be a front-illuminated image sensor or a back-illuminated image sensor.

[0088] In some embodiments, as shown in FIG8 , the present application provides a schematic structural diagram of a front-illuminated sensor, wherein the image sensor includes a sensor body, a color filter 500, and a lens 600. The sensor body includes a substrate and a CMOS device structure, i.e., a device layer 400, disposed on the substrate.

[0089] In some embodiments, the color filter 500 is used to capture light of different colors, and the following types of color filters can be selected: Bayer filter, X-Trans filter, etc.

[0090] In some embodiments, the lens 600 is used to focus the light and direct it onto the sensor. The following types of lenses can be selected: such as a plano-convex lens, a biconvex lens, etc.

[0091] In some embodiments, the semiconductor substrate prepared in the above embodiments of the present application is used in an image sensor to improve leakage caused by excessive metal ions in the device, which affects the dark current and the number of white pixels generated under different operating temperature conditions.

[0092] In some embodiments, the average number of dark current pixels (pixels) of an image sensor using the semiconductor substrate 1 of the present application ranges from 16.3 to 16.6.

[0093] In some embodiments, the number of white pixels (pixels) of an image sensor using the semiconductor substrate 1 of the present application ranges from 200 to 250.

[0094] Example 1:

[0095] Semiconductor substrate: A P-type single crystal silicon polished wafer with a diameter of 300 mm was selected as the substrate 100 , with a resistivity of 0.010-0.020 ohm-cm and a total thickness H2 of 775 μm before epitaxial growth.

[0096] An LPCVD furnace is selected to process the substrate 100, and the purity of the silicon-containing gas SiH4 is selected to be above 99.9999%, and the purity of N2 is selected to be above 99.9999999%. The LPCVD furnace is used for polysilicon deposition, and the same single crystal silicon material is selected for processing to prepare a polysilicon layer. The preparation process is shown in Table 1.

[0097] Removing the second polysilicon layer 220: Along the thickness direction X of the substrate, the polishing head 3 has a polishing chamber 300, and the chamber 300 has a first thickness H1 of 780 μm.

[0098] Preparation of back seal layer 300: Use APCVD furnace to process substrate 100, select silicon-containing gas SiH4 with a purity of more than 99.9999%, O2 with a purity of more than 99.9999999%, and N2 with a purity of more than 99.99999999%, use APCVD furnace to deposit low-temperature oxide layer, the deposition temperature range is 640-650℃, and select the same single crystal silicon material for processing, and prepare oxide layer back seal film thickness A semiconductor substrate as shown in FIG4 is obtained.

[0099] Example 2 to Example 12:

[0100] The preparation method is the same as that in Example 1, except that the preparation parameters of the polysilicon layer are adjusted, as shown in Table 1.

[0101] Comparative Example 1:

[0102] The capture layer 200 was not prepared.

[0103] Table 1 Preparation process parameters of semiconductor substrate

[0104] The geometric flatness of Example 5 (5k), Example 7 (4k), Example 8 (3k), Example 10 (2k), Example 11 (1K), and Comparative Example 1 (BSL) were tested, and the test results are shown in Table 2 and Figure 7.

[0105] Table 2 Test results of semiconductor substrate geometric flatness

[0106] From the results in Table 2 and FIG2 , it can be seen that the thickness of the capture layer 200 prepared in this application is In the range of , the deterioration of the geometric flatness of the semiconductor substrate 1 is improved compared with the comparative example 1 in which the capture layer 200 is not deposited. In addition, after the present application improves the CMP method, the thickness of the prepared capture layer 200 is within The degree of geometric flatness degradation within the range is suppressed. The capture layer thickness prepared in this application is within the range of The maximum local flatness (nm) ranges from 130nm to 250nm, and the capture layer thickness prepared in this application ranges from The maximum edge flatness (μm) ranges from 130nm to 250nm.

[0107] Figure 2 also shows the mean of the maximum local flatness (SFQR Mean / nm) and the mean of the maximum edge flatness (ESFQR Mean / nm) of the capture layer 200 of the present application. These results are consistent with the trends of the maximum local flatness and the maximum edge flatness, indicating that the preparation of the capture layer 200 of the present application improves the flatness degradation of the semiconductor substrate 1.

[0108] Application examples:

[0109] The semiconductor substrates 1 prepared in Example 2 (Poly+LTO 8k+3k), Example 5 (Poly+LTO 5k+3k), Example 8 (Poly+LTO 3k+3k) and Comparative Example 1 (POR) were applied to image sensors (CMOS).

[0110] The image sensor is prepared using the following method:

[0111] A circuit structure including NMOS and PMOS as shown in FIG8 is formed on the semiconductor substrate 1 using an ion implantation method.

[0112] Preparation of gate: A gate electrode is formed on the semiconductor substrate 1 using polysilicon to control the flow of current.

[0113] Oxide layer formation: Silicon dioxide is formed on the semiconductor substrate 1 as an oxide layer for isolation and protection of circuits.

[0114] Metal deposition: Copper metal is deposited on the oxide layer to form electrodes and connecting lines.

[0115] Photolithography and etching: Use photolithography to define the shape and structure of the circuit on the oxide layer. Then, etching is used to remove excess material to form the desired circuit structure.

[0116] Dielectric layer formation: A dielectric layer is formed between metal electrodes and connecting lines to isolate and protect circuits.

[0117] Metal fill: Filling the dielectric layer with metal to form the top of the electrodes and connecting lines.

[0118] Packaging and testing: After the image sensor is fabricated, packaging and testing are performed. The sensor body is encapsulated in packaging material and tested for electrical performance and image quality.

[0119] Test method: Dark current: Dark current is detected using a dark current imaging sensor.

[0120] White pixel: dark field test method.

[0121] Table 3 Test results of the semiconductor substrate prepared in this application used in a front-illuminated image sensor

[0122] From the data in Figure 10 (D-Mean in Figure 10 represents the test data of dark current), Figure 11 (Peak02 in Figure 11 represents the test data of white pixels) and Table 3, it can be seen that the verification results of the semiconductor substrate 1 prepared by the present application in the device show that the image sensor with a back polysilicon layer (green, blue and orange lines) has a significant improvement trend compared with the semiconductor substrate without a back polysilicon layer (red line). The dark current and white pixels are greatly reduced and tightened, proving that the leakage phenomenon caused by metal ion contamination generated during the processing can be better controlled by using the semiconductor substrate with a back polysilicon layer prepared by the present application. The present application can effectively improve the dark current and white pixels of CIS products, thereby improving the quality of CIS chip devices.

[0123] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0124] The above is a detailed introduction to a semiconductor substrate, a preparation method and an image sensor provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, based on the ideas of the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A semiconductor substrate, comprising: A substrate (100), wherein the substrate (100) has a first surface (101); A capture layer (200), the capture layer (200) being located on a side of the substrate (100) away from the first surface (101); A backing layer (300), wherein the backing layer (300) is located on a side of the capture layer (200) away from the substrate (100).

2. The semiconductor substrate according to claim 1, wherein Along the thickness direction (X) of the substrate (100), the thickness of the capture layer (200) is 3. The semiconductor substrate according to claim 1, wherein The resistivity of the substrate (100) is 0.010 ohm-cm to 0.020 ohm-cm.

4. A method for preparing a semiconductor substrate, comprising: Providing a substrate (100), wherein the substrate (100) has a first surface (101); forming a capture layer (200), wherein the capture layer (200) is located on a side of the substrate (100) away from the first surface (101); A backing layer (300) is formed, and the backing layer (300) is located on a side of the capture layer (200) away from the substrate (100).

5. The method for preparing a semiconductor substrate according to claim 4, wherein: Along the thickness direction (X) of the substrate (100), the thickness of the capture layer (200) is 6. The method for preparing a semiconductor substrate according to claim 4, wherein: The step of forming the capture layer (200) comprises: forming a second polysilicon layer (220), wherein the second polysilicon layer (220) is located on the first surface (101); A first polysilicon layer (210) is formed, the base (100) having a second surface (102) that is away from the first surface (101), and the second polysilicon layer (220) is located on the second surface (102), thereby obtaining a first substrate (110); The second polysilicon layer (220) is removed, and the first polysilicon layer (210) is retained; the first polysilicon layer (210) serves as the capture layer (200).

7. The method for preparing a semiconductor substrate according to claim 6, wherein: The first polysilicon layer (210) is prepared by the following method: using silicon-containing gas to deposit polysilicon on the surface of the substrate (100).

8. The method for preparing a semiconductor substrate according to claim 7, wherein: The consumption of the silicon-containing gas is 9. The method for preparing a semiconductor substrate according to claim 6, wherein: The second polysilicon layer (220) is prepared by the following method: using silicon-containing gas to deposit polysilicon on the surface of the substrate (100).

10. The method for preparing a semiconductor substrate according to claim 9, wherein: The consumption of the silicon-containing gas is 11. The method for preparing a semiconductor substrate according to claim 6, wherein: In the step of forming the first polysilicon layer (210), the substrate (100) is placed in an environment with a temperature range of 600°C to 660°C.

12. The method for preparing a semiconductor substrate according to claim 6, wherein: In the step of forming the second polysilicon layer (220), the substrate (100) is placed in an environment with a temperature range of 600° C. to 660° C.

13. The method for preparing a semiconductor substrate according to claim 6, wherein: The second polysilicon layer (220) is removed by a chemical mechanical polishing method.

14. The method for preparing a semiconductor substrate according to claim 13, wherein: The chemical mechanical polishing method comprises: grinding the second polysilicon layer (220) to remove the second polysilicon layer (220).

15. The method for preparing a semiconductor substrate according to claim 14, wherein: The first substrate (110) is adsorbed on a polishing head (3), the polishing head (3) having a chamber (300), along a thickness direction (X) of the semiconductor substrate (1), the chamber (300) having a first thickness H1 μm, the first substrate (110) having a second thickness H2 μm, satisfying: 0<H1-H2≤20 μm.

16. An image sensor, wherein: The image sensor comprises: a semiconductor substrate (1) according to any one of claims 1 to 3; or, the image sensor comprises: a semiconductor substrate (1) prepared by the method for preparing a semiconductor substrate (1) according to any one of claims 4 to 15; The semiconductor substrate (1) serves as a base of the image sensor.

17. The image sensor according to claim 16, wherein: The semiconductor substrate (1) comprises a P-type substrate.

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