Dual-mode single-core oscillator

Abstract

Disclosed is a dual-mode single-core oscillator, comprising a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a first capacitor C1, a second capacitor C2, a first inductor L1 to a fifth inductor L5, a first capacitor C1, and a first varactor Var1 to a fourth varactor Var4. The source of the third MOS transistor M3 is connected to the drain of the first MOS transistor, the drain of the third MOS transistor M3 is connected to the drain of the second MOS transistor, and the gate of the third MOS transistor M3 is connected to a third bias voltage input port. According to the oscillator of the present invention, switching between a differential mode and a common mode is achieved in only one oscillator core by means of a switch, and frequency tuning in differential mode and common mode states can be achieved.

Description

A dual-mode single-core oscillator Technical Field

[0001] The present invention relates to an oscillator, and in particular to a dual-mode single-core oscillator. Background Art

[0002] A traditional differential oscillator, as shown in Figure 1, can achieve differential signals in a single frequency band. By varying the capacitance of the varactor pair between the drains of the two MOS transistors, the frequency can be continuously adjusted. However, when operating in common mode, the phases at both ends of the varactor pair are aligned, and the varactors are short-circuited. At this point, the varactor capacitance has no effect on the common-mode frequency, making common-mode frequency tuning impossible. This makes it unsuitable for multi-mode operation.

[0003] Existing multi-mode oscillators typically use coupling between dual-core oscillators to achieve differential-mode and common-mode switching. However, because existing multi-mode oscillators require multiple oscillator cores, this not only increases the oscillator's power consumption and design complexity, but also increases the oscillator's area. Summary of the Invention

[0004] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a dual-mode single-core oscillator. By switching, the switching between differential mode and common mode is realized only in one oscillator core, and the frequency tuning in differential mode and common mode states can be achieved.

[0005] The objective of the present invention is achieved through the following technical solutions: a dual-mode single-core oscillator, comprising a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a first capacitor C1, a second capacitor C2, a first inductor L1 to a fifth inductor L5, the first capacitor C1, and first to fourth varactors Var1 to Var4;

[0006] The drain of the first MOS transistor M1 is connected to the first end of the second inductor L2, the drain of the second MOS transistor M2 is connected to the first end of the third inductor L3, the second end of the second inductor L2 is connected to the second end of the third inductor L3, the first end of the first inductor L1 is connected between the second inductor L2 and the third inductor L3, and the second end of the first inductor L1 is connected to the power supply; the source of the first MOS transistor M1 and the source of the second MOS transistor M2 are connected, and the common point of the connections is grounded; the gate of the first MOS transistor M1 is connected to the gate of the second MOS transistor M2 via the first capacitor C1 and the second capacitor C2 in sequence;

[0007] A first end of the fourth inductor L4 is connected to the gate of the first MOS transistor M1, and a second end of the fourth inductor L4 is connected to the drain of the second MOS transistor M2; a first end of the fifth inductor L5 is connected to the gate of the second MOS transistor M2, and a second end of the fifth inductor L5 is connected to the drain of the first MOS transistor M1;

[0008] The first end of the first varactor Var1 is connected to the first end of the second varactor Var2, the second end of the first varactor Var1 is connected to the drain of the first MOS transistor M1, and the second end of the second varactor Var2 is connected to the gate of the second MOS transistor M2; the first end of the third varactor Var3 is connected to the first end of the fourth varactor Var4, the second end of the third varactor Var3 is connected to the drain of the second MOS transistor M2, and the second end of the fourth varactor Var4 is connected to the gate of the first MOS transistor M1; a first bias voltage input port is connected between the first varactor Var1 and the second varactor Var2, and a second bias voltage input port is connected between the third varactor Var3 and the fourth varactor Var4;

[0009] The source of the third MOS transistor M3 is connected to the first end of the second inductor L2, the drain of the third MOS transistor M3 is connected to the first end of the third inductor L3, and the gate of the third MOS transistor M3 is connected to the third bias voltage input port.

[0010] Furthermore, the first MOS transistor M1 and the second MOS transistor M2 are both PMOS transistors, and the third MOS transistor M3 is an NMOS transistor; the bias voltages input to the first bias voltage input port and the second bias voltage input port are the same.

[0011] The beneficial effects of the present invention are as follows: the present invention uses the third MOS tube as a switch to switch, and can achieve switching between differential mode and common mode in only one oscillator core, and can achieve frequency tuning in differential mode and common mode states. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG1 is a schematic diagram showing the principle of a traditional differential oscillator;

[0013] FIG2 is a schematic diagram showing the principle of the present invention;

[0014] FIG3 is an equivalent circuit diagram when the third MOS transistor M3 is disconnected;

[0015] FIG4 is an equivalent circuit diagram of the third MOS transistor M3 when it is closed;

[0016] FIG5 is a circuit diagram of a dual-core oscillator. Implementation Method

[0017] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings, but the protection scope of the present invention is not limited to the following.

[0018] As shown in FIG2 , a dual-mode single-core oscillator includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a first capacitor C1, a second capacitor C2, a first inductor L1 to a fifth inductor L5, a first capacitor C1, and first to fourth varactors Var1 to Var4;

[0019] The drain of the first MOS transistor M1 is connected to the first end of the second inductor L2, the drain of the second MOS transistor M2 is connected to the first end of the third inductor L3, the second end of the second inductor L2 is connected to the second end of the third inductor L3, the first end of the first inductor L1 is connected between the second inductor L2 and the third inductor L3, and the second end of the first inductor L1 is connected to the power supply; the source of the first MOS transistor M1 and the source of the second MOS transistor M2 are connected, and the common point of the connections is grounded; the gate of the first MOS transistor M1 is connected to the gate of the second MOS transistor M2 via the first capacitor C1 and the second capacitor C2 in sequence;

[0020] A first end of the fourth inductor L4 is connected to the gate of the first MOS transistor M1, and a second end of the fourth inductor L4 is connected to the drain of the second MOS transistor M2; a first end of the fifth inductor L5 is connected to the gate of the second MOS transistor M2, and a second end of the fifth inductor L5 is connected to the drain of the first MOS transistor M1;

[0021] The first end of the first varactor Var1 is connected to the first end of the second varactor Var2, the second end of the first varactor Var1 is connected to the drain of the first MOS transistor M1, and the second end of the second varactor Var2 is connected to the gate of the second MOS transistor M2; the first end of the third varactor Var3 is connected to the first end of the fourth varactor Var4, the second end of the third varactor Var3 is connected to the drain of the second MOS transistor M2, and the second end of the fourth varactor Var4 is connected to the gate of the first MOS transistor M1; a first bias voltage input port is connected between the first varactor Var1 and the second varactor Var2, and a second bias voltage input port is connected between the third varactor Var3 and the fourth varactor Var4;

[0022] The source of the third MOS transistor M3 is connected to the first end of the second inductor L2, the drain of the third MOS transistor M3 is connected to the first end of the third inductor L3, and the gate of the third MOS transistor M3 is connected to the third bias voltage input port.

[0023] In this application, a third MOS transistor M3 is connected between the drains of the first MOS transistor M1 and the second MOS transistor. The third MOS transistor M3 acts as a switch. By changing the bias voltage of the MOS transistor input to the gate of the third MOS transistor, the on / off state of the third MOS transistor can be adjusted to achieve mode switching of the oscillator:

[0024] When the third MOS transistor M3 (considered as a switch) is disconnected, the equivalent circuit diagram is shown in Figure 3. At this time, the drain phases of the first MOS transistor M1 and the second MOS transistor M2 are in opposite phases, so the oscillator operates in differential mode. At this time, the operating frequency of the oscillator depends on the inductance values ​​of the inductors L2 to L5 and the capacitance values ​​of the varactors Var1 to Var4.

[0025] When the third MOS transistor M3 (considered as a switch) is closed, the equivalent circuit is shown in Figure 4. The drains of the first MOS transistor M1 and the second MOS transistor M2 are short-circuited and their phases are aligned, so the oscillator operates in a high-frequency common-mode mode. At this time, the operating frequency of the oscillator depends on the inductance values ​​of inductors L4 and L5 and the capacitance values ​​of varactors Var1 to Var4.

[0026] The bias voltage VCON1 input to the first bias voltage input port and the bias voltage VCON2 output from the second bias voltage input port are the same, that is, the two pairs of varactors (Var1 and Var2 are the first pair of varactors, and Var3 and Var4 are the second pair of varactors) have the same bias voltage;

[0027] This application can adjust the frequency of its operation in differential mode and common mode as follows:

[0028] (1) For the desired differential mode frequency f dif Since the frequency is determined by the product of the inductance of inductors L2 to L5 and the capacitance of varactors Var1 to Var4, the tuning range is determined by the ratio of the inductance of inductors L2 to L5 to the capacitance of varactors Var1 to Var4. Therefore, once the required frequency and tuning range are determined, the inductance of inductors L2 to L5 and the capacitance of varactors Var1 to Var4 can be scanned to make the oscillator operate at the required frequency f in common mode. dif and meet the required tuning range;

[0029] (2) For the desired differential mode frequency f com , based on (1), the inductance value of inductor L1 is scanned so that its operating frequency in common mode is f com And because the inductor L1 does not affect the differential mode frequency, it will not affect the achieved differential mode frequency;

[0030] Since the two pairs of capacitors in the present application are respectively connected in parallel with the inductors L4 and L5 (the varactor pair Var1 and Var2 are connected in parallel with the inductor L5. The varactor pair Var3 and Var4 are connected in parallel with the inductor L4), the varactor pairs will not be short-circuited regardless of the differential mode or the common mode. Therefore, the solution of the present application can achieve frequency tuning in both differential mode and common mode.

[0031] Figure 5 shows a dual-core oscillator circuit design. The two circuits within the red boxes can each function as an independent oscillator. This design couples the two oscillators (within the boxes) with a coupling structure (outside the boxes), hence the name "dual-core oscillator." A "core" refers to an independent oscillator unit.

[0032] In other multi-mode oscillators, multiple modes are often achieved by coupling multiple oscillators. This application only uses an independent oscillator unit to achieve two modes. Therefore, in order to distinguish it from other designs that use multiple oscillators to couple to achieve two modes, this design is called a single-core dual-mode oscillator. It can be seen that this application can significantly reduce the complexity of the design, reduce the power consumption of the oscillator, and reduce the area of ​​the oscillator.

[0033] In the embodiment of the present application, when the present application operates in differential mode, its frequency range is 16.95–20.35 GHz, the tuning range is 18.4%, when operating at 20.29 GHz, the power consumption is 4.7 mW, the phase noise at 10 MHz is -133.35 dBc / Hz, and the corresponding FoM is 192.7 dBc / Hz. When operating in common mode, its frequency range is 31.49–40.08 GHz, the tuning range is 24%, when operating at 39.76 GHz, the power consumption is 5.6 mW, the phase noise at 10 MHz is -126.49 dBc / Hz, and the corresponding FoM is 191 dBc / Hz. Table 1 summarizes the performance parameters of recent dual-band oscillators. This comparison demonstrates that the harmonic oscillator design's FoM performance leads the field among harmonic oscillators in the millimeter-wave band. It also achieves a single-core, dual-mode design, reducing chip design complexity while achieving excellent oscillator overall performance.

[0034] Table 1 Design Dual-Band Oscillator Performance Comparison

[0035]

[0036] The foregoing description shows and describes a preferred embodiment of the present invention. However, as previously stated, it should be understood that the present invention is not limited to the form disclosed herein and should not be construed as excluding other embodiments. Instead, the present invention is applicable to various other combinations, modifications, and environments and is capable of modification within the scope of the inventive concept described herein, through the teachings above, or through techniques or knowledge in the relevant art. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention are intended to be within the scope of the appended claims.

Claims

1. A dual-mode single-core oscillator, characterized in that: It includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a first capacitor C1, a second capacitor C2, a first inductor L1 to a fifth inductor L5, a first capacitor C1 and a first varactor Var1 to a fourth varactor Var4; The drain of the first MOS tube M1 is connected to the first end of the second inductor L2, the drain of the second MOS tube M2 is connected to the first end of the third inductor L3, the second end of the second inductor L2 is connected to the second end of the third inductor L3, the first end of the first inductor L1 is connected between the second inductor L2 and the third inductor L3, and the second end of the first inductor L1 is connected to the power supply; the source of the first MOS tube M1 is connected to the source of the second MOS tube M2, and the common point of the connection is grounded; the gate of the first MOS tube M1 is connected to the gate of the second MOS tube M2 through the first capacitor C1 and the second capacitor C2 in sequence; A first end of the fourth inductor L4 is connected to the gate of the first MOS tube M1, and a second end of the fourth inductor L4 is connected to the drain of the second MOS tube M2; a first end of the fifth inductor L5 is connected to the gate of the second MOS tube M2, and a second end of the fifth inductor L5 is connected to the drain of the first MOS tube M1; The first end of the first varactor Var1 is connected to the first end of the second varactor Var2, the second end of the first varactor Var1 is connected to the drain of the first MOS transistor M1, and the second end of the second varactor Var2 is connected to the gate of the second MOS transistor M2; the first end of the third varactor Var3 is connected to the first end of the fourth varactor Var4, the second end of the third varactor Var3 is connected to the drain of the second MOS transistor M2, and the second end of the fourth varactor Var4 is connected to the gate of the first MOS transistor M1; a first bias voltage input port is connected between the first varactor Var1 and the second varactor Var2, and a second bias voltage input port is connected between the third varactor Var3 and the fourth varactor Var4; The source of the third MOS tube M3 is connected to the drain of the first MOS tube, the drain of the third MOS tube M3 is connected to the drain of the second MOS tube, and the gate of the third MOS tube M3 is connected to a third bias voltage input port.

2. The dual-mode single-core oscillator according to claim 1, characterized in that: The first MOS transistor M1 and the second MOS transistor M2 are both PMOS transistors.

3. The dual-mode single-core oscillator according to claim 1, characterized in that: The third MOS tube M3 is an NMOS tube.

4. The dual-mode single-core oscillator according to claim 1, characterized in that: The bias voltages inputted to the first bias voltage input port and the second bias voltage input port are the same.

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