Power module and manufacturing method therefor, and power device

Abstract

The present application provides a power module and a manufacturing method therefor, and a power device. The power module comprises an integrated heat dissipation metal substrate, a chip, and a packaging member; the integrated heat dissipation metal substrate comprises a copper layer, a heat-conducting medium layer and a heat radiator; the copper layer, the heat-conducting medium layer and the heat radiator are stacked; the heat-conducting medium layer is connected between the copper layer and the heat radiator; the surface of the heat-conducting medium layer close to the copper layer is parallel to the surface of the heat-conducting medium layer close to the heat radiator; the chip is fixed on the side of the copper layer away from the heat radiator; and the packaging member is used for packaging the chip. In embodiments of the present application, by means of the integrated heat dissipation metal substrate, heat of the chip can be directly delivered from the chip to the integrated heat dissipation metal substrate, thereby reducing the thermal resistance on the heat dissipation path of the chip. In addition, according to the embodiments of the present application, the integrated heat dissipation metal substrate directly provide components and integrates the functions such as circuit connection, heat dissipation, and insulation, thereby omitting the assembly process of connection between a power device and a heat radiator.

Description

A power module and its manufacturing method, and power equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on August 31, 2023, with application number 202311128988.5 and application name “A power module, its manufacturing method, and power equipment”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of chip processing, and more specifically, to a power module and a manufacturing method thereof, and a power device. Background Art

[0003] As electronic products develop towards greater density, miniaturization, thinness, and high power, the total density and heat generation per unit volume have increased significantly. Consequently, power devices have increasingly stringent requirements for heat dissipation in thermal links. This requires continuous improvement in the thermal conductivity of materials, while also reducing the thermal resistance of the link by reducing the contact interface. Currently, power devices and heat sinks are primarily connected via thermally conductive media (such as thermal grease and gel). This increases the heat dissipation interface while reducing heat transfer efficiency. Furthermore, screws are required to secure the power device and heat sink, making the assembly process complex and preventing a minimalist architecture.

[0004] Summary of the Invention

[0005] The present application provides a power module and a manufacturing method thereof, and a power device, which can simplify the manufacturing process of the power module while improving the heat dissipation efficiency of the chip.

[0006] In a first aspect, a power module is provided, which includes an integrated heat-dissipating metal substrate, one or more chips and a package, wherein the integrated heat-dissipating metal substrate includes one or more copper layers, a thermal conductive medium layer and a heat sink, the one or more copper layers, the thermal conductive medium layer and the heat sink are stacked, the thermal conductive medium layer is connected between the one or more copper layers and the heat sink, and a side of the thermal conductive medium layer close to the one or more copper layers is parallel to a side of the thermal conductive medium layer close to the heat sink; each of the chips is connected to a side of the copper layer away from the heat sink, and the package is used to encapsulate the one or more chips.

[0007] In the embodiment of the present application, by using an integrated heat dissipation metal substrate, the heat of the chip can be directly transferred from the chip to the integrated heat dissipation metal substrate, thereby reducing the thermal resistance on the chip heat dissipation path and improving the heat dissipation efficiency of the chip. In addition, the side of the heat-conducting medium layer close to the copper layer is parallel to the side of the heat-conducting medium layer close to the radiator, and the thickness of the heat-conducting medium layer is uniform and the surface is flat, so that the heat conduction is more uniform and has a better heat conduction effect. In addition, the present application directly uses the integrated heat dissipation metal substrate to directly source materials, integrates circuit connection, heat dissipation, insulation and other functions, saves the assembly process of connecting the power device and the radiator, reduces the connection interface, and solves the heat dissipation problem caused by interface defects. At the same time, because the materials are integrated into one, the management costs of power devices, radiators, heat-conducting insulating media, and tooling and curing equipment required in the assembly process are reduced.

[0008] It should be noted that when using packaging parts to package chips, the packaging methods may include plastic packaging, glue potting, glue dispensing, etc., to form a closed space outside the chip to prevent the chip from being exposed, thereby protecting the chip and avoiding accidental damage to the chip during operation.

[0009] In a possible implementation, the heat-conducting medium layer has a uniform thickness and has no intermediate pores in a thickness direction, and the thickness direction is perpendicular to a contact surface between the heat-conducting medium layer and the heat sink.

[0010] In this implementation, the thickness of the thermal conductive medium layer is uniform and there are no intermediate pores in the thickness direction. When the heat of the chip is directly transferred to the radiator through the thermal conductive medium layer, the heat conduction on the heat dissipation path is more uniform, and the thermal conduction effect is further improved, thereby further improving the heat dissipation effect of the chip.

[0011] In a possible implementation, the heat-conducting medium layer includes a side wall, and the side wall is perpendicular to a contact surface between the heat-conducting medium layer and the heat sink.

[0012] It should be understood that in the embodiment of the present application, the thermal conductive medium layer can be a relatively regular cube, rectangular parallelepiped or other shape, and the side wall of the thermal conductive medium layer can be perpendicular to the contact surface between the thermal conductive medium layer and the heat sink, thereby facilitating the processing and production of the thermal conductive medium layer.

[0013] In a possible implementation, a projection of the heat conducting medium layer on a first plane completely overlaps with a projection of the heat sink on the first plane, and the first plane is a contact surface between the heat conducting medium layer and the heat sink.

[0014] In this implementation, the projection of the thermal conductive medium layer on the first plane completely overlaps with the projection of the heat sink on the first plane, that is, the edge of the thermal conductive medium layer is flush with the edge of the heat sink, thereby facilitating processing.

[0015] In a possible implementation, the thermal conductive medium layer may be made of a polymer composite heat dissipation material, thereby accelerating the heat transfer efficiency of the chip and further improving the heat dissipation efficiency of the chip.

[0016] For example, the thermal conductive medium layer may be an epoxy resin layer, a polyimide layer, etc.; the heat sink may be made of copper or aluminum; and the package may be a plastic sealant.

[0017] In one possible implementation, the one or more copper layers include a first pad and a second pad, the one or more chips are soldered to the first pad, and the one or more chips are interconnected with the second pad via wire bonding. The one or more chips may not be soldered to the second pad, and the second pad may be connected to a circuit board or other device via a pin.

[0018] For example, conductive lines and pads may be formed on the copper layer by combining image transfer with chemical etching.

[0019] In this implementation, wire bonding is performed between the chip and the pads to which the chip is not bonded, thereby achieving electrical connection between the chip and the copper layer. This connection can then be made to a circuit board or other device via pins for signal transmission. It should be understood that wire bonding can also be performed between chips to achieve electrical signal transmission between chips.

[0020] In one possible implementation, the package is used to independently package each of the chips and the copper layer connected thereto. Exemplarily, the package includes a first package, the one or more chips include a first chip, and the first package is used to independently package the first chip and the copper layer connected thereto. That is, the package may include multiple packages, and a single package can independently package a single chip and the copper layer connected thereto. It should be understood that the use of independent packaging can reduce the use of plastic packaging materials while protecting the chips, thereby saving costs.

[0021] In one example, the one or more copper layers include a first sub-copper layer, and multiple chips can be soldered on the first sub-copper layer. In this case, the first sub-copper layer and the multiple chips soldered on the first sub-copper layer can be integrally packaged.

[0022] In one example, a package may be used to integrally package multiple chips with the same or similar functions and a copper layer connected to the multiple chips, so that the chips with the same or similar functions are located in the same package, facilitating subsequent processing.

[0023] It should be understood that in some embodiments, a package can be used to independently package a single chip and a pad for soldering the single chip, and a package can be used to independently package a copper layer provided with a wire circuit. In other words, the copper layer can include a first sub-copper layer and a second sub-copper layer, the first sub-copper layer being used to accommodate the chip, and the second sub-copper layer being used for wire connections; the package is used to independently package a single chip and the first sub-copper layer corresponding to the single chip, and to independently package the second sub-copper layer.

[0024] In another possible implementation, the package is used to integrally package the one or more chips and the one or more copper layers, i.e., the package is used to encapsulate the entire copper layer and the at least one chip disposed on the copper layer. It should be understood that in this implementation, the package can protect the circuits on the copper layer and the chips soldered to the copper layer, thereby making the overall structure more stable.

[0025] In another possible implementation, a packaging component is used to integrally encapsulate the one or more chips, the one or more copper layers, and the thermally conductive medium layer. Specifically, the packaging component integrally encapsulates the chips, copper layers, thermally conductive medium layers, and the surface of the heat sink, thereby making the entire power module structure more stable. However, the cost of the plastic packaging component also increases accordingly.

[0026] In one possible implementation, the one or more copper layers include pads, and the power module further includes pins extending outward through the package, one end of the pin being electrically connected to the pad, and the other end of the pin being electrically connected to the circuit board. It should be understood that the provision of the pins enables electrical connection between the internal chip of the power module and an external device (e.g., a circuit board).

[0027] For example, the pins may pass through the package and be led outward in a gull-wing shape (ie, a small outline package is used), or the pins may pass through the package and be arranged outward in parallel (ie, a dual in-line package).

[0028] In one possible implementation, the heat sink may be a needle-shaped structure, that is, the heat sink may be a pin-fin heat dissipation structure, that is, the heat dissipation teeth of the heat sink may adopt a cylindrical or square columnar structure, thereby obtaining a larger heat dissipation area and improving the heat dissipation efficiency of the chip.

[0029] In another possible implementation, the heat sink may be a fin-like structure, i.e., the heat dissipation tines of the heat sink may be similar to a thin sheet. It should be understood that, compared to a pin-fin heat dissipation structure, a fin-like heat sink has a smaller heat dissipation tines width, a relatively smaller heat dissipation area, and a relatively poorer heat dissipation effect.

[0030] In another possible implementation, the heat sink may be a channel-shaped structure. That is, the heat transferred from the chip to the heat sink can be carried away by the flow of coolant in the channel, thereby achieving a higher heat dissipation effect and further improving the heat dissipation efficiency of the chip.

[0031] In a second aspect, a method for manufacturing a power module is provided, which includes: obtaining an integrated heat dissipation metal substrate, the integrated heat dissipation metal substrate including a first copper layer, a heat conductive medium layer and a first heat sink, the first copper layer, the heat conductive medium layer and the first heat sink are stacked, the heat conductive medium layer is connected between the first copper layer and the first heat sink, and a side of the heat conductive medium layer close to the first copper layer is parallel to a side of the heat conductive medium layer close to the first heat sink; soldering a chip on a side of the first copper layer away from the first heat sink; and packaging the chip using a package.

[0032] The chip may include one or more chips, and the first copper layer may include one or more chips, which is not limited in this application.

[0033] The manufacturing method provided in the embodiment of the present application manufactures and processes the power module by directly obtaining an integrated heat dissipation metal substrate, that is, adopting the process of integrated heat dissipation metal substrate manufacturing - chip welding - plastic sealing, which reduces the assembly steps compared with the existing technology. In addition, the integrated heat dissipation metal substrate is directly used as the material, which integrates the circuit connection, heat dissipation, insulation and other functions, saves the assembly process of connecting the power device and the heat sink in the existing technology, reduces the connection interface, and solves the heat dissipation problem caused by interface defects. At the same time, since the materials are integrated into one, the management cost of the power device, heat sink, thermal conductive insulating medium, and tooling and curing equipment required in the assembly process is reduced.

[0034] It should be noted that, in the embodiment of the present application, the following three methods can be used to obtain an integrated heat dissipation metal substrate.

[0035] In one possible implementation, obtaining an integrated heat dissipation metal substrate includes: obtaining a first metal substrate, the first metal substrate including a second copper layer, the thermal conductive medium layer and a first metal base, the second copper layer, the thermal conductive medium layer and the first metal base are stacked, and the thermal conductive medium layer is connected between the second copper layer and the first metal base; performing circuit pattern production on the second copper layer to form the first copper layer; and performing the first heat sink production on the first metal base.

[0036] In another possible implementation, obtaining the integrated heat dissipation metal substrate includes: obtaining a second copper layer, the thermal conductive medium layer and the first heat sink; pressing the second copper layer, the thermal conductive medium layer and the first heat sink; and producing a circuit pattern on the second copper layer to form the first copper layer.

[0037] In another possible implementation, obtaining an integrated heat dissipation metal substrate includes: obtaining a second metal substrate, the second metal substrate including a second copper layer, the thermal conductive medium layer, and a second metal base, the second copper layer, the thermal conductive medium layer, and the second metal base being stacked, with the thermal conductive medium layer connected between the second copper layer and the second metal base; forming a circuit pattern on the second copper layer to form the first copper layer; and fixedly connecting the second metal base to a second heat sink to form the first heat sink. The second heat sink may be a needle-shaped structure, a fin-shaped structure, or a channel-shaped structure.

[0038] The step of fixedly connecting the second metal base and the second heat sink to form the first heat sink may include: fixedly connecting the second metal base and the second heat sink by laser welding to form the first heat sink.

[0039] All three of the above-mentioned manufacturing methods can produce an integrated heat dissipation metal substrate. It should be understood that in the embodiments of this application, the integrated heat dissipation metal substrate can be directly processed and manufactured, or it can be obtained separately and independently processed to form an integrated heat dissipation metal substrate. By obtaining an integrated heat dissipation metal substrate and processing it to form a power module based on the integrated heat dissipation metal substrate, the process flow is relatively simple, the production efficiency is high, and it is conducive to lean manufacturing.

[0040] In one possible implementation, the packaging of the chip using a package includes: using the package to independently package a single chip and the first copper layer corresponding to the single chip; or, using the package to package multiple chips and the first copper layer as a whole; or, using the package to package the chip, the first copper layer and the thermal conductive medium layer as a whole.

[0041] It should be noted that when using a package to package a chip, the packaging form may include plastic packaging, glue potting, glue dispensing and other packaging forms, forming a closed space outside the chip, thereby protecting the chip and preventing accidental damage to the chip during operation.

[0042] In one possible implementation, wire lines and pads are formed on the first copper layer, and soldering the chip to the side of the first copper layer away from the first heat sink includes: soldering the chip to the pad on the first copper layer; before packaging the chip with a package, the method further includes: interconnecting the chip with the pad to which the chip is not soldered by wires.

[0043] In one possible implementation, a wire circuit and a pad are formed on the first copper layer. Before using the package to package the chip, the method further includes: performing pin soldering, one end of the pin is electrically connected to the pad, and the other end of the pin is used to electrically connect to the circuit board.

[0044] In a third aspect, a power device is provided, which is used for AC / DC conversion, and includes a circuit board and a power module as in the first aspect and any one of the implementations of the first aspect, or, the power device includes a circuit board and a power module made as in the second aspect and any one of the implementations of the second aspect, and the power module is arranged on the circuit board.

[0045] It should be noted that the beneficial effects of the second and third aspects can be referred to the first aspect and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] FIG1 is a schematic structural diagram of a power module according to an embodiment of the present application.

[0047] FIG2 is a schematic structural diagram of another power module according to an embodiment of the present application.

[0048] FIG3 is a schematic structural diagram of another power module according to an embodiment of the present application.

[0049] FIG4 is a schematic structural diagram of another power module according to an embodiment of the present application.

[0050] FIG5 is a schematic structural diagram of a power module provided in an embodiment of the present application.

[0051] FIG6 is a schematic structural diagram of different heat sinks provided in an embodiment of the present application.

[0052] FIG7 is a schematic diagram of the structures of different power modules provided in an embodiment of the present application.

[0053] FIG8 is a schematic diagram of a processing method for a power module provided in an embodiment of the present application.

[0054] FIG9 is a schematic diagram of a method for manufacturing an integrated heat dissipation metal substrate provided in an embodiment of the present application.

[0055] FIG10 is a schematic diagram of another method for manufacturing an integrated heat dissipation metal substrate provided in an embodiment of the present application.

[0056] FIG11 is a schematic diagram of another method for manufacturing an integrated heat dissipation metal substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0057] The technical solution in this application will be described below with reference to the accompanying drawings.

[0058] In order to facilitate understanding of the embodiments of the present application, the following explanations are made before introducing the embodiments of the present application.

[0059] In the embodiments of the present application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, features defined as "first" and "second" can sensibly or implicitly include one or more features. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two, and "at least one" and "one or more" mean one, two or more. The singular expressions "one", "a", "said", "above", "the" and "this" are intended to also include expressions such as "one or more", unless the context clearly indicates otherwise. The size of the sequence numbers of the processes below does not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. For example, in the embodiments of the present application, words such as "110", "120", and "130" are merely identifiers made for the convenience of description and do not limit the order of execution of the steps.

[0060] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in yet other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0061] As electronic products develop towards greater density, miniaturization, thinness, and high power, the total density and heat generation per unit volume have increased significantly. This has led to increasingly stringent heat dissipation requirements for power devices within the thermal link. This requires continuous improvement in the thermal conductivity of materials, while also reducing the thermal resistance of the link by minimizing the contact interface. Currently, power devices and heat sinks are primarily connected via a thermally conductive medium (such as thermal grease or gel), transferring heat to the heat sink for dissipation.

[0062] 1 to 4 are schematic structural diagrams of the power module provided in the embodiments of the present application.

[0063] In some embodiments, if the power device has its own insulation function, the heat sink and the power device can be fixedly connected through a thermal conductive medium (such as thermal grease, thermal conductive gel, etc.), that is, the power device and the heat sink can be assembled together through the thermal conductive medium.

[0064] As shown in FIG1 , the power device 130 may have its own insulation function, and the heat sink 110 and the power device 130 may be fixedly connected via a thermal conductive medium 120 . That is, the power device 130 and the heat sink 110 may be assembled together via the thermal conductive medium 120 .

[0065] The power device 130 may be a direct bonded copper (DBC) module. The DBC module may include a copper layer 131, a ceramic substrate 132 disposed on the copper layer 131, a copper layer 133 disposed on the ceramic substrate 132, a chip 134 disposed on the copper layer 133, and a package 135. Specifically, the copper layer 131, the ceramic substrate 132, the copper layer 133, and the chip 134 are sequentially disposed along the thickness direction of the power device 130 from bottom to top. A corresponding circuit pattern may be formed on the copper layer 133. The chip 134 may be soldered to a surface of the copper layer 133 away from the ceramic substrate 132. The package 135 surrounds the copper layer 131, the ceramic substrate 132, the copper layer 133, and the chip 134 to form a sealed space, thereby preventing the chip 134 from being exposed.

[0066] The copper layer 131 , the ceramic substrate 132 , and the copper layer 133 may constitute a DBC ceramic substrate. It should be understood that the DBC ceramic substrate adopts a DBC manufacturing process, where copper foil is sintered and copper-coated onto the ceramic substrate 132 .

[0067] In this example, the heat dissipation path of the chip 134 may be: chip 134 → copper layer 133 → ceramic substrate 132 → copper layer 131 → thermal conductive medium layer 120 → heat sink 110 , thereby completing the heat dissipation of the chip 134 .

[0068] The manufacturing method for power module 100 may include: first, patterning a DBC ceramic substrate to form specific conductor paths and pads; then soldering a chip 134 to the pads on the DBC ceramic substrate; then, encapsulating the DBC module using a package 135; and finally, assembling the DBC module with a heat sink 110 via a thermally conductive medium 120. In other words, the manufacturing process can be summarized as: DBC ceramic substrate patterning - chip soldering - encapsulation - assembly.

[0069] Similarly, in the structure shown in FIG2 , the DBC module in FIG1 can be replaced with a copper substrate module. That is, in some embodiments, the power device 130 in FIG1 can be replaced with the power device 230 in FIG2 . The power device 230 can have its own insulation function, and the heat sink 210 and the power device 230 can be fixedly connected via a thermal conductive medium 220 . The copper substrate module 230 can include a copper layer 231, an insulating thermal conductive layer 232 disposed on the copper layer 231, a copper layer 233 disposed on the insulating thermal conductive layer 232, a chip 234 disposed on the copper layer 233, and a package 235 surrounding the copper layer 231, the insulating thermal conductive layer 232, the copper layer 233, and the chip 234. The copper layer 231, the insulating thermal conductive layer 232, and the copper layer 233 can constitute a copper substrate.

[0070] In the example of FIG. 2 , the heat dissipation path of the chip 234 may be: chip 234 —copper layer 233 —insulating heat conductive layer 232 —copper layer 231 —thermal conductive medium layer 220 —heat sink 210 , thereby completing the heat dissipation of the chip 234 .

[0071] The manufacturing method for power module 200 may include: first, patterning a copper substrate to form specific conductor paths and pads; then soldering a chip 234 to the pads on the copper substrate; then, using a package 235 to perform plastic encapsulation to obtain a copper substrate module; and finally, assembling the copper substrate module with a heat sink 220 via a thermally conductive medium 220. In other words, the manufacturing process can be summarized as: copper substrate patterning - chip soldering - plastic encapsulation - assembly.

[0072] In other embodiments, if the power device has no insulation function, the heat sink and the power device can be fixedly connected through a thermally conductive insulating medium (such as an insulating film, PI film, etc.), that is, the power device and the heat sink can be assembled together through a thermally conductive insulating medium.

[0073] As shown in FIG3 , the power device 330 has no insulation function, and the power device 330 and the heat sink 310 may be fixedly connected via a thermally conductive insulating medium 320 , wherein the thermally conductive insulating medium 320 may be an insulating film or a PI film.

[0074] The power device 330 may include a copper layer 331, a chip 332 and a package 333. A corresponding circuit pattern may be formed on the copper layer 333. The chip 332 may be soldered on the copper layer 331. The package 333 surrounds the copper layer 331 and the chip 332 to form a sealed space, thereby preventing the chip 332 from being exposed.

[0075] In this example, the heat dissipation path of the chip 332 may be: chip 332 → copper layer 331 → thermally conductive insulating medium 320 → heat sink 310 , thereby completing the heat dissipation of the chip 332 .

[0076] The manufacturing method for power module 300 may include: first, patterning the copper layer 331 to form specific conductor tracks and pads; then soldering the chip 332 to the pads on the copper layer 331; then, using a package 333 to perform plastic encapsulation to obtain the power device 330; and finally, assembling the power device 330 with the heat sink 310 via a thermally conductive insulating medium 320. In other words, the manufacturing process can be summarized as: copper layer patterning - chip soldering - plastic encapsulation - assembly.

[0077] Similar to FIG3 , in FIG4 , the power device 430 has no insulation function, and the power device 430 and the heat sink 410 can be fixedly connected via a thermally conductive insulating medium 420 , wherein the thermally conductive insulating medium 420 can include a thermally conductive layer 421 , a ceramic sheet 422 (approximately 1 mm thick), and a thermally conductive layer 423 . The thermally conductive layer 421 , the ceramic sheet 422 , and the thermally conductive layer 423 are stacked, the ceramic sheet 422 is connected between the thermally conductive layer 421 and the thermally conductive layer 432 , and the thermally conductive layer 421 is fixedly connected to the copper layer 431 . The thermally conductive layer 421 and the thermally conductive layer 423 can be made of thermally conductive silicone.

[0078] In this example, the heat dissipation path of the chip 432 may be: chip 432 → copper layer 431 → thermally conductive insulating medium 420 → heat sink 410 , thereby completing the heat dissipation of the chip 432 .

[0079] The manufacturing method for power module 400 may include: first, patterning the copper layer 431 to form specific conductor tracks and pads; then soldering the chip 432 to the pads on the copper layer 431; then, using a package 433 to perform plastic encapsulation to obtain the power device 430; and finally, assembling the power device 430 with the heat sink 410 via a thermally conductive insulating medium 420. In other words, the manufacturing process can be summarized as: copper layer patterning - chip soldering - plastic encapsulation - assembly.

[0080] It should be noted that the power devices and heat sinks shown in Figures 1 through 4 can originate from different manufacturers and can be assembled in an electronics manufacturing service (EMS) facility. Furthermore, the power devices and heat sinks are bonded together via a thermally conductive insulating layer, creating thermal resistance at the interface. The bonding process is labor-intensive and labor-intensive, and is prone to defects such as loose bonding and bubbles. This complex process leads to low manufacturing efficiency and is not conducive to lean manufacturing.

[0081] Regardless of whether a power device has built-in insulation or not, heat must be transferred from the device to the heat sink through a thermally conductive medium. This increases the contact interface and reduces heat transfer efficiency. Thermal grease / gel, insulating film, and PI film, for example, must be thickened to address issues such as workability and the susceptibility of ceramic sheets to cracking, without sacrificing thermal conductivity. This increases thermal resistance in the heat transfer link. Power device packaging is often limited, requiring screw fastening to secure the device and heat sink. This complicates the assembly process and prevents minimalist architecture.

[0082] Therefore, the embodiments of the present application provide a power module and its manufacturing method, and power equipment to solve the problems of the existing assembly process of the whole machine in which the power device and the heat sink are bonded together through a thermally conductive insulating medium, the increase in the thermal conductive interface cannot meet the heat dissipation requirements, the interface defects lead to the failure of the heat dissipation link, the complex assembly process, the low production efficiency, and the increased management costs due to the large number of material components.

[0083] The following will introduce the structural schematic diagram of the power module provided in the embodiment of the present application in conjunction with Figures 5 to 7, and the manufacturing method of the power module provided in the embodiment of the present application in conjunction with Figures 8 to 11 in detail.

[0084] FIG5 is a schematic structural diagram of a power module provided in an embodiment of the present application.

[0085] As shown in FIG5 , the power module 500 may include an integrated heat dissipation metal substrate 510, a chip 520, and a package 540, wherein the integrated heat dissipation metal substrate 510 includes a copper layer 513, a thermal conductive medium layer 512, and a heat sink 511. The copper layer 513, the thermal conductive medium layer 512, and the heat sink 511 are stacked, and the thermal conductive medium layer 512 is connected between the copper layer 513 and the heat sink 511. The side of the thermal conductive medium layer 512 close to the copper layer 513 is parallel to the side of the thermal conductive medium layer 512 close to the heat sink 511. The chip 520 is fixed on the side of the copper layer 513 away from the heat sink 511, and the package 540 is used to package the chip 520. The chip 520 may include one or more, and the copper layer 513 may include one or more sub-copper layers. The chip may be soldered to some of the one or more sub-copper layers via pads, or may not be soldered to some of the sub-copper layers. This is not limited in this application.

[0086] In the embodiment of the present application, by using an integrated heat dissipation metal substrate, the heat of the chip can be directly transferred from the chip to the integrated heat dissipation metal substrate, thereby reducing the thermal resistance on the chip heat dissipation path and improving the heat dissipation efficiency of the chip. In addition, the side of the heat-conducting medium layer close to the copper layer is parallel to the side of the heat-conducting medium layer close to the radiator, and the thickness of the heat-conducting medium layer is uniform and the surface is flat, so that the heat conduction is more uniform and has a better heat conduction effect. In addition, the present application directly uses the integrated heat dissipation metal substrate to directly source materials, integrates circuit connection, heat dissipation, insulation and other functions, saves the assembly process of connecting the power device and the radiator, reduces the connection interface, and solves the heat dissipation problem caused by interface defects. At the same time, because the materials are integrated into one, the management costs of power devices, radiators, heat-conducting insulating media, and tooling and curing equipment required in the assembly process are reduced.

[0087] It should be noted that when using the package 540 to package the chip 520, the packaging form may include plastic packaging, glue potting, glue dispensing and other packaging forms, forming a closed space outside the chip 520, thereby protecting the chip 520 and preventing the chip 520 from accidental damage during operation.

[0088] In some embodiments, the thermal conductive medium layer 512 has a uniform thickness and has no intermediate pores in the thickness direction, where the thickness direction is perpendicular to the contact surface between the thermal conductive medium layer 512 and the heat sink 511 .

[0089] In this embodiment, the thermal conductive medium layer 512 has a uniform thickness and has no intermediate pores in the thickness direction. When the heat of the chip 520 is directly transferred to the heat sink 511 through the thermal conductive medium layer 512, the heat conduction on the heat dissipation path is more uniform, and the thermal conduction effect is further improved, thereby further improving the heat dissipation effect of the chip 520.

[0090] In some embodiments, the thermal conductive medium layer 512 includes a sidewall, which is perpendicular to the contact surface between the thermal conductive medium layer 512 and the heat sink 511 .

[0091] It should be understood that in the embodiment of the present application, the thermal conductive medium layer 512 can be a relatively regular cube, rectangular parallelepiped, etc., and the side wall of the thermal conductive medium layer 512 can be perpendicular to the contact surface between the thermal conductive medium layer 512 and the heat sink 511, thereby facilitating the processing and production of the thermal conductive medium layer 512.

[0092] In some embodiments, the projection of the thermal conductive medium layer 512 on the first plane completely overlaps with the projection of the heat sink 511 on the first plane, and the first plane is the contact surface between the thermal conductive medium layer 512 and the heat sink 511 .

[0093] In this implementation, the projection of the thermal conductive medium layer 512 on the first plane completely overlaps with the projection of the heat sink 511 on the first plane, that is, the edge of the thermal conductive medium layer 512 is flush with the edge of the heat sink 511, which is easier to process.

[0094] In some embodiments, the thermal conductive medium layer 512 may be made of a polymer composite heat dissipation material, for example, an epoxy resin layer, a polyimide layer, or the like.

[0095] In some embodiments, the structure of the heat sink 511 can be as shown in Figure 5. The heat sink 511 can be processed to form a pin-fin heat dissipation structure, that is, the heat dissipation teeth of the heat sink 511 can adopt a cylindrical or square columnar structure, so as to obtain a larger heat dissipation area and improve the heat dissipation efficiency of the chip.

[0096] In other embodiments, the structure of the radiator 511 can be as shown in (a) in Figure 6. The radiator 511 can be processed to form a fin heat dissipation structure, that is, the heat dissipation tooth structure of the radiator 511 is similar to a thin sheet. Compared with the pin-fin heat dissipation structure, the heat dissipation teeth of the fin structure heat sink are smaller in width, the heat dissipation area is relatively small, and the heat dissipation effect is relatively poor.

[0097] In some other embodiments, the structure of the radiator 511 may be as shown in (b) of FIG6 , and the radiator 511 may adopt a heat dissipation structure in the form of a flow channel. For example, a cooling liquid inlet may be provided on the side of the radiator 511 close to the chip 520, and a cooling liquid outlet may be provided on the side of the radiator 511 away from the chip 520. A plurality of pipe channels may be provided in the middle of the radiator 511. The cooling liquid may enter the radiator 511 from the inlet, exit the radiator 511 from the outlet, and dissipate heat outside the radiator 511 before entering the radiator 511 from the inlet, thereby realizing the circulation of the cooling liquid and taking away the heat transferred from the chip 520 to the radiator 511. In other words, the heat transferred from the chip 520 to the radiator 511 can be taken away by the flow of the cooling liquid in the flow channel, thereby achieving a higher heat dissipation effect and further improving the heat dissipation efficiency of the chip 520.

[0098] In some embodiments, the package 540 is used to independently package each chip and the copper layer connected to it. For example, the package 540 may include a first package, and the one or more chips may include a first chip. The first package is used to independently package the first chip and the copper layer connected to the first chip. That is, the package 540 can be used to independently package a single chip and the copper layer connected to the single chip.

[0099] As shown in (a) of FIG7 , the chip 520 may include a first chip 521 and a second chip 522, and the copper layer 513 may include a first sub-copper layer 5131, a second sub-copper layer 5132, and a third sub-copper layer 5133. The first chip 521 is soldered to the first sub-copper layer 5131, the second chip 522 is soldered to the second sub-copper layer 5132, and no chip is soldered to the third sub-copper layer 5133. When packaging the first chip 521 and the second sub-chip 522, a package 540 may be used to independently package the individual chips and the copper layers connected to the individual chips. In other words, the package 540 may include a first package 541 and a second package 542. The first chip 521 and the first sub-copper layer 5131 connected to the first chip 521 may be packaged using the first package 541, and the second chip 522 and the second sub-copper layer 5132 connected to the second chip 522 may be packaged using the second package 542. It should be understood that the use of independent packaging can reduce the use of plastic packaging materials while protecting the chip, thereby saving costs.

[0100] In one example, the copper layer 513 may include a first sub-copper layer, on which a plurality of chips may be soldered. In this case, the first sub-copper layer and the plurality of chips soldered on the first sub-copper layer may be integrally packaged.

[0101] In one example, a package 540 may be used to integrally package multiple chips with the same or similar functions and a copper layer connected to the multiple chips, so that the chips with the same or similar functions are located in the same package, facilitating subsequent processing.

[0102] It should be understood that in some embodiments, the package 540 can also be used to independently package a single chip and the pads for soldering the single chip, and to independently package the copper layer provided with wire lines. In other words, the copper layer 513 can include a first sub-copper layer and a second sub-copper layer, the first sub-copper layer being used to accommodate the chip 520, and the second sub-copper layer being used for wire connections; the package 540 is used to independently package the single chip and the first sub-copper layer corresponding to the single chip, and to independently package the second sub-copper layer.

[0103] In other embodiments, the package 540 may be used to integrally package one or more chips and one or more copper layers.

[0104] As shown in FIG7( b ), chip 520 may include a first chip 521 and a second chip 522, and copper layer 513 may include a first sub-copper layer 5131, a second sub-copper layer 5132, and a third sub-copper layer 5133. The first chip 521 is soldered to the first sub-copper layer 5131, the second chip 522 is soldered to the second sub-copper layer 5132, and no chip is soldered to the third sub-copper layer 5133. When packaging the first chip 521 and the second chip 522, the first chip 521 and the second chip 522 may be packaged simultaneously, that is, a single package 540 is used to package the first chip 521, the second chip 522, the first sub-copper layer 5131 connected to the first chip 521, and the second sub-copper layer 5132 connected to the second chip 522. It should be understood that in this example, the package 540 can protect the chip 520 soldered to the copper layer 513 and the wires on the copper layer 513, thereby making the overall structure more stable.

[0105] In yet other embodiments, the package 540 may be used to integrally package one or more chips, one or more copper layers, and the thermally conductive medium layer 512 .

[0106] As shown in FIG7( c ), chip 520 may include a first chip 521 and a second chip 522. Copper layer 513 may include a first sub-copper layer 5131, a second sub-copper layer 5132, and a third sub-copper layer 5133. First chip 521 is soldered to first sub-copper layer 5131, second chip 522 is soldered to second sub-copper layer 5132, and no chip is soldered to third sub-copper layer 5133. When packaging first chip 521 and second chip 522, an integral package may be used, i.e., packaging element 540 may be used to integrally package first chip 521, second chip 522, copper layer 513, and thermal conductive medium layer 512. This makes the structure of the entire power module more stable, but the cost of the plastic encapsulation compound may also increase accordingly.

[0107] In some embodiments, pads are formed on the copper layer 513, and the pads include a first pad and a second pad. The one or more chips are soldered to the first pad, and the one or more chips are interconnected with the second pad via wire bonding. The one or more chips may not be soldered to the second pad, and the second pad may be connected to a circuit board or other device via a pin. In other words, wire lines and pads are formed on the copper layer 513, and the chip 520 may be soldered to the pad, and the chip 520 may be interconnected with the pad to which the chip is not soldered via wire bonding.

[0108] It should be understood that by interconnecting the chip 520 with the pads of the unsoldered chip through wire bonding, the chip 520 can be electrically connected to the copper layer 513, and then electrically connected to the circuit board or other devices through pins and perform signal transmission.

[0109] It should also be understood that in order to achieve electrical signal transmission between chips, wire bonding interconnection can also be performed between chips.

[0110] In some embodiments, a conductive line and pads are formed on the copper layer 513. The power module 500 may further include a pin extending outward through the package 540, one end of the pin being electrically connected to the pad, and the other end of the pin being electrically connected to the circuit board. In one example, as shown in FIG8(a), the pin 550 may extend outward through the package 540 in a gull-wing shape. In another example, as shown in FIG8(b), the pin 560 may extend outwardly through the package 540 in parallel.

[0111] It should be noted that the power module 500 provided in the embodiment of the present application uses an integrated heat-dissipating metal substrate 510, so that the heat of the chip 520 can be directly transferred from the chip 520 to the integrated heat-dissipating metal substrate 510, thereby completing the heat dissipation of the chip 520, and can reduce the thermal resistance on the heat dissipation path of the chip 520, thereby improving the heat dissipation efficiency of the chip 520.

[0112] FIG8 is a schematic diagram of a method for manufacturing a power module provided in an embodiment of the present application.

[0113] 501, obtain an integrated heat dissipation metal substrate 510.

[0114] Among them, the integrated heat dissipation metal substrate 510 may include a heat sink 511, a thermal conductive medium layer 512 and a copper layer 513, wherein a circuit pattern is formed on the upper copper layer 513, that is, a wire circuit and a pad are formed, with a thickness of about 0 to 2 mm; the lower layer is the heat sink 511, which can be used to dissipate heat for the chip; the middle layer is the thermal conductive medium layer 512, which meets the thermal conductivity and insulation properties, realizes the insulation between the upper circuit pattern and the lower heat sink, and forms a heat dissipation link from top to bottom.

[0115] The heat sink 511 can be made of metal (e.g., aluminum, copper, etc.), and the desired tooth pattern can be produced by machining or etching. It should be understood that the heat sink 511 can have a variety of structures, such as needles, fins, and flow channels. The specific structure of the heat sink 511 can be seen in Figure 6.

[0116] The copper layer 513 , the thermal conductive medium layer 512 and the radiator 511 are stacked, and the thermal conductive medium layer 512 is located between the copper layer 513 and the radiator 511 . The side of the thermal conductive medium layer 512 close to the copper layer 513 is parallel to the side of the thermal conductive medium layer 512 close to the radiator 111 .

[0117] In some embodiments, the thermal conductive medium layer 512 has a uniform thickness and has no intermediate pores in the thickness direction, which is perpendicular to the contact surface between the thermal conductive medium layer 512 and the heat sink 111 .

[0118] In some embodiments, the thermal conductive medium layer 512 includes sidewalls that are perpendicular to the contact surface between the thermal conductive medium layer 512 and the heat sink 511. It should be understood that in the embodiments of the present application, the thermal conductive medium layer 512 can be in a relatively regular shape such as a cube or a cuboid, and the sidewalls of the thermal conductive medium layer 512 can be perpendicular to the contact surface between the thermal conductive medium layer 512 and the heat sink 511, thereby facilitating the processing and manufacture of the thermal conductive medium layer 512.

[0119] In some embodiments, the projection of the thermal conductive medium layer 512 on the first plane completely overlaps with the projection of the heat sink 511 on the first plane. The first plane is the contact surface between the thermal conductive medium layer 512 and the heat sink 511. In this embodiment, the projection of the thermal conductive medium layer 512 on the first plane completely overlaps with the projection of the heat sink 511 on the first plane. In other words, the edge of the thermal conductive medium layer 512 is flush with the edge of the heat sink 511, thereby facilitating processing.

[0120] In some embodiments, the thermal conductive medium layer 512 may be made of a polymer composite heat dissipation material, for example, an epoxy resin layer, a polyimide layer, or the like.

[0121] It should be noted that the manufacturing method of the integrated heat dissipation metal substrate 510 will be described in conjunction with Figures 9 to 11 and will not be repeated here. It should be understood that the integrated heat dissipation metal substrate 510 is manufactured in an integrated manner and can therefore be regarded as an integral structural member.

[0122] 502 , soldering the chip 520 onto the copper layer 513 of the integrated heat dissipation metal substrate 510 .

[0123] Specifically, in this step, the chip 520 can be soldered to the surface of the copper layer 513 away from the heat sink 511. The copper layer 513 can be patterned using a printed circuit board (PCB) factory pattern transfer process. For example, a conductive line and pads can be formed on the copper layer 513 using image transfer combined with chemical etching, and the chip 520 can be soldered to the pads of the copper layer 513.

[0124] In some embodiments, this step may further include: performing wire bonding 530 after the chip 520 is soldered, i.e., bonding the chip 520 to the pads to which the chip is not soldered. In this embodiment, the chip 520 is electrically connected to the copper layer 513 by bonding the pads to which the chip is not soldered.

[0125] It should be understood that in order to realize the transmission of electrical signals between chips, wire bonding interconnection can also be performed between chips.

[0126] Among them, wire bonding can be understood as pressure welding, binding, bonding, and wire bonding. It refers to the use of metal wire (such as gold wire, aluminum wire, etc.) and the use of hot pressing or ultrasonic energy to complete the connection of the internal interconnection wiring of the solid-state circuit in the microelectronic device, that is, the connection between the chip and the circuit or lead frame.

[0127] 503 , the chip 520 is packaged using a package 540 .

[0128] In this step, the chip 520 can be packaged using a package 540, that is, the chip 520 can be packaged using a packaging process (such as plastic packaging or glue potting). It should be understood that when packaging the chip 520, reference can be made to FIG. 7 , that is, the individual chip and the copper layer connected to the individual chip can be packaged; the chip 520 and the copper layer 513 can also be packaged as a whole; the chip 520, the copper layer 513, and the thermal conductive medium layer 512 can also be packaged as a whole, that is, the entire heat dissipation metal substrate can be packaged; the specific selection can be based on product requirements.

[0129] It should be noted that when using the package 540 to package the chip 520, the packaging form may include plastic packaging, glue potting, glue dispensing and other packaging forms, forming a closed space outside the chip 520 to prevent the chip 520 from being exposed, thereby protecting the chip 520 and avoiding accidental damage to the chip 520 during operation.

[0130] It should be noted that when the chip 520 is packaged using a packaging process, various packaging forms may be used, including but not limited to a small out-line package (SOP), a dual in-line package (DIP), and the like.

[0131] Among them, SOP packaging is a component packaging form and one of the commonly used surface mount packages, mainly used in various integrated circuits. Common packaging materials for SOP packaging include plastic, ceramic, glass, and metal, with plastic and ceramic packaging materials being more widely used.

[0132] The DIP package is a type of integrated circuit packaging. The IC is rectangular in shape, with two rows of parallel metal pins, called pin headers, on either side. DIP-packaged components can be soldered into plated through-holes on PCBs or inserted into DIP sockets. Therefore, this package facilitates through-hole soldering on PCBs and offers excellent compatibility with motherboards. However, due to its relatively large package area and thickness, and the pins being easily damaged during insertion and removal, its reliability is relatively poor.

[0133] In some embodiments, before performing this step, the manufacturing method may further include: performing pin soldering, wherein one end of the pin is electrically connected to the pad on the copper layer 513, and the other end of the pin is used to electrically connect to the circuit board. It should be understood that by providing the pins, electrical connection between the internal chip of the power module and an external device (such as a PCB board) can be achieved.

[0134] In one example, as shown in (a) in Figure 8, if an SOP package is used, the pin 550 can be led outward through the package 540 in a seagull wing shape, and one end of the pin 550 can be electrically connected to the pad on the copper layer 513, and the other end of the pin 550 can be electrically connected to the PCB board.

[0135] In another example, as shown in (b) of Figure 8, if a DIP package is used, the pin 560 can be arranged parallel to the outside through the package 540, and one end of the pin 560 can be electrically connected to the pad on the copper layer 513, and the other end of the pin 560 can be electrically connected to the PCB board.

[0136] It should be understood that after steps 501 to 503, when the processing of the entire power module is completed, the power module can be cut to form an independent integrated heat dissipation metal substrate packaging module.

[0137] It should be noted that the manufacturing method of the power module 500 can also be simply summarized as: integrated heat dissipation metal substrate manufacturing - chip welding - plastic packaging, which reduces the assembly steps compared to the processing method in Figures 1 to 4. The embodiment of the present application directly uses the integrated heat dissipation metal substrate as the raw material, integrating circuit connection, heat dissipation, insulation and other functions, saving the assembly process of connecting the power device and the heat sink, reducing the connection interface, and solving the heat dissipation problem caused by interface defects. At the same time, because the raw materials are integrated into one, the management cost of the power device, heat sink, thermal conductive insulating medium, and the tooling and curing equipment required in the assembly process is reduced.

[0138] 9 to 11 introduce three different methods for manufacturing the integrated heat dissipation metal substrate in the embodiments of the present application.

[0139] FIG9 is a schematic diagram of a method for manufacturing an integrated heat dissipation metal substrate provided in an embodiment of the present application.

[0140] 801, obtain a metal substrate 810.

[0141] It should be understood that the metal substrate 810 is an independent integral structure, and the metal substrate 810 can be composed of a copper layer 820, a thermal conductive medium layer 830 and a metal base 840. The copper layer 820, the thermal conductive medium layer 830 and the metal base 840 are stacked in sequence, and the thermal conductive medium layer 830 is connected between the copper layer 820 and the metal base 840.

[0142] The copper layer 820 has a thickness of approximately 0 to 2 mm, and the copper layer 820 can be etched to form conductive lines and pads. The metal substrate 840 can be made of a metal material (e.g., aluminum, copper, etc.), and its thickness can be customized as needed. The thermal conductive medium layer 830 must meet thermal conductivity and insulation properties to achieve insulation between the upper copper layer 820 and the lower metal substrate 840, and to form a heat dissipation link from top to bottom.

[0143] 802 , patterning is performed on the copper layer 820 of the metal substrate 810 to form conductor lines and pads.

[0144] In this step, conductive lines and pads (i.e., forming copper layer 850) can be formed on the copper layer 820 of the metal substrate 810 by image transfer combined with chemical etching, and the chip 520 can be soldered to the pads.

[0145] 803 , a heat sink 860 is manufactured on the metal base 840 of the metal substrate 810 .

[0146] In this step, heat dissipation teeth may be fabricated on the metal base 840 of the metal substrate 810 by machining or etching to obtain a desired tooth-shaped pattern, thereby forming the heat sink 860 .

[0147] It is understandable that in this step, a heat sink structure such as a needle-shaped, fin-shaped, or flow channel-shaped heat sink can be obtained by machining or etching. The specific structure of the heat sink 860 can be seen in FIG6 .

[0148] It should be noted that, through steps 801 to 803, an integrated heat dissipation metal substrate 870 (including a thermal conductive medium layer 830 and a copper layer 850 and a heat sink 860 connected to both sides of the thermal conductive medium layer 830) is formed. It should be understood that the integrated heat dissipation metal substrate 870 is the aforementioned integrated heat dissipation metal substrate 510.

[0149] FIG10 is a schematic diagram of another method for manufacturing an integrated heat dissipation metal substrate provided in an embodiment of the present application.

[0150] 901 , obtaining a copper layer 910 , a thermal conductive medium layer 920 and a heat sink 930 .

[0151] It should be understood that in this step, the copper layer 910, the thermal conductive medium layer 920 and the radiator metal base 930 can be obtained respectively, wherein the thermal conductive medium layer 920 can be composed of a polymer composite heat dissipation material. Exemplarily, the thermal conductive medium layer 920 can be an epoxy resin layer, a polyimide layer, etc.; the radiator 930 is the above-mentioned radiator 511, and its material can be copper or aluminum.

[0152] It should be noted that the structure of the heat sink metal base 930 is the same as that of the above-mentioned heat sink 511 , that is, the heat sink metal base 930 can be formed during the original processing. The structure of the heat sink metal base 930 can be seen in FIG. 6 .

[0153] 902 , the copper layer 910 , the thermal conductive medium layer 920 and the heat sink 930 are laminated to form a heat sink metal substrate 940 .

[0154] In this step, the copper layer 910 , the thermal conductive medium layer 920 and the heat sink 930 obtained in step 901 may be pressed together to form a heat sink metal substrate 940 .

[0155] It should be understood that the difference between the heat sink metal substrate 940 and the integrated heat sink metal substrate 510 is that the copper layer 910 on the heat sink metal substrate 940 is not processed to form wire lines and pads.

[0156] 903 , a circuit pattern is produced on the copper layer 910 of the heat sink metal substrate 940 to form a conductor circuit and a pad.

[0157] It should be understood that in this step, a circuit pattern can be processed on the copper layer 910 of the heat sink metal substrate 940 through a PCB factory pattern transfer process to form a conductive line and a pad (i.e., copper layer 950). For example, a circuit pattern can be produced on the copper layer 910 using chemical etching to form pads and conductive lines, and the pads can be used to solder chips.

[0158] It should be noted that, through steps 901 to 903, an integrated heat dissipation metal substrate 960 (including a thermal conductive medium layer 920 and a copper layer 950 and a heat sink 930 connected to both sides of the thermal conductive medium layer 920) can be formed. It should be understood that the integrated heat dissipation metal substrate 960 is the integrated heat dissipation metal substrate 510 described above.

[0159] FIG11 is a schematic diagram of another method for manufacturing an integrated heat dissipation metal substrate provided in an embodiment of the present application.

[0160] 1001. Obtain a metal substrate 1010.

[0161] It should be understood that the metal substrate 1010 is an independent integral structure, and the metal substrate 1010 can be composed of a copper layer 1020, a thermal conductive medium layer 1030 and a metal base 1040. The copper layer 1020, the thermal conductive medium layer 1030 and the metal base 1040 are stacked in sequence, and the thermal conductive medium layer 1030 is connected between the copper layer 1020 and the metal base 1040.

[0162] The copper layer 1020 has a thickness of approximately 0 to 2 mm and can be etched to form conductive lines and pads. The metal substrate 1040 can be made of a metal material (e.g., aluminum, copper, etc.), and its thickness can be customized as needed. The thermal conductive medium layer 1030 must meet thermal conductivity and insulation properties to achieve insulation between the upper copper layer 1020 and the lower metal substrate 1040, and to form a heat dissipation link from top to bottom.

[0163] 1002 , a circuit pattern is produced on the copper layer 1020 of the metal substrate 1010 to form a conductor circuit and a pad.

[0164] It should be understood that in this step, a circuit pattern can be processed on the copper layer 1020 of the metal substrate 1010 through a pattern transfer process in a PCB factory to form a conductive line and a pad (i.e., the copper layer 1050). In other words, chemical etching can be used to pattern the copper layer 1020 to form pads and conductive lines, and the pads can be used to solder chips.

[0165] 1003 , fixedly connecting the metal base 1040 and the heat dissipation teeth to form an integrated heat dissipation metal substrate 1090 .

[0166] In this step, the heat dissipation teeth can be fixedly connected to the metal base 1040 by laser welding to form an integrated heat dissipation metal substrate 1090.

[0167] In some embodiments, the structure of the heat dissipation tooth can be as shown in 1060 in Figure 10. The heat dissipation tooth 1060 may include at least one fin. In this step, the heat dissipation tooth 1060 can be integrated with the metal base 1040 by laser welding to form a heat sink 1080, and then an integrated heat dissipation metal substrate 1090 can be formed.

[0168] In some embodiments, the structure of the heat dissipation tooth can be as shown in 1070 in Figure 10. The heat dissipation tooth 1070 may include at least one fin and a connecting portion connected to the at least one fin. In this step, the connecting portion of the heat dissipation tooth 1070 can be fused with the metal base 1040 by laser welding to form a heat sink 1080, and then an integrated heat dissipation metal substrate 1090 can be formed.

[0169] It should be noted that, through steps 1001 to 1003, an integrated heat dissipation metal substrate 1090 (including a thermal conductive medium layer 1030 and a copper layer 1050 and a heat sink 1080 connected to both sides of the thermal conductive medium layer 1030) can be formed. It should be understood that the integrated heat dissipation metal substrate 1090 is the aforementioned integrated heat dissipation metal substrate 510.

[0170] In addition, an embodiment of the present application also provides a power device, which is used for AC / DC conversion. The power device may include a circuit board and a power module as shown in Figure 5, or the power device may include a circuit board and a power module manufactured by the manufacturing method as shown in Figure 8, and the power module is arranged on the circuit board.

[0171] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A power module, characterized in that: include: An integrated heat dissipation metal substrate, one or more chips and a package, wherein: The integrated heat dissipation metal substrate comprises one or more copper layers, a heat conductive medium layer and a heat sink, wherein the one or more copper layers, the heat conductive medium layer and the heat sink are stacked, the heat conductive medium layer is connected between the one or more copper layers and the heat sink, and a side of the heat conductive medium layer close to the one or more copper layers is parallel to a side of the heat conductive medium layer close to the heat sink; Each of the chips is connected to a side of the copper layer away from the heat sink, and the package is used to package the one or more chips.

2. The power module according to claim 1, characterized in that: The thickness of the heat-conducting medium layer is uniform and has no intermediate pores in the thickness direction, and the thickness direction is perpendicular to the contact surface between the heat-conducting medium layer and the heat sink.

3. The power module according to claim 1 or 2, characterized in that: The heat-conducting medium layer comprises a side wall, and the side wall is perpendicular to a contact surface between the heat-conducting medium layer and the heat sink.

4. The power module according to any one of claims 1 to 3, characterized in that: The projection of the heat-conducting medium layer on the first plane completely overlaps with the projection of the heat sink on the first plane, and the first plane is the contact surface between the heat-conducting medium layer and the heat sink.

5. The power module according to any one of claims 1 to 4, characterized in that: The heat-conducting medium layer is made of a polymer composite heat-dissipating material.

6. The power module according to any one of claims 1 to 5, characterized in that: The package is used to independently package each chip and the copper layer connected thereto.

7. The power module according to any one of claims 1 to 5, characterized in that: The package is used to integrally package the one or more chips and the one or more copper layers.

8. The power module according to any one of claims 1 to 5, characterized in that: The package is used to integrally package the one or more chips, the one or more copper layers, and the thermal conductive medium layer.

9. The power module according to any one of claims 1 to 8, characterized in that: The heat sink is a needle-shaped structure, or the heat sink is a fin-shaped structure, or the heat sink is a flow channel-shaped structure.

10. The power module according to any one of claims 1 to 9, characterized in that: The one or more copper layers include a first pad and a second pad, the one or more chips are soldered on the first pad, and the one or more chips are interconnected with the second pad via wire bonding.

11. The power module according to any one of claims 1 to 9, characterized in that: The one or more copper layers include a pad, and the power module also includes a pin that passes through the package and is arranged outward, one end of the pin is electrically connected to the pad, and the other end of the pin is used to be electrically connected to a circuit board.

12. A method for manufacturing a power module, characterized in that: include: Obtain an integrated heat dissipation metal substrate, the integrated heat dissipation metal substrate comprising one or more copper layers, a heat conductive medium layer and a heat sink, the one or more copper layers, the heat conductive medium layer and the heat sink are stacked, the heat conductive medium layer is connected between the one or more copper layers and the heat sink, and a side of the heat conductive medium layer close to the copper layer is parallel to a side of the heat conductive medium layer close to the heat sink; Soldering a chip on a side of the one or more copper layers away from the heat sink; The chip is packaged using a package.

13. A power device, characterized in that: The power device is used for AC / DC conversion, and the power device includes a circuit board and a power module as described in any one of claims 1 to 11, or the power device includes a circuit board and a power module manufactured by the manufacturing method as described in claim 12, and the power module is arranged on the circuit board.

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