Semi-floating gate transistor and manufacturing method therefor, chip, and electronic device

Abstract

A semi-floating gate transistor and a manufacturing method therefor, a chip, and an electronic device, relating to the technical field of semiconductors, and aiming at reducing a leakage current of a device. The manufacturing method for the semi-floating gate transistor comprises: forming a dielectric layer on a substrate, and forming a via hole passing through the dielectric layer, wherein the via hole exposes the substrate; forming in the via hole a plug structure of a single crystal material, wherein the plug structure is electrically connected to the substrate, and forming a floating gate on the dielectric layer, wherein the floating gate is electrically connected to the plug structure; and forming a control gate on the side of the floating gate distant from the substrate, and forming a source and a drain on the substrate. The semi-floating gate transistor can be applied to a memory so as to realize data reading and writing.

Description

Semi-floating gate transistor, manufacturing method thereof, chip, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on August 31, 2023, with application number 202311131415.8 and application name “Semi-floating gate transistor and its preparation method, chip, and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to a semi-floating gate transistor and a preparation method thereof, a chip, and an electronic device. Background Art

[0003] A semi-floating gate transistor (SFGT) is a microelectronic device that can be used in various integrated circuits. For example, a semi-floating gate transistor can be used as a storage unit in a memory, and has the advantage of being erasable and rewritable an unlimited number of times.

[0004] However, there is leakage current in the semi-floating gate transistor, which results in its poor data retention ability as a storage unit. Based on this, how to reduce the leakage current in the semi-floating gate transistor has become an urgent problem to be solved in the field.

[0005] Summary of the Invention

[0006] The present application provides a semi-floating gate transistor and a preparation method thereof, a chip, and an electronic device, aiming to reduce the leakage current of the device.

[0007] To achieve the above objectives, this application adopts the following technical solutions:

[0008] In a first aspect, a method for fabricating a semi-floating gate transistor is provided. The method comprises the following steps: forming a dielectric layer on a substrate, forming a via hole through the dielectric layer, the via hole exposing the substrate; forming a plug structure of a single crystal material within the via hole, the plug structure electrically connected to the substrate; forming a floating gate on the dielectric layer, the floating gate electrically connected to the plug structure; forming a control gate on the side of the floating gate facing away from the substrate; and forming a source and drain on the substrate.

[0009] The fabrication method provided herein first forms a dielectric layer with a via on a substrate, the via exposing the substrate. Then, a plug structure of single-crystal material is formed within the via, and a floating gate is formed on the dielectric layer. The floating gate is electrically connected to the substrate via the plug structure. Finally, a control gate is formed on the side of the floating gate facing away from the substrate, and a source and drain are formed on the substrate to produce a semi-floating-gate transistor.

[0010] The vias in the dielectric layer serve as a "window" for charge transfer between the floating gate and the substrate. By forming a plug structure of single-crystal material within the via, the leakage current of the single crystal is low, as the single crystal is composed of regularly arranged grains with identical crystal plane orientations. The plug structure acts as a low-leakage "plug" that blocks the window. During the data retention phase, the plug structure prevents charge within the floating gate from flowing through the window into the substrate, thereby reducing leakage current in the semi-floating-gate transistor and improving the data retention capability of the memory device equipped with the semi-floating-gate transistor.

[0011] In one possible implementation, the steps of forming the plug structure and the floating gate may include: forming a conductive layer, the conductive layer including a first conductive portion filling the via hole and a second conductive portion located on the dielectric layer, the first conductive portion being in contact with the substrate; and annealing the conductive layer, whereby the first conductive portion forms the plug structure and the second conductive portion forms the floating gate.

[0012] For example, the conductive layer may be made of polycrystalline silicon. At the interface where the first conductive portion of the conductive layer contacts the substrate, the crystal lattice of the first conductive portion terminates at the interface, resulting in dangling bonds on the surface of the first conductive portion. Annealing the conductive layer in a hydrogen atmosphere allows hydrogen ions to penetrate into the first conductive portion of the conductive layer, saturating the dangling bonds. The high temperature promotes the growth of crystal nuclei in the first conductive portion, converting the polycrystalline silicon material into single crystal silicon, resulting in a low-leakage plug structure.

[0013] In a possible implementation, the atmosphere for annealing the conductive layer includes hydrogen and nitrogen.

[0014] In a possible implementation, the temperature range of the annealing treatment on the conductive layer is 400° C. to 450° C.

[0015] In a possible implementation, the duration of the annealing treatment on the conductive layer is 60 minutes to 90 minutes.

[0016] In another possible implementation, the step of forming the plug structure and the floating gate may include: forming the plug structure on the surface of the substrate through the hole using a selective epitaxial process, and forming the floating gate on the dielectric layer, wherein the floating gate is electrically connected to the plug structure.

[0017] For example, if the substrate is made of single crystal silicon, a selective epitaxial process may be used to selectively epitaxially grow single crystal silicon on the surface of the substrate through the hole using the substrate as a seed layer to form a low leakage plug structure at the window.

[0018] In a possible implementation, the temperature range of forming the plug structure by the selective epitaxial process is 400° C. to 1650° C.

[0019] In a possible implementation, the pressure of the reaction chamber of the selective epitaxial process ranges from 40 Torr to 150 Torr.

[0020] In a second aspect, a semi-floating gate transistor is provided. The semi-floating gate transistor includes a substrate, a source electrode, a drain electrode, a dielectric layer, a plug structure of a single crystal material, a floating gate, and a control gate disposed on the substrate. The plug structure extends through the dielectric layer and is electrically connected to a portion of the substrate located between the source electrode and the drain electrode. A floating gate is disposed on the dielectric layer and is electrically connected to the plug structure. The control gate is disposed on a side of the floating gate away from the substrate.

[0021] The semi-floating gate transistor provided in the present application is provided with a plug structure at the window between the floating gate and the substrate. The material of the plug structure includes a single crystal. The single crystal has a small leakage current. During the data retention stage, the charge in the floating gate can be suppressed from flowing into the substrate through the window, thereby reducing the leakage current in the semi-floating gate transistor and improving the data retention capability of the memory equipped with the semi-floating gate transistor.

[0022] In a possible implementation, the material of the plug structure includes at least one of single crystal silicon, single crystal germanium, or single crystal silicon germanium.

[0023] In one possible implementation, the dielectric layer includes a first portion and a second portion, the floating gate includes a first sub-floating gate and a second sub-floating gate connected to each other, the first portion and the first sub-floating gate are located inside the substrate, the second portion and the second sub-floating gate are located above the substrate, a portion of the floating gate is embedded in the substrate, a plug structure passes through the second portion, and the second sub-floating gate is electrically connected to the plug structure.

[0024] In one possible implementation, the floating gate includes a first sub-floating gate and a second sub-floating gate. The dielectric layer, the first sub-floating gate, and the second sub-floating gate are located within the substrate, and the floating gate is completely embedded in the substrate. The plug structure includes a first plug and a second plug. The first plug extends through the dielectric layer, and the first sub-floating gate is electrically connected to the first plug. The second plug extends through the dielectric layer, and the second sub-floating gate is electrically connected to the second plug.

[0025] In one possible implementation, the thickness direction of the dielectric layer is a reference direction, and the size (thickness) of the plug structure along the reference direction is equal to the thickness of the dielectric layer, so that the thickness of the plug structure is consistent with the thickness of the dielectric layer and the thickness is relatively thin. This can avoid the need to reduce the volume of the floating gate due to the excessive thickness of the plug structure, thereby avoiding affecting the performance of the floating gate in storing charge.

[0026] In one possible implementation, the plug structure includes two surfaces opposite to each other along a reference direction, and the dielectric layer includes two surfaces opposite to each other along the reference direction. The two surfaces of the plug structure correspond one-to-one with the two surfaces of the dielectric layer, and the corresponding surfaces are located on the same plane. This ensures that the thickness of the plug structure is consistent with that of the dielectric layer and is relatively thin. This avoids the need to reduce the volume of the floating gate due to an excessive thickness of the plug structure, thereby avoiding an impact on the charge storage performance of the floating gate.

[0027] In a third aspect, a chip is provided, which includes a controller and the above-mentioned half-floating gate transistor, and the half-floating gate transistor is electrically connected to the controller.

[0028] In a fourth aspect, an electronic device is provided. The electronic device includes a circuit board and the above-mentioned chip, and the chip is electrically connected to the circuit board.

[0029] It can be understood that the beneficial effects that can be achieved by the chip and electronic device provided in this application can refer to the beneficial effects of the semi-floating gate transistor mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG1 is a schematic diagram of the structure of the server provided by this application;

[0031] FIG2 is an architectural diagram of the memory provided by this application;

[0032] FIG3 is a structural diagram of a half-floating gate transistor provided by the present application;

[0033] FIG4A is a schematic diagram of a half-floating gate transistor performing a write operation;

[0034] FIG4B is a schematic diagram of an erase operation of a semi-floating gate transistor;

[0035] FIG5 is a structural diagram of another half-floating gate transistor provided by the present application;

[0036] FIG6 is a structural diagram of another half-floating gate transistor provided by the present application;

[0037] 7A and 7B are flowcharts of manufacturing a semi-floating gate transistor provided by the present application;

[0038] 8A to 8K are diagrams showing the steps of fabricating a semi-floating gate transistor according to the present application;

[0039] 9A and 9B are flowcharts of manufacturing a semi-floating gate transistor provided by the present application;

[0040] 10A to 10K are diagrams showing the steps of fabricating a semi-floating gate transistor provided in this application. DETAILED DESCRIPTION

[0041] To facilitate understanding, the technical terms involved in this application are first introduced as follows:

[0042] Crystal: A structure composed of a large number of microscopic material units (atoms, ions, molecules, etc.) arranged in an orderly manner according to certain rules.

[0043] Lattice: The atoms inside the crystal are arranged according to certain geometric rules, and the spatial grid of this atomic arrangement is called the lattice.

[0044] Crystal plane: A plane passing through the centers of atoms in a crystal.

[0045] Nucleus: the growth center of a crystal.

[0046] Grain: Grains are small crystals with irregular shapes that make up polycrystals.

[0047] Grain boundary: The interface between grains with the same structure but different crystal plane orientations.

[0048] The present application provides an electronic device, which may be, for example, a server. The present application does not impose any particular limitation on the specific type of the electronic device.

[0049] FIG1 is a schematic diagram of the structure of the server provided in this application.

[0050] 1 , a server 1 includes a cabinet 11, a circuit board 12 disposed in the cabinet 11, and a chip 13 disposed on the circuit board 12. The chip 13 is electrically connected to the circuit board 12. The circuit board 12 includes but is not limited to a printed circuit board (PCB).

[0051] The chip 13 may include a memory chip, an image sensor chip, or the like. For example, if the chip 13 is a memory chip, the memory may include, for example, dynamic random access memory (DRAM) or static random access memory (SRAM). For example, if the chip 13 is an image sensor chip, the image sensor may be an active image sensor.

[0052] Taking DRAM as an example, FIG2 is an architecture diagram of the memory provided in this application.

[0053] 2 , the memory 2 includes a memory array 21 , a row decoder 22 , a column decoder 23 , a controller 24 , a read / write control circuit 25 , and a sense amplifier 26 .

[0054] The memory array 21 includes a plurality of memory cells 210 arranged in an array, wherein the plurality of memory cells 210 include a plurality of rows arranged along a first direction X and a plurality of columns arranged along a second direction Y. The first direction X and the second direction Y intersect, for example, are perpendicular to each other.

[0055] The controller 24 is electrically connected to the row decoder 22 , the column decoder 23 , the memory array 21 , the read / write control circuit 25 , and the sense amplifier 26 , respectively. The controller 24 is configured to control each circuit.

[0056] The row decoder 22 is electrically connected to the memory array 21 . The row decoder 22 is configured to select the memory cells 210 in the corresponding row according to the row address so as to address the memory cells 210 in the corresponding row.

[0057] The column decoder 23 is electrically connected to the memory array 21. After the memory cells 210 of the corresponding row are selected, the column decoder 23 is configured to address the memory cells 210 of the corresponding column according to the column address, thereby selecting the memory cells 210 that need to be read or written.

[0058] The read / write control circuit 25 is electrically connected to the memory array 21 , and is configured to control the selected memory cell 210 to perform a read operation or a write operation.

[0059] The sense amplifier 26 is electrically connected to the memory array 21 and is configured to read, amplify and output the data information stored in the selected memory cell 210 to implement a data read operation; or, input a data signal to the selected memory cell 210 to implement a data write operation.

[0060] In traditional DRAM, the memory cell 210 is based on a transistor and storage capacitor architecture. As devices become smaller, this architecture faces numerous challenges. For example, transistor drive current decreases, leakage current increases, and the storage capacitor's capacity decreases, leading to decreased data retention and increased power consumption. Furthermore, the device's manufacturing process becomes complex, leading to a sharp increase in cost. Therefore, a new type of memory is urgently needed to replace DRAM.

[0061] Semi-Floating Gate Transistor (SFGT) memory is an alternative to DRAM. The storage array 21 of the semi-floating gate transistor memory can be arranged in a 4F2 formation. The semi-floating gate transistor memory can be compatible with the controller 24 and control instructions of the DRAM. That is, the read and write operations of the semi-floating gate transistor memory can be implemented using the controller 24 and control instructions of the DRAM, so as to avoid as much as possible the impact on the original functions or structures of other DRAM-related hardware circuits when using the semi-floating gate transistor memory to replace DRAM, thereby reducing the cost and complexity of replacing DRAM.

[0062] Unlike DRAM, the memory cells in semi-floating-gate transistor memory include semi-floating-gate transistors and lack storage capacitors. Semi-floating-gate transistor memory offers low operating (read / write) voltage, fast operation, unlimited erasable cycles, small device size, and high storage density. Furthermore, the fabrication process for semi-floating-gate transistors is compatible with the currently mature complementary metal oxide semiconductor (CMOS) process, making the fabrication process simple and cost-effective. However, semi-floating-gate transistors suffer from leakage current, resulting in poor data retention in semi-floating-gate transistor memory. Consequently, reducing leakage current in semi-floating-gate transistors has become a pressing issue in the field.

[0063] In order to solve the above problems, the present application provides a semi-floating gate transistor. FIG3 is a structural diagram of a semi-floating gate transistor provided by the present application.

[0064] 3 , the semi-floating gate transistor 3 includes a substrate 30 , and a source S, a drain D, a floating gate 31 and a control gate 32 arranged on the substrate 30 . The floating gate 31 is located between the source S and the drain D, and the control gate 32 is arranged on a side of the floating gate 31 away from the substrate 30 .

[0065] Exemplarily, the substrate 30 includes a p-well 30a and an n-well 30b disposed on the p-well 30a. The material of the p-well 30a includes a p-type semiconductor material, the material of the n-well 30b includes an n-type semiconductor material, and the source S and the drain D are located on the n-well 30b.

[0066] 3 , the semi-floating gate transistor 3 further includes a first dielectric layer 33 disposed between the floating gate 31 and the substrate 30 . The first dielectric layer 33 has a via H formed therein, which serves as a “window” for charge transfer between the floating gate 31 and the substrate 30 .

[0067] For example, the projection of the via H on the plane XY may be circular or rectangular. When the via H is circular, the diameter of the via H is in the range of 10 nm to 20 nm. When the via H is rectangular, the length of the via H is in the range of 10 nm to 20 nm, and the width is in the range of 10 nm to 20 nm.

[0068] FIG. 4A is a schematic diagram of a semi-floating gate transistor performing a write operation; FIG. 4B is a schematic diagram of a semi-floating gate transistor performing an erase operation.

[0069] Referring to FIG4A , a write operation voltage is applied to the control gate 32, source S, and drain D of the semi-floating gate transistor 3. For example, the operation voltage received by the control gate 32 is -1.5V, the source S is connected to the ground terminal GND, and the operation voltage of the drain D is 3V. Under the action of the electric field, positive charges pass from the drain D and the n-well 30b through the hole H into the floating gate 31. The positive charges in the floating gate 31 increase, causing the threshold voltage of the semi-floating gate transistor 3 to decrease, thereby realizing data writing (writing data "1").

[0070] Based on this, by applying a fixed read operation voltage to the control gate 32, source S and drain D of the semi-floating gate transistor 3, due to the low threshold voltage of the semi-floating gate transistor 3, the semi-floating gate transistor 3 is fully turned on, and a large drain-source current Ids is generated between the drain D and the source S. At this time, the data "1" can be read.

[0071] Referring to FIG4B , an operating voltage is applied to the control gate 32, source S, and drain D of the semi-floating gate transistor 3. For example, the operating voltage received by the control gate 32 is 1.2 V, the source S is connected to the ground terminal GND, and the operating voltage of the drain D is 0.6 V. Under the action of the electric field, positive charges pass from the floating gate 31 through the hole H into the n-well 30 b and the drain D. The positive charges in the floating gate 31 are reduced, thereby increasing the threshold voltage of the semi-floating gate transistor 3, thereby achieving data erasure (also known as writing data "0").

[0072] Based on this, by applying the same read operation voltage to the control gate 32, source S and drain D of the semi-floating gate transistor 3, due to the high threshold voltage of the semi-floating gate transistor 3, the semi-floating gate transistor 3 is not fully turned on, and a small drain-source current Ids is generated between the drain D and the source S. At this time, the data "0" can be read.

[0073] The inventors of the present application have discovered that in the semi-floating gate transistor 3, the material of the floating gate 31 is a polycrystalline material. For example, the polycrystalline material may include polycrystalline silicon. Polycrystalline silicon is composed of irregularly arranged grains with different crystal plane orientations. The grain boundaries of polycrystalline silicon present complex grain structures and structural defects, which form leakage channels at the grain boundaries, resulting in poor data retention capability of the semi-floating gate transistor 3.

[0074] For example, the data "1" stored in the half-floating gate transistor 3, during the data retention stage, due to the existence of the leakage channel in the polysilicon, the positive charge in the floating gate 31 will be lost through the window (via H), generating leakage current at the window, and the threshold voltage of the half-floating gate transistor 3 will increase. During the data reading stage, the data "0" is read in the half-floating gate transistor 3, and the data "1" stored in the half-floating gate transistor 3 is lost, making its data retention ability poor.

[0075] Based on this, referring again to FIG. 3 , the semi-floating-gate transistor 3 further includes a plug structure 34, which is disposed in the via H to penetrate the first dielectric layer 33. The plug structure 34 is electrically connected to the portion of the substrate 30 located between the source S and the drain D. For example, the plug structure 34 is electrically connected to the n-well 30 b. The plug structure 34 is also electrically connected to the floating gate 31. It can be understood that, at the window, the floating gate 31 and the n-well 30 b are separated by the plug structure 34. The material of the plug structure 34 includes a single crystal, which may include, for example, at least one of single crystal silicon, single crystal germanium, or single crystal silicon germanium (chemical formula: SiGe).

[0076] By setting a plug structure 34 at the window, the material of the plug structure 34 includes a single crystal, which is composed of grains arranged in a regular pattern and with the same crystal plane orientation. The leakage channel of the single crystal is less than that of the polycrystalline. The plug structure 34 is equivalent to a low-leakage "plug" that can block the window. During the data retention stage, the positive charge in the floating gate 31 can be suppressed from flowing into the n-well 30b through the window, thereby reducing the leakage current in the semi-floating gate transistor 3 and improving the data retention capability of the semi-floating gate transistor memory.

[0077] Referring to Figure 3 , the half-floating-gate transistor 3 also includes a split gate (also called a "select gate") 35. Split gate 35 is located on the side of the control gate 32 near the drain D. Therefore, the half-floating-gate transistor 3 can be referred to as a "split-gate half-floating-gate transistor." A second dielectric layer 36 is provided between the control gate 32 and the split gate 35 to provide insulation between them. Furthermore, a second dielectric layer 36 is also provided between the control gate 32 and the floating gate 31 to provide insulation between them.

[0078] Referring to Figure 3, the half-floating gate transistor 3 also includes a spacer layer 37. Typically, multiple half-floating gate transistors 3 are arranged on the substrate 30, and the spacer layer 37 is located between two adjacent half-floating gate transistors 3 to separate the floating gate 31, control gate 32 and split gate 35 of the two adjacent half-floating gate transistors 3 to achieve insulation between the devices.

[0079] FIG5 is a structural diagram of another half-floating gate transistor provided in this application.

[0080] Referring to Figure 5, the floating gate 31 of the semi-floating gate transistor 3 includes a first sub-floating gate 31a and a second sub-floating gate 31b connected to each other, and the first dielectric layer 33 includes a first portion 33a and a second portion 33b. The first sub-floating gate 31a and the first portion 33a are located inside the substrate 30, and the second sub-floating gate 31b and the second portion 33b are located above the substrate 30, that is, part of the floating gate 31 (the first sub-floating gate 31a) is embedded in the substrate 30. The semi-floating gate transistor 3 can be called a "trench-gate semi-floating gate transistor."

[0081] 5 , the plug structure 34 penetrates the second portion 33 b of the first dielectric layer 33 , and the second sub-floating gate 31 b of the floating gate 31 is electrically connected to the plug structure 34 .

[0082] By adopting a design in which the floating gate 31 is partially embedded in the substrate 30, the size of the floating gate 31 along direction Z (the thickness direction of the device) is increased. While ensuring that the charge storage performance of the floating gate 31 remains unchanged, the area of ​​the floating gate 31 along plane XY can be reduced, which is beneficial to reducing the occupied area of ​​the device.

[0083] The difference from the semi-floating gate transistor shown in Figure 3 is that the semi-floating gate transistor 3 shown in Figure 5 does not include a split gate 35. The control gate 32 of the semi-floating gate transistor 3 in Figure 5 is equivalent to a structure in which the control gate 32 and the split gate 35 of the semi-floating gate transistor 3 in Figure 3 are combined into one.

[0084] FIG6 is a structural diagram of another semi-floating gate transistor provided by the present application. The difference from the semi-floating gate transistor in FIG5 is that the floating gate in FIG6 is divided into two and both are embedded in the substrate, as follows:

[0085] Referring to Figure 6, the floating gate 31 of the half-floating gate transistor 3 includes a first sub-floating gate 31a and a second sub-floating gate 31b. The first dielectric layer 33, the first sub-floating gate 31a and the second sub-floating gate 31b are all located inside the substrate 30. The first sub-floating gate 31a and the second sub-floating gate 31b are all embedded in the substrate 30, and the first sub-floating gate 31a and the second sub-floating gate 31b extend along the direction Z. Therefore, the half-floating gate transistor 3 can be called a "vertical half-floating gate transistor".

[0086] 6 , plug structure 34 includes a first plug 34a and a second plug 34b. First plug 34a penetrates first dielectric layer 33, and first sub-floating gate 31a is electrically connected to first plug 34a. Second plug 34b also penetrates first dielectric layer 33, and second sub-floating gate 31b is electrically connected to second plug 34b.

[0087] Exemplarily, the first sub-floating gate 31a is not connected to the second sub-floating gate 31b, and the split gate 35 is located between the first sub-floating gate 31a and the second sub-floating gate 31b, thereby enabling the first sub-floating gate 31a and the second sub-floating gate 31b to share the split gate 35.

[0088] By adopting a design in which the floating gate 31 is fully embedded in the substrate 30, the size of the floating gate 31 along the direction Z is further increased. While ensuring the charge storage performance of the floating gate 31 remains unchanged, the area of ​​the floating gate 31 along the plane XY can be reduced, which is beneficial to reducing the occupied area of ​​the device.

[0089] Taking the semi-floating gate transistor shown in Figure 3 as an example, the present application provides a method for preparing the semi-floating gate transistor. Figures 7A and 7B are the flow charts of preparing the semi-floating gate transistor provided by the present application; Figures 8A to 8K are the step diagrams of preparing the semi-floating gate transistor provided by the present application.

[0090] 7A , the method for manufacturing a semi-floating gate transistor includes the following steps S10 to S50 :

[0091] S10 : Referring to FIG. 8A and FIG. 8B , a first dielectric layer 33 is formed on the substrate 30 .

[0092] Exemplarily, referring to FIG. 8A , a substrate 30 is formed on a substrate 4 , the substrate 30 including a p-well 30 a and an n-well 30 b disposed on the p-well 30 a . Then, a photolithography process is used to etch the substrate 30 to form a trench C1 .

[0093] 8B , a first dielectric layer 33 and a mask layer K are sequentially formed on the surface of the substrate 30 using a thin film deposition process. Then, a chemical mechanical polishing (CMP) process is used to polish the surface of the mask layer K away from the substrate 30 to improve the surface flatness of the mask layer K.

[0094] S20 : ​​Referring to FIG. 8C , a via hole H is formed penetrating the first dielectric layer 33 , where the via hole H exposes the substrate 30 .

[0095] Illustratively, a photolithography process is adopted to etch the mask layer K, and the mask layer K is used as a mask to etch the first dielectric layer 33 to form a via H penetrating the first dielectric layer 33 , thereby “opening a window” on the first dielectric layer 33 .

[0096] S30: Referring to Figures 8C-8E , a plug structure 34 and a floating gate 31 are formed. Plug structure 34 is located within via H in first dielectric layer 33 and is electrically connected to substrate 30. The material of plug structure 34 comprises a single crystal. Floating gate 31 is located on first dielectric layer 33 and is electrically connected to plug structure 34.

[0097] For example, referring to FIG. 7B , the above S30 may include the following S31 to S32:

[0098] S31: Referring to FIG. 8C and FIG. 8D , the material of the mask layer K may be the same as the material of the floating gate 31 , for example, both may include polysilicon. Based on this, a thin film deposition process may be used to deposit polysilicon material to fill the mask layer K. Then, a chemical mechanical polishing process may be used to polish the surface of the mask layer K away from the substrate 30 , and the obtained mask layer K is used as the conductive layer L.

[0099] 8D , the conductive layer L includes a first conductive portion L1 filling the via hole H, and a second conductive portion L2 located on the first dielectric layer 33 . The first conductive portion L1 contacts the substrate 30 .

[0100] S32 : referring to FIG. 8D and FIG. 8E , the conductive layer L is annealed. The first conductive portion L1 of the conductive layer L forms a plug structure 34 , and the second conductive portion L2 forms a floating gate 31 .

[0101] It can be understood that at the interface where the first conductive part L1 of the conductive layer L contacts the substrate 30, the crystal lattice of the material of the first conductive part L1 terminates at the interface, and each atom in the outermost layer of the surface of the first conductive part L1 will have an unpaired electron, that is, there is an unsaturated bond, which is called an interface dangling bond.

[0102] The conductive layer L is annealed in a hydrogen atmosphere, and hydrogen ions can penetrate into the first conductive portion L1 of the conductive layer L to saturate the interface dangling bonds of the first conductive portion L1. Under the promotion of high temperature, the crystal nucleus of the first conductive portion L1 grows, so that the material of the first conductive portion L1 is converted from polycrystalline silicon to single crystal silicon, so as to obtain a low leakage plug structure 34 at the window.

[0103] The second conductive portion L2 of the conductive layer L does not react with hydrogen ions. Therefore, the material of the second conductive portion L2 is still polysilicon. The second conductive portion L2 can serve as the floating gate 31 .

[0104] The process conditions of the annealing treatment may, for example, include: the atmosphere of the annealing treatment may include nitrogen in addition to hydrogen, and the volume ratio of hydrogen to nitrogen is 1:5; the annealing treatment is under normal pressure, and the temperature range is 400°C to 450°C, for example, the temperature of the annealing treatment is 400°C, 415°C, 425°C, 435°C or 450°C; the duration of the annealing treatment is 60 minutes to 90 minutes, for example, the duration of the annealing treatment is 60 minutes, 65 minutes, 75 minutes, 85 minutes or 90 minutes.

[0105] S40 : Referring to FIG. 8F , a control gate 32 is formed. The control gate 32 is located on a side of the floating gate 31 away from the substrate 30 .

[0106] Illustratively, a second dielectric layer 36 is first formed on the surface of the floating gate 31 , and then a conductive material is deposited on the surface of the second dielectric layer 36 . The upper surface of the conductive material is polished using a chemical mechanical polishing process to form the control gate 32 .

[0107] 8F and 8G , after the control gate 32 is formed, the control gate 32 , the second dielectric layer 36 , the floating gate 31 and the first dielectric layer 33 are etched to form a trench C2 .

[0108] 8G and 8H , a third dielectric layer 38 and a split gate 35 are sequentially formed on the surface of the trench C2 .

[0109] 8H and 8I , the gate 35 and the third dielectric layer 38 are etched to form a trench C3 .

[0110] 8I and 8J , a spacer 37 is formed on the sidewalls of trench C3, with the bottom of spacer 37 exposing substrate 30. Spacer 37 can disconnect the floating gate 31, control gate 32, and split gate 35 of two adjacent half-floating-gate transistors 3, thereby achieving insulation between the two adjacent half-floating-gate transistors 3.

[0111] S50 : Referring to FIG. 8K , a source S and a drain D are formed on the substrate 30 .

[0112] Illustratively, an ion implantation process is used to implant n-type ions into the n-well 30 b of the substrate 30 , and an annealing process is performed to form a source S and a drain D on the substrate 30 .

[0113] The fabrication method provided herein first forms a first dielectric layer 33 on a substrate 30, and forms a penetrating via H in the first dielectric layer 33, exposing the substrate 30. A plug structure 34 made of a single crystal material is then formed within the via H, electrically connected to the substrate 30. A floating gate 31 is then formed on the first dielectric layer 33, electrically connected to the plug structure 34. Finally, a control gate 32 is formed on the side of the floating gate 31 away from the substrate 30, and a source S and a drain D are formed on the substrate 30.

[0114] By forming a plug structure 34 made of a single crystal material in the via H, the single crystal is a low leakage material. During the data retention stage, the plug structure 34 can inhibit the positive charge in the floating gate 31 from flowing into the n-well 30b of the substrate 30 through the hole H, thereby reducing the leakage current in the semi-floating gate transistor 3 and improving the data retention capability of the semi-floating gate transistor memory.

[0115] The present application also provides another method for preparing a semi-floating gate transistor. Figures 9A and 9B are flow charts for preparing a semi-floating gate transistor provided by the present application; Figures 10A to 10K are step diagrams for preparing a semi-floating gate transistor provided by the present application.

[0116] 9A , the method for manufacturing a semi-floating gate transistor includes the following steps S60 to S100 :

[0117] S60 : Referring to FIG. 10A and FIG. 10B , a first dielectric layer 33 is formed on the substrate 30 .

[0118] Exemplarily, referring to FIG. 10A , a substrate 30 is formed on a substrate 4 , the substrate 30 including a p-well 30 a and an n-well 30 b disposed on the p-well 30 a . Then, a photolithography process is used to etch the substrate 30 to form a trench C1 .

[0119] 10B , a thin film deposition process is used to sequentially form a first dielectric layer 33 and a mask layer K on the surface of the substrate 30 . Then, a chemical mechanical polishing process is used to polish the surface of the mask layer K away from the substrate 30 to improve the surface flatness of the mask layer K.

[0120] S70 : Referring to FIG. 10C , a via hole H is formed penetrating the first dielectric layer 33 , where the via hole H exposes the substrate 30 .

[0121] Illustratively, a photolithography process is adopted to etch the mask layer K, and the mask layer K is used as a mask to etch the first dielectric layer 33 to form a via H penetrating the first dielectric layer 33 , thereby “opening a window” on the first dielectric layer 33 .

[0122] S80: Referring to FIG10D and FIG10E , a plug structure 34 and a floating gate 31 are formed. The plug structure 34 is located in the via H of the first dielectric layer 33 and is electrically connected to the substrate 30. The floating gate 31 is located on the first dielectric layer 33 and is electrically connected to the plug structure 34.

[0123] For example, referring to FIG. 9B , the above S80 may include the following S81 to S82:

[0124] S81 : Referring to FIG. 10D , a plug structure 34 is formed on the surface of the substrate 30 through the hole H by adopting a selective epitaxial process.

[0125] For example, the n-well 30b in the substrate 30 is made of single crystal silicon. Chemical vapor deposition (CVD) equipment can be used to selectively epitaxially grow single crystal silicon on the surface of the substrate 30 through the hole H using the substrate 30 as a seed layer to form a low leakage plug structure 34 at the window.

[0126] The process conditions for selective epitaxy may, for example, include: a temperature range of the equipment reaction chamber of 400°C to 1650°C, for example, the temperature of the equipment reaction chamber is 400°C, 700°C, 1025°C, 1300°C or 1650°C; a pressure range of the equipment reaction chamber of 40 Torr to 150 Torr, for example, the pressure of the equipment reaction chamber is 40 Torr, 70 Torr, 95 Torr, 125 Torr or 150 Torr.

[0127] It is understood that the selective epitaxial growth process is mature, and the thickness of the grown film layer is controllable. Taking the thickness direction of the first dielectric layer 33 as a reference direction, for example, the reference direction in FIG10D is direction Z, the size of the plug structure 34 along direction Z can be controlled by adjusting the process parameters.

[0128] For example, the dimension of the plug structure 34 along the direction Z is equal to the thickness of the first dielectric layer 33. For another example, two opposing surfaces of the plug structure 34 along the direction Z correspond one-to-one with two opposing surfaces of the first dielectric layer 33 along the direction Z, and the corresponding surfaces are coplanar. In other words, by making the thickness of the plug structure 34 as thin as that of the first dielectric layer 33, the volume of the floating gate 31 can be prevented from being reduced due to an excessively thick plug structure 34, thereby preventing the charge storage performance of the floating gate 31 from being affected.

[0129] S82 : Referring to FIG. 10D and FIG. 10E , a floating gate 31 is formed. The floating gate 31 is located on the first dielectric layer 33 , and the floating gate 31 is electrically connected to the plug structure 34 .

[0130] Exemplarily, the material of the mask layer K may be the same as that of the floating gate 31, for example, both may include polysilicon. Based on this, a thin film deposition process may be used to deposit polysilicon material to fill the mask layer K. Then, a chemical mechanical polishing process may be used to polish the surface of the mask layer K away from the substrate 30, and the obtained mask layer K serves as the floating gate 31.

[0131] S90 : Referring to FIG. 10F , a control gate 32 is formed. The control gate 32 is located on a side of the floating gate 31 away from the substrate 30 .

[0132] Illustratively, a second dielectric layer 36 is first formed on the surface of the floating gate 31 , and then a conductive material is deposited on the surface of the second dielectric layer 36 . The upper surface of the conductive material is polished using a chemical mechanical polishing process to form the control gate 32 .

[0133] 10F and 10G , after the control gate 32 is formed, the control gate 32 , the second dielectric layer 36 , the floating gate 31 and the first dielectric layer 33 are etched to form a trench C2 .

[0134] 10G and 10H , a third dielectric layer 38 and a split gate 35 are sequentially formed on the surface of the trench C2 .

[0135] 10H and 10I , the gate 35 and the third dielectric layer 38 are etched to form a trench C3 .

[0136] 10I and 10J , a spacer 37 is formed on the sidewalls of trench C3, with the bottom of spacer 37 exposing substrate 30. Spacer 37 can disconnect the floating gate 31, control gate 32, and split gate 35 of two adjacent half-floating-gate transistors 3, thereby achieving insulation between the two adjacent half-floating-gate transistors 3.

[0137] S100 : Referring to FIG. 10K , a source S and a drain D are formed on the substrate 30 .

[0138] Illustratively, an ion implantation process is used to implant n-type ions into the n-well 30 b of the substrate 30 , and an annealing process is performed to form a source S and a drain D on the substrate 30 .

[0139] In addition, the half-floating gate transistor 3 provided in the present application can also be used as a photoelectric sensor, and the photoelectric sensor can be applied to an active image sensor to realize image acquisition.

[0140] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention are intended to be covered by the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope of protection of the claims.

Claims

1. A method for preparing a semi-floating gate transistor, characterized in that: include: forming a dielectric layer on the substrate; forming a via hole penetrating the dielectric layer, wherein the via hole exposes the substrate; forming a plug structure and a floating gate, wherein the plug structure is located in the via hole and is electrically connected to the substrate, and the material of the plug structure includes a single crystal; the floating gate is located on the dielectric layer and is electrically connected to the plug structure; forming a control gate, wherein the control gate is located on a side of the floating gate away from the substrate; A source electrode and a drain electrode are formed on the substrate.

2. The preparation method according to claim 1, characterized in that: The forming of the plug structure and the floating gate comprises: forming a conductive layer, wherein the conductive layer comprises a first conductive portion filling the via hole and a second conductive portion located on the dielectric layer, wherein the first conductive portion contacts the substrate; The conductive layer is annealed, the first conductive portion forms the plug structure, and the second conductive portion forms the floating gate.

3. The preparation method according to claim 2, characterized in that: The annealing process is performed in an atmosphere including hydrogen and nitrogen.

4. The preparation method according to claim 2 or 3, characterized in that: The temperature range of the annealing treatment is 400°C to 450°C.

5. The preparation method according to any one of claims 2 to 4, characterized in that: The annealing treatment lasts for 60 to 90 minutes.

6. The preparation method according to claim 1, characterized in that: The forming of the plug structure and the floating gate comprises: Using a selective epitaxial process, a plug structure is formed on the surface of the substrate through the via hole; The floating gate is formed, and the floating gate is located on the dielectric layer and is electrically connected to the plug structure.

7. The preparation method according to claim 6, characterized in that: The temperature range of the selective epitaxial process is 400°C to 1650°C.

8. The preparation method according to claim 6 or 7, characterized in that: The pressure range of the reaction chamber of the selective epitaxial process is 40 Torr to 150 Torr.

9. A semi-floating gate transistor, characterized in that: include: substrate; A source electrode and a drain electrode are arranged on the substrate; A dielectric layer is disposed on the substrate; A plug structure, penetrating the dielectric layer and electrically connected to a portion of the substrate located between the source and the drain; A floating gate, disposed on the dielectric layer and electrically connected to the plug structure; A control gate is disposed on a side of the floating gate away from the substrate; Wherein, the material of the plug structure includes single crystal.

10. The semi-floating gate transistor according to claim 9, characterized in that: The material of the plug structure includes at least one of single crystal silicon, single crystal germanium or single crystal silicon germanium.

11. The semi-floating gate transistor according to claim 9 or 10, characterized in that: The dielectric layer includes a first portion and a second portion, and the floating gate includes a first sub-floating gate and a second sub-floating gate connected to each other; The first portion and the first sub-floating gate are located inside the substrate, and the second portion and the second sub-floating gate are located above the substrate; The plug structure passes through the second portion, and the second sub-floating gate is electrically connected to the plug structure.

12. The semi-floating gate transistor according to claim 9 or 10, characterized in that: The floating gate includes a first sub-floating gate and a second sub-floating gate; The dielectric layer, the first sub-floating gate and the second sub-floating gate are located inside the substrate; The plug structure includes a first plug and a second plug. The first plug penetrates the dielectric layer, and the first sub-floating gate is electrically connected to the first plug. The second plug penetrates the dielectric layer, and the second sub-floating gate is electrically connected to the second plug.

13. The semi-floating gate transistor according to any one of claims 9 to 12, characterized in that: The thickness direction of the dielectric layer is a reference direction; The dimension of the plug structure along the reference direction is equal to the thickness of the dielectric layer.

14. The semi-floating gate transistor according to any one of claims 9 to 13, characterized in that: The thickness direction of the dielectric layer is a reference direction; The plug structure includes two surfaces opposite to each other along the reference direction, and the dielectric layer includes two surfaces opposite to each other along the reference direction. The two surfaces of the plug structure correspond to the two surfaces of the dielectric layer in a one-to-one manner and are coplanar.

15. A chip, characterized in that: include: The semi-floating gate transistor according to any one of claims 9 to 14; A controller is electrically connected to the semi-floating gate transistor.

16. An electronic device, characterized in that: include: The chip as claimed in claim 15; A circuit board, the chip is electrically connected to the circuit board.

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