Semiconductor packaging structure and packaging method thereof, and electronic device

Abstract

Provided are a semiconductor packaging structure and a packaging method thereof, and an electronic device, relating to the technical field of electronics, and used for solving the problem of defects generated by semiconductor package-on-package. The semiconductor packaging structure comprises: a substrate, and a first die and a second die that are stacked on the substrate, wherein the first die is located between the substrate and the second die; a filling portion, which is arranged around the side surfaces of the first die and the second die, and is continuous in a direction perpendicular to the substrate; and a supporting ring, wherein the orthographic projection of the supporting ring on the substrate surrounds the orthographic projection of the first die on the substrate, the supporting ring is embedded into the filling portion and is located on the side of a first reference surface close to the substrate, and the first reference surface is a plane where the surface of the second die close to the first die is located. The semiconductor packaging structure can be applied to an electronic device.

Description

Semiconductor packaging structure and packaging method thereof, and electronic equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on September 1, 2023, with application number 202311138713.X and application name “Semiconductor packaging structure and packaging method thereof, electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of electronic technology, and in particular to a semiconductor packaging structure and a packaging method thereof, and an electronic device. Background Art

[0003] With the rapid advancement of technology, people are demanding increasingly advanced features from high-tech electronic products, such as personal computers, mobile phones, and smartwatches. Semiconductor device performance is a key factor in determining the functionality of these products. Semiconductor devices are typically fabricated by sequentially depositing dielectric, conductive, and semiconductor material layers on a semiconductor substrate. These layers are then patterned through processes such as photolithography and etching to form circuit components or elements. Multiple integrated circuits are typically fabricated on a single semiconductor substrate. To protect and facilitate the use of these integrated circuits, they are typically packaged.

[0004] Generally speaking, packaging involves cutting the semiconductor substrate from the front-end process into small chips (Die) through a dicing process, and then gluing the cut chips to the corresponding islands of the substrate (lead frame) frame. Then, ultra-fine metal (gold, tin, copper, and aluminum) wires or conductive resins are used to connect the bonding pads (Bond Pad) of the chip to the corresponding pins (Lead) of the substrate to form the required circuit; and then the independent chips are encapsulated and protected with a plastic shell.

[0005] As the size of circuit components and elements approaches physical limits, further reductions in size are becoming increasingly difficult. Consequently, researchers are turning their attention to high-performance packaging of integrated circuits with various functions to improve semiconductor device performance while also reducing their size. Consequently, various advanced packaging technologies are emerging, with stacked packaging gaining a niche within this field due to its compact size and low energy consumption. However, existing stacked packaging techniques also present certain challenges. For example, the plastic encapsulation material between stacked chips can easily create voids, which not only affect the reliability of the packaged semiconductor device but can also cause cracks during cutting. Therefore, improvements to stacked packaging structures and methods are needed.

[0006] Summary of the Invention

[0007] The embodiments of the present application provide a semiconductor packaging structure and a packaging method thereof, and an electronic device, which are used to solve the problem that holes are easily generated in the semiconductor packaging structure and affect the stability of the semiconductor device.

[0008] To achieve the above objectives, this embodiment adopts the following technical solutions:

[0009] In a first aspect, a semiconductor packaging structure is provided, comprising: a substrate, and a first chip and a second chip stacked on the substrate, the first chip being located between the substrate and the second chip; a filling portion surrounding the side surfaces of the first chip and the second chip and being continuous in a direction perpendicular to the substrate; and a support ring, wherein the orthographic projection of the support ring on the substrate surrounds the orthographic projection of the first chip on the substrate, the support ring being embedded in the filling portion and being located on a side of a first reference plane close to the substrate, the first reference plane being the plane where the surface of the second chip close to the first chip is located.

[0010] The semiconductor packaging structure provided by the embodiment of the present application, on the one hand, the first chip and the second chip are stacked on the substrate, which can reduce the volume of the package and is conducive to realizing the lightness and thinness of the electronic device. On the other hand, a support ring is embedded in the filling part, and the support ring surrounds the orthographic projection of the first chip on the substrate, and is located on the side of the first reference surface close to the substrate. The first reference surface is the plane where the surface of the second chip close to the first chip is located, thereby realizing the arrangement of the support ring in the area prone to bowl-shaped defects, increasing the wear resistance of the area, and thus improving or avoiding bowl-shaped defects. When filling above this area, no hole defects will be formed inside the filling part, thereby improving the stability of the semiconductor packaging structure. The improved technical problem to be solved.

[0011] In one possible implementation of the first aspect, the support ring is located between a first reference plane and a second reference plane, where the second reference plane is a plane where the surface of the first chip is closest to the second chip. By defining the position of the support ring, the support ring and the redistribution layer can be placed at the same height, thereby simplifying the process by placing them on the same layer.

[0012] In one possible implementation of the first aspect, a redistribution layer is provided on a surface of the first chip facing away from the substrate, the redistribution layer including a dielectric layer. The filling portion includes a first filling layer, which surrounds at least a portion of the area between the first chip and the second chip. The first filling layer is made of the same material as the dielectric layer, and the support ring is embedded in the first filling layer. In this implementation, the first filling layer and the dielectric layer are made of the same material and can be manufactured using the same process, thereby reducing the process flow.

[0013] In a possible implementation of the first aspect, the first filling layer and the dielectric layer are provided in the same layer. Thus, they can be implemented through the same process, which reduces the number of process steps.

[0014] In one possible implementation of the first aspect, the redistribution layer further includes multiple wiring layers, stacked in a direction perpendicular to the substrate; the wiring layers are embedded in the dielectric layer, and the support ring is made of the same material as the wiring layers. In this embodiment, the support ring and the wiring layers can be provided using the same process, simplifying the process.

[0015] In a possible implementation of the first aspect, the support ring is provided in the same layer as at least one wiring layer farthest from the substrate, thereby avoiding defects caused by lack of support from the support ring when forming the final wiring layer.

[0016] In one possible implementation of the first aspect, the surface of the support ring facing away from the substrate is flush with the surface of the wiring layer furthest from the substrate. In this implementation, the height of the support ring is limited to prevent the support ring from being lower than the surface of the wiring layer when the final wiring layer is formed, thereby exacerbating defects.

[0017] In a possible implementation of the first aspect, the support ring penetrates the first filling layer in a direction perpendicular to the substrate, so that the support ring can be provided during the formation of the entire redistribution layer to avoid defects.

[0018] In one possible implementation of the first aspect, the filling portion further includes a first filling portion, the first filling portion being located between the first filling layer and the substrate and surrounding a side surface of the first chip. The first filling layer is made of a different material than the first filling portion. This allows the first filling layer to have different properties than the first filling portion, thereby preventing stress accumulation in the filling portion.

[0019] In a possible implementation of the first aspect, the filling portion further includes a second filling portion provided on a side of the first filling layer away from the substrate, the second filling portion surrounds a side surface of the second chip, and a material of the first filling layer is different from that of the second filling portion.

[0020] In one possible implementation of the first aspect, multiple support rings are provided and radially arranged from the inside outward in a direction parallel to the substrate. Providing multiple support rings can increase the uniformity of regional wear resistance and further avoid bowl-shaped defects.

[0021] In one possible implementation of the first aspect, of adjacent support rings, the width of the inner support ring is greater than the width of the outer support ring, where the width is measured in a direction parallel to the substrate. In this way, a larger support ring can be provided where the depression is large to reduce the depression and avoid defects.

[0022] In a second aspect, a packaging method for a semiconductor package structure is provided, comprising: bonding a first chip to a substrate; surrounding the first chip with a filling material to form a first filling portion surrounding a side surface of the first chip; forming a redistribution layer, a first filling layer surrounding the redistribution layer, and a support ring located within the first filling layer on a surface of the first chip remote from the substrate, wherein the first filling layer contacts the first filling portion, and the support ring's orthographic projection on the substrate surrounds the orthographic projection of the first chip on the substrate; bonding a second chip to the redistribution layer; surrounding the second chip with a filling material to form a second filling portion surrounding the second chip, the second filling portion contacting the first filling layer. In one technique known to the inventors of this application, a support ring surrounding the first chip is not provided. When stacking the first and second chips, misalignment occurs during alignment of the first and second chips, resulting in inconsistent aspect ratios around the first chip, which can result in void defects when filling around the first and second chips. In another technique known to the inventors of this application, after the first chip is stacked and placed on the substrate, filling is performed around the first chip, and a redistribution layer is formed on the top surface of the first chip. A second chip is then stacked on the redistribution layer and filled around it. Because the redistribution layer has bowl-shaped defects, this filling around the second chip also creates holes. The presence of holes affects the stability of the semiconductor package structure and can cause cracks during singulation and extend into the chip, damaging it.

[0023] The packaging method for a semiconductor package structure provided in this embodiment utilizes a support ring disposed on the same layer as the wiring layer of the redistribution layer. The support ring surrounds the first chip, providing support for the area where the bowl-shaped defect occurs and increasing its wear resistance, thereby improving or avoiding the bowl-shaped defect. Consequently, when filling the area around the second chip, voids are correspondingly improved or avoided, thereby enhancing the stability of the semiconductor package structure.

[0024] In a possible implementation of the second aspect, the redistribution layer includes a dielectric layer and a wiring layer, and the first filling layer and the dielectric layer are formed simultaneously. Thus, by forming the first filling layer and the dielectric layer simultaneously, the process can be reduced.

[0025] In one possible implementation of the second aspect, the support ring is formed simultaneously with at least a portion of the wiring layer. This simultaneous formation of the support ring and the wiring layer can reduce the number of processes and also allow the support ring to be positioned where bowl-shaped defects are most likely to occur, thereby avoiding defects.

[0026] In a third aspect, an electronic device is provided, comprising any semiconductor package structure according to the first aspect and a printed circuit board, wherein the semiconductor package structure is combined with the printed circuit board.

[0027] The electronic device provided in this embodiment, by adopting the semiconductor packaging structure in the above technical solution, achieves lightweight and thinness while improving the performance of the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIG1A is a schematic structural diagram of a first chip stacked on a substrate in an embodiment of the present application;

[0029] FIG1B is a schematic diagram of a structure in which a second chip is stacked on a first chip, as known to the inventors of this application;

[0030] FIG1C is a schematic diagram of a structure in which a hole is generated after filling a chip-on-chip package known to the inventors of the present application;

[0031] FIG1D is a schematic diagram of the structure of an ideal chip stack package;

[0032] 2A-2F are schematic diagrams showing a process for preparing another package-on-package structure known to the inventors of this application;

[0033] FIG3 is a perspective schematic diagram of a semiconductor packaging structure provided by an embodiment of the present application;

[0034] FIG4 is a cross-sectional view taken along the line AA′ in FIG3 ;

[0035] FIG5 is a partial enlarged view of the portion in the dotted box P2 in FIG4 ;

[0036] 6A-6I are schematic diagrams of a preparation process for forming a redistribution layer and other structures in a semiconductor packaging structure provided by an embodiment of the present application;

[0037] FIG7A is a cross-sectional view along the BB′ direction in FIG3 ;

[0038] FIG7B is another cross-sectional view along the line BB′ in FIG3 ;

[0039] 8A-8C are schematic diagrams of a manufacturing process for stacking a second chip on a first chip to form a semiconductor package structure according to an embodiment of the application;

[0040] FIG9 is a flow chart of a packaging method for a semiconductor packaging structure provided by an embodiment of the present application;

[0041] FIG10 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] Unless otherwise defined, the technical or scientific terms used in this application should have the usual meanings understood by those skilled in the art. The terms "first", "second", "third" and similar words used in this specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Thus, features defined as "first", "second", and "third" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise stated, "multiple" means two or more.

[0043] The directional terms such as "left", "right", "up" and "down" are defined relative to the orientation of the device schematically placed in the accompanying drawings. It should be understood that these directional terms are relative concepts. They are used for relative descriptions and clarifications, and they may change accordingly according to changes in the orientation of the chip or semiconductor packaging structure.

[0044] With the development of technology, people have increasingly higher requirements for the functions of electronic devices. For example, improving the portability of electronic devices requires reducing the size of the devices and improving the integration of the devices. Another example is improving the response speed of electronic devices and reducing latency. Increasing the number of transistors integrated into the chip is one way to achieve this. However, based on the development trend of existing memory chips, the size of transistors in the chip is approaching the physical limit, and the speed of improving the performance of a single chip by reducing the size of transistors has slowed down. Therefore, in order to reduce the size of electronic devices and improve their performance, technicians have moved from traditional chip packaging to a multi-layer chip stacking packaging format.

[0045] Multi-layer chip stacking includes wafer-to-wafer, die-to-wafer, and die-to-die. While substrate-to-substrate stacking is the most efficient, substrate warping can affect the bonding accuracy of the metal pads on the two substrates. Furthermore, substandard chips may exist on a substrate, which then bond to another chip on another substrate, reducing product yield. Choosing known good die for stacking in die-to-substrate stacking avoids the use of substandard chips for packaging, balancing both product and production yield. Therefore, die-to-substrate stacking offers a good compromise.

[0046] 1A to 1C , the process of a chip stacking process known to the inventor and possible problems thereof will be described below.

[0047] Figure 1A illustrates the stacking of a first chip 200 and a substrate 100 during the chip-substrate stacking process. The substrate 100 includes a substrate body 101 and a substrate interconnect layer 102, while the first chip 200 includes a first chip body 201 and a first interconnect layer 202. The substrate 100 is bonded to the first interconnect layer 202 of the first chip 200 via the substrate interconnect layer 102, achieving the stacking process.

[0048] In some embodiments, the substrate body 101 and the first chip body 201 can be formed of silicon, or can be formed of other Group III elements, Group IV elements and / or Group V elements (for example, silicon, germanium, gallium, arsenic and combinations thereof). The substrate body 101 can also be in the form of a silicon-on-insulator (SOI). The SOI substrate body may include a layer of semiconductor material (for example, silicon, germanium and / or the like) formed on an insulator layer (for example, buried oxide and / or the like), wherein the insulator layer is formed on the silicon substrate body. The substrate body 101 is formed with circuit elements (not shown in the figure) through semiconductor process steps such as doping, photolithography, etching, deposition, etc. In some embodiments, the various circuit elements may include various n-type metal-oxide semiconductor (NMOS) and / or p-type metal-oxide semiconductor (PMOS) devices such as transistors, capacitors, resistors, diodes, photodiodes, fuses and / or the like. The circuit elements on the substrate body 101 are divided into multiple regions. The circuit elements in each region are connected by conductive lines within the substrate interconnect layer 102, thereby realizing specific functions such as logical operations and data storage. When the substrate body 101 is cut into pieces, the final product will only include one or several of these regions. When there are multiple regions, the functions of these multiple regions may be the same or different. The first chip body 201 differs from the substrate body 101 only in that the first chip body 201 does not need to be cut into pieces when the final product is formed. However, the circuit elements on the first chip body 201 may be one region or multiple regions. Similarly, when there are multiple regions, the functions of these multiple regions may be the same or different.

[0049] In some embodiments, the substrate interconnect layer 102 and the first interconnect layer 202 can be formed by depositing an insulating dielectric layer on the substrate body 101 and the first chip body 201, and forming a wiring layer (not shown in the figure) on the insulating dielectric layer through semiconductor process steps such as photolithography, development, etching, sputtering, chemical mechanical polish (CMP), etc. The wiring layer may include conductive wires and bonding contacts. The insulating dielectric layer may be a low-k dielectric material, and the conductive wires and bonding contacts may be metal materials such as copper, tungsten, and tin. In some embodiments, the conductive wires and bonding contacts may also include a seed layer and a barrier layer (not shown in the figure), wherein a seed layer is formed at a preset position, and then the conductive material of the conductive wires and bonding contacts is deposited on the thin seed layer. The seed layer may contain copper, titanium, nickel, gold, manganese, the like, or a combination thereof, and may be formed by ALD, PVD, a similar process, or a combination thereof.

[0050] The circuit elements on substrate body 101 and first chip body 201 are interconnected via upper substrate interconnect layer 102 and first interconnect layer 202 to form an integrated circuit that implements a specific function. Bonding contacts enable connections to other circuits, such as other chips or printed circuit boards. The integrated circuits described herein may be logic integrated circuits, memory integrated circuits, sensor integrated circuits, analog integrated circuits, and the like.

[0051] In some embodiments, before stacking the first chip 200 and the substrate 100, the first chip 200 needs to be picked up from the dicing tape and placed on the substrate 100. The first chip 200 and the substrate 100 can be bonded using a bonding process, such as eutectic bonding, metal thermocompression bonding, hybrid bonding, etc.

[0052] Please refer to Figure 1B, which is a schematic diagram of a structure in which a second chip 500 is stacked on a first chip 200 in a related art known to the inventors of this application. The packaging is described using the example of stacking two layers of chips on a substrate 100. In some embodiments, there are multiple first chips 200, which are evenly distributed on the surface of the substrate and bonded to the substrate 100. After the first chip 200 is bonded to the substrate 100, the second chip 500 is stacked on the first chip 200, that is, the second chip 500 is bonded to the first chip 200. The structure of the second chip 500 is similar to that of the first chip 200 and will not be repeated here.

[0053] In some embodiments, before bonding the second chip 500 to the first chip 200, a redistribution layer 400 is pre-formed on the upper surface of the first chip 200. The redistribution layer 400 is provided with a communication channel extending through the first chip body 201. Conductive lines are provided in the communication channel, and the redistribution layer 400 is electrically connected to the first chip 200 or the substrate 100 via the conductive lines. Due to factors such as the placement accuracy of the second chip 500 and substrate warpage, the alignment of the second chip 500 with the redistribution layer 400 on the first chip 200 may be inaccurate. For example, the left second chip 500 may be offset to the right, while the right second chip 500 may be offset to the left. If some second chips 500 other than the aforementioned two second chips 500 are precisely aligned, the left gap of the left second chip 500 may be inconsistent with the right gap. The left gap refers to the distance between the left second chip 500 and the adjacent left second chip 500, while the right gap refers to the distance between the left second chip 500 and the adjacent right second chip 500. Therefore, the aspect ratios of the gaps around the second chips 500 are inconsistent. In addition, in the same gap, due to the misalignment of the second chips 500 , the gap width d1 between the first chips 200 is greater than the gap width d2 between the second chips 500 .

[0054] Referring to FIG. 1C , after the second chip 500 is bonded to the first chip 200, a filler material 301 is used to fill the gaps around the first chip 200 and the second chip 500. In some embodiments, the filler material may include molding compounds such as epoxy resin, resin, moldable polymer, polyimide, and silicides such as silicon oxide, silicon nitride, silicon oxynitride, and silicon-glass bonding. The gap width d1 between the first chips 200 is different from the gap width d2 between the second chips 500, and the aspect ratios of the gaps around the second chips 500 are inconsistent. If the same filler material is used for filling, defects may occur after filling. For example, after the filler material cures, a void 306 may be formed within it, and the presence of the void 306 may affect the stability of the chip. To avoid this problem, the filler material used to fill the gaps between the first chips 200 and the filler material used to fill the gaps between the second chips 500 must have certain differences, such as differences in fluidity and volume change after curing. First, the differences in these filling materials make it difficult to achieve precise control. Second, since the position of the second chip 500 after bonding is also uncertain, it is difficult to select the properties of the filling material according to the specific gap.

[0055] Please refer to Figure 1D, which is a schematic diagram of the chip stacking structure under an ideal state, wherein the first chip 200 and the second chip 500 are not misaligned when bonded, and there are no hole defects in the filling material 301 around the first chip 200 and the second chip 500.

[0056] In order to improve the problems caused by the stacking method shown above and to achieve an ideal device, the following technical solutions are provided.

[0057] Please refer to FIG. 2A to FIG. 2F , which are schematic diagrams of a preparation process of a stacked package structure known to the inventor of the present application.

[0058] Referring to Figure 2A, in some embodiments, after the first chip 200 is bonded to the substrate 100, a filling material 301 is used to fill around the first chip 200. In a specific embodiment, multiple first chips 200 are bonded simultaneously on a substrate 100, and the multiple first chips 200 are arranged in a plane on the surface of the substrate 100, and the filling material 301 fills the gaps between the first chips 200. The filling material may include molding compounds such as epoxy resin, resin, moldable polymer, polyimide, etc. A dicing street (dicing street) for forming a separate package by monomerization may be provided in the gap between the first chips 200. In order to ensure the filling effect, the height of the filling material 301 after filling will be higher than the upper surface of the first chip 200. Therefore, in order to continue to stack chips on the upper surface of the first chip 200, it is necessary to planarize the upper surface of the first chip 200 and the filling material 301.

[0059] Referring to FIG. 2B , after the filler material 301 fills the periphery of the first chip 200, the top surfaces of the first chip 200 and the filler material 301 are planarized. Planarization can be performed by chemical mechanical polishing (CMP), etching, or other suitable processes. After planarization, it is desirable that the top surface of the filler material 301 is substantially coplanar with the top surface of the first chip 200 within process variations, with the filler material 301 surrounding the first chip 200 forming a first filler portion 311. However, due to the difference in material between the first chip 200 and the filler material 301, a bowl-shaped depression 308 ("dishing") may appear on the top surface of the first filler portion 311 after planarization. For example, when a chemical mechanical polishing process is used for planarization, the filler material 301 has lower wear resistance than the first chip 200 to reduce wear on the first chip 200. Consequently, the filler material 301 is polished at a higher rate than the first chip 200, resulting in a bowl-shaped depression on the top surface of the first filler portion 311.

[0060] After the planarization process, in order to realize the chip stacking arrangement, that is, to combine the second chip 500 on the upper surface of the first chip 200, it is necessary to electrically connect the second chip 500 to the substrate 100 or the first chip 200. In some embodiments, a channel (not shown in the figure) is formed on the first chip 200, which at least passes through the first chip body 201 of the first chip 200. By filling the channel with a conductive material such as copper, tungsten, or polysilicon, an electrical connection between the first chip 200 or the substrate 100 and the second chip 500 can be achieved. The formation of the channel can be achieved by a plasma etching process or by some other processes. It is easy to understand that if electrical connection is achieved only by filling the channel with a conductive material, the position of the channel will limit the position of the bonding contact of the second chip 500, which is not conducive to stacking.

[0061] Therefore, before stacking the second chip 500 on the first chip 200, a redistribution layer 400 needs to be formed on the upper surface of the first chip 200. The redistribution layer 400 is used to change the layout of the bonding contacts on the upper surface of the first chip 200 that are electrically connected to the second chip 500. In some embodiments, to meet certain specific requirements, other film layers, such as a film layer to improve insulation, are provided between the redistribution layer 400 and the first chip 200.

[0062] The redistribution layer 400 includes an insulating dielectric layer 401 and a wiring layer 402. Referring to FIG2C , a layer of insulating dielectric material 701 is first deposited on the upper surfaces of the first chip 200 and the first filling portion 311 to form the dielectric layer 401 in subsequent processes. The deposited insulating dielectric material 701 can be considered to have a uniform thickness, so a bowl-shaped defect 308 may also exist on the upper surface of the first filling portion 311.

[0063] Continuing with FIG2D , the insulating dielectric material 701 is subjected to processes such as photolithography, etching, sputtering, and planarization to form an insulating dielectric layer 401 and a wiring layer 402, with the wiring layer 402 embedded in the insulating dielectric layer 401. During the planarization process, the insulating dielectric material 701 in the upper region of the first chip 200 includes a wiring layer, i.e., conductive wiring. This conductive wiring increases the wear resistance of the upper region of the first chip 200. However, the insulating dielectric material 701 above the first filling portion 311 lacks a wiring layer and has lower wear resistance than the upper surface of the first chip 200. Therefore, the bowl-shaped defect 308 of the insulating dielectric material 701 in the upper region of the first filling portion is exacerbated during the planarization process. For example, the bowl-shaped defect 308 of the insulating dielectric material 701 is larger than the opening of the bowl-shaped defect 308 of the first filling portion 311.

[0064] Referring to Figure 2E , after forming the redistribution layer 400, the second chip 500 is bonded to the redistribution layer 400 in the same manner as the first chip 200 is bonded to the substrate 100. The second chip 500 is picked from the dicing tape and placed on the redistribution layer 400. Due to factors such as substrate warpage and the lack of a reliable reference, the bonding contacts of the second chip 500 and the bonding contacts of the redistribution layer 400 may also be misaligned, resulting in misalignment.

[0065] 2F , the second chip 500 is filled with filling material 301 to form a second filling portion 313. Since the first filling layer 312 has a bowl-shaped defect 308, a hole 306 may be formed in the second filling portion 313, affecting the stability of the semiconductor package structure.

[0066] In the stacked packaging method shown in Figures 2A-2F , although misalignment may occur after the second chip 500 is bonded, the gap around the first chip 200 is filled first, followed by the gap around the second chip 500. This multi-step filling method can alleviate the impact of inconsistent gap aspect ratios. It is easy to understand that although the redistribution layer 400 is formed on the upper surface of the first chip 200 after the first chip 200 is bonded to the substrate 100 in the stacked packaging method shown in Figures 2A-2F , it should be understood that forming the redistribution layer on the upper surface of the first chip 200 before bonding the first chip 200 to the substrate 100 can also achieve similar technical effects. Furthermore, these two stacked packaging methods, which form the redistribution layer at different times, both include a planarization process step, namely, a planarization process step is performed after the gap around the first chip 200, which has already been bonded to the substrate 100, is filled with a filler material. As previously mentioned, the planarization process can introduce bowl-shaped defects 308. After filling, the bowl-shaped defect 308 may cause a void 306 to be generated in the filling material, thereby affecting the reliability of the device formed after the stacking package.

[0067] In order to avoid or improve the problems caused by the bowl-shaped defect 308, an embodiment of the present application proposes a semiconductor packaging structure. Taking the example of stacking two layers of chips on a substrate for explanation, it is easy to understand that the present application can be extended to stacking multiple layers of chips on a substrate during specific implementation. As shown in Figure 3, this is a three-dimensional schematic diagram of the semiconductor packaging structure. The semiconductor packaging structure 1 includes: a substrate 100 and a filling portion 310, the filling portion includes a first filling portion 311, a first filling layer 312 and a second filling portion 313, and the substrate 100 includes a substrate body 101 and a substrate interconnection layer 102. A first chip 200 and a second chip 500 are arranged in the filling portion 310.

[0068] The materials and structures of the substrate 100 , the first filling portion 311 , the first filling layer 312 and the second filling portion 313 may be consistent with those described in the embodiments in FIG. 1A to FIG. 2F , and are not described in detail here.

[0069] As shown in FIG4 (a cross-sectional view along the AA′ direction in FIG3 ), the first chip 200 and the second chip 500 are stacked on the substrate 100 , with the first chip 200 located between the substrate 100 and the second chip 500 ; a redistribution layer 400 is provided between the first chip 200 and the second chip 500 .

[0070] Among them, the first chip 200 includes a first interconnection layer 202 and a first chip body 201, and the second chip 500 includes a second interconnection layer 502 and a second chip body 501. In some embodiments, the first chip 200 and the second chip 500 are packaged in the embodiment of the present application after they are manufactured in the wafer fab, that is, the first chip 200 and the second chip 500 are bare chips. In some embodiments, the first chip 200 and the second chip 500 are packaged before being packaged in the embodiment of the present application. The first chip 200 and the second chip 500 can be chips with the same function or chips with different functions, and there is no limitation on the size relationship between the first chip 200 and the second chip 500. For example, the size of the first chip 200 and the size of the second chip 500 can be the same or different.

[0071] In some embodiments, the first interconnect layer 202 of the first chip 200 is disposed opposite to and bonded to the substrate interconnect layer 102 of the substrate 100 , using bonding methods including eutectic bonding, metal thermocompression bonding, hybrid bonding, etc. The second interconnect layer 502 of the second chip 500 is bonded to the first chip 200 via the distribution layer 400 .

[0072] Referring to FIG. 5 , FIG. 5 is a partial enlarged view of the portion within the dashed box P2 in FIG. 4 , the redistribution layer 400 includes a dielectric layer 401 and a wiring layer 402. The dielectric layer 401 is made of an insulating material, such as silicon dioxide, for electrical isolation. The wiring layer includes conductive wires and bonding contacts for electrically connecting the second chip 500 to the first chip 200 or the substrate 100.

[0073] The filling portion 310 is continuous in a direction perpendicular to the substrate 100, and the support ring 600 is embedded in the filling portion 310. The filling portion includes a first filling portion 311, a first filling layer 312, and a second filling portion 313. The first filling layer 312 is the portion indicated by reference numeral 312 in the dashed box P1 in FIG4 , and does not include the support ring 600.

[0074] The first filling portion 311 surrounds the side surfaces of the first chip 200, and the second filling portion 313 surrounds the side surfaces of the second chip 500. The bottom surface of the first filling portion 311 is in close contact with the upper surface of the substrate 100, thereby sealing the first chip 200 and the like. The second filling portion 313 is continuous with the first filling portion 311 in a direction perpendicular to the substrate surface or is continuous with the first filling portion 311 through the first filling layer 312. The second filling portion 313 also covers the top of the second chip 500, thereby sealing the second chip 500 and the like. In some embodiments, the second filling portion 313 may surround a portion of the area between the first chip 200 and the second chip 500.

[0075] The first filling layer 312 is disposed between the first filling portion 311 and the second filling portion 313 , thereby achieving continuity between the first filling portion 311 and the second filling portion 313 , ie, continuity of the filling portion 310 . At this time, the support ring 600 is embedded in the first filling layer 312 .

[0076] In some embodiments, the redistribution layer 400 can be formed on the first chip 200 before stacking. For example, after completing the front-end fabrication and singulation of the substrate, the first chip 200 is obtained. Multiple chips are arranged and placed on a carrier with temporary bonding adhesive. After the gaps between the chips are filled with molding material and the back surfaces of the chips are aligned with the molding material, the chips and carrier are separated, and the redistribution layer 400 is formed on the back surfaces of the chips and in the same plane as the molding material. Finally, the first chip 200 with the redistribution layer 400 is cut to obtain. Therefore, after the filling material is filled around the first chip 200 and planarized, the redistribution layer 400 is no longer required. At this point, the upper surface of the planarized first filling portion 311 is flush with the upper surface of the redistribution layer 400, facilitating the bonding of the second chip 500 to the first chip 200. That is, the second filling portion 313 is positioned immediately adjacent to the first filling portion 311, thereby achieving a continuous filling portion 310. In these embodiments, there is no first filling layer 312, and the support ring 600 is embedded in the first filling portion 311 or the second filling portion 313. That is, in this embodiment, after the first chip 200 is bonded to the substrate 100 and filled to form the first filling portion 311, since the redistribution layer 400 has already been formed on the first chip 200, there is no need to dispose the redistribution layer 400 on the upper surface formed by the first chip 200 and the first filling portion 311. For example, the support ring 600 can be formed on the upper surface of the first filling portion 311 through steps such as photolithography and deposition.

[0077] It is understood that in various situations where the support ring 600 is embedded in the filling portion 310, the orthographic projection of the support ring 600 on the substrate 100 surrounds the orthographic projection of the first chip 200 on the substrate 100. Preferably, the orthographic projection of the support ring 600 on the substrate 100 surrounds the orthographic projection of the first chip 200 on the substrate 100 and is spaced apart.

[0078] If the surface of the second chip 500 closest to the substrate 100 is used as the first reference plane, the support ring 600 is substantially located on the side of the first reference plane closest to the substrate 100. This "substantially" means that the impact of process errors is not considered. That is, in actual products, the upper surface of the support ring 600 may extend beyond the first reference plane by a certain distance, which is caused by process errors.

[0079] In some embodiments, the redistribution layer 400 may include a multi-layer dielectric layer 401 and a multi-layer wiring layer 402. That is, both the dielectric layer 401 and the wiring layer 402 may have multiple layers. When forming the dielectric layer 401, the first filling layer 312 may be provided in the same layer. "Provided in the same layer" means provided using the same process, which not only means employing the same process but also employing the same process simultaneously. Specifically, this means that the dielectric layer 401 and the first filling layer 312 are formed using the same film formation process, and a film layer for forming a specific pattern is formed using this film formation process. Subsequently, the dielectric layer 401 and the first filling layer 312 are simultaneously formed using a single patterning process using the same mask. Depending on the structure formed, a single patterning process may include multiple exposure, development, and etching processes, and the layer structure formed by this same layer formation process may be continuous or discontinuous. More specifically, in some embodiments, the dielectric layer 401 is formed by depositing silicon dioxide on the upper surface of the first chip 200 using a deposition process. Silicon dioxide is also deposited on the upper surface of the first filling portion 311 using the same deposition process. After the silicon dioxide film layer is deposited, in order to form the wiring layer 402 on the dielectric layer 401 and embed the support ring 600 in the first filling layer 312, a photoresist is coated on the silicon dioxide film layer and exposed using the same mask. After exposure, the photoresist is developed to obtain a pattern not blocked by the photoresist. Finally, the pattern is formed in the silicon dioxide film layer through an etching process. This forms the dielectric layer 401 located directly above the first chip 200 and the first filling layer 312 located directly above the first filling portion 311. In this embodiment, the first filling layer 312 and the dielectric layer 401 are arranged continuously. However, it is easy to understand that in some embodiments, the first filling layer 312 may not be arranged continuously with the dielectric layer 401, that is, there is a gap between the first filling layer 312 and the dielectric layer 401, and the support ring 600 is embedded in this gap.

[0080] In some embodiments, the material of the dielectric layer 401 of the redistribution layer 400 is different from the material of the first filling portion 311 and the second filling portion 313. Since the dielectric layer 401 of the redistribution layer 400 and the first filling layer 312 are provided on the same layer, the dielectric layer 401 of the redistribution layer 400 and the first filling layer 312 are made of the same material. Furthermore, the material of the redistribution layer 400 can be different from the gap-filling material 301 used in the package, that is, the material of the first filling layer 312 can be different from the material of the first filling portion 311 or the second filling portion 313. In other embodiments, the material of the first filling layer 312 can also be the same as the material of the first filling portion 311 or the second filling portion 313.

[0081] In some embodiments, the support ring 600 is provided in the same layer as the wiring layer 402 of the redistribution layer 400. After forming the dielectric layer 401 located directly above the first chip 200 and the first filling layer 312 located directly above the first filling portion 311, a conductive material, such as copper or tungsten, is provided in the pattern produced by etching using a process such as sputtering or deposition, thereby forming the wiring layer 402 and the support ring 600, and the wiring layer 402 is embedded in the dielectric layer 401. Thus, the wiring layer 402 and the support ring 600 are made of the same material. In some embodiments, the support ring 600 may not be provided in the same layer as the wiring layer 402, thereby enabling the support ring 600 and the wiring layer 402 to be made of different materials to meet specific requirements for the support ring 600. Specifically, a conductive material may first be provided in the pattern produced by etching the dielectric layer 401, and then another material that meets the requirements may be provided in the pattern produced by etching the first filling layer 312.

[0082] In some embodiments, the support ring 600 is disposed within the first filling layer 312, which is located on the side of the first filling portion 311 away from the substrate 100. Therefore, the support ring 600 is located above the upper surface of the first filling portion 311. When the filling material 301 is filled around the second chip 500, if the surface of the first filling layer 312 in contact with the filling material 301 is uneven, this unevenness can affect the formation of the second filling portion 313 around the second chip 500, causing defects in the second filling portion 313 and affecting the reliability of the semiconductor package structure 1. Therefore, the support ring 600 is located on the side of the plane of the lower surface of the second chip 500 that is closer to the substrate 100.

[0083] The following uses the support ring 600 provided in the first filling layer 312 to illustrate the technical effect of the support ring 600 in improving or avoiding the bowl-shaped defect 308, thereby improving or avoiding the generation of holes 306 in the second filling portion that affect the reliability of the semiconductor package structure 1.

[0084] Please refer to FIG. 6A to FIG. 6I (partially enlarged views of the corresponding area within the dotted box P2 in FIG. 4 ), which are schematic diagrams of the formation process of the redistribution layer 400 and the first filling layer 312 .

[0085] 6A shows that the first chip 200 is stacked on the substrate 100. After the first chip 200 is bonded to the substrate 100, a filling material 301 may be filled around the first chip 200 to form a first filling portion 311.

[0086] 6B shows filling material 301 around the first chip 200. To ensure packaging effect, after filling, the upper surface of the filling material 301 will be higher than the upper surface of the first chip 200, which will be detrimental to forming the redistribution layer 400 on the upper surface of the first chip 200.

[0087] Figure 6C shows the planarization process performed on the top surface of the first chip 200 and / or the filling material 301. After filling around the first chip 200, the filling material 301 and the top surface of the first chip 200 need to be planarized. However, due to the difference in material between the filling material 301 and the top surface of the first chip 200, a bowl-shaped defect 308 may be generated on the top surface of the filling material 301 during the planarization process.

[0088] As shown in Figure 6D, after planarization, a redistribution layer 400 is formed on the upper surface of the first chip 200 to stack the second chip 500. When forming the redistribution layer 400, an insulating dielectric material 701, such as silicon dioxide, is deposited simultaneously on the upper surface of the first chip 200 and the first filling portion 311 formed by planarization to form a dielectric layer 401 and a first filling layer 312. That is, the dielectric layer 401 and the first filling layer 312 are disposed on the same layer. It should be noted that the distinction between the dielectric layer 401 and the first filling layer 312 is based on their location: the dielectric layer 401 is located directly above the first chip 200, while the first filling layer 312 is located directly above the first filling portion 311. Because planarization produces a bowl-shaped defect 308 on the upper surface of the first filling portion 311, depositing the insulating dielectric material 701 on the first filling portion 311 also produces a bowl-shaped defect 308 at the location of the insulating dielectric material 701 corresponding to the bowl-shaped defect 308 on the first filling portion 311.

[0089] The inventors of this application have discovered that the bowl-shaped defect 308 is primarily caused by the generally uniform deposition process. However, due to the deposition of insulating dielectric material 701, the insulating dielectric material 701 slows down the bowl-shaped defect 308. Specifically, due to the uniform thickness of the deposited insulating dielectric material 701, the maximum depth of the bowl-shaped defect 308 remains unchanged. However, for the transition from the edge of the flat region to the edge of the bowl-shaped region, the insulating dielectric material 701 slows down this region, similar to how deposition on a right-angled surface turns the deposited surface into an arc. Therefore, within a certain error range, the diameter of the bowl-shaped defect 308 can be considered to have decreased. This diameter refers to the maximum size of the opening perpendicular to the depth direction of the bowl-shaped defect 308.

[0090] As shown in Figures 6E-6F , the step of forming dielectric layer 401 also includes forming patterns for wiring layer 402 through processes such as exposure, development, and etching. Figure 6E shows contact holes or through-holes 702 for electrically connecting wiring layer 402 to first chip 200, and annular grooves 601 for embedding support ring 600 in first filling layer 312. Figure 6F shows wiring grooves 703 for forming conductive connections in wiring layer 402.

[0091] As shown in FIG6G , to form the wiring layer 402 and the support ring 600, a conductive material 704, such as copper, is deposited on the pattern formed in the wiring layer 402 and the first filling layer 312. In some processes, to ensure that the conductive material is evenly applied to the predetermined surface, a seed layer is formed on the predetermined surface by sputtering before this process.

[0092] As shown in FIG6H , in order to remove excess conductive material 704, a planarization process, such as chemical and physical polishing, is then performed. Before the planarization process, the support ring 600 is embedded in the bowl-shaped defect 308, which changes the wear resistance of the entire bowl-shaped defect 308 area, making it closer to the area where the wiring layer 402 is located. This avoids the bowl-shaped defect on the insulating dielectric material 701 being aggravated by the poor wear resistance of the first filling layer 312. In addition, since the bowl-shaped defect 308 is reduced during the deposition of the insulating dielectric material 701, after the support ring 600 is set in the bowl-shaped defect 308, during the planarization process, the support ring 600 provides support and protects the bowl-shaped area around the support ring 600. As a result, the problem of the formation of holes 306 in the second filling portion caused by this defect can be alleviated or avoided.

[0093] The redistribution layer 400 may include a multi-layer dielectric layer 401 and a wiring layer 402 . The multi-layer dielectric layer 401 and the wiring layer 402 may be operated multiple times through the processes shown in FIG. 6B to FIG. 6F , with a support ring 600 provided in each operation.

[0094] The semiconductor package structure 1 provided in the embodiment of the present application is described below with reference to several specific examples.

[0095] Example 1

[0096] Returning to FIG. 3 , the semiconductor package structure 1 includes a substrate 100 and a filling portion 310 . The substrate 100 includes a substrate body 101 and a substrate interconnection layer 102 . The filling portion 310 includes a first filling portion 311 , a first filling layer 312 , and a second filling portion 313 .

[0097] The upper surface of the substrate 100 is in close contact with the lower surface of the filling part 310 , that is, the upper surface of the substrate 100 is in close contact with the lower surface of the first filling part 311 .

[0098] The first filling layer 312 is provided between the first filling portion 311 and the second filling portion 313, so that the filling portion 310 is continuous in a direction perpendicular to the substrate surface. The interior of the filling portion 310 forms an area for encapsulating the components to be encapsulated.

[0099] Figure 4 is a cross-sectional view taken along line A-A' of Figure 3. A first chip 200, a redistribution layer 400, and a second chip 500 are stacked on the upper surface of the substrate 100. The first chip 200 includes a first interconnect layer 202 and a first chip body 201, and the second chip includes a second interconnect layer 502 and a second chip body 501. The first chip 200 is bonded to the substrate interconnect layer 102 via the first interconnect layer 202. A redistribution layer 400 is formed above the first chip 200. The redistribution layer 400 is electrically connected to the first chip via conductive wires in through-holes running through the first chip body 201. The second chip 500 is bonded to the redistribution layer 400 via the second interconnect layer 502. It is understandable that redistribution layers and chips can continue to be stacked in sequence above the second chip 500 to achieve a higher level of integration.

[0100] The first filling portion 311 surrounds the side of the first chip 200 , the first filling layer 312 surrounds the side of the redistribution layer 400 , and the second filling portion 313 surrounds the side of the second chip 500 and covers the upper surface of the second chip 500 .

[0101] Referring to Figure 5 , a support ring 600 is embedded in the first filling layer 312. The first reference plane is the plane where the surface of the second chip 500 near the first chip 200 lies. The support ring 600 is located on the side of the first reference plane that is closest to the substrate 100. In this case, the upper surface of the support ring 600 does not exceed the lower surface of the second chip 500, thereby avoiding any adverse effects when setting the second filling portion 313.

[0102] In some embodiments, the support ring 600 penetrates the first filling layer 312 in a direction perpendicular to the substrate, that is, the lower surface of the support ring 600 contacts the first filling portion 311 , and the upper surface contacts the second filling portion 313 .

[0103] Please continue to refer to Figure 7A, which is a cross-sectional view taken along line BB' in Figure 3. The orthographic projection of the support ring 600 on the substrate 100 surrounds the orthographic projection of the first chip 200, and the orthographic projection of the support ring 600 is spaced apart from the orthographic projection of the first chip 200. In some embodiments, a sealing ring 203 is provided on the first chip 200, and the shape of the support ring 600 is the same as that of the sealing ring 203, that is, the support ring 600 is a proportionally enlarged shape of the sealing ring 203. For example, the distance from any point on the inner side of the orthographic projection of the support ring 600 on the substrate 100 to the orthographic projection of the sealing ring 203 on the substrate 100 is equal.

[0104] Regarding the packaging method of the semiconductor package structure 1 in this example, in some embodiments, a first chip 200 is placed on a substrate 100 and bonded to the substrate 100. A filling material 301 is filled around the first chip 200, and the filling material 301 and the upper surface of the first chip 200 are planarized.

[0105] After the planarization process, as shown in FIG. 8A , a redistribution layer 400 , a first filling layer 312 and a support ring 600 are provided.

[0106] As shown in FIG. 8B , a second chip 500 is stacked on the redistribution layer 400 .

[0107] 8C , the second chip 500 is further filled with the filling material 301 . The filling material 301 is also located above the first filling layer 312 to form a second filling portion 313 . This completes the main steps of manufacturing the semiconductor package structure 1 .

[0108] Since the support ring 600 is provided in the first filling layer 312 , when the planarization process is performed after the sputtering process is completed, the wear resistance of the area where the first filling layer 312 is located is improved, which helps to improve or avoid the bowl-shaped defect.

[0109] Example 2

[0110] Example 2 differs from Example 1 in the process of forming the redistribution layer 400 , the first filling layer 312 , and the support ring 600 .

[0111] Continuing with Figure 5 , the redistribution layer 400 includes a dielectric layer 401 and a wiring layer 402. The first filling layer 312 is co-located with the dielectric layer 401, and the wiring layer 402 is co-located with the support ring 600. It should be emphasized that the term "co-located" does not necessarily refer to height, but rather refers to simultaneous formation through the same process. Therefore, the first filling layer 312 and the dielectric layer 401 are made of the same material.

[0112] Specifically, an insulating dielectric material 701 is deposited on the planarized upper surface, and a photolithography process is performed on the insulating dielectric material 701 to form a dielectric layer 401, contact holes or through-holes 702, and wiring grooves 703 for forming the wiring layer 402 in the area directly above the first chip. A first filling layer 312 and an annular groove 601 for accommodating the support ring 600 are formed in the area directly above the first filling portion 311. Thus, the dielectric layer 401 and the first filling layer 312 are arranged on the same layer. This arrangement avoids the need for additional process steps and saves costs.

[0113] Then, a conductive material is deposited in the contact holes or through-holes 702, the wiring grooves 703, and the annular groove 601 that accommodates the support ring 600 through a sputtering process, and then planarization is performed again, thereby forming the wiring layer 402 and the support ring 600 through the same layer arrangement. For a complex redistribution layer 400, multiple photolithography processes, sputtering processes, and planarization processes can be performed to form a multi-layer dielectric layer 401, a wiring layer 402, a first filling layer 312, and the support ring 600. As can be easily understood, after planarization, the support ring 600 is embedded in the first filling layer 312. In the above preparation process, because the conductive material is deposited in the contact holes or through-holes 702, the wiring grooves 703, and the annular groove 601 that accommodates the support ring 600 through the same sputtering process, the support ring 600 and the wiring layer 402 are made of the same material.

[0114] Example 3

[0115] Example 3 differs from Examples 1 and 2 in the timing of setting the redistribution layer 400. In this example, the redistribution layer 400 can be formed on the first chip 200 before the first chip 200 is bonded to the substrate. For example, the redistribution layer 400 can be formed on the first chip body 201 of the first chip 200 through a front-end process, or can be formed on the first chip 200 through an RDL (Redistribution Layer) process after the front-end process is completed and the substrate is cut to form the first chip 200.

[0116] After the first chip 200 is bonded to the substrate 100, the first chip 200 is filled with a filling material 301, and then a support ring 600 is provided on the first filling portion 311 formed by the filling material 301. The support ring 600 can also be provided by sputtering after photolithography.

[0117] To prevent the filling material from blocking the bonding contacts on the redistribution layer 400 and facilitate the stacking of the second chip 500, the redistribution layer 400 and the filling material 301 also need to be planarized. Similarly, during the planarization process, the support ring 600 is provided on the upper portion of the first filling portion 311 to improve the wear resistance of the area where the first filling layer 312 is located, helping to reduce or avoid concave areas.

[0118] It can be seen from this that in this example, the material of the support ring 600 can be selected based on the specific differences between the filling material 301 and the support ring 600, so that the wear resistance of the surface jointly formed by the support ring 600 and the filling material 301 is consistent with the wear resistance of the redistribution layer 400 on the first chip 200, thereby avoiding the bowl-shaped defect 308 as much as possible.

[0119] After planarization, the second chip 500 is stacked on the redistribution layer 400 and then directly filled with a filling material around the second chip 500 to form a second filling portion 313. Therefore, the first filling portion 311 and the second filling portion 313 are arranged immediately adjacent to each other, that is, the first filling portion 311 and the second filling portion 313 are continuous in a direction perpendicular to the substrate 100. In this case, the filling portion 310 only includes the first filling portion 311 and the second filling portion 313.

[0120] Example 4

[0121] The fourth example differs from the first to third examples in the number of support rings 600. In the third example, there are multiple support rings 600. In this example, two support rings 600 are used for illustration.

[0122] In some embodiments, Fig. 7B is another cross-sectional view along line BB' in Fig. 3. As shown in Fig. 7B, the support ring 600 includes a support ring 600a and a second support ring 600b.

[0123] Multiple support rings 600 are arranged radially from the inside to the outside. Specifically, the size of the support ring 600a is smaller than the second support ring 600b. The support ring 600a is arranged inside the second support ring 600b, and the outer wall of the support ring 600a is arranged at a certain distance from the inner wall of the second support ring 600b.

[0124] In this example, by setting up multiple support rings 600, the wear resistance of the area where the first filling layer 312 or the first filling part 311 is located can be improved during the flattening process, and the wear resistance of the area will not change significantly within the area, thereby improving the uniformity of the wear resistance within the area, which helps to further alleviate or avoid concave areas.

[0125] In some embodiments, the cross-section of the second support ring 600b has a width c2 in a direction parallel to the substrate 100, and the cross-section of the support ring 600a has a width c1 in a direction parallel to the substrate 100, where c2 is greater than c1. For the singulated semiconductor package structure 1, the bowl-shaped defect becomes more concave the further away from the edge of the first chip 200 in a direction parallel to the substrate 100. Therefore, increasing the width of the support ring 600 as it becomes farther from the edge of the first chip 200 can increase the wear resistance of the area in which it is located and better compensate for the bowl-shaped concave defect.

[0126] The embodiment of the present application further provides a packaging method for a semiconductor packaging structure 1 . As shown in FIG. 9 , the packaging method for the semiconductor packaging structure 1 includes: S10 - S50 .

[0127] S10 , as shown in FIG. 1A , bonding the first chip 200 to the substrate 100 .

[0128] In some embodiments, the substrate 100 includes a substrate body 101 and a substrate interconnect layer 102, with bonding contacts provided on the substrate interconnect layer 102. The first chip 200 includes a first chip body 201 and a first interconnect layer 202, with bonding contacts also provided on the first interconnect layer 202. The first interconnect layer 202 is placed on the substrate interconnect layer 102 so that the bonding contacts of the two are aligned one-to-one and bonded.

[0129] For example, as shown in FIG2A , multiple first chips 200 can be bonded to the same substrate 100, and the gaps between the multiple chips can be used as scribe lines to facilitate singulation after subsequent packaging. In some embodiments, a single first chip 200 can be bonded to a substrate 100, and a filler material can be filled around the first chip 200 to cover the surface of the substrate 100. Therefore, after the stacked package forms the semiconductor package structure 1, the singulation operation does not need to be performed. However, in order to remove surface defects such as burrs on the semiconductor package structure 1, the surface of the formed semiconductor package structure 1 can be polished.

[0130] Here, the bonding may be eutectic bonding, metal thermal compression bonding, hybrid bonding, or the like.

[0131] S20 , as shown in FIG. 2B , use a filling material 301 to surround and fill the first chip 200 .

[0132] After the filling material 301 surrounds the first chip 200, the bottom of the filling material 301 contacts the substrate 100, fills the gaps between the multiple first chips 200, and contacts the first chip 200 from the side, thereby surrounding the side of the first chip 200. For example, in the direction perpendicular to the substrate 100, the height of the filling material 301 can be flush with the upper surface of the first chip 200.

[0133] The height of the filling material 301 may be higher than the upper surface of the first chip 200, or even cover the upper surface of the first chip 200. Therefore, a planarization process is required to expose the upper surface of the first chip 200. The planarization process may be performed by chemical mechanical polishing, etching, or other suitable processes.

[0134] At this point, the filling material 301 only includes the portion surrounding the side edges of the first chip, thus forming a first filling portion 311. Ideally, after planarization, the upper portion of the first chip 200 and the upper surface of the first filling portion 311 are flush and coplanar. However, due to differences in wear resistance or corrosion resistance between the filling material 301 and the upper surface of the first chip 200, a bowl-shaped depression 308 forms on the upper surface of the first filling portion 311 formed after planarization of the filling material 301, as shown in FIG6C . This bowl-shaped depression 308 can adversely affect the package and should be avoided as much as possible.

[0135] S30 , as shown in FIG. 6D to FIG. 6G , a redistribution layer 400 , a first filling layer 312 surrounding the redistribution layer 400 , and a support ring 600 embedded in the first filling layer 312 are formed on a surface of the first chip 200 away from the substrate 100 .

[0136] Specifically, as shown in FIG6D , an insulating dielectric material 701 is deposited on the surface formed by the first chip 200 and the first filling portion 311. The insulating dielectric material 701 is typically silicon nitride, silicon dioxide, or the like. Chemical vapor deposition (CVD) is typically used to deposit the insulating dielectric material 701, and it can be assumed that the insulating dielectric material 701 is uniformly deposited on the upper surfaces of the first chip 200 and the first filling portion 311. Due to the deposition of the insulating dielectric material 701, the insulating dielectric material 701 mitigates the bowl-shaped defect 308.

[0137] As shown in Figures 6E-6F , a photolithography process is performed on the insulating dielectric material 701 to form a dielectric layer 401 above the first chip 200, which is provided with contact holes or through-holes 702 and wiring grooves 703. A first filling layer 312 is formed above the first filling portion 311, which is provided with the support ring 600. It can be understood that the dielectric layer 401 and the first filling layer 312 are formed simultaneously using the same process, i.e., provided on the same layer. The dielectric layer 401 and the first filling layer 312 are distinguished based on their respective locations.

[0138] As shown in Figures 6G-6H, conductive material 704 is deposited in the contact holes or through-holes 702, wiring grooves 703, and annular grooves 601 formed by processes such as photolithography and etching, thereby forming the wiring layer 402 and support ring 600 of the redistribution layer 400. Conductive material 704 is typically deposited using physical vapor deposition (PVD), but CVD can also be used. Conductive material 704 is typically copper. Before depositing conductive material 704, an isolation layer and seed layer are also required to prevent the conductive material from diffusing into the insulating dielectric material and affecting its insulation properties.

[0139] Similarly, to ensure the conductivity of the wiring layer 402, the contact holes or through-holes 702, the wiring grooves 703, and the annular groove 601 must be completely filled during the deposition of the conductive material 704. Consequently, the conductive material 704 may overflow from the contact holes or through-holes 702, the wiring grooves 703, and the annular groove 601, necessitating a planarization process to remove the overflowed conductive material 704. Thus, the conductive material 704 above the first chip 200 forms the wiring layer 402, and the conductive material 704 above the first filling portion 311 forms the support ring 600.

[0140] Since the support ring 600 formed of a conductive material is added to the first filling layer 312, the wear resistance or corrosion resistance of the area where the first filling layer 312 is located is improved, and the support ring 600 provides support. Therefore, when the conductive material 704 is removed by planarization, the planarization rate of the area where the first filling layer 312 is located is slowed down, thereby improving the bowl-shaped depression in this area.

[0141] In some embodiments, the redistribution layer 400 comprises multiple dielectric layers 401 and wiring layers 402. In this case, the first filling layer 312 also comprises multiple layers. The layers in which the support ring 600 is formed can be selected based on the degree of bowl-shaped defects. For example, referring to FIG. 6I , the dielectric layer 401 and the wiring layer 402 comprise two layers, but the support ring 600 is only present in the layer away from the first chip 200. This is achieved by not forming an annular groove 601 corresponding to the support ring 600 in the insulating dielectric material during photolithography, etching, or other processes on the layer closer to the first chip 200. Consequently, when the conductive material 704 is deposited, the portion of the support ring 600 corresponding to the layer is not formed in the annular groove 601. Thus, it can be achieved that in some embodiments, the support ring 600 is located on one side of the plane where the surface of the first chip 200 close to the second chip 500 is located, that is, the setting position of the support ring 600 is not lower than the upper surface of the first chip 200, or in other words, at this time, the support ring 600 is located between the first chip 200 and the second chip 500.

[0142] It can be understood that in order to achieve electrical connection between the redistribution layer 400 and the second chip 500 , bonding contacts are further provided on the redistribution layer 400 .

[0143] Thus, the formed support ring 600 is located at the periphery of the redistribution layer 400 , and the first filling layer 312 is in contact with the first filling portion 311 . The orthographic projection of the support ring 600 on the substrate 100 surrounds the orthographic projection of the first chip 200 on the substrate 100 .

[0144] S40 , as shown in FIG. 8B , bonding the first surface of the second chip 500 to the redistribution layer 400 .

[0145] Bonding the first surface of the second chip 500 to the redistribution layer 400 is similar to bonding the first chip 200 to the substrate 100 , and thus will not be further described herein.

[0146] Since the second chip 500 is bonded to the redistribution layer 400 after the redistribution layer 400 and the first filling layer 312 are planarized, it can be seen that if the plane where the lower surface of the second chip 500 is located is the first reference plane, the support ring 600 is located on the side of the first reference plane close to the substrate 100.

[0147] S50 , as shown in FIG. 8C , a filling material 301 is used to fill the side surface of the second chip 500 to form a second filling portion 313 surrounding the second chip 500 .

[0148] The lower surface of the filled filling material 301 contacts the redistribution layer 400 and surrounds the side surfaces of the second chip 500. It is understood that when only two chips are stacked, the filling material 301 can cover the upper surface of the second chip 500, isolating the semiconductor package structure 1 from the external environment, thereby providing a stable environment for the first chip 200 and the second chip 500 within the semiconductor package structure 1 and improving the service life of the semiconductor package structure 1.

[0149] Furthermore, the support ring 600 is provided when forming the redistribution layer 400 and the first filling layer 312, thereby improving the bowl-shaped defect on the first filling layer 312, thereby preventing the formation of holes 306 in the second filling portion 313, and improving the stability of the semiconductor package structure 1. In some embodiments, multiple first chips 200 and multiple second chips 500 are stacked and packaged on a single substrate 100. Since the support ring 600 is provided around the redistribution layer 400, the integrity of the redistribution layer 400 can be ensured when the semiconductor package structure 1 is singulated, thereby improving the yield rate.

[0150] The present application also provides an electronic device 20, which is a type of electronic device having functions such as data storage and / or program execution, and includes any of the above-mentioned semiconductor package structures 1. Specifically, the electronic device includes but is not limited to a mobile phone, a tablet personal computer, a laptop computer, a personal digital assistant (PDA), a personal computer, a notebook computer, an in-vehicle device, a wearable device, etc. Among them, the wearable device includes but is not limited to a smart bracelet, a smart watch, a smart head-mounted display, smart glasses, etc.

[0151] This application uses a laptop computer as an example for explanation. FIG10 shows a schematic diagram of the laptop computer's structure. The laptop computer's core components include a motherboard 10, which is responsible for connecting various hardware devices and providing power and data transmission. The motherboard contains many different components, including a processor chip 11, memory chips 12, a power outlet 13, a USB port 14, and an IDE serial port 15. The motherboard is a printed circuit board (PCB). Its primary function is to transmit electrical signals between components on the motherboard. Electrical signals from various chips are transmitted frequently, particularly from the processor chip 11. Chips can be categorized by function and include processor chips, memory chips, and power chips. The method by which chips are attached to the motherboard varies depending on the specific application scenario. For example, to improve the laptop's scalability, chips can be attached to the motherboard via a slot; to ensure a high-quality electrical connection, chips can be attached to the motherboard via soldering. For example, the processor chip 11 is typically attached to the motherboard 10 via soldering, while the memory chip is typically attached via a slot.

[0152] In some embodiments, the semiconductor packaging structure 1 may be a memory chip 12 of a laptop computer. The memory chip 12 stacks and packages multiple single memory chips. The memory chip 12 is mounted on a computer motherboard and connected to a power supply, input and output devices, etc. through the printed circuit board.

[0153] In other embodiments, the semiconductor package structure 1 may include a processor chip and a memory chip. The processor chip and the memory chip are stacked and packaged to form a semiconductor package structure 1, which is then installed on a computer motherboard and electrically connected to other components on the computer motherboard.

[0154] The above are only specific embodiments of the present application, but the scope of protection of the application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A semiconductor packaging structure, characterized in that: include: A substrate, and a first chip and a second chip stacked on the substrate, wherein the first chip is located between the substrate and the second chip; a filling portion, surrounding the side surfaces of the first chip and the second chip and being continuous in a direction perpendicular to the substrate; A support ring, wherein the orthographic projection of the support ring on the substrate surrounds the orthographic projection of the first chip on the substrate, the support ring is embedded in the filling portion, and is located on a side of a first reference plane close to the substrate, and the first reference plane is a plane where a surface of the second chip close to the first chip is located.

2. The semiconductor package structure according to claim 1, wherein: The support ring is located between the first reference plane and the second reference plane, and the second reference plane is a plane where the surface of the first chip close to the second chip is located.

3. The semiconductor packaging structure according to any one of claims 1 to 2, characterized in that: A redistribution layer is arranged on a surface of the first chip away from the substrate, and the redistribution layer includes a dielectric layer; the filling part includes a first filling layer, and the first filling layer surrounds at least a part of the area between the first chip and the second chip; the material of the first filling layer is the same as that of the dielectric layer, and the support ring is embedded in the first filling layer.

4. The semiconductor package structure according to claim 3, characterized in that: The first filling layer is arranged on the same layer as the dielectric layer.

5. The semiconductor package structure according to claim 3, characterized in that: The redistribution layer further comprises a plurality of wiring layers, which are stacked and arranged in a direction perpendicular to the substrate; the wiring layers are embedded in the dielectric layer, and the material of the support ring is the same as that of the wiring layers.

6. The semiconductor package structure according to claim 5, characterized in that: The support ring is arranged in the same layer as at least one of the wiring layers which is farthest from the substrate.

7. The semiconductor package structure according to claim 5, characterized in that: A surface of the support ring facing away from the substrate is flush with a surface of the wiring layer farthest from the substrate facing away from the substrate.

8. The semiconductor package structure according to claim 3, wherein: The support ring penetrates the first filling layer in a direction perpendicular to the substrate.

9. The semiconductor packaging structure according to any one of claims 3 to 8, characterized in that: The filling part further includes a first filling part, which is located between the first filling layer and the substrate and surrounds a side surface of the first chip; and a material of the first filling layer is different from that of the first filling part.

10. The semiconductor package structure according to claim 9, characterized in that: The filling portion further includes a second filling portion disposed on a side of the first filling layer away from the substrate, the second filling portion surrounding a side surface of the second chip; and a material of the first filling layer is different from that of the second filling portion.

11. The semiconductor package structure according to any one of claims 1 to 10, characterized in that: The number of the support rings is multiple and they are arranged radially from inside to outside in a direction parallel to the substrate.

12. The semiconductor package structure according to claim 11, characterized in that: Among the adjacent support rings, the width of the support ring located on the inner side is greater than the width of the support ring located on the outer side, and the width is the dimension in a direction parallel to the substrate.

13. A packaging method for a semiconductor packaging structure, characterized in that: include: bonding the first chip to the substrate; Filling the first chip with a filling material to form a first filling portion surrounding a side surface of the first chip; forming a redistribution layer, a first filling layer surrounding the redistribution layer, and a support ring located in the first filling layer on a surface of the first chip away from the substrate, wherein the first filling layer is in contact with the first filling portion, and the orthographic projection of the support ring on the substrate surrounds the orthographic projection of the first chip on the substrate; bonding a second chip to the redistribution layer; The second chip is filled with a filling material around its side surface to form a second filling portion surrounding the second chip, wherein the second filling portion is in contact with the first filling layer.

14. The method according to claim 13, characterized in that The redistribution layer includes a dielectric layer and a wiring layer, and the first filling layer and the dielectric layer are formed simultaneously.

15. The method according to claim 14, characterized in that The support ring is formed simultaneously with at least a portion of the wiring layer.

16. An electronic device, characterized in that: The invention comprises a semiconductor package structure and a printed circuit board according to any one of claims 1 to 12, wherein the semiconductor package structure is combined with the printed circuit board.

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