Input buffer, analog-to-digital converter, and receiver

Abstract

Provided in the present disclosure is an input buffer, comprising: a first current mirror module, a first source follower module, a first common gate amplification module, a first tail current source module and a first coupling capacitor. The first current mirror module is connected to a first common level end, a first node and a second node, and is configured to allocate current proportions of the first source follower module and the first common gate amplification module; the first source follower module is connected to the second node, a first input end and a first output end; the first common gate amplification module is connected to the first node, the first output end and a first bias voltage end; the first tail current source module is connected to a second common level end, a second bias voltage end and the first output end, and is configured to provide current bias for the first source follower module and the first common gate amplification module; and the first coupling capacitor is connected to the first input end and the first node. Further provided in the present disclosure are an analog-to-digital converter and a receiver.

Description

Input buffer, analog-to-digital converter, receiver

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202311128877.4 filed with the China Patent Office on August 31, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to, but is not limited to, the technical field of communication equipment. Background Art

[0004] With the rapid development of high-speed communication technology, the throughput of communication equipment is increasing, and the speed requirements for the serializer and deserializer (SerDes) systems of the receiver are also increasing. To support the increase in speed, the use of advanced integrated circuit processes is inevitable.

[0005] However, advanced processes generally use low power supply voltage designs, which do not match the power supply voltage requirements of the input buffers of high-speed analog-to-digital converters.

[0006] Summary of the Invention

[0007] Embodiments of the present disclosure provide an input buffer, an analog-to-digital converter, and a receiver.

[0008] In the first aspect, an embodiment of the present disclosure provides an input buffer, comprising: a first current mirror module, a first source follower module, a first common-gate amplifier module, a first tail current source module, and a first coupling capacitor; the first current mirror module is connected to the first common level terminal, the first node, and the second node, and is configured to distribute the current ratio of the first source follower module and the first common-gate amplifier module; the first source follower module is connected to the second node, the first input terminal, and the first output terminal; the first common-gate amplifier module is connected to the first node, the first output terminal, and the first bias voltage terminal; the first tail current source module is connected to the second common level terminal, the second bias voltage terminal, and the first output terminal, and is configured to provide current bias for the first source follower module and the first common-gate amplifier module; the first coupling capacitor is connected to the first input terminal and the first node.

[0009] In a second aspect, an embodiment of the present disclosure provides an analog-to-digital converter, comprising the input buffer described in the first aspect of the embodiment of the present disclosure.

[0010] In a third aspect, an embodiment of the present disclosure provides a receiver, comprising the analog-to-digital converter described in the second aspect of the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG1 is a schematic diagram of a common-gate amplifier structure;

[0012] FIG2 is a schematic diagram of an input buffer according to an embodiment of the present disclosure;

[0013] FIG3 is a schematic diagram of another input buffer according to an embodiment of the present disclosure;

[0014] FIG4 is a schematic diagram of another input buffer according to an embodiment of the present disclosure;

[0015] FIG5 is a schematic diagram of another input buffer according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] To enable those skilled in the art to better understand the technical solution of the present disclosure, the input buffer, analog-to-digital converter, and receiver provided by the present disclosure are described in detail below with reference to the accompanying drawings.

[0017] Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art.

[0018] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0019] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0020] The terms used herein are used only to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements, and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof is not excluded.

[0021] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined as such herein.

[0022] Using a common-gate amplifier structure to compensate for the insertion loss of the source-follower structure is an economical and effective solution. This solution places the common-gate amplifier tube below the source follower, and the two are in the same branch. As shown in Figure 1, the gate of the source follower tube M11 is connected to the input terminal V in Connect the first pole to the output terminal V out Connect the second pole to the power supply terminal V DD Connect the gate of the common gate amplifier tube M12 to the bias voltage terminal V G Connect, the first pole is grounded, the second pole is connected to the output terminal V out Connection, capacitor C L One pole and the output terminal V out Connect, the other pole is grounded, the resistor R s One end and the input terminal V s Connect the other end to the input terminal V in Connection, capacitor C R One terminal and the input terminal V in Connect, the other pole is grounded, I B , I CR , I ZL represents the current. Common-gate amplifier M12 is placed below source-follower M11. M12 compensates for the high-frequency insertion loss of M11, thereby extending the bandwidth. To ensure proper operation of this structure, the source-follower M11, common-gate amplifier M12, and the MOS transistor serving as the micro-current source must all operate in the saturation region. This requires a sufficiently high input voltage to ensure sufficient voltage margin, which is difficult to achieve in low-voltage designs.

[0023] In view of this, in a first aspect, referring to Figures 2 to 5, an embodiment of the present disclosure provides an input buffer, comprising: a first current mirror module 101, a first source follower module 102, a first common gate amplifier module 103, a first tail current source module 104, and a first coupling capacitor C1; the first current mirror module 101 is connected to the first common level terminal, the first node Q1, and the second node Q2, and is configured to distribute the current ratio of the first source follower module 102 to the first common gate amplifier module 103; the first source follower module 102 is connected to the second node Q2, the first input terminal V in,p , the first output terminal V out,p Connection; the first common gate amplifier module 103 and the first node Q1, the first output terminal V out,p , the first bias voltage terminal V bcg Connection; the first tail current source module 104 and the second common level terminal, the second bias voltage terminal V b , the first output terminal V out,p connected to provide current bias for the first source follower module 102 and the first common gate amplifier module 103; the first coupling capacitor C1 is connected to the first input terminal V in,p, the first node Q1 is connected.

[0024] In the embodiment of the present disclosure, the input signal Vinp is generated by the first input terminal V in,p After the input, it is divided into two paths, one of which passes through the first source follower module 102 and is output to the first output terminal V out,p The other path is coupled to the first common-gate amplifier module 103 through the first coupling capacitor C1 and output to the first output terminal V out,p The output signal Voutp is the sum of the outputs of the first source follower module 102 and the first common gate amplifier module 103. The outputs of the first source follower module 102 and the first common gate amplifier module 103 are output through the first output terminal V out,p Superimposed output.

[0025] The embodiment of the present disclosure arranges the first source follower module 102 and the first common-gate amplifier module 103 in two branches respectively to form a parallel relationship, thereby reducing the input and output voltages, thereby being applicable to low-voltage input designs, and facilitating the implementation of advanced integrated circuit technology.

[0026] In the disclosed embodiment, the source-follower structure and the common-gate amplifier structure are each implemented using two branches. Adjusting the common-gate amplifier's ability to compensate for the buffer circuit's bandwidth not only allows for adjusting the size of common-gate transistor M12 but also the magnitude and ratio of the current mirror current, increasing design freedom and flexibility.

[0027] In some embodiments, the input buffer is a fully differential structure.

[0028] Accordingly, in some embodiments, referring to FIG3 , the input buffer further includes: a second current mirror module 201, a second source follower module 202, a second common gate amplifier module 203, a second tail current source module 204, and a second coupling capacitor C2; the second current mirror module 201 is connected to the first common level terminal, the third node Q3, and the fourth node Q4, and is configured to distribute the current ratio of the second source follower module 202 to the second common gate amplifier module 203; the second source follower module 202 is connected to the fourth node Q4, the second input terminal V in,n , the second output terminal V out,n The second common gate amplifier module 203 is connected to the third node Q3 and the second output terminal V out,n , the first bias voltage terminal V bcg The second tail current source module 204 is connected to the second common level terminal and the second bias voltage terminal V b , the second output terminal V out,n connected to provide a current bias for the second source follower module 202 and the second common gate amplifier module 203; the second coupling capacitor C2 is connected to the second input terminal V in,n , the third node Q3 is connected.

[0029] In the embodiment of the present disclosure, the input signal Vinn is input from the second input terminal V in,n After the input, it is divided into two paths, one of which passes through the second source follower module 202 and is output to the second output terminal V out,n The other path is coupled to the second common-gate amplifier module 203 through the second coupling capacitor C2 and output to the second output terminal V out,n The output signal Voutn is the sum of the outputs of the second source follower module 202 and the second common gate amplifier module 203. The outputs of the second source follower module 202 and the second common gate amplifier module 203 are output through the second output terminal V out,n Superimposed output.

[0030] Accordingly, in some embodiments, the first input terminal V in,p With the second input terminal V in,n Differential input, the first output terminal V out,p With the second output terminal V out,n They are differential outputs.

[0031] In some embodiments, referring to Figures 4 and 5, the first current mirror module 101 includes a first transistor M1 and a second transistor M2; the gate of the first transistor M1 is connected to the second node Q2, the first electrode is connected to the first common level end, and the second electrode is connected to the second node Q2; the gate of the second transistor M2 is connected to the second node Q2, the first electrode is connected to the first common level end, and the second electrode is connected to the first node Q1.

[0032] In some embodiments, the first source follower module 102 includes a third transistor M3; the gate of the third transistor M3 is connected to the first input terminal V in,p , the first electrode is connected to the first output terminal V out,p , the second electrode is connected to the second node Q2.

[0033] In some embodiments, the first common-gate amplifier module 103 includes a fourth transistor M4; the gate of the fourth transistor M4 is connected to the first bias voltage terminal V bcg The first electrode is connected to the first node Q1, and the second electrode is connected to the first output terminal V out,p .

[0034] In some embodiments, the first tail current source module 104 includes a fifth transistor M5; the gate of the fifth transistor M5 is connected to the second bias voltage terminal V b , the first electrode is connected to the second common level terminal, and the second electrode is connected to the first output terminal V out,p .

[0035] In some embodiments, referring to Figures 4 and 5, the second current mirror module 201 includes a sixth transistor M6 and a seventh transistor M7; the gate of the sixth transistor M6 is connected to the fourth node Q4, the first electrode is connected to the first common level end, and the second electrode is connected to the fourth node Q4; the gate of the seventh transistor M7 is connected to the fourth node Q4, the first electrode is connected to the first common level end, and the second electrode is connected to the third node Q3.

[0036] In some embodiments, the second source follower module 202 includes an eighth transistor M8; the gate of the eighth transistor M8 is connected to the second input terminal V in,n , the first electrode is connected to the second output terminal V out,n , and the second electrode is connected to the fourth node Q4.

[0037] In some embodiments, the second common-gate amplifier module 203 includes a ninth transistor M9; the gate of the ninth transistor M9 is connected to the first bias voltage terminal V bcg The first electrode is connected to the third node Q3, and the second electrode is connected to the second output terminal V out,n .

[0038] In some embodiments, the second tail current source module 204 includes a tenth transistor M10; the gate of the tenth transistor M10 is connected to the second bias voltage terminal V b , the first electrode is connected to the second common level terminal, and the second electrode is connected to the second output terminal V out,n .

[0039] In some embodiments, referring to Figure 4, the first common level terminal is the power supply voltage terminal VDD, the second common level terminal is the ground terminal, the first transistor M1, the second transistor M2, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, and the ninth transistor M9 are N-type transistors; the third transistor M3, the fifth transistor M5, the eighth transistor M8, and the tenth transistor M10 are P-type transistors.

[0040] In some embodiments, referring to Figure 5, the first common level terminal is the ground terminal, the second common level terminal is the power supply voltage terminal VDD, the first transistor M1, the second transistor M2, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, and the ninth transistor M9 are P-type transistors; the third transistor M3, the fifth transistor M5, the eighth transistor M8, and the tenth transistor M10 are N-type transistors.

[0041] In a second aspect, an embodiment of the present disclosure provides an analog-to-digital converter, comprising the input buffer described in the first aspect of the embodiment of the present disclosure.

[0042] In a third aspect, an embodiment of the present disclosure provides a receiver, comprising the analog-to-digital converter described in the second aspect of the embodiment of the present disclosure.

[0043] In some embodiments, the receiver is a high-speed SerDes receiver.

[0044] In the disclosed embodiment, an input signal is input from a first input terminal and is divided into two paths. One path passes through a first source follower module and is output to a first output terminal, and the other path passes through a first coupling capacitor and is coupled to a first common-gate amplifier module and is output to the first output terminal. The output signal is the sum of the outputs of the first source follower module and the first common-gate amplifier module. The outputs of the first source follower module and the first common-gate amplifier module are superimposed and output through the first output terminal. By placing the first source follower module and the first common-gate amplifier module in two branches, respectively, to form a parallel relationship, the disclosed embodiment can reduce the input and output voltages, thereby enabling application in low-voltage input designs and facilitating the implementation of advanced integrated circuit processes.

[0045] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. An input buffer, comprising: A first current mirror module, a first source follower module, a first common gate amplifier module, a first tail current source module, and a first coupling capacitor; The first current mirror module is connected to the first common level terminal, the first node, and the second node, and is configured to distribute the current ratio of the first source follower module and the first common gate amplifier module; The first source follower module is connected to the second node, the first input terminal, and the first output terminal; The first common-gate amplification module is connected to the first node, the first output terminal, and the first bias voltage terminal; The first tail current source module is connected to the second common level terminal, the second bias voltage terminal, and the first output terminal, and is configured to provide current bias for the first source follower module and the first common gate amplifier module; The first coupling capacitor is connected to the first input terminal and the first node.

2. The input buffer according to claim 1, wherein The input buffer further includes: a second current mirror module, a second source follower module, a second common gate amplifier module, a second tail current source module, and a second coupling capacitor; The second current mirror module is connected to the first common level terminal, the third node, and the fourth node, and is configured to distribute the current ratio of the second source follower module and the second common gate amplifier module; The second source follower module is connected to the fourth node, the second input terminal, and the second output terminal; The second common-gate amplification module is connected to the third node, the second output terminal, and the first bias voltage terminal; The second tail current source module is connected to the second common level terminal, the second bias voltage terminal, and the second output terminal, and is configured to provide current bias for the second source follower module and the second common gate amplifier module; The second coupling capacitor is connected to the second input terminal and the third node.

3. The input buffer according to claim 2, wherein: The first input terminal and the second input terminal are differential inputs to each other, and the first output terminal and the second output terminal are differential outputs to each other.

4. The input buffer according to claim 1 or 2, wherein: The first current mirror module includes a first transistor and a second transistor; The gate of the first transistor is connected to the second node, the first electrode is connected to the first common level terminal, and the second electrode is connected to the second node; The second transistor has a gate connected to the second node, a first electrode connected to the first common level terminal, and a second electrode connected to the first node.

5. The input buffer according to claim 4, wherein: The first source follower module includes a third transistor; The third transistor has a gate connected to the first input terminal, a first electrode connected to the first output terminal, and a second electrode connected to the second node.

6. The input buffer according to claim 5, wherein: The first common-gate amplification module includes a fourth transistor; The fourth transistor has a gate connected to the first bias voltage terminal, a first electrode connected to the first node, and a second electrode connected to the first output terminal.

7. The input buffer according to claim 6, wherein: The first tail current source module includes a fifth transistor; The gate of the fifth transistor is connected to the second bias voltage terminal, the first electrode is connected to the second common level terminal, and the second electrode is connected to the first output terminal.

8. The input buffer according to claim 7, wherein: The second current mirror module includes a sixth transistor and a seventh transistor; The gate of the sixth transistor is connected to the fourth node, the first electrode is connected to the first common level terminal, and the second electrode is connected to the fourth node; The gate of the seventh transistor is connected to the fourth node, the first electrode is connected to the first common level end, and the second electrode is connected to the third node.

9. The input buffer according to claim 8, wherein: The second source follower module includes an eighth transistor; The gate of the eighth transistor is connected to the second input terminal, the first electrode is connected to the second output terminal, and the second electrode is connected to the fourth node.

10. The input buffer according to claim 9, wherein: The second common-gate amplification module includes a ninth transistor; The gate of the ninth transistor is connected to the first bias voltage terminal, the first electrode is connected to the third node, and the second electrode is connected to the second output terminal.

11. The input buffer according to claim 10, wherein: The second tail current source module includes a tenth transistor; The gate of the tenth transistor is connected to the second bias voltage terminal, the first electrode is connected to the second common level terminal, and the second electrode is connected to the second output terminal.

12. The input buffer according to claim 11, wherein The first common level terminal is a power supply voltage terminal, the second common level terminal is a ground terminal, the first transistor, the second transistor, the fourth transistor, the sixth transistor, the seventh transistor, and the ninth transistor are N-type transistors; the third transistor, the fifth transistor, the eighth transistor, and the tenth transistor are P-type transistors.

13. The input buffer according to claim 11, wherein: The first common level terminal is a ground terminal, the second common level terminal is a power supply voltage terminal, the first transistor, the second transistor, the fourth transistor, the sixth transistor, the seventh transistor, and the ninth transistor are P-type transistors; the third transistor, the fifth transistor, the eighth transistor, and the tenth transistor are N-type transistors.

14. An analog-to-digital converter comprising an input buffer according to any one of claims 1 to 13.

15. A receiver comprising the analog-to-digital converter according to claim 14.

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