Electric power conversion device

Abstract

n cells (102_1-102_n) are configured to select one of, according to a switching pattern of semiconductor switching elements (107a-107d), a first operation of outputting a positive voltage with discharging or charging of a capacitor (108), an operation of outputting a negative voltage with charging or discharging of the capacitor (108) opposite to the first operation, and an operation of outputting a zero voltage without charging and discharging the capacitor (108). A controller (120) determines, from a plurality of combination patterns in which a total output voltage (Vttl) of a switching circuit (100) matches a voltage command level set according to an output voltage command value, a combination of the switching patterns of the n cells (102_1-102_n) so as to select one combination pattern in which an operation for reducing the voltage deviation with respect to the cell voltage command value is executed in a cell having a high priority in the voltage control of the capacitor (108).

Description

Power Conversion Device

[0001] The present disclosure relates to a power conversion device.

[0002] Japanese Patent Laid-Open Publication No. 2022-119256 (Patent Document 1) describes a technology for miniaturizing and simplifying the configuration of a device that converts DC power to AC power. In the power conversion device of Patent Document 1, a filter circuit can be omitted or made smaller by combining a switching circuit that converts power between DC power and AC power and a linear circuit that operates as a variable resistor by adjusting the conduction resistance of a semiconductor element.

[0003] Furthermore, in the second embodiment (FIG. 4) of Patent Document 1, it is described that the total output voltage of the switching circuit is made multi-level by using the sum of the outputs of N converters, and in particular, the number of levels is efficiently increased by making the capacitor voltages corresponding to the output voltages of the N converters have a power ratio of 1, 1 / 2, 1 / 4, ..., 1 / (2^N) or 1, 1 / 3, 1 / 9, ..., 1 / (3^N).

[0004] Japanese Patent Application Laid-Open No. 2022-119256

[0005] Patent Document 1 describes that there are multiple combinations of switching patterns of N converters for one total output voltage, and mentions that the capacitor voltage of each converter can be controlled by controlling the time ratio for switching between multiple combinations of switching patterns that have the same total output voltage.

[0006] However, in the control method of Patent Document 1, in addition to the need to switch the switching pattern of each converter to change the total output voltage in response to the sinusoidal AC voltage command, it is also necessary to switch the switching pattern to control the capacitor voltage of each converter even during a period in which the total output voltage is the same.

[0007] As a result, the switching cycle of the switching pattern becomes shorter, and the number of times the semiconductor switching elements in each converter switch per unit time increases. This raises concerns about a decrease in efficiency due to increased switching loss. In particular, if the number of converters (N) is increased to increase the number of levels of the total output voltage, the step difference in the total output voltage following the AC voltage command can be reduced, but the shortened switching cycle of the total output voltage raises concerns about a greater impact of the increased number of switching times.

[0008] The present disclosure has been made to solve such problems, and an object of the present disclosure is to stably control the DC voltage of the energy storage element of each cell while suppressing an increase in the number of switching operations of the semiconductor switching element of each cell in a power conversion device configured to switch the total output voltage of a plurality of cells, each of which includes an energy storage element and a semiconductor switching element, in accordance with a voltage command value.

[0009] According to one aspect of the present disclosure, there is provided a power conversion device. The power conversion device has an output voltage command value that changes over time, and includes a switching circuit and a controller. The switching circuit includes n cells (n: an integer greater than or equal to 2) connected in series. Each of the n cells includes a plurality of first semiconductor switching elements and an energy storage element, and is configured to select, according to a switching pattern of the plurality of first semiconductor switching elements, a first operation that outputs a positive voltage that corresponds to a DC voltage of the energy storage element by discharging or charging the energy storage element, a second operation that outputs a negative voltage that corresponds to a DC voltage of the energy storage element by charging or discharging the energy storage element in a manner opposite to the first operation, or a third operation that outputs a zero voltage without charging or discharging the energy storage element. The controller determines a combination pattern of operations of the n cells and controls the switching pattern of each of the n cells according to the combination pattern in order to control the output voltage of the power conversion device. The controller determines priorities for voltage control of the energy storage elements among the n cells based on the degree of deviation of the voltage detection values ​​of the energy storage elements from a cell voltage command value (Vcr) of the energy storage elements in each of the n cells. Furthermore, the controller controls the switching pattern of each of the n cells according to one combination pattern selected from a plurality of combination patterns for matching the total output voltage of the switching circuits to a voltage command level set according to the output voltage command value so that an operation is performed to reduce the voltage deviation of the voltage detection value from the cell voltage command value in a cell with a high priority.

[0010] According to the present disclosure, by selecting a combination of switching patterns for n cells to control the total output voltage of the switching circuit in accordance with a voltage command level for following the output voltage command, it is possible to reduce the voltage deviation of cells that have a high priority for voltage control of their energy storage elements, thereby making it possible to stably control the DC voltage of the energy storage elements of each cell while suppressing an increase in the number of switching times of the semiconductor switching elements of each cell.

[0011] 1 is a block diagram illustrating a schematic configuration of a power conversion device according to a first embodiment. FIG. 2 is a conceptual diagram illustrating an example of setting cell voltage command values ​​for n cells shown in FIG. 1. FIG. 3 is a table illustrating switching patterns of the main converter shown in FIG. 1. FIG. 4 is a conceptual circuit diagram illustrating switching patterns for each cell shown in FIG. 1. FIG. 5 is a conceptual diagram illustrating control of the total output voltage in an example where n=3. FIG. 6 is a table illustrating combinations of switching patterns for each level of the total output voltage. FIG. 7 is a table illustrating an example of switching pattern selection control. FIG. 8 is a flowchart illustrating processing for switching pattern selection control in a power conversion device according to the first embodiment. FIG. 9 is a conceptual diagram illustrating control timing of switching patterns in a power conversion device according to the first embodiment. FIG. 10 is a conceptual diagram illustrating an example operation of a power conversion device according to the first embodiment. FIG. 11 is a conceptual diagram illustrating control timing of switching patterns in a first modification of the first embodiment. FIG. 12 is a flowchart illustrating processing for determining control timing by a power conversion device according to the first modification of the first embodiment. FIG. 13 is a conceptual diagram illustrating the influence of dead time when transitioning from a switching pattern that outputs zero voltage to a switching pattern that outputs a positive voltage in each cell. FIG. 14 is a flowchart illustrating processing for setting switching patterns for each cell in a power conversion device according to a second modification of the first embodiment. FIG. 15 is a flowchart illustrating pattern correction processing in a power conversion device according to the second embodiment.

[0012] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings will be denoted by the same reference numerals, and their description will not be repeated in principle.

[0013] First Embodiment Fig. 1 is a block diagram illustrating a schematic configuration of a power conversion device 10 according to a first embodiment.

[0014] 1, the power conversion device 10 includes a switching circuit 100, a linear circuit 103, and a controller 120. The switching circuit 100 includes a main converter 101 and n (n: an integer of 2 or more) cells 102_1 to 102_n connected in series. The main converter 101 and the cells 102_1 to 102_n are connected in series to an output terminal 109, and a total output voltage Vttl of the main converter 101 and the cells 102_1 to 102_n is generated at the output terminal 109.

[0015] In the example shown in FIG. 1 , the main converter 101 is configured as a so-called T-type NPC (Neutral Point Clamped) circuit and is capable of outputting three levels: a positive voltage (+E), a negative voltage (−E), and a zero voltage (0) relative to the potential of the neutral point Np. Specifically, the main converter 101 includes DC power supplies 104P and 104N connected in series via the neutral point Np, and semiconductor switching elements (hereinafter simply referred to as “switching elements”) 105P, 105N, 106a, and 106b. Each of the DC power supplies 104P and 104N outputs a DC voltage E. The switching elements 105P and 105N form upper and lower arms for outputting a positive voltage and a negative voltage, respectively. The switching elements 106a and 106b form bidirectional switches for clamping the output voltage during zero voltage output to the reference potential of the neutral point Np.

[0016] Since the n cells 102_1 to 102_n have the same configuration, in the following, when referring to all n cells, they will be referred to simply as cell 102, while when distinguishing between the n cells, they will be given subscripts (_1, ..., _n).

[0017] Each cell 102 has switching elements 107a to 107d that form a full-bridge circuit, and a capacitor 108 that is a representative example of an "energy storage element." Each cell 102 is also provided with a voltage detector 114 for detecting a DC voltage (capacitor voltage Vc) held by the capacitor 108. As the "energy storage element," other storage elements such as a secondary battery (e.g., a lithium-ion battery) can also be used instead of the capacitor 108. The capacitor voltages Vc1 to Vcn of the cells 102_1 to 102_n detected by the voltage detector 114 are input to the controller 120.

[0018] Switching elements 107a and 107b are connected in series between high-voltage line PL and low-voltage line NL via node Na. Switching elements 107c and 107d are connected in series between high-voltage line PL and low-voltage line NL via node Nb. Capacitor 108 is connected between high-voltage line PL and low-voltage line NL in a manner sandwiched between switching elements 107a, 107b and switching elements 107c, 107d.

[0019] Each cell 102 can control the cell output voltage Vt, which is the terminal voltage between nodes Na and Nb, in three ways depending on the on / off combinations of switching elements 107a to 107d: a positive voltage (+Vc) according to the capacitor voltage Vc, a negative voltage (-Vc), or a zero voltage (0). When distinguishing between n cells, the cell output voltage Vt and capacitor voltage Vc are also assigned subscripts (1, .... n).

[0020] Therefore, the total output voltage Vttl output at the output terminal 109 can be any stepped voltage level according to the sum of the output voltage Vm of the main converter 101 and the cell output voltages Vt1 to Vtn of each of the n cells 102_1 to 102_n, each of which is controlled in three ways.

[0021] The linear circuit 103 is connected between the output terminal 109 of the switching circuit 100 and the load 200. The current detector 113 detects the output current Io from the switching circuit 100 to the load 200. The detected value of the output current Io is input to the controller 120.

[0022] The linear circuit 103 is configured in the same manner as in Patent Document 1 and includes semiconductor elements 110a and 110b connected in series in opposite directions. The semiconductor elements 110a and 110b can be configured as transistors whose conduction resistance changes when the voltage of their control electrodes (gate or base) is controlled by a controller 120.

[0023] The linear circuit 103 operates as a variable resistor, similar to Patent Document 1, and generates a voltage difference between the output voltage command value Voutr of the power conversion device 10 and the total output voltage Vttl at the output terminal 109. Specifically, the controller 120 adjusts the voltage of the control electrodes of the semiconductor elements 110a and 110b operating in the linear region so as to obtain a conduction resistance such that the amount of voltage drop due to the product of the output current Io detected by the current detector 113 and the conduction resistance of the semiconductor elements 110a and 110b is equivalent to the voltage difference between the output voltage command value Voutr and the total output voltage Vttl.

[0024] As a result, the total output voltage Vttl that changes stepwise can be used to supply an AC voltage that follows the output voltage command value Voutr to the load 200. In this embodiment, the description will proceed assuming that the output voltage command value Voutr is a sinusoidal AC voltage.

[0025] The controller 120 generates gate signals that control the on / off of each switching element included in the main converter 101 and the cells 102_1 to 102_n. Hereinafter, the on / off combinations of the switching elements in the main converter 101 and the cells 102_1 to 102_n are also referred to as "switching patterns."

[0026] The controller 120 may be configured with a digital electronic circuit such as an FPGA (Field Programmable Gate Array) that performs predetermined arithmetic processing via an A / D conversion device (not shown), or may be configured with analog electronic circuits such as a comparator, an operational amplifier, and a differential amplifier circuit. Alternatively, the controller 120 may be configured with both digital and analog electronic circuits. The controller 120 may also be configured with a microcomputer or the like that performs predetermined arithmetic processing by executing a pre-stored program.

[0027] In this embodiment, the switching element can be configured by connecting, for example, a metal oxide semiconductor field effect transistor (MOSFET) and a free wheel diode (FWD) in anti-parallel, but any self-extinguishing element may also be used. That is, any configuration of the switching element can be used as long as it has the function of cutting off current in a specific direction and the function of blocking voltage in response to a control signal such as a gate signal.

[0028] The controller 120 can perform output voltage control to supply the load 200 with an output voltage according to the output voltage command value Voutr that changes on the time axis by switching the total output voltage Vttl of the output terminal 109. On the other hand, if the capacitor voltage Vc of each cell 102 deviates from the predetermined cell voltage command value Vc*, an error will occur in the total output voltage Vttl, which may reduce the accuracy of the output voltage control.

[0029] Therefore, the controller 120 selects a switching pattern and generates gate signals for each switching element so that cell voltage control for maintaining the capacitor voltage Vc in each cell 102 at the cell voltage command value Vc* is performed together with output voltage control based on the detection value of the voltage detector 114. In this embodiment, a description will be given of the selection control of a switching pattern for realizing both output voltage control and cell voltage control by suppressing an increase in the number of on / off cycles (per unit time) of each switching element.

[0030] FIG. 2 shows a conceptual diagram illustrating an example of setting capacitor voltages in n cells 102_1 to 102_n.

[0031] 2, the cell voltage command value Vc* can be set to different values ​​among the cells 102. For example, the output voltage Vm of the main converter 101 is controlled to E, −E, or 0, while the cell voltage command values ​​Vc1* to Vcn* of the cells 102_1 to 102_n can be set in accordance with the inverse ratio of a power of two.

[0032] Specifically, the cell voltage command value Vc1* of cell 102_1 can be set to E / 2, the cell voltage command value Vc2* of cell 102_2 can be set to E / (2^2)=E / 4, the cell voltage command value Vc3* of cell 102_3 can be set to E / (2^3)=E / 8, and the cell voltage command value Vcn* of cell 102_n can be set to E / (2^n). This makes it possible for the total output voltage Vttl to achieve a number of levels of (2^(N+1)-1).

[0033] Alternatively, the cell voltage command values ​​Vc1* to Vcn* of cells 102_1 to 102_n can be set to other numbers other than 2, for example, in accordance with the inverse ratio of a power of 3, as follows: Vc1* = E / 3, Vc2* = E / (3^2) = E / 9, Vc3* = E / (3^3) = E / 27, Vcn* = E / (3^n).

[0034] FIG. 3 shows a diagram illustrating the switching pattern of the main converter 101 shown in FIG.

[0035] As shown in FIG. 3, in the main converter 101 (FIG. 1) configured with a T-type NPC circuit, by using a switching pattern PTa in which the switching elements 105P and 106a are turned on while the switching elements 105N and 106b are turned off, the output voltage Vm becomes a positive voltage that is higher than the reference potential of the neutral point Np by the output voltage of the DC power supply 104P (Vm=+E).

[0036] Conversely, by using switching pattern PTb, which turns on switching elements 105N and 106b while turning off switching elements 105P and 106a, the output voltage Vm of the main converter 101 becomes a negative voltage that is lower than the reference potential of the neutral point Np by the output voltage of the DC power supply 104N (Vm = -E).

[0037] Furthermore, by using a switching pattern PTc in which the switching elements 105P and 105N are turned off while the switching elements 106a and 106b are turned on, the output voltage Vm becomes zero voltage (Vm=0) equivalent to the reference potential of the neutral point Np. The switching elements 105P, 105N, 106a, and 106b of the main converter 101 correspond to one example of the "plurality of second semiconductor switching elements."

[0038] Next, a description will be given of the on / off control of the switching elements in each cell 102. Fig. 4 is a conceptual circuit diagram illustrating the switching pattern of the on / off control in each cell 102.

[0039] Each cell 102 shown in FIG. 1 has a first leg in which switching elements 107a and 107b are connected in series, and a second leg in which switching elements 107c and 107d are connected in series. In each of the first leg and the second leg, the two series-connected switching elements are complementarily switched on and off to prevent short circuits. Therefore, each cell 102 has four switching patterns shown in FIGS. 4(a) and 4(b). Below, we will explain the case where the current direction in each cell 102 is from node Na to node Nb, i.e., the case where output current Io flows from power conversion device 10 to load 200 in FIG. 1.

[0040] 4A (positive voltage operation), switching elements 107b and 107c are turned on, while switching elements 107a and 107d are turned off. This causes the cell output voltage Vt between nodes Na and Nb to equal Vc, accompanied by a current Ia discharging capacitor 108, so that cell 102 performs positive voltage operation. During the positive voltage operation, capacitor voltage Vc gradually decreases as capacitor 108 discharges.

[0041] In the switching pattern shown in Figure 4(b) (negative voltage operation), switching elements 107a and 107d are turned on, while switching elements 107b and 107c are turned off. As a result, contrary to the positive voltage operation in Figure 4(a), the cell output voltage Vt becomes -Vc with the current Ib charging the capacitor 108, and the cell 102 performs negative voltage operation. During the negative voltage operation, the capacitor voltage Vc gradually increases as the capacitor 108 charges.

[0042] 4(c), the upper switching elements 107a and 107c of each leg are turned on, while the upper switching elements 107b and 107d are turned off. As a result, a current Ic is generated through a path that does not include the capacitor 108, and the capacitor 108 is not charged or discharged, resulting in the cell output voltage Vt=0.

[0043] In the switching pattern shown in Figure 4(d), the lower switching elements 107b and 107d of each leg are turned on, while the switching elements 107a and 107c are turned off. This generates a current Id through a path that does not include the capacitor 108, and as in Figure 4(d), the capacitor 108 is not charged or discharged, resulting in a cell output voltage Vt = 0. During the switching patterns of Figures 4(c) and 4(d), the cell 102 performs zero voltage operation. During zero voltage operation, the capacitor 108 is not charged or discharged, so the capacitor voltage Vc is maintained.

[0044] In this way, each cell 102 can control the capacitor voltage Vc to increase or decrease by selecting one of a positive voltage operation, a negative voltage operation, and a zero voltage operation. Therefore, when the capacitor voltage Vc is lower than the cell voltage command value Vc* in the cell 102, the switching pattern of FIG. 4B is selected, and when the capacitor voltage Vc is higher than the cell voltage command value Vc* in the cell 102, the switching pattern of FIG. 4A is selected, thereby performing cell voltage control to maintain the capacitor voltage Vc at the cell voltage command value Vc*. It should be understood that two types of switching patterns with different current paths can be selected to maintain the capacitor voltage Vc.

[0045] In this embodiment, the switching elements 107a to 107d of each cell correspond to an example of "plurality of first semiconductor switching elements." A positive voltage operation selected according to the switching pattern of the switching elements 107a to 107d corresponds to an example of a "first operation," a negative voltage operation corresponds to an example of a "second operation," and a zero voltage operation corresponds to an example of a "third operation."

[0046] Note that when the current direction in the cell 102 is reversed and the output current Io flows from the load 200 to the power conversion device 10, in the switching pattern (positive voltage operation) of FIG. 4A where Vt = Vc, the capacitor 108 is charged, causing the capacitor voltage Vc to increase. In the switching pattern (negative voltage operation) of FIG. 4B where Vt = −Vc, the capacitor 108 is discharged, causing the capacitor voltage Vc to decrease, in contrast to the positive voltage operation. Therefore, when the capacitor voltage Vc is lower than the cell voltage command value Vc*, the switching pattern of FIG. 4A is selected, while when the capacitor voltage Vc is higher than the cell voltage command value Vc*, the switching pattern of FIG. 4B is selected, thereby achieving similar cell voltage control. In this case, too, two types of switching patterns with different current paths can be selected to maintain the capacitor voltage Vc.

[0047] Below, the selection control of the switching pattern according to this embodiment for realizing both output voltage control and cell voltage control will be explained for the case where n = 3. Note that the selection of the switching pattern in the cell 102 for cell voltage control will be explained on the premise of the current directions exemplified in Figures 4(a) to 4(d).

[0048] Fig. 5 is a conceptual diagram illustrating control of the total output voltage Vttl in an example where n = 3. In the following, similar to the example in Fig. 2, the control of the total output voltage Vttl within the range of 0≦Vttl≦E will be described under the assumption that the cell voltage command values ​​Vc1* = E / 2, the cell voltage command values ​​Vc2* = E / 4, and the cell voltage command values ​​Vc3* = E / (2^3) = E / 8 for the cells 102_1 to 102_3, for the sake of simplicity.

[0049] 5, the main converter 101 is controlled to output zero voltage operation (0) or positive voltage operation (1) by selecting a switching pattern, and is therefore controlled to Vm = 0 or +E. In contrast, the operation of each cell 102 is controlled to execute positive voltage operation (1), zero voltage operation (0), or negative voltage operation (-1).

[0050] Therefore, by selecting the switching pattern, the cell output voltage Vt1 of the cell 102_1 can be controlled to (E / 2), −(E / 2), or 0. Similarly, by selecting the switching pattern, the cell output voltage Vt2 of the cell 102_2 can be controlled to (E / 4), −(E / 4), or 0, and the cell output voltage Vt3 of the cell 102_3 can be controlled to (E / 8), −(E / 8), or 0.

[0051] The total output voltage Vttl of the output terminal 109 is expressed as the sum of the above-mentioned Vm and Vt1 to Vt3 (Vttl = Vm + Vt1 + Vt2 + Vt3), and is therefore controlled by the combination of the operations (positive voltage operation / negative voltage operation / zero voltage operation) of the main converter 101 and cells 102_1 to 102_2, i.e., the combination of selected switching patterns.

[0052] 6 is a table showing combinations of switching patterns for each level of the total output voltage Vttl. As described above, an example of control when the total output voltage Vttl is set within the range of 0≦Vttl≦E is shown.

[0053] As shown in FIG. 6, by setting the capacitor voltages Vc1 to Vc3 of the n=3 cells 102 in inverse ratios of powers of 2, the level of the total output voltage Vttl can be set in increments of the lowest capacitor voltage Vc3=(1 / 8)E.

[0054] While there is only one combination of switching patterns for Vttl=E and Vttl=0, at other levels, there may be multiple combinations of Vm and Vt1 to Vt3, i.e., multiple combinations of the operation (switching patterns) of the main converter 101 and cells 102_1 to 102_2, to obtain the same total output voltage Vttl.

[0055] FIG. 7 shows, as an example, a chart for explaining in detail the selection control of the switching pattern for controlling the total output voltage Vttl=(7 / 8)E.

[0056] As shown in FIG. 7, it is possible to obtain Vttl=(7 / 8)E by different combinations of Vm and Vt1 to Vt3 using four combination patterns PT1 to PT4.

[0057] In combination pattern PT1, the switching pattern of the main converter 101 is selected so that Vm=E, and the switching patterns of the cells 102_1 to 102_3 are selected so that Vt1=Vt2=0 and Vt3=-(E / 8), thereby obtaining Vttl=(7 / 8)E. In combination pattern PT1, Vttl=(7 / 8)E is achieved in a manner in which the capacitor 108 is charged only by the cell 102_3, while the capacitor 108 is not charged or discharged by the cells 102_1 and 102_2.

[0058] In combination pattern PT2, the switching pattern of the main converter 101 is selected so that Vm=E, and the switching patterns of the cells 102_1 to 102_3 are selected so that Vt1=0, Vt2=-(E / 4), and Vt3=(E / 8), thereby obtaining Vttl=(7 / 8)E. In combination pattern PT2, Vttl=(7 / 8)E is achieved in a manner in which the capacitor 108 is charged in the cell 102_2, the capacitor 108 is discharged in the cell 102_3, and the capacitor 108 is not charged or discharged in the cell 102_1.

[0059] In combination pattern PT3, the switching pattern of the main converter 101 is selected so that Vm=E, and the switching patterns of the cells 102_1 to 102_3 are selected so that Vt1=-(E / 2), Vt2=(E / 4), and Vt3=(E / 8), thereby obtaining Vttl=(7 / 8)E. In combination pattern PT3, Vttl=(7 / 8)E is achieved in a manner in which the capacitor 108 is charged by the cell 102_1 and discharged by the cells 102_2 and 102_3.

[0060] In combination pattern PT4, the switching pattern of the main converter 101 is selected so that Vm = 0, and the switching patterns of the cells 102_1 to 102_3 are selected so that Vt1 = (E / 2), Vt2 = (E / 4), and Vt3 = (E / 8), thereby obtaining Vttl = (7 / 8) E. In combination pattern PT4, Vttl = (7 / 8) E is achieved in a manner in which the capacitors 108 are discharged in all of the cells 102_1 to 102_3.

[0061] Therefore, when it is necessary to control the total output voltage Vttl = (7 / 8)E in accordance with the output voltage command value Voutr, it is possible to simultaneously increase or decrease the voltage of the capacitor 108 of the cell 102 (cell voltage control) by selecting one of the combination patterns PT1 to PT4.

[0062] For example, in cell voltage control at cell 102_1, when the capacitor voltage Vc1 is lower than the cell voltage command value Vc1*, combination pattern PT3 is selected, whereas when the capacitor voltage Vc1 is higher than the cell voltage command value Vc1*, combination pattern PT4 is selected, thereby making it possible to bring the capacitor voltage Vc1 closer to the cell voltage command value Vc1*. On the other hand, when the difference between the capacitor voltage Vc1 and the cell voltage command value Vc1* is small, combination pattern PT1 or PT2 is selected, thereby making it possible to maintain the capacitor voltage Vc1. In this way, cell voltage control at cell 102_1 can be realized while achieving output voltage control such that the total output voltage Vttl = (7 / 8)E.

[0063] However, when selecting among the combination patterns PT1 to PT4, the combinations of charging and discharging the capacitors 108 in the cells 102_1 to 102_3 are limited. For this reason, it may not be possible to select a switching pattern that brings the capacitor voltage Vc closer to the cell voltage command value Vc* in all of the cells 102_1 to 102_3.

[0064] For example, when the combination pattern PT3 or PT4 for increasing or decreasing the capacitor voltage of the cell 102_1 is selected, the capacitor voltage Vc cannot be increased in the cells 102_2 and 102_3 because only switching patterns for discharging the capacitor 108 can be selected.

[0065] Therefore, in this embodiment, the selection control of the switching pattern of the power conversion device is performed so as to achieve both output voltage control and cell voltage control, along with prioritizing the cell voltage control among the n cells 102 .

[0066] 8 is a flowchart illustrating the process of controlling the selection of a switching pattern in the power conversion device according to embodiment 1. The process shown in FIG. 8 is repeatedly executed by the controller 120 while the power conversion device 10 is in operation.

[0067] Referring to FIG. 8, in S100, controller 120 determines whether or not the timing for controlling the switching pattern has arrived.

[0068] FIG. 9 shows a conceptual diagram illustrating the control timing of the switching pattern in the power conversion device according to the first embodiment.

[0069] As shown in FIG. 9, as the output voltage command value Voutr changes over time, the voltage level command Vttlr of the total output voltage Vttl needs to be updated so as to follow the output voltage command value Voutr.

[0070] For example, each time the voltage difference ΔVt between the current voltage level command Vttlr and the output voltage command value Voutr reaches the determination value Va, the controller 120 determines YES in S100, updates the voltage level command Vttlr, and executes control to switch the switching pattern.

[0071] Here, the determination value Va can be set in advance in accordance with the settable step size (i.e., resolution) of the level of the total output voltage Vttl. In the examples of Figures 5 to 8, since the resolution of the total output voltage Vttl is (E / 8), Va = (E / 8) can be set.

[0072] 9, at each of the times ta to te, ΔVt≧Va is established, so that a YES determination is made in S100, and it is determined that the timing for controlling the switching pattern has arrived. On the other hand, during the period in which ΔVt<Va, a NO determination is made in S100.

[0073] When a control timing arrives, the voltage level command Vttlr is updated in accordance with the output voltage command value Voutr at that timing. As in the example of FIG. 9 , the voltage level command Vttlr can be updated by setting Vttlr=Voutr at that timing.

[0074] Alternatively, Vttlr may be set to Vout-α or Vttlr=Vout+α (α: a predetermined constant) at each control timing so that Vout>Vttlr or Vout<Vttlr is maintained.

[0075] Referring again to FIG. 8, in response to the arrival of the control timing (YES at S100), controller 120 updates voltage level command Vttlr at S110 and extracts a combination pattern corresponding to the updated voltage level command Vttlr.

[0076] 6 and 7, each combination pattern represents a combination of switching patterns for selecting the operation (positive voltage output / negative voltage output / zero voltage output) of each of the main converter 101 and the cells 102_1 to 102_n. On the other hand, at times other than times ta to td in Fig. 9, a NO determination is made in S100, the current voltage level command Vttlr is maintained, and the switching patterns of the main converter 101 and each of the cells 102 are maintained.

[0077] In S110, M patterns (M: natural number) are extracted. For example, when Vttlr=(7 / 8)E is set under n=3, combination patterns PT1 to PT4 in Fig. 7 are extracted, so M=4. The M combination patterns extracted in S110 are used as the initial values ​​for one or more candidate patterns.

[0078] Furthermore, in S120, the controller 120 acquires the capacitor voltages Vc1 to Vcn of the cells 102_1 to 102_n from the voltage detector 114 of each cell 102. This makes it possible to calculate the voltage error ΔVc (ΔVc=Vc*−Vc) of the capacitor voltage Vc relative to the cell voltage command value Vc* in each cell 102.

[0079] In step S130, the controller 120 determines the priority of the cell voltage control among the n cells 102. As will be described below, the priority is determined based on the voltage error ΔVc of each cell 102, in descending order of the degree of deviation from the cell voltage command value Vc*.

[0080] In this case, rather than simply comparing the magnitude of |ΔVc|, the priority can be determined based on the absolute value of the weighted voltage deviation ΔVc between the cells 102. That is, by setting the weighting coefficients k1 to kn of the cells 102_1 to 102_n in advance, the priority can be determined so that the priority increases in descending order of the absolute values ​​of k1·ΔVt1 to kn·ΔVtn.

[0081] In a first example, the weighting coefficients k1 to kn (k1 to kn > 0) can be determined in advance in accordance with the magnitude of the cell voltage command value Vc*. That is, for Vc1*>Vc2*> ...>Vcn*, the weighting coefficients k1 to kn can be set so that the larger the cell voltage command value Vc*, the larger the value becomes, so that k1>k2> ...>kn.

[0082] The voltage error ΔVt relative to the cell voltage command value Vc* directly affects the voltage error of the total output voltage Vttl relative to the voltage level command Vttlr. Furthermore, it can be understood that the larger the cell voltage command value Vc* of a cell 102, the greater the impact that the voltage error ΔVt of that cell 102 has on the voltage error of the total output voltage Vttl. Therefore, in the first example, by preferentially suppressing the voltage error of the cell 102 with a large cell voltage command value Vc*, it is possible to suppress the voltage error of the total output voltage Vttl.

[0083] Alternatively, as a second example, if the capacitance values ​​of the capacitors 108 differ between the cells 102, it is also possible to set the weighting coefficients k1 to kn according to the magnitude of the capacitance values. For example, it is conceivable to increase the capacitance value of the capacitor 108 of a cell 102 having a smaller cell voltage command value Vc* in order to reduce the rate of voltage fluctuation. Because the voltage change in the capacitor voltage Vc with respect to charging and discharging increases in inverse proportion to the capacitance value of the capacitor 108, the weighting coefficients k1 to kn can be set according to a rule such that the smaller the capacitance value of the capacitor 108 of the cell 102, the larger the value.

[0084] Alternatively, in order to suppress a voltage error for a specific cell voltage command value Vc*, it is possible to increase the capacitance value of the capacitor 108 and set a large weighting coefficient for the cell 102 to which the specific cell voltage command value Vc* is set. In this case, it is also possible to set the weighting coefficients k1 to kn so that the larger the capacitance value of the capacitor 108 of the cell 102, the larger the weighting coefficients k1 to kn.

[0085] Furthermore, by using the above combinations, it is also possible to set the weighting coefficients k1 to kn according to the combination of the magnitude of the cell voltage command value Vc* and the magnitude of the capacitance value of the capacitor 108 among the n cells 102.

[0086] In this way, when determining the priority in S130, the degree of deviation from the cell voltage command value Vc* can be evaluated depending on the magnitude of the cell voltage command value Vc* between cells 102 and the magnitude of the absolute value of the voltage error (k1·ΔV1 to kn·ΔVn) that reflects weighting based on at least one of the magnitude of the capacitance value of capacitor 108.

[0087] After determining the priority order in S130, the controller 120 sets the parameter value i (i: natural number) to the initial value "1" (i=1) in S135, and then proceeds to S140. In S140, it is determined whether or not a combination pattern that reduces the absolute value (|ΔV|) of the voltage error of the cell 102 with the i-th priority order exists among the current candidate patterns according to the parameter value i. If a combination pattern that reduces |ΔV| exists (YES in S140), the combination pattern is extracted as a new candidate pattern from the current candidate patterns in S150.

[0088] In S140, if there is no pattern that reduces |ΔV| among the current candidate patterns (NO in S140), then in S160 it is determined whether there is a pattern among the current candidate patterns that can maintain |ΔV| of the i-th priority cell 102, i.e., a combination pattern that causes the cell 102 to perform zero-voltage operation. If there is a combination pattern that can maintain |ΔV| (YES in S160), then in S170 the corresponding candidate pattern is extracted from the current candidate patterns as a new candidate pattern.

[0089] On the other hand, if there is no combination pattern that can maintain |ΔV| of the i-th cell 102 (NO in S160), no further narrowing down of candidate patterns is performed from the current candidate patterns.

[0090] When the processes of S140 to S170 are completed, the controller 120 compares the current parameter value i with the number n of cells 102 in S180. If i<n (NO in S180), the controller 120 increments the parameter value i by 1 in S190 and returns to S140. As a result, the processes of S140 to S170 are executed for each of the parameter values ​​i=1 to n.

[0091] When i=1, that is, in the processing of S140 to S170 for the cell 102 with the first priority, one or more combination patterns less than M are extracted as candidate patterns in S150 from the M combination patterns corresponding to the voltage level command Vttlr extracted in S110, when M≧2.

[0092] When i≧2, further narrowing down is performed in S150 or S170 on the candidate pattern extracted after processing (S140 to S170) for the (i−1)th cell 102, which is one cell higher in priority. Alternatively, by skipping both S150 and S170, the candidate pattern extracted after processing for the (i−1)th cell 102 is maintained as is. It should be understood that after the candidate pattern is narrowed down to one, that candidate pattern is maintained until processing for i=n is completed, regardless of the determination results in S140 and S160.

[0093] When i=n in S180 (YES in S180), the controller 120 determines a combination of operations (switching patterns) of the main converter 101 and the cells 102_1 to 102_n according to the last remaining candidate pattern in S195. Then, according to the combination of switching patterns determined in S195, gate signals are generated for the main converter 101 and each of the switching elements of the cells 102_1 to 102_n shown in FIG.

[0094] In this way, the power conversion device 10 according to the first embodiment can determine the switching pattern for each cell 102 so as to extract, from a plurality of combinations of switching patterns that result in the same total output voltage Vttl, one combination of switching patterns for charging or discharging the capacitor 108 so as to reduce the voltage error |ΔVc| in the cell 102 that has a large degree of deviation from the cell voltage command value Vc* (high priority). This determines the operation of each cell 102, i.e., whether to perform positive voltage operation, negative voltage operation, or zero voltage operation.

[0095] As a result, cell voltage control can be performed in which one combination of switching patterns is selected from multiple combinations of switching patterns for output voltage control that switches the total output voltage Vttl in accordance with the output voltage command value Voutr so as to preferentially reduce the voltage error |ΔVc| in the cell 102 that has a large degree of deviation from the cell voltage command value Vc*.

[0096] This allows cell voltage control to be achieved by selecting a switching pattern for output voltage control that causes the total output voltage Vttl to follow the output voltage command value Voutr, eliminating the need to switch the switching pattern for cell voltage control. Therefore, the DC voltage of the capacitor 108 (energy storage element) of each cell 102 can be stably controlled while suppressing an increase in the number of switching operations of the switching elements of each cell 102.

[0097] 10 is a conceptual diagram illustrating an example of the operation of the power conversion device according to embodiment 1. As shown in Fig. 10, the output voltage Vout supplied from the power conversion device 10 to the load 200 is represented by the sum of the total output voltage Vttl of the switching circuit 100 and the output voltage Vlnr of the linear circuit 103.

[0098] 10 shows output voltage control in which the output voltage command value Voutr is set to a sinusoidal voltage. In this case, the output voltage Vm of the main converter 101 is controlled to either a positive voltage (+E), a negative voltage (-E), or zero voltage (0), and similar to FIG. 7, a combination of switching patterns is set in advance for a total output voltage Vttl in the range of 0 > Vttl ≧ -E. Even in the range of 0 > Vttl > -E, similar to FIG. 7, a plurality of combinations of switching patterns can be selected corresponding to the same total output voltage Vttl, enabling similar cell voltage control.

[0099] The total output voltage Vttl is set to a stepped voltage with a step size equivalent to the capacitor voltage of the cell 102_3 (Vc=E / 8). Furthermore, the linear circuit 103 shares the voltage difference between the output voltage command value Voutr and the total output voltage Vttl, so that any sinusoidal voltage can be supplied to the load 200.

[0100] As described above, the linear circuit 103 operates as a variable resistor by changing the conduction resistance by controlling the gate voltages of the semiconductor elements 110 a and 110 b connected in series in opposite directions. The controller 120 controls the resistances, i.e., the gate voltages, of the semiconductor elements 110 a and 110 b so that the output voltage Vlnr of the linear circuit 103, which corresponds to the product of the output current Io and the resistance value (conduction resistance of the semiconductor elements 110 a and 110 b) of the linear circuit 103, becomes equivalent to the voltage difference between the output voltage command value Voutr and the total output voltage Vttl.

[0101] As described in Patent Document 1, during the period when Voutr>0, the total output voltage Vttl is set higher than the output voltage command value Voutr so that the output voltage Vlnr of the linear circuit 103 is generated in the negative direction (Vlnr<0) with respect to the output current Io flowing to the load 200.

[0102] On the other hand, during the period when Voutr<0, the total output voltage Vttl is set lower than the output voltage command value Voutr so that the output voltage Vlnr of the linear circuit 103 is generated in the positive direction (Vlnr>0) in response to the output current Io flowing to the load 200.

[0103] In this way, by arranging a linear circuit 103 similar to that of Patent Document 1 and generating the total output voltage Vttl in correspondence with the output voltage command value Voutr that changes over time so that the absolute value of the total output voltage Vttl is greater than the absolute value of the output voltage command value Voutr, it is possible to supply an arbitrary voltage waveform that conforms to the output voltage command value Voutr to the load 200.

[0104] Depending on the configuration of the load 200, even if the linear circuit 103 is omitted, it is possible to supply a voltage waveform according to the output voltage command value Voutr to the load 200 by output voltage control of the total output voltage Vttl. For example, if the inductance of the input path to the load 200 is high, and it is possible to directly supply a stepped total output voltage Vttl, it is possible to configure the power conversion device according to the first embodiment without omitting the linear circuit 103.

[0105] Modification 1 of Embodiment 1 In Modification 1 of Embodiment 1, a modification of the determination of the control timing will be described.

[0106] 11 is a conceptual diagram illustrating the control timing of the switching pattern in Modification 1 of Embodiment 1. The horizontal axis of Fig. 11 is the time axis, and the vertical axis represents the capacitor voltages Vc1 to Vc3 of the cells 102_1 to 102_3 and the voltage level command Vttlr of the total output voltage Vttl.

[0107] 11, the capacitor voltages Vc1 to Vc3 are expressed in units of [pu] by dividing them by the cell voltage command values ​​Vc1* to Vc3*. That is, 1.0 [pu] indicates a state in which the capacitor voltage Vc is equal to the cell voltage command value Vc1*. In the modification of the first embodiment, an upper limit value Vcmax [pu] and a lower limit value Vcmin [pu] are set to maintain Vc1 [pu] to Vc3 [pu] within an appropriate range.

[0108] As explained in Fig. 9, when the voltage difference ΔVt between the voltage level command Vttlr and the output voltage command value Voutr increases, the voltage level command Vttlr is updated and the control timing of the switching pattern is set. In the example of Fig. 11, the voltage level command Vttlr is updated at each of times t0 to t4, and the combination of the switching patterns of the main converter 101 and the cells 102_1 to 102_n is determined according to the control process of Fig. 8.

[0109] For example, at time t0, a combination of switching patterns that increases the capacitor voltage Vc3 while decreasing the capacitor voltages Vc1 and Vc2 is selected from the multiple combinations of switching patterns corresponding to the updated voltage level command Vttlr. The combination of switching patterns determined at time t1 is maintained until the next control timing arrives at time t2.

[0110] 11, after the combination of switching patterns is set at time t3, the capacitor voltage Vc1 rises and reaches Vc1=Vmax[pu] at time t3x. If the combination of switching patterns determined at time t3 is maintained after time t3x, Vc1>Vmax[pu], and there is a concern that the voltage error ΔV at cell 102_1 will become excessive.

[0111] Therefore, in the power conversion device according to the modified example of the first embodiment, in addition to the timing of updating the voltage level command Vttlr in response to a change in the output voltage command value Voutr, as in FIG. 9 , a control timing of the switching pattern is also set when a voltage error occurs in any of the cells 102, causing the capacitor voltage Vc to deviate from a predetermined upper or lower limit value.

[0112] Fig. 12 shows a flowchart illustrating the control timing determination process according to Modification 1 of Embodiment 1. That is, in Modification 1 of Embodiment 1, the process of S100 is executed in accordance with the flowchart of Fig. 12 during the control process of Fig. 8.

[0113] As shown in FIG. 12, in the first modification of the first embodiment, S100 (FIG. 8) includes S111 to S114.

[0114] In S111, the controller 120 determines whether the capacitor voltage Vc is outside the upper or lower limit value in any of the n cells 102. For example, as illustrated in FIG. 11, the determination in S111 can be made by comparing the capacitor voltages Vc1 to Vc3 in [pu] with the upper limit value Vcmax and the lower limit value Vcmin.

[0115] If the capacitor voltage Vc of any of the n cells 102 falls outside the upper or lower limit (YES in S111), the controller 120 proceeds to S113 and determines YES in S100 to set control timing. On the other hand, if the capacitor voltage Vc of all of the n cells 102 is within the range of the upper or lower limit (NO in S111), the controller 120 proceeds to S112.

[0116] In S112, the controller 120 determines whether the voltage difference ΔVt between the current voltage level command Vttlr and the current output voltage command value Voutr reaches the determination value Va, as described in Fig. 9. If ΔVt≧Va (YES determination in S112), the process proceeds to S113, and a YES determination is made in S100. On the other hand, while ΔVt<Va (NO determination in S112), the process proceeds to S114, and a NO determination is made in S100.

[0117] 8, when the determination in S100 is YES, the process proceeds to S110 and thereafter, whereby the control timing of the switching pattern is set. On the other hand, when the determination in S100 is NO, the control timing is not set, and the determination in S100 is repeatedly executed.

[0118] In the first embodiment, S100 in Fig. 8 can be configured by S112 to S114 in Fig. 12. That is, in a modification of the first embodiment, in the form of an interrupt process for the control timing setting in the first embodiment (Fig. 9), a control timing for the switching pattern can be set when the capacitor voltage Vc in any of the n cells 102 falls outside the upper or lower limit. Note that when the control timing is set by the interrupt process, the voltage level command Vttlr is not updated in S110 (Fig. 8), and the combination pattern selection in S120 to S190 is re-executed.

[0119] Referring again to FIG. 11, by providing control timing according to the flowchart of FIG. 12, it is possible to provide control timing for the switching pattern not only at times t0, t1, t2, t3, and t4 when S112 is determined to be YES, but also at time t3x between times t3 and t4 when the capacitor voltage Vc1 reaches the upper limit value Vcmax.

[0120] As a result, at time t3x, the combination of switching patterns of the main converter 101 and the cells 102_1 to 102_n is changed so that, from the multiple combination patterns corresponding to the same voltage level command Vttlr as at time t3, a combination in which the cell 102_1 performs positive voltage operation and reduces the capacitor voltage Vc1 is selected. Accordingly, at time t3x, the capacitor voltage Vc1 begins to decrease, thereby preventing the voltage error from increasing.

[0121] That is, in the first modification of the first embodiment, it is preferable that the cell 102 that caused the interrupt process be given the highest priority in the process of determining the priority of cell voltage control in S130 of FIG.

[0122] In this way, in the power conversion device according to the first variant of the first embodiment, in addition to the effects of the power conversion device according to the first embodiment, it is possible to suppress excessive voltage errors in the capacitor voltage Vc in each cell 102.

[0123] In the example of Figure 11, a common upper limit value Vcmax [pu] and lower limit value Vcmin [pu] are set for each cell 102, but the upper limit value Vcmax [pu] and lower limit value Vcmin [pu] may be set to different values ​​between at least some of the cells 102.

[0124] Variation 2 of Embodiment 1. In the selection control of the switching pattern for output voltage control and cell voltage control described in Embodiment 1 and Variation 1, the switching pattern, i.e., the on / off of the switching elements 107a to 107d, is switched for at least some of the cells 102 at each control timing. Generally, when the switching elements 107a to 107d are switched on and off, a dead time is provided in which both of the two switching elements in the same leg are turned off to prevent a short circuit between the high-voltage line PL and the low-voltage line NL. However, there is a concern that during this dead time, the output voltage of the cell 102 may differ from the voltage in the commanded operation, thereby affecting the total output voltage Vttl.

[0125] On the other hand, as already explained, there are two switching patterns shown in Fig. 4(c) and Fig. 4(d) for each cell 102 to output zero voltage. Therefore, for a cell 102 for which zero voltage operation has been determined by output voltage control and cell voltage control, one of the two switching patterns can be selected.

[0126] Therefore, in the second modification of the first embodiment, a description will be given of the selection of a switching pattern that suppresses the influence of dead time in the cell 102 that performs the zero voltage operation.

[0127] FIG. 13 is a conceptual diagram illustrating the influence of the dead time when transitioning from a switching pattern that outputs zero voltage to a switching pattern that outputs a positive voltage.

[0128] As shown in Figure 13(a), in the switching pattern (positive voltage operation) for outputting a positive voltage (+Vc) from each cell 102, switching elements 107b and 107c are turned on, while switching elements 107a and 107d are turned off. This results in the cell output voltage Vt = Vc, accompanied by a current Ia that discharges the capacitor 108. The switching pattern shown in Figure 13(a) is the same as the switching pattern in Figure 4(a).

[0129] The switching patterns during zero voltage operation of each cell 102 include a first zero voltage switching pattern shown in Fig. 13(b) and a second zero voltage switching pattern shown in Fig. 13(c). The switching pattern shown in Fig. 13(b) is the same as the switching pattern in Fig. 4(c), and the switching pattern shown in Fig. 13(c) is the same as the switching pattern in Fig. 4(d).

[0130] In the first zero voltage switching pattern shown in FIG. 13(b), the upper switching elements 107a and 107c of each leg are turned on, thereby forming a path for current Ic between nodes Na and Nb that does not charge or discharge capacitor 108.

[0131] In the second zero voltage switching pattern shown in FIG. 13(c), the lower switching elements 107d, 107d of each leg are turned on, thereby forming a path for current Id between nodes Na and Nb that does not charge or discharge capacitor 108.

[0132] When switching the cell 102 from zero voltage operation (FIG. 13(b)) according to the first zero voltage switching pattern to positive voltage operation (FIG. 13(a)), the switching elements 107a and 107b of the leg on the node Na side are switched on and off. Therefore, after the switching element 107a is turned off, a dead time is provided, and then the switching element 107b is turned on, thereby realizing a transition to the switching pattern of FIG. 13(a).

[0133] For example, consider the case where dead time is applied only to the upper switching elements 107a and 107c. In this case, in FIG. 13(b), commutation occurs in response to the turning on of switching element 107b, causing a transition from the path of current Ic to the path of current Ia. Therefore, a positive voltage (+Vc) can be output without being affected by the dead time.

[0134] In contrast, when switching the cell 102 from zero voltage operation ( FIG. 13(c) ) according to the second zero voltage switching pattern to positive voltage operation ( FIG. 13(a) ), the switching elements 107c and 107d of the leg on the node Nb side are switched on and off. Therefore, after the switching element 107d is turned off, a dead time is provided, and then the switching element 107c is turned on, thereby realizing a transition to the switching pattern of FIG. 13(a) .

[0135] In this case, in Fig. 13(c), no commutation occurs when switching element 107d is turned off, and the path of current Id is maintained by the anti-parallel diode. Then, in Fig. 13(a), commutation occurs in response to turning on switching element 107c, causing a transition from the path of current Id to the path of current Ia. Therefore, current Ia does not flow during the dead time period, and the output of positive voltage (+Vc) is delayed by the amount of the dead time.

[0136] Therefore, for example, when a dead time is applied only to the upper switching elements 107 a and 107 c, in order to transition to a switching pattern that outputs a positive voltage, it is preferable to select the switching pattern of FIG. 13( b) in which the upper switching elements 107 a and 107 c of each leg are turned on as a switching pattern that outputs zero voltage.

[0137] Conversely, for transition from the zero voltage operation to the negative voltage operation switching pattern, although not illustrated, it is preferable to select the switching pattern of FIG. 13( c) in which the lower switching elements 107 b and 107 d of each leg are turned on as the switching pattern during zero voltage operation.

[0138] Furthermore, even when the dead time is applied only to the lower switching elements 107c and 107d, it is possible to determine whether it is preferable to select Figure 13(b) or Figure 13(c) in zero voltage operation by focusing on which switching element is turned on in response to which commutation occurs in each of the transitions of the switching pattern from zero voltage operation to positive voltage operation and the transition of the switching pattern from zero voltage operation to negative voltage operation.

[0139] FIG. 14 is a flowchart illustrating a process of setting a switching pattern in each cell in a power conversion device according to the second modification of the first embodiment.

[0140] The control process shown in FIG. 14 is executed by the controller 120 for each cell 102 after the operation (positive voltage operation / negative voltage operation / zero voltage operation) of the main converter 101 and each of the cells 102_1 to 102_n is determined in S195 of FIG. 8.

[0141] As shown in FIG. 15, the controller 120 determines in S210 whether the operation determined for the cell 102 is zero voltage operation, and if it is zero voltage operation (YES in S210), compares the current capacitor voltage Vc (detected value) with the cell voltage command value Vc* in S220.

[0142] When the capacitor voltage Vc (detected value) is higher than the cell voltage command value Vc*, it can be assumed that the cell 102 is more likely to perform a discharge operation than a charge operation after the zero voltage operation ends. Therefore, when Vc>Vc* (YES in S220), the process proceeds to S240, and the switching pattern of Figure 4(c) (Figure 13(b)) that can suppress the dead time effect when transitioning to a discharge operation (positive voltage operation) is selected from the two switching patterns of Figure 4(c) (Figure 13(b)) and Figure 4(d) (Figure 13(c)) for zero voltage operation.

[0143] Conversely, when the capacitor voltage Vc (detected value) is lower than the cell voltage command value Vc*, it can be assumed that the cell 102 is more likely to perform a charging operation than a discharging operation after the zero voltage operation ends. Therefore, when Vc≦Vc* (NO in S230), the process proceeds to S250, and the switching pattern in FIG. 4(d) (FIG. 13(c)), which can suppress the dead time effect when transitioning to a charging operation (negative voltage operation), is selected from the two switching patterns in FIG. 4(c) (FIG. 13(b)) and FIG. 4(d) (FIG. 13(c)) for zero voltage operation.

[0144] If the operation determined for cell 102 is not zero voltage operation (NO in S210), S230 determines whether positive voltage operation has been determined. As described with reference to FIG. 4, there is only one switching pattern for positive voltage operation and one for negative voltage operation. Therefore, if positive voltage operation has been determined (YES in S230), S270 selects the switching pattern shown in FIG. 4(a). On the other hand, if negative voltage operation has been determined (NO in S230), S260 selects the switching pattern shown in FIG. 4(b).

[0145] In this way, according to the power conversion device of the second modification of the first embodiment, during zero voltage operation in which two switching patterns can be selected, it is possible to suppress the influence of the dead time provided when transitioning to positive voltage operation or negative voltage operation on the error in the total output voltage Vttl.

[0146] Second Embodiment In the first embodiment and the first modification, the combination of operations (switching patterns) of each cell 102 is determined by narrowing down from a plurality of patterns corresponding to the voltage level command Vttlr, on the premise that the capacitor voltage Vc of each cell 102 is approximately equal to the cell voltage command value Vc*.

[0147] Therefore, if the error of the capacitor voltage Vc with respect to the cell voltage command value Vc* is large, the voltage error between the total output voltage Vttl and the voltage level command Vttlr may be large in the combination pattern (S195) determined in accordance with the first embodiment and the first modification. In the second embodiment, a correction process for the combination pattern determined in accordance with the first embodiment and the first modification will be described.

[0148] FIG. 15 is a flowchart illustrating a process for setting a switching pattern in each cell in the power conversion device according to the second embodiment.

[0149] The control process shown in FIG. 15 is executed by the controller 120 after the combination of the switching patterns of the main converter 101 and the cells 102_1 to 102_n is determined in S195 of FIG.

[0150] In S310, the controller 120 calculates a total output voltage estimate Vttl# based on the current capacitor voltage Vc using the determined combination of switching patterns, i.e., the operation of each cell 102 (positive voltage output / negative voltage output / zero voltage output) and the capacitor voltage Vc (detected value) of each cell 102.

[0151] In S320, the controller 120 calculates a voltage error ΔVttl (ΔVttl=Vttl#-Vttlr) between the total output voltage estimate value Vttl# calculated in S310 and the voltage level command Vttlr, and in S330 compares the absolute value of the voltage error ΔVttl with a threshold value Ver.

[0152] If |ΔVttl| > Ver (YES in S330), the controller 120 determines whether ΔVttl is positive or negative in S340. If ΔVttl > 0 (YES in S340), the controller 120 generates a correction pattern in S350 by changing the combination of the switching patterns of the cells 102 so as to reduce the total output voltage Vttl.

[0153] Conversely, when ΔVttl<0 (NO in S340), the controller 120 generates a correction pattern in S360 by changing the combination of the switching patterns of the cells 102 in a direction that increases the total output voltage Vttl.

[0154] The method for generating the correction pattern in S350 and S360 is arbitrary, but the total output voltage estimated value Vttl# can be calculated for the corrected pattern in the same way as in S310, so that a correction pattern in which the voltage error ΔVttl is reduced can be obtained.

[0155] For example, among n cells 102_1 to 102_n arranged in the order in which the cell voltage command value Vc* gradually decreases, by switching the operation (positive voltage operation / negative voltage operation / zero voltage operation) between two adjacent cells 102, correction pattern candidates can be created. Since multiple correction pattern candidates are created by selecting two cells 102 for which the operation patterns are to be switched, one correction pattern can be determined by comparing the estimated total output voltage value Vttl# for each correction pattern.

[0156] When determining the correction pattern, it is preferable to prioritize the cells 102 with a low priority for capacitor voltage control determined in S130 (Figure 8) within the range of |ΔVttl|≦Ver as the target for replacing the operation pattern.

[0157] In S330, if |ΔVttl|≦Ver (NO in S330), the controller 120 skips the processes of S340 to S360. As a result, the pattern determined in S195 of FIG. 8, i.e., the combination of the switching patterns of the main converter 101 and the cells 102_1 to 102_n, is maintained.

[0158] According to the power conversion device of embodiment 2, in addition to the effects of embodiment 1 and its variant example 1, it is possible to suppress the voltage error of the total output voltage Vttl caused by the error of the capacitor voltage Vc relative to the cell voltage command value Vc*.

[0159] Furthermore, in the second embodiment, for a cell 102 for which zero voltage operation has been determined in the correction pattern generated in S350 and S360, it is also possible to select a switching pattern depending on the level of the capacitor voltage Vc and the cell voltage command value Vc*, as in the second variant of the first embodiment.

[0160] Although the output voltage command value Voutr has been described as a sinusoidal voltage in the present embodiment, the output voltage command value Voutr may be set according to any voltage waveform that changes over time. For example, the output voltage command value Voutr may be set according to a DC voltage waveform that changes only within a range of positive voltage or negative voltage.

[0161] Furthermore, the configuration of the cell 102 described in this embodiment is an example, and any circuit configuration capable of selectively outputting a positive voltage, a negative voltage, and a zero voltage according to the switching pattern can be applied. The circuit configuration of the main converter 101 in this embodiment is also an example, and any circuit configuration capable of selectively outputting a positive voltage, a negative voltage, and a zero voltage can be applied. Alternatively, in cases such as when the output voltage command value Voutr is a DC voltage, the main converter 101 can be applied with any circuit configuration capable of selectively outputting a positive voltage or a negative voltage, and a zero voltage.

[0162] Alternatively, the power conversion device according to this embodiment may be configured without the main converter 101. In the power conversion device 10 illustrated in FIG. 1 , the main converter 101 having a DC power supply is provided to supply charging power to the capacitor 108 of each cell 102. However, considering that the charging and discharging operations of the capacitor 108 are reversed even when the current of each cell 102 is reversed as described in FIG. 4 , it is understood that similar switching pattern selection control can be performed even when the output current Io flows from the load 200 to the power conversion device 10 (Io<0). Therefore, if the load 200 has a power generation function and a period occurs in which the output current Io<0, charging power for the capacitor 108 of each cell 102 can be secured by power from the load 200, and therefore the main converter 101 may be omitted.

[0163] In each embodiment and its modified examples, the switching pattern selection control has been described for the case where the current direction in the cell 102 is as shown in Figures 4(a) to 4(d). However, similar switching pattern selection control can also be performed when the current direction is opposite. As described above, when the current direction in the cell 102 is reversed, the capacitor 108 is charged by positive voltage operation, while the capacitor 108 is discharged by negative voltage operation, as opposed to Figures 4(a) and 4(b). Taking this into consideration, by appropriately changing the selection of the switching pattern in the cell 102 for cell voltage control from the examples described above, it is possible to achieve switching pattern selection control that achieves the same effect.

[0164] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0165] 10 Power conversion device, 100 Switching circuit, 101 Main converter, 102 Cell, 103 Linear circuit, 104N, 104P DC power supply, 105N, 105P, 106a, 106b, 107a to 107d Switching element, 108 Capacitor, 109 Output end, 110a, 110b Semiconductor element, 113 Current detector, 114 Voltage detector, 120 Controller, 200 Load, Ia to Id Current, Io Output current, NL Low voltage line, Na, Nb Node, Np Neutral point, PL High voltage line, PT1 to PT4 Combination pattern, PTa to PTc Switching pattern (main converter), Vc*, Vc1* to Vcn* Cell voltage command value, Vc, Vc1 to Vcn Capacitor voltage, Vcmax Upper limit value (capacitor voltage), Vcmin lower limit value (capacitor voltage), Vout output voltage (power conversion device), Voutr output voltage command value, Vt, Vt1 to Vt3, Vtn cell output voltages, Vttl total output voltage, Vttl# total output voltage estimated value, Vttlr voltage level command.

Claims

1. A power conversion device in which an output voltage command value changes over time, comprising: a switching circuit including n cells (n: an integer of 2 or more) connected in series, each of the n cells including a plurality of first semiconductor switching elements and an energy storage element, and configured to select, according to a switching pattern of the plurality of first semiconductor switching elements, a first operation of outputting a positive voltage according to a DC voltage of the energy storage element by discharging or charging the energy storage element, a second operation of outputting a negative voltage according to the DC voltage of the energy storage element by charging or discharging the energy storage element inversely to the first operation, and a third operation of outputting a zero voltage without charging or discharging the energy storage element, and further comprising a controller that determines a combination pattern of operations of the n cells and controls the switching pattern of each of the n cells in accordance with the combination pattern in order to control the output voltage of the power conversion device, wherein the controller: determines a priority order of voltage control of the energy storage element among the n cells based on a degree of deviation of a voltage detection value of the energy storage element from a cell voltage command value of the energy storage element in each of the n cells, and A power conversion device that controls the switching pattern of each of the n cells according to one combination pattern selected from a plurality of combination patterns for matching the total output voltage of the switching circuit to a voltage command level set according to the output voltage command value, such that an operation of reducing a voltage deviation of the voltage detection value from the cell voltage command value is performed in the cell having a high priority.

2. A power conversion device as described in claim 1, wherein the controller determines the priority order among the n cells by treating the degree of deviation as being greater the greater the product of a weighting coefficient predetermined for the n cells and the deviation between the cell voltage command value and the voltage detection value.

3. The power conversion device according to claim 2, wherein the cell voltage command values ​​are set to different values ​​among the n cells, and the weighting coefficient is set to a larger value as the cell voltage command value is higher.

4. The power conversion device according to claim 2 or 3, wherein the capacity values ​​of the energy storage elements differ among at least some of the n cells, and the weighting coefficients are set to reflect the differences in the capacity values.

5. A power conversion device as described in any one of claims 1 to 4, wherein the controller operates to determine the priority and select one of the combination patterns to provide control timing for switching the switching pattern each time a difference between the current voltage command level and the output voltage command value reaches a predetermined judgment value.

6. The power conversion device according to claim 5, wherein said controller is operable to further provide said control timing when said voltage deviation in any of said n cells reaches a predetermined upper or lower limit value.

7. A power conversion device as claimed in any one of claims 1 to 6, wherein each of the n cells is configured to have a plurality of switching patterns capable of outputting the zero voltage, and the controller selects a different one of the switching patterns in the cell performing the third operation depending on the magnitude relationship between the cell voltage command value of the energy storage element and the voltage detection value.

8. A power conversion device as described in any one of claims 1 to 7, wherein the controller calculates an estimate of the total output voltage using a selected combination pattern and the voltage detection values ​​of the energy storage elements of each of the n cells, and when a voltage error between the voltage command level and the estimate is greater than a predetermined threshold, executes a correction process to switch the operation of at least a portion of the n cells from the one selected combination pattern so as to reduce the voltage error.

9. A power conversion device according to any one of claims 1 to 8, wherein the cell voltage command values ​​among the n cells are set to different values ​​according to an inverse ratio of a power ratio of 2 or 3.

10. A power conversion device as claimed in any one of claims 1 to 9, wherein the switching circuit further comprises a main converter connected in series with the n cells, the main converter being configured to include at least one DC power source and a plurality of second semiconductor switching elements, and configured to select at least one of an operation to output a positive voltage and an operation to output a negative voltage, and an operation to output a zero voltage, depending on a switching pattern of the plurality of second semiconductor switching elements, and the total output voltage is the sum of the output voltage of the main converter and the output voltage of each of the n cells.

11. A power conversion device as claimed in any one of claims 1 to 10, further comprising: a linear circuit connected between a load and the switching circuit, the resistance value of which is variably controlled by the controller; and a current detector that detects an output current supplied from the switching circuit to the load via the linear circuit, wherein the controller controls the resistance value of the linear circuit based on the detected value of the output current so that a voltage drop amount equivalent to a voltage difference between the output voltage command value and the total output voltage occurs in the linear circuit.

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