Nitride semiconductor device

Abstract

A nitride semiconductor device (1) comprises: a substrate (10); a channel layer (22) that contains a nitride semiconductor as a main component; a vertical GaN transistor (2) that performs a normally-on operation; and a lateral GaN transistor (3) that performs a normally-off operation. The vertical GaN transistor (2) includes a first part (22a) of the channel layer (22), a gate electrode (37) provided above the first part (22a), and a drain electrode (44) provided below the substrate (10). The lateral GaN transistor (3) includes a second part (22b) of the channel layer (22), a gate electrode (38) provided above the second part (22b), and a source electrode (42) provided above the substrate (10). The gate electrode (37) and the source electrode (42) are electrically connected. The source potential of the vertical GaN transistor (2) and the drain potential of the lateral GaN transistor (3) are equal.

Description

Nitride Semiconductor Devices

[0001] The present disclosure relates to nitride semiconductor devices.

[0002] Nitride semiconductors, typified by GaN (gallium nitride), are wide bandgap semiconductors that have the advantage of a higher breakdown field and a higher electron saturation drift velocity than existing semiconductors such as Si (silicon) and GaAs (gallium arsenide). This makes them advantageous for achieving higher voltage resistance, higher output, and higher speeds, and research and development of power transistors using nitride semiconductors is being actively pursued.

[0003] For example, Patent Document 1 discloses a vertical field effect transistor (FET) including a regrowth layer positioned so as to cover an opening provided in a GaN-based stacked body, and a gate electrode positioned on the regrowth layer along the regrowth layer. A channel is formed by two-dimensional electron gas (2DEG) generated in the regrowth layer. Vertical FETs are generally more suitable for large current operation than lateral FETs. However, they have a problem in that they are not suitable for high-speed switching due to their large gate-drain capacitance (feedback capacitance).

[0004] To achieve high-current and high-speed switching, Non-Patent Document 1 discloses a configuration in which a vertical FET made of SiC material and a low-voltage lateral FET made of GaN material are cascode-connected. With this configuration, the switching speed is primarily determined by the low-voltage lateral FET, enabling high-speed switching. Furthermore, while current flows through both the vertical FET and the low-voltage lateral FET, high-current operation is easy if the lateral FET is also designed for low voltage. Therefore, a cascode-connected device can operate at high current. As described above, by using a cascode-connected high-current vertical FET and a low-voltage lateral FET, both high-speed switching and high-current operation can be achieved.

[0005] Patent No. 6511645

[0006] G. Lyu. et al., “A Normally-OFF Copackaged SiC-JFET / GaN-HEMT Cascode Device for High-Voltage and High-Frequency Applications”, IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL.35, NO.9, SEPTEMBER 2020, pp.9669-9679

[0007] In the configuration of Non-Patent Document 1, the vertical FET and the lateral FET are made of different materials, so the FETs must be fabricated individually and electrically connected during packaging. This creates a problem of large parasitic inductance between the vertical FET and the lateral FET, making stable operation difficult during high-speed operation due to the influence of the parasitic inductance. While it is possible to reduce the parasitic inductance to some extent by packaging the vertical FET and the lateral FET close to each other, a smaller parasitic inductance is more advantageous for stable operation under all operating conditions.

[0008] Therefore, the present disclosure provides a nitride semiconductor device that can achieve high-current and high-speed switching with stable operation.

[0009] a nitride semiconductor device according to one aspect of the present disclosure comprising: a substrate; a channel layer provided above the substrate and containing a nitride semiconductor as a main component; a vertical transistor that operates normally and is provided in a first region of the substrate in a planar view; and a lateral transistor that operates normally and is provided in a second region of the substrate different from the first region in a planar view, wherein the vertical transistor includes a first portion that is a part of the channel layer and overlaps the first region in a planar view of the substrate, a first gate electrode provided above the first portion, and a first drain electrode provided below the substrate; and the lateral transistor includes a second portion that is a part of the channel layer and overlaps the second region in a planar view of the substrate, a second gate electrode provided above the second portion, and a second source electrode provided above the substrate, wherein the first gate electrode and the second source electrode are electrically connected, and a source potential of the vertical transistor and a drain potential of the lateral transistor are the same potential.

[0010] According to the present disclosure, it is possible to achieve large current and high speed switching with stable operation.

[0011] FIG. 1 is a cross-sectional view of a nitride semiconductor device according to the first embodiment. FIG. 2 is a circuit diagram of the nitride semiconductor device according to the first embodiment. FIG. 3 is a plan view of the nitride semiconductor device according to the first embodiment. FIG. 4 is a cross-sectional view of a nitride semiconductor device according to a first modification of the first embodiment. FIG. 5 is a cross-sectional view of a nitride semiconductor device according to a second modification of the first embodiment. FIG. 6 is a cross-sectional view of a nitride semiconductor device according to a third modification of the first embodiment. FIG. 7 is a cross-sectional view of a nitride semiconductor device according to a fourth modification of the first embodiment. FIG. 8 is a circuit diagram of a nitride semiconductor device according to a fifth modification of the first embodiment. FIG. 9 is a cross-sectional view of a nitride semiconductor device according to the fifth modification of the first embodiment. FIG. 10 is a plan view of a nitride semiconductor device according to the fifth modification of the first embodiment. FIG. 11 is a plan view of a nitride semiconductor device according to the second embodiment. FIG. 12 is a cross-sectional view of a nitride semiconductor device according to the second embodiment. FIG. 13 is a cross-sectional view of a nitride semiconductor device according to the first modification of the second embodiment. FIG. 14 is a cross-sectional view of a nitride semiconductor device according to the second modification of the second embodiment.

[0012] (Summary of the Disclosure) a nitride semiconductor device according to a first aspect of the present disclosure comprising: a substrate; a channel layer provided above the substrate and containing a nitride semiconductor as a main component; a vertical transistor that operates normally and is provided in a first region of the substrate in a planar view; and a lateral transistor that operates normally and is provided in a second region of the substrate different from the first region in a planar view, wherein the vertical transistor includes a first portion that is a part of the channel layer and overlaps the first region in a planar view of the substrate, a first gate electrode provided above the first portion, and a first drain electrode provided below the substrate; and the lateral transistor includes a second portion that is a part of the channel layer and overlaps the second region in a planar view of the substrate, a second gate electrode provided above the second portion, and a second source electrode provided above the substrate, wherein the first gate electrode and the second source electrode are electrically connected, and a source potential of the vertical transistor and a drain potential of the lateral transistor are the same potential.

[0013] This allows the cascode-connected vertical and horizontal transistors to be provided on the same substrate, thereby suppressing the parasitic inductance of the interconnections between the vertical and horizontal transistors, and thus the nitride semiconductor device according to this aspect can achieve stable operation with high current and high speed switching.

[0014] A nitride semiconductor device according to a second aspect of the present disclosure is the nitride semiconductor device according to the first aspect, comprising: a first nitride semiconductor layer of a first conductivity type provided between the substrate and the channel layer; and a second nitride semiconductor layer of a second conductivity type opposite in polarity to the first conductivity type provided between the first nitride semiconductor layer and the channel layer.

[0015] This makes it possible to suppress leakage current flowing between the first drain electrode and the second source electrode. Also, the depletion layer formed by the pn junction between the first nitride semiconductor layer and the second nitride semiconductor layer makes it possible to increase the breakdown voltage of the vertical transistor.

[0016] A nitride semiconductor device according to a third aspect of the present disclosure is the nitride semiconductor device according to the second aspect, wherein the vertical transistor includes a first source electrode set to the source potential, and the lateral transistor includes a second drain electrode set to the drain potential.

[0017] As a result, for example, by using a highly conductive material as the electrode material, the vertical transistor and the lateral transistor can be connected with low resistance, and the on-resistance of the nitride semiconductor device can be reduced.

[0018] A nitride semiconductor device according to a fourth aspect of the present disclosure is the nitride semiconductor device according to the third aspect, wherein a portion of the second nitride semiconductor layer that overlaps the first region and a portion that overlaps the second region in a plan view of the substrate are electrically separated.

[0019] This allows different potentials to be applied to the vertical transistor and the lateral transistor when applying a predetermined potential to the second nitride semiconductor layer, making it possible to apply potentials suitable for realizing the respective characteristics of a high-voltage vertical transistor and a low-voltage lateral transistor capable of high-speed operation.

[0020] A nitride semiconductor device according to a fifth aspect of the present disclosure is the nitride semiconductor device according to the fourth aspect, wherein a portion of the second nitride semiconductor layer that overlaps the second region in a planar view of the substrate is electrically connected to the second source electrode.

[0021] As a result, the second nitride semiconductor layer, which is set to the source potential of the lateral transistor, is disposed between the second gate electrode and the first drain electrode, thereby suppressing leakage current flowing from the first drain electrode of the vertical transistor to each electrode of the lateral transistor.

[0022] A nitride semiconductor device according to a sixth aspect of the present disclosure is the nitride semiconductor device according to the fourth or fifth aspect, wherein a portion of the second nitride semiconductor layer that overlaps the first region in a planar view of the substrate is electrically connected to the first source electrode.

[0023] As a result, the second nitride semiconductor layer, which is set to the source potential of the vertical transistor, is disposed between the first gate electrode and the first drain electrode, thereby mitigating the electric field strength applied between the gate and drain and further increasing the breakdown voltage of the vertical transistor.

[0024] A nitride semiconductor device according to a seventh aspect of the present disclosure is the nitride semiconductor device according to the fourth or fifth aspect, wherein a portion of the second nitride semiconductor layer that overlaps the first region in a planar view of the substrate is electrically connected to the first gate electrode.

[0025] As a result, the second nitride semiconductor layer, which is set to the gate potential of the vertical transistor, is disposed between the first source electrode and the first drain electrode, thereby reducing the drain-source capacitance of the vertical transistor, thereby lowering the source potential of the vertical transistor and the drain potential of the lateral transistor, enabling faster switching operation.

[0026] A nitride semiconductor device according to an eighth aspect of the present disclosure is the nitride semiconductor device according to any one of the first to seventh aspects, wherein the channel layer includes a stacked structure of a GaN layer and an AlGaN layer.

[0027] This allows the two-dimensional electron gas generated near the heterointerface between GaN and AlGaN to be used as a current path, thereby realizing a nitride semiconductor device suitable for high output and / or high-speed switching.

[0028] A nitride semiconductor device according to a ninth aspect of the present disclosure is the nitride semiconductor device according to any one of the first to eighth aspects, further comprising a third nitride semiconductor layer or insulating layer of a second conductivity type opposite to the first conductivity type, disposed between the first gate electrode and the first portion.

[0029] This makes it possible to adjust the threshold voltage of the vertical transistor by adjusting the thickness or material of the third nitride semiconductor layer or the insulating layer, etc. For example, a vertical transistor that operates normally can be easily realized.

[0030] A nitride semiconductor device according to a tenth aspect of the present disclosure is a nitride semiconductor device according to any one of the first to ninth aspects, comprising a fourth nitride semiconductor layer of a second conductivity type opposite to the first conductivity type, disposed between the second gate electrode and the second portion.

[0031] This makes it possible to adjust the threshold voltage of the lateral transistor by adjusting the thickness or material of the fourth nitride semiconductor layer or the insulating layer, etc. For example, a lateral transistor that operates normally-off can be easily realized.

[0032] A nitride semiconductor device according to an eleventh aspect of the present disclosure is a nitride semiconductor device according to any one of the first to tenth aspects, wherein the second portion includes an impurity region provided in a range overlapping with the second gate electrode in a planar view of the substrate, and the second gate electrode is electrically connected to the impurity region.

[0033] This makes it possible to adjust the threshold voltage of the vertical transistor by adjusting the thickness of the impurity region, the impurity material, etc. For example, a lateral transistor that operates normally off can be easily realized.

[0034] A nitride semiconductor device according to a twelfth aspect of the present disclosure is a nitride semiconductor device according to any one of the third to seventh aspects, comprising a source wiring electrically connected to the second source electrode and a drain wiring electrically connected to the second drain electrode, and in a planar view of the substrate, the source wiring and the drain wiring partially overlap each other.

[0035] This increases the drain-source capacitance of the lateral transistor, which allows the drain potential of the lateral transistor to be lowered, thereby enabling faster switching.

[0036] A nitride semiconductor device according to a thirteenth aspect of the present disclosure is the nitride semiconductor device according to any one of the third to seventh aspects, comprising a PN diode including an electrode connected to the second drain electrode, and a fifth nitride semiconductor layer of the second conductivity type provided between the electrode and the channel layer.

[0037] This allows the intermediate potential at the connection point between the vertical transistor and the horizontal transistor to be set to a desired value, and also prevents the horizontal transistor from being subjected to a voltage higher than the threshold voltage of the PN diode, thereby realizing a lower breakdown voltage and faster switching speed for the lateral transistor.

[0038] A nitride semiconductor device according to a fourteenth aspect of the present disclosure is the nitride semiconductor device according to the thirteenth aspect, further comprising a plurality of the PN diodes, the plurality of PN diodes being connected in series.

[0039] This allows the intermediate potential to be adjusted by changing the number of PN diodes connected in series.

[0040] A nitride semiconductor device according to a fifteenth aspect of the present disclosure is a nitride semiconductor device according to any one of the first to fourteenth aspects, comprising a plurality of the vertical transistors and a plurality of the horizontal transistors, wherein the plurality of vertical transistors are arranged adjacent to each other in a third region in a planar view of the substrate, and the plurality of lateral transistors are arranged adjacent to each other in a fourth region that does not overlap with the third region in a planar view of the substrate.

[0041] This allows multiple vertical transistors and multiple horizontal transistors to be arranged together. Placing transistors of the same type together makes it easier to design the interconnection layout. Reducing unnecessary wiring reduces parasitic inductance, enabling stable high-speed switching.

[0042] A nitride semiconductor device according to a sixteenth aspect of the present disclosure is a nitride semiconductor device according to any one of the first to fourteenth aspects, comprising a plurality of the vertical transistors and a plurality of the lateral transistors, the vertical transistors and the lateral transistors being arranged alternately in a planar view of the substrate.

[0043] This improves area efficiency, enabling the miniaturization of nitride semiconductor devices. In addition, the region directly below the lateral transistor can also be used as a current path for the drain current of the vertical transistor, reducing the on-resistance of the nitride semiconductor device.

[0044] A nitride semiconductor device according to a seventeenth aspect of the present disclosure is the nitride semiconductor device according to the second or third aspect, wherein the second source electrode is electrically connected to a portion of the second nitride semiconductor layer that overlaps the second region in a planar view of the substrate, and the second nitride semiconductor layer is not electrically separated between a portion that overlaps the first region and a portion that overlaps the second region in a planar view of the substrate.

[0045] As a result, even if the source electrode of the vertical transistor and the drain electrode of the lateral transistor are not provided, the potential of the second nitride semiconductor layer of the vertical transistor can be fixed to the gate potential of the vertical transistor. This reduces the drain-source capacitance of the vertical transistor, enabling faster switching. Furthermore, the area efficiency is improved, allowing for the miniaturization of nitride semiconductor devices.

[0046] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0047] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0048] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0049] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or perpendicular, terms indicating the shape of elements, such as rectangle or trapezoid, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0050] Furthermore, the side of the substrate on which the gate electrode and source electrode are provided is considered to be "upper" or "upper side", and the side of the substrate on which the drain electrode of the vertical FET is provided is considered to be "lower" or "lower side".

[0051] In this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms "above" and "below" are applied not only to a case where two components are arranged with a gap between them and another component exists between them, but also to a case where two components are arranged closely together and the two components are in contact with each other.

[0052] In this specification, the term "plan view" refers to a view perpendicular to the main surface of the substrate of the nitride semiconductor device, that is, a view of the main surface of the substrate from the front.

[0053] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0054] In this specification, AlGaN refers to a ternary mixed crystal Al ｘ Ga １－ｘ Hereinafter, multi-element mixed crystals are abbreviated by the arrangement of the symbols of the respective constituent elements, such as AlInN, GaInN, etc. For example, AlInN, which is an example of a nitride semiconductor, ｘ Ga １－ｘ－ｙ In ｙ N (0<x<1, 0<y<1, and 0<x+y<1) is abbreviated as AlGaInN.

[0055] First Embodiment [Outline] A nitride semiconductor device according to a first embodiment will be described with reference to Fig. 1. Fig. 1 is a cross-sectional view of a nitride semiconductor device 1 according to the present embodiment.

[0056] The nitride semiconductor device 1 is a device having a stacked structure of semiconductor layers whose main component is a nitride semiconductor such as GaN, and specifically has a heterostructure of an AlGaN film and a GaN film. The nitride semiconductor layers are generally formed by metalorganic vapor phase epitaxy (MOVPE), but can also be formed by other methods such as hydride vapor phase epitaxy (HVPE).

[0057] 1, a nitride semiconductor device 1 includes a vertical GaN transistor 2 and a lateral GaN transistor 3 formed on the same substrate. The vertical GaN transistor 2 and the lateral GaN transistor 3 are provided in different regions of the substrate in a plan view.

[0058] The vertical GaN transistor 2 is an example of a vertical transistor that includes a semiconductor layer whose main component is a nitride semiconductor. A vertical transistor is a transistor that allows current to flow mainly in a direction perpendicular to the main surface of the substrate. The vertical GaN transistor 2 operates in a normally-on mode.

[0059] The lateral GaN transistor 3 is an example of a lateral transistor that includes a semiconductor layer whose main component is a nitride semiconductor. A lateral transistor is a transistor that allows current to flow mainly in a direction parallel to the main surface of the substrate. The lateral GaN transistor 3 operates in a normally-off mode.

[0060] For example, the nitride semiconductor device 1 includes at least a substrate 10 having n-type conductivity, a drift layer 12 made of n-type GaN, a current blocking layer 16 made of p-type GaN, an electron transit layer 24 made of GaN, and an electron supply layer 26 made of AlGaN. A two-dimensional electron gas (2DEG) is induced near the interface between the electron supply layer 26 and the electron transit layer 24, and functions as a current path. In the example shown in FIG. 1 , a high-resistance layer 14 heavily doped with, for example, carbon (C) is provided below the current blocking layer 16. This reduces leakage current between the current blocking layer 16 and the substrate 10. The high-resistance layer 14 is not necessarily required.

[0061] In the vertical GaN transistor 2, a gate opening 20 is provided such that the current blocking layer 16 and a portion of the high-resistance layer 14 are completely removed to expose the drift layer 12. A channel layer 22 and a gate layer 28 made of p-type GaN are provided to cover the gate opening 20. A portion of the channel layer 22 is removed to expose the current blocking layer 16, to provide a source opening 34. A source electrode 40 is provided so as to contact the channel layer 22 exposed on the side surface of the source opening 34 and the current blocking layer 16 exposed on the bottom surface of the source opening 34. A gate electrode 37 is provided so as to contact the gate layer 28. A drain electrode 44 is provided so as to contact the lower surface of the substrate 10.

[0062] In the vertical GaN transistor 2, drain current flows from the drain electrode 44 through the substrate 10, drift layer 12, and channel layer 22 to the source electrode 40. The vertical GaN transistor 2 has a normally-on characteristic in which current flows even when the gate voltage is 0 V. The threshold voltage of the vertical GaN transistor 2 is, for example, −5 V. The vertical GaN transistor 2 performs a switching operation in which a drain current flows when the source potential and the gate potential are the same, and the drain current stops flowing when the gate potential is 5 V or more lower than the source potential.

[0063] In the lateral GaN transistor 3, a recess 30 is provided in the electron supply layer 26, thereby partially thinning the electron supply layer 26. A gate layer 32 made of p-type GaN is provided on at least a portion of the recess 30. Furthermore, a gate electrode 38 is provided in contact with the gate layer 32. A source electrode 42 and a drain electrode 46 are provided so as to sandwich the gate electrode 38 therebetween. A source opening 35 is provided by removing a portion of the channel layer 22 to expose the current blocking layer 16. The source electrode 42 is provided so as to contact the channel layer 22 exposed on the side surface of the source opening 35 and the current blocking layer 16 exposed on the bottom surface of the source opening 35. A drain opening 36 is provided by removing a portion of the electron supply layer 26 to expose the electron transit layer 24. The drain electrode 46 is provided so as to contact the electron transit layer 24 at the bottom surface of the drain opening 36. Note that the drain opening 36 may not be provided and the drain electrode 46 may be provided on the upper surface of the electron supply layer 26. The current blocking layer 16 and the drain electrode 46 are electrically separated by the electron transit layer 24. A field plate 54 electrically connected to the source electrode 42 is formed to cover the gate layer 32 and the gate electrode 38. This reduces the electric field strength applied to the gate end. However, if the electric field strength applied to the gate end is small, the field plate 54 does not need to be provided.

[0064] In the lateral GaN transistor 3, a drain current flows from the drain electrode 46 through the channel layer 22 to the source electrode 42. The lateral GaN transistor 3 has a normally-off characteristic in which no drain current flows when the gate potential and the source potential are the same. The threshold voltage of the lateral GaN transistor 3 is higher than the threshold voltage of the vertical GaN transistor 2, and is, for example, 2 V. The lateral GaN transistor 3 performs a switching operation in which no drain current flows when the gate potential is 0 V relative to the source potential of 0 V, but the drain current flows when the gate potential is 2 V or higher.

[0065] [Cross-Sectional Configuration] Next, a specific cross-sectional configuration of the nitride semiconductor device 1 will be described.

[0066] 1 , the nitride semiconductor device 1 includes a substrate 10, a drift layer 12, a high-resistance layer 14, a current blocking layer 16, a channel layer 22, gate layers 28 and 32, gate electrodes 37 and 38, source electrodes 40 and 42, drain electrodes 44 and 46, an insulating film 50, a wiring electrode 52, and a field plate 54. The channel layer 22 includes an electron transit layer 24 and an electron supply layer 26. The nitride semiconductor device 1 also includes a gate opening 20, source openings 34 and 35, and a drain opening 36.

[0067] In this embodiment, the substrate 10, the drift layer 12, the high-resistance layer 14, the current blocking layer 16, the channel layer 22, and the drain electrode 44 are provided across the first region 10 a and the second region 10 b. The first region 10 a and the second region 10 b are different regions from each other in a plan view of the substrate 10.

[0068] The first region 10a is a region where the vertical GaN transistor 2 is provided, specifically includes two source electrodes 40 arranged on either side of the gate electrode 37, and can be considered to be the region between the two source electrodes 40. The second region 10b is a region where the lateral GaN transistor 3 is provided, specifically includes a source electrode 42 and a drain electrode 46, and can be considered to be the region between them. For example, as shown in FIG. 1 , the current blocking layer 16, the channel layer 22, the electron transit layer 24, and the electron supply layer 26 each include first portions 16a, 22a, 24a, and 26a that overlap the first region 10a, and second portions 16b, 22b, 24b, and 26b that overlap the second region 10b, respectively.

[0069] The vertical GaN transistor 2 includes a first portion 22a that is a part of the channel layer 22. Specifically, the vertical GaN transistor 2 includes a stacked structure of a first portion 24a that is a part of the electron transit layer 24 and a first portion 26a that is a part of the electron supply layer 26. The vertical GaN transistor 2 also includes a first portion 16a that is a part of the current blocking layer 16. The vertical GaN transistor 2 further includes parts of the substrate 10 and the drift layer 12, a gate layer 28, a gate electrode 37, a source electrode 40, and a drain electrode 44.

[0070] The lateral GaN transistor 3 includes a second portion 22b that is a part of the channel layer 22. Specifically, the lateral GaN transistor 3 includes a stacked structure of a second portion 24b that is a part of the electron transit layer 24 and a second portion 26b that is a part of the electron supply layer 26. The lateral GaN transistor 3 also includes a second portion 16b that is a part of the current blocking layer 16. The lateral GaN transistor 3 further includes a gate layer 32, a gate electrode 38, a source electrode 42, and a drain electrode 46.

[0071] In this embodiment, the nitride semiconductor device 1 includes a wiring electrode 52 that connects the source electrode 40 of the vertical GaN transistor 2 and the drain electrode 46 of the lateral GaN transistor 3. An insulating film 50 is provided between the wiring electrode 52 and the gate electrode 37 and gate layer 28 of the vertical GaN transistor 2, and between the field plate 54 and the gate electrode 38 and gate layer 32 of the lateral GaN transistor 3. The insulating film 50 is provided so as to electrically isolate the current blocking layer 16 and the channel layer 22 between the vertical GaN transistor 2 and the lateral GaN transistor 3.

[0072] Each of the components of the nitride semiconductor device 1 will be described in detail below.

[0073] The substrate 10 is made of a nitride semiconductor and has two main surfaces, an upper surface and a lower surface, facing each other, as shown in FIG. 1 . The upper surface is the surface on which the drift layer 12 is provided. Specifically, the upper surface roughly coincides with the c-plane. The lower surface, also called the back surface, is the surface on which the drain electrode 44 is provided.

[0074] The substrate 10 has a thickness of, for example, 300 μm and a carrier concentration of 1×10 １８ cm －３ The substrate 10 is a substrate made of n-type GaN, where n is a nitride semiconductor. The substrate 10 does not have to be a nitride semiconductor substrate as long as it is conductive. For example, the substrate 10 may be a silicon (Si) substrate, a silicon carbide (SiC) substrate, or the like.

[0075] The n-type is an example of the first conductivity type. A state in which the concentration of n-type impurities is high, that is, a state in which the n-type impurities are heavily doped, is called n ＋ The concentration of n-type impurities is low, and the so-called lightly doped state is called n － The p-type is an example of a second conductivity type, which is the opposite polarity to the first conductivity type. A state in which the concentration of p-type impurities is high, or a so-called heavily doped state, is called a p-type. ＋ The concentration of p-type impurities is low, and the so-called lightly doped state is called p － These are also examples of the second conductivity type.

[0076] The drift layer 12 is an example of a first conductivity type first nitride semiconductor layer, and specifically, is a nitride semiconductor layer provided above the substrate 10 and having the same conductivity type as the substrate 10. The drift layer 12 is provided between the substrate 10 and the channel layer 22. The carrier concentration and film thickness of the drift layer 12 are important parameters that determine the breakdown voltage of the nitride semiconductor device 1, and are adjusted depending on the operating voltage. For example, when the rated voltage is 650 V, the drift layer 12 has a thickness of 8 μm and a carrier concentration of 1×10 １６ cm －３ An n-type GaN layer is provided on the substrate 10. The impurity that exhibits n-type conductivity is generally Si. The drift layer 12 is provided, for example, in contact with the upper surface of the substrate 10.

[0077] The high-resistance layer 14 is provided between the drift layer 12 and the current blocking layer 16. The high-resistance layer 14 is a GaN or AlGaN layer doped with a high concentration of C (carbon), but is not limited to this. The high-resistance layer 14 is provided in contact with the upper surface of the drift layer 12.

[0078] The current blocking layer 16 is an example of a second nitride semiconductor layer of a second conductivity type, and specifically, is a layer made of p-type GaN provided above the drift layer 12. The current blocking layer 16 is provided between the drift layer 12 and the channel layer 22. In this embodiment, the current blocking layer 16 is provided in contact with the upper surface of the high resistance layer 14. The current blocking layer 16 has a thickness of 300 nm and a carrier concentration of 1×10 １７ cm －３ In general, Mg can be used as the impurity that exhibits p-type conductivity. The current blocking layer 16 may be composed of multiple layers including at least a p-type semiconductor layer.

[0079] The vertical GaN transistor 2 has a gate opening 20 that penetrates the current blocking layer 16 and the high-resistance layer 14 to expose the drift layer 12. The side surfaces of the gate opening 20 are inclined with respect to the bottom surface of the gate opening 20, but may be perpendicular. A drain current flows from the drift layer 12 to the channel layer 22 through the bottom surface of the gate opening 20.

[0080] The channel layer 22 is provided to cover the inner surface of the gate opening 20 and the upper surface of the current blocking layer 16. Specifically, an electron transit layer 24 and an electron supply layer 26 are provided in this order. The electron transit layer 24 and the electron supply layer 26 are in contact with each other. Typically, the electron supply layer 26 is an AlGaN layer, and the electron transit layer 24 is a GaN layer. Both the electron supply layer 26 and the electron transit layer 24 are undoped layers, i.e., layers that are not intentionally doped with impurities. Note that "undoped" here means that the GaN is not doped with dopants such as Si or Mg that change the polarity of GaN to n-type or p-type, but also includes very small amounts of doping that do not contribute to conductivity. A high concentration of 2DEG is generated at the heterointerface between the electron supply layer 26 and the electron transit layer 24 due to spontaneous polarization or piezoelectric polarization on the (0001) plane. The 2DEG is a layer with high electron mobility, and this layer functions as a channel under the gate.

[0081] The concentration of the 2DEG is determined by the Al composition and film thickness of AlGaN constituting the electron supply layer 26, etc. The threshold voltage of the vertical GaN transistor 2 can be adjusted according to the concentration of the 2DEG. For example, the thinner the film thickness of the electron supply layer 26, the more the threshold voltage of the vertical GaN transistor 2 shifts to the positive side. The electron supply layer 26 of the vertical GaN transistor 2 of this embodiment has, for example, an Al composition ratio of 20% and a film thickness of 50 nm. In this case, the threshold voltage of the vertical GaN transistor 2 becomes negative, and the vertical GaN transistor 2 becomes a transistor with normally-on characteristics.

[0082] The electron supply layer of the lateral GaN transistor 3, i.e., the portion of the second portion 26b of the electron supply layer 26 where the recess 30 is not provided, is formed simultaneously with the electron supply layer of the vertical GaN transistor 2, i.e., the first portion 26a of the electron supply layer 26. Therefore, the second portion 26b also has the same Al composition of 20% and film thickness of 50 nm as the first portion 26a. However, the recess 30 is provided in at least a portion below the gate electrode 38 of the lateral GaN transistor 3, and the electron supply layer 26 is thinned to a film thickness of, for example, 20 nm. This allows the lateral GaN transistor 3 to achieve normally-off characteristics.

[0083] The channel layer 22 is formed by regrowth of crystals of nitride semiconductors such as GaN and AlGaN after the gate opening 20 is formed. Source openings 34 and 35 and a drain opening 36 can be formed by removing a portion of the stacked structure of GaN and AlGaN formed by regrowth of the crystals.

[0084] The gate opening 20, the source openings 34 and 35, and the drain opening 36 are formed by removing portions of the nitride semiconductor film formed by crystal growth. For example, dry etching such as inductively coupled plasma etching (ICP) can be used to remove portions of the current blocking layer 16, the electron transit layer 24, and the electron supply layer 26. A chlorine-based gas, for example, can be used as a process gas for dry etching.

[0085] The gate layer 28 is an example of a third nitride semiconductor layer of the second conductivity type, and is provided between the gate electrode 37 and the first portion 22a of the channel layer 22. The gate layer 28 is made of, for example, p-type GaN, and is provided in contact with the first portion 26a of the electron supply layer 26 so as to cover the gate opening 20.

[0086] The gate layer 32 is an example of a fourth nitride semiconductor layer of the second conductivity type, and is provided between the gate electrode 38 and the second portion 22b of the channel layer 22. The gate layer 32 is made of, for example, p-type GaN, and is provided in contact with the second portion 26b of the electron supply layer 26 so as to cover the recess portion 30.

[0087] The gate layers 28 and 32 can be formed simultaneously by crystal growth of nitride semiconductors. In this case, Mg can be used as the impurity exhibiting p-type conductivity. For example, after forming the recessed portion 30, a p-type GaN film is epitaxially grown while introducing the p-type impurity so as to cover the electron supply layer 26. The formed p-type GaN film is patterned to separate the first region 10a and the second region 10b, thereby forming the gate layers 28 and 32 simultaneously. This allows the gate layers 28 and 32 to have the same composition, impurity concentration, film thickness, etc.

[0088] The gate layers 28 and 32 may be formed in different processes. For example, the electron transit layer 24, the electron supply layer 26, and the gate layer 28 may be formed by continuous crystal growth, and then the p-type GaN film (gate layer 32) provided in the second region 10b may be removed when the gate layer 28 is patterned. After forming the recess 30, the gate layer 32 may be formed in the second region 10b by crystal regrowth and patterning. In this case, the composition, impurity concentration, thickness, etc. of the gate layers 28 and 32 may be made different, thereby forming gate layers 28 and 32 that are suitable for achieving, for example, the normally-on characteristics of the vertical GaN transistor 2 and the normally-off characteristics of the lateral GaN transistor 3. Furthermore, in the vertical GaN transistor 2, the generation of impurity levels at the interface between the gate layer 28 and the channel layer 22 can be suppressed, thereby forming a good pn junction between the gate layer 28 and the channel layer 22 and improving the off-state characteristics.

[0089] The gate electrode 37 is an example of a first gate electrode, and is provided above the first portion 22a of the channel layer 22. Specifically, the gate electrode 37 is provided in contact with the upper surface of the gate layer 28.

[0090] The gate electrode 38 is an example of a second gate electrode, and is provided above the second portion 22b of the channel layer 22. Specifically, the gate electrode 38 is provided in contact with the upper surface of the gate layer 32.

[0091] The source electrode 40 is an example of a first source electrode, and is provided above the substrate 10 and spaced apart from the gate electrode 37 and the gate layer 28. Specifically, the source electrode 40 is provided along the inner surface of the source opening 34. The source electrode 40 is in contact with the first portion 16 a of the current blocking layer 16 and the first portion 24 a of the electron transit layer 24.

[0092] The source electrode 42 is an example of a second source electrode, and is provided above the substrate 10 and spaced apart from the gate electrode 38 and the gate layer 32. Specifically, the source electrode 42 is provided along the inner surface of the source opening 35. The source electrode 42 is in contact with the second portion 16b of the current blocking layer 16 and the second portion 26b of the electron transit layer 24.

[0093] 1, both the source electrodes 40 and 42 are in contact with the electron supply layer 26, but they may not be in contact. The source openings 34 and 35 may not be provided. In this case, the source electrodes 40 and 42 are provided in contact with the upper surface of the electron supply layer 26, away from the gate electrodes 37 and 38 and the gate layers 28 and 32, respectively.

[0094] The drain electrode 44 is an example of a first drain electrode, and is provided below the substrate 10. The drain electrode 44 is provided so as to contact the entire lower surface of the substrate 10, but is not limited to this. For example, the drain electrode 44 may be provided in a range that overlaps the first region 10a in a planar view, but may not be provided in a range that overlaps the second region 10b in a planar view.

[0095] The drain electrode 46 is an example of a second drain electrode, and is provided above the substrate 10 so as to sandwich the gate electrode 38 between the drain electrode 46 and the source electrode 42. Specifically, the drain electrode 46 is provided along the inner surface of the drain opening 36. The drain electrode 46 is in contact with the second portion 24b of the electron transit layer 24. The drain electrode 46 is also in contact with the electron supply layer 26, but this is not essential. Alternatively, the drain opening 36 may not be provided, in which case the drain electrode 46 is provided in contact with the upper surface of the electron supply layer 26.

[0096] The electrodes can be formed by electron beam (EB) deposition, sputtering, or the like. After forming a conductive film such as a metal film, the electrodes can be formed by patterning the film into a predetermined shape using photolithography and wet or dry etching. The gate electrodes 37 and 38 can be made of a material that forms an ohmic contact with the p-type nitride semiconductor layer, such as a Pd-based material. The source electrodes 40 and 42 and the drain electrodes 44 and 46 can be made of a material that forms an ohmic contact with the n-type nitride semiconductor layer, such as a Ti / Al-based material.

[0097] The insulating film 50 is provided to protect the upper surfaces of the vertical GaN transistor 2 and the lateral GaN transistor 3. Specifically, the insulating film 50 covers the upper surfaces of the gate electrodes 37 and 38, the gate layers 28 and 32, and the channel layer 22. The insulating film 50 is formed using an insulating material such as a silicon oxide film or a silicon nitride film. The insulating film 50 has openings for exposing portions of the electrodes. Wiring electrodes 52, field plates 54, and electrode pads provided above the insulating film 50 are connected to the electrodes through the openings.

[0098] In this embodiment, the current blocking layer 16 is removed from the boundary between the vertical GaN transistor 2 and the lateral GaN transistor 3. An insulating film 50 is provided in the removed portion of the current blocking layer 16. This electrically separates the first portion 16a of the current blocking layer 16 from the second portion 16b of the current blocking layer 16.

[0099] The wiring electrode 52 is an example of a drain wiring, and electrically connects the source electrode 40 of the vertical GaN transistor 2 and the drain electrode 46 of the lateral GaN transistor 3. Although not shown in Fig. 1, a wiring electrode is provided as an example of a source wiring, electrically connecting the source electrode 42 of the lateral GaN transistor 3 and the gate electrode 37 of the vertical GaN transistor 2.

[0100] The field plate 54 is a part of the source wiring and is electrically connected to the source electrode 42. The field plate 54 is provided so as to overlap the gate electrode 38 and the gate layer 32 in a plan view of the substrate 10. This makes it possible to reduce the electric field strength applied to the gate end.

[0101] Each wiring, such as the wiring electrode 52 and the field plate 54, is formed using a conductive material such as metal. After a conductive film is formed by EB evaporation or sputtering, the conductive film is patterned into a predetermined shape to form each wiring.

[0102] [Circuit Configuration] Next, the circuit configuration of the vertical GaN transistor 2 and the lateral GaN transistor 3 will be described with reference to FIG.

[0103] 2 is a circuit diagram of the nitride semiconductor device 1 according to this embodiment. As shown in FIG. 2 , in the nitride semiconductor device 1, a voltage (potential) is applied from the outside to the drain electrode 44 of the vertical GaN transistor 2 and to the source electrode 42 and gate electrode 38 of the lateral GaN transistor 3. This causes the nitride semiconductor device 1 to perform a switching operation. The source electrode 40 of the vertical GaN transistor 2 and the drain electrode 46 of the lateral GaN transistor 3 are electrically connected, and the operation of the nitride semiconductor device 1 will be described assuming that this potential is an intermediate potential. Note that the voltages described below are merely examples and are not necessarily the same as the voltages described above.

[0104] When a voltage of 0 V is applied to the gate electrode 38 of the lateral GaN transistor 3, the nitride semiconductor device 1 is off. That is, no current flows between the drain electrode 44 of the vertical GaN transistor 2 and the source electrode 42 of the lateral GaN transistor 3. At this time, the voltage of the drain electrode 44 of the vertical GaN transistor 2 is a voltage set by the system, for example, 400 V. Since the voltage of the source electrode 42 of the lateral GaN transistor 3 is 0 V, the voltage of the gate electrode 37 of the vertical GaN transistor 2, which is electrically connected to it, is also 0 V. The value of the intermediate potential is determined from the drain-source capacitance ratio between the vertical GaN transistor 2 and the lateral GaN transistor 3. The value of the intermediate potential can be designed to a desired value, but in this embodiment, it is set to, for example, 10 V.

[0105] In this case, a voltage of 390 V is applied between the drain and source of the vertical GaN transistor 2 when it is off, so the vertical GaN transistor 2 needs to be a device with a relatively high breakdown voltage. On the other hand, only 10 V is applied between the drain and source of the lateral GaN transistor 3, so a low breakdown voltage device can be used as the lateral GaN transistor 3. Note that the threshold voltage of the vertical GaN transistor 2 is −5 V, so when the intermediate potential is 10 V and the gate voltage of the vertical GaN transistor is 0 V, the vertical GaN transistor 2 is off.

[0106] When a voltage of, for example, 5 V is applied to the gate electrode 38 of the lateral GaN transistor 3, the lateral GaN transistor 3 is turned on. At the same time, the intermediate potential becomes approximately 0 V, so the vertical GaN transistor 2 is turned on. As a result, the nitride semiconductor device 1 is turned on, and a current flows between the drain electrode 44 of the vertical GaN transistor 2 and the source electrode 42 of the lateral GaN transistor 3. Both the vertical GaN transistor 2 and the low-voltage lateral GaN transistor 3 are capable of passing a large current with a small area, enabling high-current operation. Furthermore, in the nitride semiconductor device 1, since it is the low-voltage lateral GaN transistor 3 that controls the on / off of the switch, in addition to the small gate-drain capacitance, the Miller effect is also small, enabling very high-speed switching.

[0107] [Planar Layout] Next, an example of a planar layout of the nitride semiconductor device 1 according to this embodiment will be described with reference to FIG.

[0108] 3 is a plan view of the nitride semiconductor device 1 according to the present embodiment. In this embodiment, as shown in FIG. 3, when the substrate 10 is viewed in plan, the vertical GaN transistor 2 is provided in the region 11a, and the lateral GaN transistor 3 is provided in the region 11b. The regions 11a and 11b do not overlap each other when the substrate 10 is viewed in plan. The regions 11a and 11b are adjacent to each other.

[0109] Specifically, the nitride semiconductor device 1 includes a plurality of vertical GaN transistors 2 and a plurality of lateral GaN transistors 3. The plurality of vertical GaN transistors 2 are provided side by side in a region 11a, and the plurality of lateral GaN transistors 3 are provided side by side in a region 11b.

[0110] For example, in the multiple vertical GaN transistors 2, the gate electrodes 37 and source electrodes 40 each have an elongated shape extending in the depth direction of the paper in the cross-sectional view of FIG. 1. The multiple gate electrodes 37 and multiple source electrodes 40 are arranged alternately in the short direction within the region 11a. In this case, two adjacent vertical GaN transistors 2 may share one source electrode 40. Note that this shape and arrangement are merely an example, and the arrangement and shape of the gate electrodes 37 and source electrodes 40 are not particularly limited.

[0111] In the multiple lateral GaN transistors 3, the gate electrodes 38, source electrodes 42, and drain electrodes 46 each have an elongated shape extending in the depth direction of the paper in the cross-sectional view of Figure 1. The multiple gate electrodes 38, source electrodes 42, and drain electrodes 46 are arranged in the region 11b in such a manner that the source electrodes 42 and drain electrodes 46 are alternately arranged in their respective short sides, and the gate electrodes 38 are arranged between them. Note that this shape and arrangement are merely an example, and the arrangement and shape of the gate electrodes 38, source electrodes 42, and drain electrodes 46 are not particularly limited.

[0112] 3 , the nitride semiconductor device 1 also includes a gate pad 56 and a source pad 58. The gate pad 56 is a pad for receiving an external voltage to be applied to the gate electrode 38 of the lateral GaN transistor 3. The source pad 58 is a pad for receiving an external voltage to be applied to the source electrode 42 of the lateral GaN transistor 3.

[0113] In this way, the vertical GaN transistor 2 and the lateral GaN transistor 3 are provided on the same substrate 10. This allows the vertical GaN transistor 2 and the lateral GaN transistor 3 to be integrated in close proximity, shortening the wiring distance between them. Specifically, the parasitic inductance between the source electrode 40 of the vertical GaN transistor 2 and the drain electrode 46 of the lateral GaN transistor 3, and between the source electrode 42 of the lateral GaN transistor 3 and the gate electrode 37 of the vertical GaN transistor 2, can be made extremely small. This suppresses the occurrence of noise and malfunction even during high-frequency operation, making the nitride semiconductor device 1 suitable for high-frequency switching.

[0114] As described above, the nitride semiconductor device 1 according to this embodiment can achieve high-current and high-speed switching with stable operation.

[0115] In this embodiment, both the vertical GaN transistor 2 and the lateral GaN transistor 3 are configured to include p-type nitride semiconductor layers as the gate layers 28 and 32, but the present invention is not limited to this. As long as a vertical GaN transistor 2 having normally-on characteristics and a lateral GaN transistor 3 having normally-off characteristics can be realized, other gate structures may be used for the gate layers 28 and 32, such as a metal-insulator-semiconductor (MIS) structure using a gate insulating film. For example, a silicon nitride film formed by plasma-enhanced chemical vapor deposition can be used as the gate insulating film.

[0116] (Modifications of Embodiment 1) Next, a description will be given of several modifications of Embodiment 1. The following description will focus on the differences from Embodiment 1, and the description of commonalities will be omitted or simplified.

[0117] [Modification 1] First, a nitride semiconductor device according to Modification 1 will be described with reference to FIG.

[0118] 4 is a cross-sectional view of a nitride semiconductor device 101 according to Modification 1 of the present embodiment. The nitride semiconductor device 101 shown in Fig. 4 differs from the nitride semiconductor device 1 shown in Fig. 1 in that the lateral GaN transistor 3 does not have a recessed portion 30. The vertical GaN transistor 2 has the same configuration as the nitride semiconductor device 1.

[0119] 4, the nitride semiconductor device 101 includes a channel layer 122 instead of the channel layer 22. The channel layer 122 includes an electron transit layer 24 and an electron supply layer 126. The configuration of a second portion 122b of the channel layer 122 differs from that of the first embodiment.

[0120] Specifically, in the lateral GaN transistor 3, the film thickness of the electron supply layer 126, i.e., the film thickness of the second portion 126b, is constant from the end of the source electrode 42 to the end of the drain electrode 46. The second portion 126b of the electron supply layer 126 does not have a recess 30, and there is no region below the gate electrode 38 where the electron supply layer 126 is partially thinned.

[0121] In order to make the lateral GaN transistor 3 normally-off, the second portion 126b of the electron supply layer 126 is thinner than the first portion 126a. Generally, the electron supply layers 126 of the vertical GaN transistor 2 and the lateral GaN transistor 3 are formed simultaneously by crystal growth. Therefore, the Al composition and thickness of the electron supply layers 126 are the same. In this embodiment, the thickness of the second portion 126b can be reduced by partially removing the surface layer of the second portion 126b after crystal growth, for example, by dry etching.

[0122] This configuration allows the gate length (the horizontal length in the cross section) to be shortened, thereby enabling the lateral GaN transistor 3 to be realized in a small area. This allows the nitride semiconductor device 101 to be miniaturized. Furthermore, the cost of the nitride semiconductor device 101 can also be reduced.

[0123] This modification also has the same effect of realizing stable operation of large current and high speed switching of the nitride semiconductor device 101. Another advantage is that the chip area of ​​the nitride semiconductor device 101 can be reduced.

[0124] [Modification 2] Next, a nitride semiconductor device according to Modification 2 will be described with reference to FIG.

[0125] 5 is a cross-sectional view of a nitride semiconductor device 201 according to Modification 2 of the present embodiment. The nitride semiconductor device 201 shown in Fig. 5 differs from the nitride semiconductor device 1 shown in Fig. 1 in that an impurity region 232 is provided in place of the recess portion 30 and the gate layer 32 in the lateral GaN transistor 3. The configuration of the vertical GaN transistor 2 is the same as that of the nitride semiconductor device 1.

[0126] 5, the nitride semiconductor device 201 includes a channel layer 222 instead of the channel layer 22. The channel layer 222 includes an electron transit layer 24 and an electron supply layer 226. The configuration of the second portion 222b of the channel layer 222 differs from that of the first embodiment. Specifically, an impurity region 232 is provided in the second portion 226b of the electron supply layer 226.

[0127] The impurity region 232 is provided in a range overlapping with the gate electrode 38 in a plan view of the substrate 10. The gate electrode 38 is connected to the impurity region 232. The impurity region 232 is formed, for example, by ion implantation into a surface layer of the second portion 226b of the electron supply layer 226. For example, the implanted atoms are Mg or F. Since the concentration of the 2DEG is low in the impurity region 232, it is easy to make the lateral GaN transistor 3 normally-off even without the gate layer 32 made of p-type GaN shown in FIGS. 1 and 4 .

[0128] In this configuration, as in the first modification of the first embodiment, the gate length can be shortened, and the lateral GaN transistor 3 can be realized in a small area. This allows the nitride semiconductor device 201 to be miniaturized. Furthermore, the cost of the nitride semiconductor device 201 can also be reduced.

[0129] As described above, this modification also has the same effect of realizing stable operation of large current and high speed switching of the nitride semiconductor device 201. Furthermore, there are advantages in that the nitride semiconductor device 201 can be made smaller and its manufacturing costs can be reduced.

[0130] [Modification 3] Next, a nitride semiconductor device according to Modification 3 will be described with reference to FIG.

[0131] 6 is a cross-sectional view of a nitride semiconductor device 301 according to Modification 3 of the present embodiment. The nitride semiconductor device 301 shown in FIG. 6 differs from the nitride semiconductor device 1 shown in FIG. 1 in that the vertical GaN transistor 2 includes a potential fixed electrode 340. The configuration of the lateral GaN transistor 3 is the same as that of the nitride semiconductor device 1. In this modification, the first region 10a is regarded as the region between the two potential fixed electrodes 340, but it may also be regarded as the region between the two source electrodes 40, as in the first embodiment and the other modifications.

[0132] 6 , the potential fixed electrode 340 is provided in contact with the current blocking layer 16 at the bottom surface of the source opening 34. The potential fixed electrode 340 is electrically connected to the gate electrode 37. This causes the current blocking layer 16 (i.e., the first portion 16 a) of the vertical GaN transistor 2 to have the same potential as the gate electrode 37, not the source electrode 40.

[0133] In this modification, the source electrode 40 is not in contact with the first portion 16a of the current blocking layer 16. The source electrode 40 and the potential fixed electrode 340 are spaced apart so as not to contact each other.

[0134] 2, in order to achieve faster switching, it is advantageous to design the intermediate potential at the off time to be as low as possible within the range that allows turning off the vertical GaN transistor 2. To achieve this, it is necessary to make the drain-source capacitance of the vertical GaN transistor 2 smaller than the drain-source capacitance of the lateral GaN transistor 3.

[0135] In this modification, when viewed from the drain electrode 44 of the vertical GaN transistor 2, the source electrode 40 is shielded by the first portion 16a of the current blocking layer 16 connected to the potential fixed electrode 340. This makes it possible to make the drain-source capacitance of the vertical GaN transistor 2 extremely small.

[0136] As described above, in this modification, by lowering the intermediate potential, a lateral GaN transistor with a low breakdown voltage can be used as the lateral GaN transistor 3. Therefore, the nitride semiconductor device 301 has the effect of enabling faster switching.

[0137] [Modification 4] Next, a nitride semiconductor device according to Modification 4 will be described with reference to FIG.

[0138] 7 is a cross-sectional view of a nitride semiconductor device 401 according to Modification 4 of the present embodiment. The nitride semiconductor device 401 shown in Fig. 7 differs from the nitride semiconductor device 1 shown in Fig. 1 in that it includes a wiring electrode 452 and a field plate 454 instead of the wiring electrode 52 and the field plate 54. The wiring electrode 452 and the field plate 454 differ from the wiring electrode 52 and the field plate 54 in that they partially overlap each other in a plan view.

[0139] 7, the wiring electrode 452 is provided above the field plate 454 so as to overlap the field plate 454 in a plan view. The wiring electrode 452 also overlaps the gate electrode 38 in a plan view, but this is not limitative. A parasitic capacitance is formed by the wiring electrode 452 and the field plate 454.

[0140] As described in the third modification of the first embodiment, in order to reduce the intermediate potential in the off state, it is necessary to reduce the drain-source capacitance of the vertical GaN transistor 2 relative to the drain-source capacitance of the lateral GaN transistor 3. In addition to the method of reducing the drain-source capacitance of the vertical GaN transistor 2 as in the third modification, there is also a method of increasing the drain-source capacitance of the lateral GaN transistor 3.

[0141] An external capacitor may be connected separately to increase the drain-source capacitance of the lateral GaN transistor 3. However, this poses a problem in that parasitic inductance occurs between the nitride semiconductor device 1 and the external capacitor, making it prone to instability during high-speed operation.

[0142] 7, in this modification, the wiring electrode 452 connected to the drain electrode 46 and the field plate 454 connected to the source electrode 42 are overlapped when viewed from above with the insulating film 50 interposed therebetween. This overlapping region becomes a capacitance, and therefore the drain-source capacitance of the lateral GaN transistor 3 can be increased.

[0143] As described above, in this modification, by lowering the intermediate potential, a lateral GaN transistor with a low breakdown voltage can be used as the lateral GaN transistor 3. Therefore, the nitride semiconductor device 401 has the effect of enabling faster switching.

[0144] [Modification 5] Next, a nitride semiconductor device according to Modification 5 will be described with reference to FIGS. 8, 9 and 10. FIG.

[0145] Fig. 8 is a circuit diagram of a nitride semiconductor device 501 according to Modification 5 of the present embodiment. The nitride semiconductor device 501 shown in Fig. 8 differs from the nitride semiconductor device 1 shown in Fig. 2 in that it includes a plurality of PN diodes 504.

[0146] 8, the multiple PN diodes 504 are connected in series with each other and connected between the drain electrode 46 and the source electrode 42 of the lateral GaN transistor 3. Specifically, the anode electrode of one of the multiple PN diodes 504 is electrically connected to the drain electrode 46 of the lateral GaN transistor 3. The cathode electrode of another of the multiple PN diodes 504 is electrically connected to the source electrode 42. The number of PN diodes 504 may be only one.

[0147] When the intermediate potential becomes higher than the turn-on voltage of the multiple PN diodes 504, current begins to flow through the PN diodes 504, and the intermediate potential does not exceed the turn-on voltage. If the intermediate potential becomes higher than the breakdown voltage of the lateral GaN transistor 3, the lateral GaN transistor 3 may be destroyed. However, by designing the turn-on voltage of the multiple PN diodes 504 to be equal to or lower than the breakdown voltage of the lateral GaN transistor 3, it is possible to prevent the lateral GaN transistor 3 from being destroyed. The turn-on voltage of the multiple PN diodes 504 can be adjusted to a desired value by adjusting the number of diodes connected in series. For example, the turn-on voltage of one PN diode 504 formed using a GaN material is generally approximately 3 V. Therefore, connecting three PN diodes 504 in series results in a turn-on voltage of approximately 9 V.

[0148] The PN diode 504 may be connected externally. However, if it is connected externally, the parasitic inductance between the nitride semiconductor device 501 and the PN diode 504 increases, which can easily cause instability during high-speed operation. Therefore, in this modification, the PN diode 504 is integrated on the same substrate 10 as the vertical GaN transistor 2 and the lateral GaN transistor 3, as shown in FIG. 9 . Note that FIG. 9 is a cross-sectional view of a nitride semiconductor device 501 according to a fifth modification of this embodiment.

[0149] 9 , the PN diode 504 includes a third portion 22c of the channel layer 22, a p-type semiconductor layer 532, an anode electrode 538, and a cathode electrode 542. The PN diode 504 is provided in a third region 10c that does not overlap with either the first region 10a or the second region 10b in a plan view of the substrate 10. The third region 10c is a region in which the PN diode 504 is provided, and specifically, can be considered to be a region between the p-type semiconductor layer 532 and the cathode electrode 542.

[0150] The third portion 22c of the channel layer 22 is a part of the channel layer 22 and is a region that overlaps with the third region 10c in a plan view of the substrate 10. The third portion 22c of the channel layer 22 includes a third portion 24c of the electron transit layer 24 and a third portion 26c of the electron supply layer 26. The 2DEG generated in the third portion 24c of the electron transit layer 24 and the p-type semiconductor layer 532 form a pn junction in the main body of the PN diode 504.

[0151] The p-type semiconductor layer 532 is an example of a fifth nitride semiconductor layer of the second conductivity type, and is provided between the anode electrode 538 and the channel layer 22. The p-type semiconductor layer 532 is made of, for example, p-type GaN, and is provided in contact with the third portion 26 c of the electron supply layer 26.

[0152] The anode electrode 538 is an electrode connected to the drain electrode 46. The anode electrode 538 is provided in contact with the upper surface of the p-type semiconductor layer 532.

[0153] The cathode electrode 542 is an electrode connected to the source electrode 42. Specifically, the cathode electrode 542 is provided along the inner surface of the source opening 35. The cathode electrode 542 is in contact with the current blocking layer 16 and the third portion 24c of the electron transit layer 24. The cathode electrode 542 is also in contact with the third portion 26c of the electron supply layer 26, but does not necessarily have to be in contact with it.

[0154] The cathode electrode 542 may be integral with the source electrode 42. That is, one electrode may function as the source electrode 42 of the lateral GaN transistor 3 and also as the cathode electrode 542 of the PN diode 504. In this case, the boundary between the second region 10b and the third region 10c can be regarded as, for example, the center of the integrated electrode.

[0155] The third portion 22c of the channel layer 22, the p-type semiconductor layer 532, the anode electrode 538, and the cathode electrode 542 included in the PN diode 504 can be formed in the same process as the second portion 22b of the channel layer 22, the gate layer 32, the gate electrode 38, and the source electrode 42 of the lateral GaN transistor 3, respectively. That is, the PN diode 504 can be fabricated simultaneously with the process of fabricating the vertical GaN transistor 2 and the lateral GaN transistor 3. Therefore, there is no increase in process costs for providing the PN diode 504.

[0156] 10 is a plan view of a nitride semiconductor device 501 according to a fifth modification of this embodiment. A PN diode 504 is provided in region 11c shown in FIG. The PN diode 504 may be a small-current device, so a large area does not need to be secured. Therefore, region 11c can be made smaller than regions 11a and 11b, and area loss is also very small.

[0157] As described above, the nitride semiconductor device 501 according to this modification not only has the effect of enabling stable operation of large current and high-speed switching, but also has the effect of suppressing breakdown of the lateral GaN transistor 3.

[0158] Second Embodiment Next, a second embodiment will be described.

[0159] The second embodiment differs from the first embodiment mainly in that a plurality of vertical GaN transistors and lateral GaN transistors are provided as a single unit. The following description will focus on the differences from the first embodiment, and the description of the commonalities will be omitted or simplified.

[0160] FIG. 11 is a plan view of a nitride semiconductor device 601 according to this embodiment.

[0161] In the first embodiment, as shown in Fig. 3, all of the vertical GaN transistors 2 and all of the horizontal GaN transistors 3 are arranged in separate regions. In contrast, in the second embodiment, as shown in Fig. 11, some of the vertical GaN transistors 2 and some of the horizontal GaN transistors 3 form a unit 604, and at least two or more unit units 604 are arranged.

[0162] The basic unit 604 includes, for example, one vertical GaN transistor 2 and one horizontal GaN transistor 3 shown in any one of Figures 1, 4 to 7. By arranging the basic units 604 side by side, the vertical GaN transistors 2 and the horizontal GaN transistors 3 can be arranged alternately one by one as shown in Figure 11.

[0163] Alternatively, the unit 604 may include a plurality of vertical GaN transistors 2 and a plurality of lateral GaN transistors 3. Fig. 12 is a cross-sectional view of a nitride semiconductor device 601 according to this embodiment.

[0164] 12 includes one or two vertical GaN transistors 2 and two lateral GaN transistors 3 as a unit 604. In the unit 604, two lateral GaN transistors 3 are arranged symmetrically with respect to the source electrode 42. In the example shown in FIG. 12, the source electrode 42 of the lateral GaN transistors 3 can be shared. This has the advantage of improving area efficiency and enabling the nitride semiconductor device 601 to be made smaller.

[0165] In this way, by forming the vertical GaN transistor 2 and the lateral GaN transistor 3 adjacent to each other in one region, the parasitic inductance between the vertical GaN transistor 2 and the lateral GaN transistor 3 is reduced, which is advantageous for higher speed operation. In addition, when a current flows through the vertical GaN transistor 2, the current can also flow by utilizing the drift layer 12 below the lateral GaN transistor 3, which is advantageous for reducing the on-resistance of the vertical GaN transistor 2.

[0166] As described above, according to the nitride semiconductor device 601 of the second embodiment, it is possible to perform high-speed switching with a large current more stably, and also to reduce losses by reducing the on-resistance.

[0167] (Modification of Second Embodiment) Next, a modification of the second embodiment will be described with reference to Figures 13 and 14. The following description will focus on differences from the second embodiment, and description of commonalities will be omitted or simplified.

[0168] Fig. 13 is a cross-sectional view of a nitride semiconductor device 701 according to Modification 1 of Embodiment 2. Fig. 14 is a cross-sectional view of a nitride semiconductor device 801 according to Modification 2 of Embodiment 2.

[0169] 13 and 14 show a configuration corresponding to a single unit 604. Nitride semiconductor devices 701 and 801 each include a vertical GaN transistor 702 and a lateral GaN transistor 703. The vertical GaN transistor 702 differs from the vertical GaN transistor 2 in that it does not include a source electrode 40. The lateral GaN transistor 703 differs from the lateral GaN transistor 3 in that it does not include a drain electrode 46.

[0170] The current path runs from the drain electrode 44 of the vertical GaN transistor 702 through the substrate 10, drift layer 12, and channel layer 22, and then flows to the channel layer 22 and source electrode 42 of the lateral GaN transistor 703. Since no external voltage is applied to the intermediate potentials, which are the source potential of the vertical GaN transistor 702 and the drain potential of the lateral GaN transistor 703, no electrodes are required. In this modification, the current blocking layer 16 is electrically connected to the source electrode 42 of the lateral GaN transistor 703.

[0171] With this configuration, in addition to the effect of the second embodiment, the regions where the source electrode of vertical GaN transistor 702 and the drain electrode of lateral GaN transistor 703 are formed can be reduced, and the length of unit 604 can be significantly shortened. As a result, nitride semiconductor devices 701 and 801 can be realized with a smaller area. Furthermore, the manufacturing cost of nitride semiconductor devices 701 and 801 can also be reduced.

[0172] 12, in the nitride semiconductor device 801 shown in Fig. 14, the lateral GaN transistor 703 is formed symmetrically with respect to the source electrode 42. By sharing the source electrode 42, it is possible to further improve the area efficiency.

[0173] As described above, the nitride semiconductor devices 701 and 801 according to this modification can achieve further miniaturization in addition to the effects of the second embodiment. Another effect is that the manufacturing costs of the nitride semiconductor devices 701 and 801 can be reduced.

[0174] While nitride semiconductor devices according to one or more aspects have been described above based on embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the present embodiments and configurations constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0175] For example, layers not shown may be provided between the components such as the semiconductor layers, insulating films, and electrodes shown in each figure, as long as they do not interfere with device operation. For example, an AlN layer with a thickness of approximately 1 nm may be provided between the electron transit layer 24 and the electron supply layer 26. This suppresses alloy scattering, improves channel mobility, and reduces on-resistance.

[0176] Furthermore, for example, the components such as the semiconductor layer, insulating film, and electrodes shown in each drawing may have a single-layer structure or a multi-layer structure. For example, the drift layer 12 may include multiple n-type nitride semiconductor layers with different impurity concentrations.

[0177] Furthermore, for example, the first conductivity type may be p-type and the second conductivity type may be n-type.

[0178] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to each of the above-described embodiments within the scope of the claims or their equivalents.

[0179] The present disclosure can be used as a power device capable of high-speed switching at a large current, and is used, for example, in power supply circuits or inverter circuits of in-vehicle equipment or industrial equipment.

[0180] 1, 101, 201, 301, 401, 501, 601, 701, 801 Nitride semiconductor device 2, 702 Vertical GaN transistor 3, 703 Lateral GaN transistor 10 Substrate 10a First region 10b Second region 10c Third region 11a, 11b, 11c Region 12 Drift layer 14 High resistance layer 16 Current blocking layer 16a, 22a, 24a, 26a First portion 16b, 22b, 24b, 26b, 122b, 126b, 222b, 226b Second portion 20 Gate opening 22, 122, 222 Channel layer 22c, 24c, 26c Third portion 24 Electron transit layer 26, 126, 226 Electron supply layer 28, 32 Gate layer 30 Recessed portion 34, 35 Source opening 36 Drain opening 37, 38 Gate electrode 40, 42 Source electrode 44, 46 Drain electrode 50 Insulating film 52, 452 Wiring electrode 54, 454 Field plate 56 Gate pad 58 Source pad 232 Impurity region 340 Potential fixing electrode 504 PN diode 532 P-type semiconductor layer 538 Anode electrode 542 Cathode electrode 604 Unit

Claims

1. A nitride semiconductor device comprising: a substrate; a channel layer provided above the substrate, the channel layer including a nitride semiconductor as a main component; a vertical transistor providing a normally-on operation in a first region of the substrate in a planar view; and a lateral transistor providing a normally-off operation in a second region of the substrate different from the first region in a planar view, wherein the vertical transistor includes: a first portion that is a part of the channel layer and overlaps the first region in a planar view of the substrate; a first gate electrode provided above the first portion; and a first drain electrode provided below the substrate; and the lateral transistor includes: a second portion that is a part of the channel layer and overlaps the second region in a planar view of the substrate; a second gate electrode provided above the second portion; and a second source electrode provided above the substrate, wherein the first gate electrode and the second source electrode are electrically connected, and a source potential of the vertical transistor and a drain potential of the lateral transistor are the same potential.

2. The nitride semiconductor device according to claim 1, comprising: a first nitride semiconductor layer of a first conductivity type provided between said substrate and said channel layer; and a second nitride semiconductor layer of a second conductivity type opposite to said first conductivity type provided between said first nitride semiconductor layer and said channel layer.

3. The nitride semiconductor device according to claim 2, wherein the vertical transistor includes a first source electrode set to the source potential, and the lateral transistor includes a second drain electrode set to the drain potential.

4. The nitride semiconductor device according to claim 3, wherein a portion of the second nitride semiconductor layer that overlaps with the first region and a portion that overlaps with the second region in a planar view of the substrate are electrically separated.

5. The nitride semiconductor device according to claim 4, wherein a portion of the second nitride semiconductor layer that overlaps with the second region in a planar view of the substrate is electrically connected to the second source electrode.

6. The nitride semiconductor device according to claim 4, wherein a portion of the second nitride semiconductor layer that overlaps with the first region in a planar view of the substrate is electrically connected to the first source electrode.

7. The nitride semiconductor device according to claim 4, wherein a portion of the second nitride semiconductor layer that overlaps with the first region in a plan view of the substrate is electrically connected to the first gate electrode.

8. The nitride semiconductor device according to claim 1, wherein the channel layer includes a stacked structure of a GaN layer and an AlGaN layer.

9. The nitride semiconductor device according to any one of claims 1 to 7, further comprising a third nitride semiconductor layer or an insulating layer of a second conductivity type opposite to the first conductivity type, provided between the first gate electrode and the first portion.

10. The nitride semiconductor device according to any one of claims 1 to 7, further comprising a fourth nitride semiconductor layer of a second conductivity type opposite to the first conductivity type, provided between the second gate electrode and the second portion.

11. A nitride semiconductor device according to any one of claims 1 to 7, wherein the second portion includes an impurity region provided in a range overlapping with the second gate electrode in a planar view of the substrate, and the second gate electrode is electrically connected to the impurity region.

12. The nitride semiconductor device according to claim 3, comprising: a source wiring electrically connected to the second source electrode; and a drain wiring electrically connected to the second drain electrode, wherein, in a planar view of the substrate, the source wiring and the drain wiring partially overlap each other.

13. The nitride semiconductor device according to claim 3, comprising a PN diode including an electrode connected to the second drain electrode, and a fifth nitride semiconductor layer of the second conductivity type provided between the electrode and the channel layer.

14. The nitride semiconductor device according to claim 13, comprising a plurality of said PN diodes, the plurality of said PN diodes being connected in series.

15. The nitride semiconductor device according to any one of claims 1 to 7, comprising a plurality of the vertical transistors and a plurality of the horizontal transistors, the plurality of vertical transistors being arranged adjacent to each other in a third region in a planar view of the substrate, and the plurality of lateral transistors being arranged adjacent to each other in a fourth region not overlapping with the third region in a planar view of the substrate.

16. The nitride semiconductor device according to claim 1, comprising a plurality of the vertical transistors and a plurality of the lateral transistors, the vertical transistors and the lateral transistors being arranged alternately in a plan view of the substrate.

17. The nitride semiconductor device according to claim 2, wherein the second source electrode is electrically connected to a portion of the second nitride semiconductor layer that overlaps the second region in a planar view of the substrate, and the second nitride semiconductor layer is not electrically separated between a portion that overlaps the first region and a portion that overlaps the second region in a planar view of the substrate.

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