Plasma processing apparatus and impedance matching method

Abstract

Provided is a technique for suppressing intermodulation distortion. Provided is a plasma processing apparatus comprising: a chamber; a substrate support that is disposed in the chamber and includes a lower electrode; an upper electrode that is disposed above the substrate support; a source RF generator that is configured to supply a source RF signal to the upper electrode or the lower electrode to generate plasma in the chamber; an impedance matching device that is electrically connected to a transmission line between the source RF generator and the upper electrode or the lower electrode, the impedance matching device including a first low-speed matching circuit and a first high-speed matching circuit that are connected in parallel to each other; a bias generator that is configured to supply a bias signal to the lower electrode; and a control unit that is configured to perform a low-speed matching operation on the source RF signal by the first low-speed matching circuit during the first period, and to perform a high-speed matching operation on the source RF signal by the first high-speed matching circuit during a second period after the first period.

Description

Plasma processing apparatus and impedance matching method

[0001] SUMMARY OF THE INVENTION Exemplary embodiments of the present disclosure relate to a plasma processing apparatus and an impedance matching method.

[0002] Patent Document 1 discloses a matching box including a mechanically controlled variable capacitor. Patent Document 2 discloses a matching box including an electronically controlled variable capacitor.

[0003] JP 2006-134606 A JP 2012-142285 A

[0004] The present disclosure provides techniques for suppressing intermodulation distortion.

[0005] In one exemplary embodiment of the present disclosure, there is provided a plasma processing apparatus including: a chamber; a substrate support disposed within the chamber and including a lower electrode; an upper electrode disposed above the substrate support; a source RF generator configured to supply a source RF signal to the upper electrode or the lower electrode to generate plasma in the chamber; an impedance matching circuit electrically connected to a transmission line between the source RF generator and the upper electrode or the lower electrode, the impedance matching circuit including a first slow matching circuit and a first fast matching circuit connected in parallel to each other; a bias generator configured to supply a bias signal to the lower electrode; and a controller configured to perform a slow matching operation on the source RF signal by the first slow matching circuit during a first time period and to perform a fast matching operation on the source RF signal by the first fast matching circuit during a second time period after the first time period.

[0006] According to one exemplary embodiment of the present disclosure, a technique for suppressing intermodulation distortion can be provided.

[0007] FIG. 4 is a diagram for explaining an example of the configuration of a plasma processing system. FIG. 5 is a diagram for explaining an example of the configuration of a capacitively coupled plasma processing apparatus. FIG. 6 is a diagram showing an example of coupling between a power supply 30 and a chamber 10. FIG. 7 is a diagram showing an example of an electronic variable capacitor. FIG. 8 is a flowchart showing an example of the matching method. FIG. 9 is an example of a timing chart of the matching method. FIG. 10 is an example of a timing chart when a high-speed matching operation is not performed. FIG. 11 is an example of a timing chart when a high-speed matching operation is performed. FIG. 12 is a diagram showing a modified example of the configuration shown in FIG. 3. FIG. 13 is a diagram showing a modified example of the configuration shown in FIG. 3.

[0008] Hereinafter, each embodiment of the present disclosure will be described.

[0009] In one exemplary embodiment, there is provided a plasma processing apparatus comprising: a chamber; a substrate support disposed within the chamber and including a lower electrode; an upper electrode disposed above the substrate support; a source RF generator configured to supply a source RF signal to the upper electrode or the lower electrode to generate plasma in the chamber; an impedance matching circuit electrically connected to a transmission line between the source RF generator and the upper electrode or the lower electrode, the impedance matching circuit including a first slow matching circuit and a first fast matching circuit connected in parallel to each other; a bias generator configured to supply a bias signal to the lower electrode; and a controller configured to perform a slow matching operation on the source RF signal by the first slow matching circuit during a first time period and to perform a fast matching operation on the source RF signal by the first fast matching circuit during a second time period after the first time period.

[0010] In one exemplary embodiment, the first low-speed matching circuit includes a first mechanically variable capacitor, and the first high-speed matching circuit includes a first electronically variable capacitor, and the first electronically variable capacitor includes a plurality of first capacitor elements and a plurality of first switching elements electrically connected to the plurality of first capacitor elements, respectively.

[0011] In one exemplary embodiment, the maximum capacitance of the first mechanical variable capacitor is at least 10 times the maximum capacitance of the first electronic variable capacitor.

[0012] In one exemplary embodiment, the first slow matching circuit is configured to perform a slow matching operation at a frequency of about once every 10 ms to several hundred ms, and the first fast matching circuit is configured to perform a fast matching operation at a frequency of about once every several tens of ns to several μs.

[0013] In one exemplary embodiment, the first period is the period from when the plasma begins to form in the chamber until the slow matching operation stabilizes.

[0014] In one exemplary embodiment, the first low speed matching circuit and the first high speed matching circuit are disposed between the transmission line and ground potential.

[0015] In one exemplary embodiment, the impedance matching box includes a second slow matching circuit and a second fast matching circuit connected in parallel with each other, and the second slow matching circuit and the second fast matching circuit are disposed on the transmission line.

[0016] In one exemplary embodiment, the first slow matching circuit includes a first mechanically variable capacitor, the first fast matching circuit includes a first electronically variable capacitor, the first electronically variable capacitor including a plurality of first capacitor elements and a plurality of first switching elements electrically connected to the plurality of first capacitor elements respectively, the second slow matching circuit includes a second mechanically variable capacitor, the second fast matching circuit includes a second electronically variable capacitor, the second electronically variable capacitor including a plurality of second capacitor elements and a plurality of second switching elements electrically connected to the plurality of second capacitor elements respectively.

[0017] In one exemplary embodiment, the source RF generator is configured to allow the frequency of the source RF signal to be varied.

[0018] In one exemplary embodiment, the bias generator includes a bias RF generator configured to generate a bias RF signal.

[0019] In one exemplary embodiment, the bias generator includes a bias DC generator configured to generate a bias DC signal, the bias DC signal having a sequence of voltage pulses.

[0020] In one exemplary embodiment, there is provided a plasma processing apparatus comprising: a chamber; a substrate support disposed within the chamber and including a lower electrode; an antenna disposed above the chamber; a source RF generator configured to supply a source RF signal to the antenna to generate plasma in the chamber; an impedance matching circuit electrically connected to a transmission line between the source RF generator and the antenna, the impedance matching circuit including a first slow matching circuit and a first fast matching circuit connected in parallel to each other; a bias generator configured to supply a bias signal to the lower electrode; and a controller configured to perform a slow matching operation on the source RF signal by the first slow matching circuit during a first time period and to perform a fast matching operation on the source RF signal by the first fast matching circuit during a second time period after the first time period.

[0021] In one exemplary embodiment, the first low-speed matching circuit includes a first mechanically variable capacitor, and the first high-speed matching circuit includes a first electronically variable capacitor, and the first electronically variable capacitor includes a plurality of first capacitor elements and a plurality of first switching elements electrically connected to the plurality of first capacitor elements, respectively.

[0022] In one exemplary embodiment, the first low speed matching circuit and the first high speed matching circuit are disposed between the transmission line and ground potential.

[0023] In one exemplary embodiment, the impedance matching box includes a second slow matching circuit and a second fast matching circuit connected in parallel with each other, and the second slow matching circuit and the second fast matching circuit are disposed on the transmission line.

[0024] In one exemplary embodiment, the first slow matching circuit includes a first mechanically variable capacitor, the first fast matching circuit includes a first electronically variable capacitor, the first electronically variable capacitor including a plurality of first capacitor elements and a plurality of first switching elements electrically connected to the plurality of first capacitor elements respectively, the second slow matching circuit includes a second mechanically variable capacitor, the second fast matching circuit includes a second electronically variable capacitor, the second electronically variable capacitor including a plurality of second capacitor elements and a plurality of second switching elements electrically connected to the plurality of second capacitor elements respectively.

[0025] In one exemplary embodiment, the source RF generator is configured to allow the frequency setting of the source RF signal to be variably set.

[0026] In one exemplary embodiment, an impedance matching method is provided, including the steps of: supplying an RF signal from an RF generator to a load; performing a slow matching operation on the RF signal by a first slow matching circuit during a first period; and performing a fast matching operation on the RF signal by a first fast matching circuit connected in parallel to the first slow matching circuit during a second period after the first period.

[0027] In one exemplary embodiment, the first low-speed matching circuit includes a first mechanically variable capacitor, and the first high-speed matching circuit includes a first electronically variable capacitor, and the first electronically variable capacitor includes a plurality of first capacitor elements and a plurality of first switching elements electrically connected to the plurality of first capacitor elements, respectively.

[0028] Hereinafter, each embodiment of the present disclosure will be described in detail with reference to the drawings. In each drawing, the same or similar elements are designated by the same reference numerals, and redundant explanations will be omitted. Unless otherwise specified, the positional relationships, such as up, down, left, and right, will be described based on the positional relationships shown in the drawings. The dimensional ratios in the drawings do not represent actual ratios, and the actual ratios are not limited to the ratios shown in the drawings.

[0029] <Configuration Example of Plasma Processing System> FIG. 1 is a diagram illustrating a configuration example of a plasma processing system. In one embodiment, the plasma processing system includes a plasma processing apparatus 1 and a control unit 2. The plasma processing system is an example of a substrate processing system, and the plasma processing apparatus 1 is an example of a substrate processing apparatus. The plasma processing apparatus 1 includes a plasma processing chamber 10, a substrate support 11, and a plasma generation unit 12. The plasma processing chamber 10 has a plasma processing space. The plasma processing chamber 10 also has at least one gas supply port for supplying at least one processing gas to the plasma processing space and at least one gas exhaust port for exhausting gas from the plasma processing space. The gas supply port is connected to a gas supply unit 20 (described later), and the gas exhaust port is connected to an exhaust system 40 (described later). The substrate support 11 is disposed in the plasma processing space and has a substrate support surface for supporting a substrate.

[0030] The plasma generating unit 12 is configured to generate plasma from at least one processing gas supplied into the plasma processing space. The plasma generated in the plasma processing space may be capacitively coupled plasma (CCP), inductively coupled plasma (ICP), electron-cyclotron-resonance plasma (ECR plasma), helicon wave plasma (HWP), surface wave plasma (SWP), or the like. Various types of plasma generators may be used, including alternating current (AC) plasma generators and direct current (DC) plasma generators. In one embodiment, the AC signal (AC power) used in the AC plasma generator has a frequency in the range of 100 kHz to 10 GHz. Thus, AC signals include radio frequency (RF) signals and microwave signals. In one embodiment, the RF signal has a frequency in the range of 100 kHz to 150 MHz.

[0031] The control unit 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform various processes described in this disclosure. The control unit 2 may be configured to control each element of the plasma processing apparatus 1 to perform various processes described herein. In one embodiment, part or all of the control unit 2 may be included in the plasma processing apparatus 1. The control unit 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The control unit 2 may be implemented by, for example, a computer 2a. The processing unit 2a1 may be configured to read a program from the storage unit 2a2 and execute the read program to perform various control operations. This program may be stored in the storage unit 2a2 in advance or may be acquired via a medium when needed. The acquired program is stored in the storage unit 2a2 and read from the storage unit 2a2 by the processing unit 2a1 for execution. The medium may be various storage media readable by the computer 2a or a communication line connected to the communication interface 2a3. The processing unit 2a1 may be a CPU (Central Processing Unit). The storage unit 2a2 may include a random access memory (RAM), a read-only memory (ROM), a hard disk drive (HDD), a solid state drive (SSD), or a combination thereof. The communication interface 2a3 may communicate with the plasma processing apparatus 1 via a communication line such as a local area network (LAN).

[0032] The following describes a configuration example of a capacitively coupled plasma processing apparatus as an example of the plasma processing apparatus 1. Fig. 2 is a diagram for explaining a configuration example of a capacitively coupled plasma processing apparatus.

[0033] The capacitively coupled plasma processing apparatus 1 includes a plasma processing chamber 10, a gas supply 20, a power supply 30, and an exhaust system 40. The plasma processing apparatus 1 also includes a substrate support 11 and a gas inlet. The gas inlet is configured to introduce at least one process gas into the plasma processing chamber 10. The gas inlet includes a showerhead 13. The substrate support 11 is disposed within the plasma processing chamber 10. The showerhead 13 is disposed above the substrate support 11. In one embodiment, the showerhead 13 forms at least a portion of the ceiling of the plasma processing chamber 10. The plasma processing chamber 10 has a plasma processing space 10s defined by the showerhead 13, a sidewall 10a of the plasma processing chamber 10, and the substrate support 11. The plasma processing chamber 10 is grounded. The showerhead 13 and the substrate support 11 are electrically insulated from the housing of the plasma processing chamber 10.

[0034] The substrate support 11 includes a main body 111 and a ring assembly 112. The main body 111 has a central region 111a for supporting a substrate W and an annular region 111b for supporting the ring assembly 112. A wafer is an example of a substrate W. The annular region 111b of the main body 111 surrounds the central region 111a of the main body 111 in a plan view. The substrate W is disposed on the central region 111a of the main body 111, and the ring assembly 112 is disposed on the annular region 111b of the main body 111 so as to surround the substrate W on the central region 111a of the main body 111. Therefore, the central region 111a is also called a substrate support surface for supporting the substrate W, and the annular region 111b is also called a ring support surface for supporting the ring assembly 112.

[0035] In one embodiment, the main body 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 includes a conductive member. The conductive member of the base 1110 can function as a lower electrode. The electrostatic chuck 1111 is disposed on the base 1110. The electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic electrode 1111b disposed within the ceramic member 1111a. The ceramic member 1111a has a central region 111a. In one embodiment, the ceramic member 1111a also has an annular region 111b. Note that the annular region 111b may also be provided by another member surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating member. In this case, the ring assembly 112 may be disposed on the annular electrostatic chuck or the annular insulating member, or may be disposed on both the electrostatic chuck 1111 and the annular insulating member. Furthermore, at least one RF / DC electrode coupled to an RF power supply 31 and / or a DC power supply 32, which will be described later, may be disposed within the ceramic member 1111a. In this case, the at least one RF / DC electrode functions as a lower electrode. When a bias RF signal and / or a DC signal, which will be described later, is supplied to the at least one RF / DC electrode, the RF / DC electrode is also called a bias electrode. Note that the conductive member of the base 1110 and the at least one RF / DC electrode may function as multiple lower electrodes. Furthermore, the electrostatic electrode 1111b may function as a lower electrode. Therefore, the substrate support 11 includes at least one lower electrode.

[0036] The ring assembly 112 includes one or more annular members. In one embodiment, the one or more annular members include one or more edge rings and at least one cover ring. The edge rings are formed of a conductive or insulating material, and the cover rings are formed of an insulating material.

[0037] The substrate support 11 may also include a temperature adjustment module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature. The temperature adjustment module may include a heater, a heat transfer medium, a flow passage 1110a, or a combination thereof. A heat transfer fluid such as brine or a gas flows through the flow passage 1110a. In one embodiment, the flow passage 1110a is formed in the base 1110, and one or more heaters are disposed in the ceramic member 1111a of the electrostatic chuck 1111. The substrate support 11 may also include a heat transfer gas supply configured to supply a heat transfer gas to a gap between the backside of the substrate W and the central region 111a.

[0038] The showerhead 13 is configured to introduce at least one process gas from the gas supply unit 20 into the plasma processing space 10s. The showerhead 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and multiple gas inlets 13c. The process gas supplied to the gas supply port 13a passes through the gas diffusion chamber 13b and is introduced into the plasma processing space 10s from the multiple gas inlets 13c. The showerhead 13 also includes at least one upper electrode. In addition to the showerhead 13, the gas inlet may also include one or more side gas injectors (SGIs) attached to one or more openings formed in the sidewall 10a.

[0039] The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is configured to supply at least one process gas from a corresponding gas source 21 to the showerhead 13 via a corresponding flow controller 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. Additionally, the gas supply unit 20 may include at least one flow modulation device that modulates or pulses the flow rate of the at least one process gas.

[0040] The power supply 30 includes an RF power supply 31 coupled to the plasma processing chamber 10 via at least one impedance matching circuit. The RF power supply 31 is configured to supply at least one RF signal (RF power) to at least one lower electrode and / or at least one upper electrode. This generates a plasma from at least one processing gas supplied to the plasma processing space 10s. Therefore, the RF power supply 31 can function as at least a part of the plasma generation unit 12. Furthermore, by supplying a bias RF signal to the at least one lower electrode, a bias potential is generated on the substrate W, thereby attracting ion components in the formed plasma to the substrate W.

[0041] In one embodiment, the RF power supply 31 includes a first RF generating unit 31a and a second RF generating unit 31b. The first RF generating unit 31a is coupled to at least one lower electrode and / or at least one upper electrode via at least one impedance matching circuit and is configured to generate a source RF signal (source RF power) for plasma generation. In one embodiment, the source RF signal has a frequency in the range of 10 MHz to 150 MHz. In one embodiment, the first RF generating unit 31a may be configured to generate multiple source RF signals having different frequencies. The generated one or more source RF signals are supplied to at least one lower electrode and / or at least one upper electrode.

[0042] The second RF generator 31b is coupled to at least one lower electrode via at least one impedance matching circuit and is configured to generate a bias RF signal (bias RF power). The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency lower than the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency in the range of 100 kHz to 60 MHz. In one embodiment, the second RF generator 31b may be configured to generate multiple bias RF signals having different frequencies. The generated one or more bias RF signals are supplied to at least one lower electrode. In various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed.

[0043] The power supply 30 may also include a DC power supply 32 coupled to the plasma processing chamber 10. The DC power supply 32 includes a first DC generator 32a and a second DC generator 32b. In one embodiment, the first DC generator 32a is connected to the at least one lower electrode and configured to generate a first DC signal. The generated first DC signal is applied to the at least one lower electrode. In one embodiment, the second DC generator 32b is connected to the at least one upper electrode and configured to generate a second DC signal. The generated second DC signal is applied to the at least one upper electrode.

[0044] In various embodiments, the first and second DC signals may be pulsed. In this case, a sequence of voltage pulses is applied to at least one lower electrode and / or at least one upper electrode. The voltage pulses may have a rectangular, trapezoidal, triangular, or combination thereof pulse waveform. In one embodiment, a waveform generator for generating the sequence of voltage pulses from the DC signal is connected between the first DC generator 32a and at least one lower electrode. Thus, the first DC generator 32a and the waveform generator constitute a voltage pulse generator. When the second DC generator 32b and the waveform generator constitute a voltage pulse generator, the voltage pulse generator is connected to at least one upper electrode. The voltage pulses may have either positive or negative polarity. Furthermore, the sequence of voltage pulses may include one or more positive voltage pulses and one or more negative voltage pulses within one period. The first and second DC generating units 32a and 32b may be provided in addition to the RF power supply 31, or the first DC generating unit 32a may be provided instead of the second RF generating unit 31b.

[0045] The exhaust system 40 may be connected to, for example, a gas exhaust port 10e provided at the bottom of the plasma processing chamber 10. The exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure in the plasma processing space 10s is regulated by the pressure regulating valve. The vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.

[0046] FIG. 3 is a diagram showing an example of coupling between the power supply 30 and the plasma processing chamber 10 (hereinafter also referred to as "chamber 10"). In one embodiment, the first RF generating unit 31a is coupled to the chamber 10 via a first transmission line TL1. In one embodiment, coupling the first RF generating unit 31a to the chamber 10 includes electrically connecting the first RF generating unit 31a to an upper electrode or a lower electrode of the plasma processing apparatus 1. The first RF generating unit 31a is configured to generate a source RF signal for plasma generation and supply the source RF signal to the upper electrode or the lower electrode. In other words, the first RF generating unit 31a is an example of a source RF generator.

[0047] An impedance matching box 50 is disposed on the first transmission line TL1 between the first RF generating unit 31a and the chamber 10. The impedance matching box 50 is electrically connected to the first transmission line TL1. In one embodiment, the impedance matching box 50 may include a first matching circuit 52 and a second matching circuit 54. The impedance matching box 50 is configured to match the impedance on the first RF generating unit 31a side with the impedance on the chamber 10 side by controlling the variable capacitors of the first matching circuit 52 and the second matching circuit 54.

[0048] The first matching circuit 52 is disposed between the first transmission line TL1 and ground potential. Specifically, as shown in FIG. 3 , one end of the first matching circuit 52 is electrically connected to the first transmission line TL1. The other end of the first matching circuit 52 is electrically connected to ground potential. The first matching circuit 52 includes a first low-speed matching circuit 52A and a first high-speed matching circuit 52B. The first low-speed matching circuit 52A and the first high-speed matching circuit 52B each include a variable capacitor. As shown in FIG. 3 , the first low-speed matching circuit 52A and the first high-speed matching circuit 52B are connected in parallel with each other. That is, the capacitance of the first matching circuit 52 is the sum of the capacitances of the first low-speed matching circuit 52A and the first high-speed matching circuit 52B.

[0049] The first low-speed matching circuit 52A is configured to perform a low-speed matching operation on the source RF signal on the first transmission line TL1 by changing the capacitance of the first low-speed matching circuit 52A. In one embodiment, the low-speed matching operation may be repeatedly performed multiple times at a frequency of once every 10 msec to several 100 msec.

[0050] In one embodiment, the first low-speed matching circuit 52A includes a mechanical variable capacitor. The mechanical variable capacitor may be configured so that its capacitance can be adjusted by driving a motor, actuator, or the like. The mechanical variable capacitor may be appropriately selected so as to have the response performance (switching speed from maximum capacitance to minimum capacitance) required for low-speed matching operation. The mechanical variable capacitor may be, for example, a vacuum variable capacitor. In one embodiment, the first low-speed matching circuit 52A may include multiple mechanical variable capacitors. In one embodiment, the maximum capacitance of the mechanical variable capacitors constituting the first low-speed matching circuit 52A (when the first low-speed matching circuit 52A includes multiple variable capacitors, this refers to the total maximum capacitance; the same applies hereinafter in this specification) may be approximately several tens of pF to several thousand pF.

[0051] The first high-speed matching circuit 52B is configured to perform a high-speed matching operation on the source RF signal on the first transmission line TL1 by changing the capacitance of the first high-speed matching circuit 52B. In one embodiment, the high-speed matching operation may be repeatedly performed multiple times at a frequency of once every several tens of nanoseconds to several microseconds. In one embodiment, the speed of the high-speed matching operation is set according to the frequency of the bias signal.

[0052] In one embodiment, the first high-speed matching circuit 52B includes an electronic variable capacitor. FIG. 4 is a diagram illustrating an example of an electronic variable capacitor. As shown in FIG. 4, the electronic variable capacitor may include a plurality of capacitor elements (C1 to Cn) and a plurality of switching elements (S1 to Sn) electrically connected to the plurality of capacitor elements. The electronic variable capacitor may be configured such that the overall capacitance can be adjusted by controlling the on / off of each switching element (S1 to Sn) in accordance with a control signal. In one embodiment, the switching elements (S1 to Sn) may be appropriately selected to have the response performance (on / off switching speed) required for high-speed matching operation. In one embodiment, the switching elements may be field-effect transistors (FETs).

[0053] In one embodiment, the electronic variable capacitor may be a board-mounted capacitor. In one embodiment, the first high-speed matching circuit 52B may include multiple electronic variable capacitors. The maximum capacitance of the electronic variable capacitors constituting the first high-speed matching circuit 52B (if the first high-speed matching circuit 52B includes multiple variable capacitors, this refers to the total maximum capacitance; the same applies hereinafter in this specification) may be approximately 10 pF to several hundred pF. In one embodiment, the maximum capacitance of the mechanical variable capacitor constituting the first low-speed matching circuit 52A may be 10 times or more the maximum capacitance of the electronic variable capacitor constituting the first high-speed matching circuit 52B.

[0054] Returning to FIG. 3 , the description continues. The second matching circuit 54 is disposed on the first transmission line TL1. Specifically, one end of the second matching circuit 54 is electrically connected to the first RF generating unit 31a side of the first transmission line TL1. The other end of the second matching circuit 54 is electrically connected to the chamber 10 side of the first transmission line TL1. The second matching circuit 54 includes a second low-speed matching circuit 54A and a second high-speed matching circuit 54B. The second low-speed matching circuit 54A and the second high-speed matching circuit 54B each include a variable capacitor. As shown in FIG. 3 , the second low-speed matching circuit 54A and the second high-speed matching circuit 54B are connected in parallel with each other. That is, the capacitance of the second matching circuit 54 is the sum of the capacitances of the second low-speed matching circuit 54A and the second high-speed matching circuit 54B. In one embodiment, the second low-speed matching circuit 54A may be configured similarly to the first low-speed matching circuit 52A described above. The second high-speed matching circuit 54B may be configured similarly to the first high-speed matching circuit 52B described above.

[0055] In one embodiment, the first DC generating unit 32a is coupled to the chamber 10 via a second transmission line TL2. In one embodiment, coupling the first DC generating unit 32a to the chamber 10 includes electrically connecting the first DC generating unit 32a to a lower electrode of the plasma processing apparatus 1. The first DC generating unit 32a is configured to generate a first DC signal and supply the first DC signal to the lower electrode as a bias DC signal. That is, the first DC generating unit 32a is an example of a bias generator.

[0056] In one embodiment, a waveform generating unit 60 may be disposed on the second transmission line TL2. The waveform generating unit 60 may be configured to generate a sequence of voltage pulses from the first DC signal generated by the first DC generating unit 32a. That is, the sequence of voltage pulses may be applied to the lower electrode. The voltage pulses may have a pulse waveform that is rectangular, trapezoidal, triangular, or a combination thereof. In one embodiment, the waveform generating unit 60 may be provided integrally with the first DC generating unit 32a as part of the power supply 30.

[0057] In one embodiment, an RF filter 62 may be disposed on the second transmission line TL2. The RF filter is configured to suppress RF signals, such as a source RF signal and a bias RF signal, from entering the first DC generating unit 32a via the second transmission line TL2. The RF filter may remove signals of a specific frequency depending on the frequency of the RF signal. In one embodiment, the RF filter may be a coil. Note that, in one embodiment, the RF filter 62 may not be provided.

[0058] 3 may be controlled by the control unit 2 (see FIG. 2). For example, the control unit 2 may control the first matching circuit 52 and the second matching circuit 54 to perform the impedance matching operation described below when plasma generation starts (hereinafter also referred to as "ignition").

[0059] 5 is a flowchart showing an example of an impedance matching method according to one embodiment (hereinafter also referred to as "this matching method"). As shown in Fig. 5, this matching method may include a step ST1 of igniting plasma, a step ST2 of performing a low-speed matching operation, a step ST3 of determining whether the low-speed matching operation has stabilized, and a step ST4 of performing a high-speed matching operation.

[0060] FIG. 6 is an example of a timing chart of this matching method. In FIG. 6, the horizontal axis is a time axis including steps ST1 to ST4 of this matching method. In one embodiment, the scale of the time axis in FIG. 6 (the time from the left end to the right end) can be from about 1 second to several thousand seconds. In FIG. 6, "RF" indicates whether or not a source RF signal is supplied (on / off). "DC" indicates whether or not a bias DC signal is supplied (on / off). "RF reflected wave" indicates the power level of the reflected wave of the source RF signal propagating through the first transmission line TL1.

[0061] In step ST1, plasma is ignited in the chamber 10. In one embodiment, a gas for generating plasma is supplied from the gas supply unit 20 into the plasma processing space 10s via the shower head 13. A source RF signal is also supplied from the first RF generator 31a ("RF" in FIG. 6 is turned from "OFF" to "ON"). This starts plasma generation in the chamber 10. That is, the plasma is ignited. In one embodiment, the controller 2 may determine whether plasma has been ignited in the chamber 10, and may start the slow matching operation in step ST2 if it determines that plasma has been ignited.

[0062] In step ST2, a slow matching operation is performed. Immediately after plasma is ignited (started to be generated) in the chamber 10, the plasma in the chamber is unstable and fluctuates greatly. The control unit 2 performs a slow matching operation on the source RF signal on the first transmission line TL1 using the impedance matching device 50. The slow matching operation may be a process for adjusting the impedance on the first RF generating unit 31a side to follow a relatively large load fluctuation (impedance change) on the chamber 10 side, for example, during plasma ignition. In one embodiment, the slow matching operation may be repeatedly performed at a frequency of approximately once every 10 ms to several hundred ms. In one embodiment, step ST2 may be performed for approximately 0.1 seconds to several seconds. Step ST2 is an example of a first period.

[0063] In one embodiment, the control unit 2 changes the capacitances of the first low-speed matching circuit 52A and the second low-speed matching circuit 54A based on the RF reflection characteristics of the source RF signal propagating through the first transmission line TL1. The RF reflection characteristics may include, for example, one or more of: (a) the ratio of the power of the forward wave (Pf) to the power of the reflected wave (Pr) of the source RF signal at the input end or the output end of the impedance matching circuit 50; (b) the resistance component of the impedance; (c) the reflection coefficient; (d) the return loss; and (e) the S-parameter.

[0064] In one embodiment, the control unit 2 may independently change the capacitances of the first low-speed matching circuit 52A and the second low-speed matching circuit 54A. For example, the control unit 2 may change the capacitance of the first low-speed matching circuit 52A independently of the second low-speed matching circuit 54A by controlling the drive amount of a motor or the like of a mechanical variable capacitor that constitutes the first low-speed matching circuit 52A. For another example, the control unit 2 may change the capacitance of the second low-speed matching circuit 54A independently of the first low-speed matching circuit 52A by controlling the drive amount of a motor or the like of a mechanical variable capacitor that constitutes the second low-speed matching circuit 54A.

[0065] In one embodiment, during the slow matching operation in step ST2, the capacitances of the first high-speed matching circuit 52B and the second high-speed matching circuit 54B may not be changed. For example, the capacitances of the first high-speed matching circuit 52B and the second high-speed matching circuit 54B may each be maintained at a constant value (e.g., an intermediate value between the maximum and minimum capacitances). In one embodiment, during the slow matching operation, the capacitance of the first high-speed matching circuit 52B is maintained at a fixed value between the maximum and minimum capacitances of the first high-speed matching circuit 52B, and the capacitance of the second high-speed matching circuit 54B is maintained at a fixed value between the maximum and minimum capacitances of the second high-speed matching circuit 54B. In one embodiment, during the slow matching operation, the capacitance of the first high-speed matching circuit 52B is maintained at a fixed value near the intermediate value between the maximum and minimum capacitances of the first high-speed matching circuit 52B, and the capacitance of the second high-speed matching circuit 54B is maintained at a fixed value near the intermediate value between the maximum and minimum capacitances of the second high-speed matching circuit 54B.

[0066] In one embodiment, in process ST2, a bias DC signal may be supplied to the lower electrode from the first DC generator 32a via the second transmission line TL2 ("DC" in FIG. 6 is turned from "OFF" to "ON"). The bias DC signal may have a negative polarity. The bias DC signal may be pulsed by the waveform generator 60 and have a sequence of voltage pulses (hereinafter also referred to as a "pulsed DC signal"). The pulsed DC signal has a frequency lower than that of the source RF signal. In one embodiment, the pulsed DC signal has a frequency in the range of approximately 100 kHz to 1 MHz. Note that the bias DC signal may have a positive polarity as long as it applies a potential difference between the plasma in the chamber 10 and the lower electrode (or the substrate on the lower electrode). In one embodiment, the bias DC signal may be supplied simultaneously with the start of process ST2, or may be supplied at the time of plasma ignition before the start of process ST2.

[0067] 6, the power level of the reflected wave of the source RF signal gradually decreases. That is, the impedance on the first RF generating unit 31a side follows the fluctuation in the plasma load (change in the impedance on the chamber 10 side) caused by plasma ignition, and the slow matching operation becomes stable.

[0068] In step ST3, the control unit 2 determines whether the low-speed matching operation has stabilized. If it is determined that the low-speed matching operation has stabilized, the low-speed matching operation is terminated, and the high-speed matching operation of step ST4 is executed. If it is not determined that the low-speed matching operation has stabilized, the low-speed matching operation is continued. This determination may be made, for example, based on whether the power level of the reflected wave of the source RF signal is equal to or less than a given threshold. Furthermore, for example, this determination may be made based on the duration of the low-speed matching operation, the amount of fluctuation in the flow rate of the gas supplied to the chamber 10, whether the power level of the source RF signal is at a set output, or the like.

[0069] In step ST4, a high-speed matching operation is performed. The control unit 2 uses the impedance matching device 50 to perform a high-speed matching operation on the source RF signal on the first transmission line TL1. The high-speed matching operation may be a process for causing the impedance on the first RF generating unit 31a side to follow a relatively high-speed load fluctuation (impedance change) of the chamber 10, for example, when a bias signal is supplied. In one embodiment, the high-speed matching operation may be repeatedly performed at a frequency of once every tens of nanoseconds to several microseconds. In one embodiment, the high-speed matching operation may be performed after a low-speed matching operation. In one embodiment, step ST4 may be performed for a period of several seconds to several tens of minutes. Step ST4 is an example of a second period.

[0070] In one embodiment, the control unit 2 changes the capacitances of the first high-speed matching circuit 52B and the second high-speed matching circuit 54B based on the RF reflection characteristics of the source RF signal propagating through the first transmission line TL1. The RF reflection characteristics may include, for example, one or more of: (a) the ratio of the power (Pf) of the forward wave of the source RF signal to the power (Pr) of the reflected wave thereof at the input end or the output end of the impedance matching box 50; (b) the resistance component of the impedance; (c) the reflection coefficient; (d) the return loss; and (e) the S-parameter. In one embodiment, the control unit 2 changes the capacitances of the first high-speed matching circuit 52B and the second high-speed matching circuit 54B based on a synchronization signal. A synchronization signal generator for generating the synchronization signal may be provided in the first RF generating unit 31a or the second RF generating unit 31b, or may be provided outside the first RF generating unit 31a or the second RF generating unit 31b.

[0071] In one embodiment, the control unit 2 may independently change the capacitances of the first high-speed matching circuit 52B and the second high-speed matching circuit 54B. For example, the control unit 2 may independently change the capacitance of the first high-speed matching circuit 52B from the second high-speed matching circuit 54B by controlling the on / off of each switching element of an electronic variable capacitor that constitutes the first high-speed matching circuit 52B. For another example, the control unit 2 may independently change the capacitance of the second high-speed matching circuit 54B from the first high-speed matching circuit 52B by controlling the on / off of each switching element of an electronic variable capacitor that constitutes the second high-speed matching circuit 54B.

[0072] In one embodiment, the capacitances of the first low-speed matching circuit 52A and the second low-speed matching circuit 54A may not be changed during the high-speed matching operation in step ST4. For example, the capacitances of the first low-speed matching circuit 52A and the second low-speed matching circuit 54A may be maintained at the values ​​(stable matching points) at the end of step ST2. Furthermore, if the plasma is switched during the high-speed matching operation in step ST4 due to a change in the process gas or RF conditions, for example, it is necessary to return from the high-speed matching operation to the low-speed matching operation in order to perform the stabilization sequence again. In this case, the high-speed matching operation in step ST4 is returned to the low-speed matching operation in step ST2, and the sequence of FIG. 5 is executed again.

[0073] FIG. 7A is an example of a timing chart when a high-speed matching operation is not performed. FIG. 7B is an example of a timing chart when a high-speed matching operation is performed. In FIGS. 7A and 7B, the horizontal axis is a time axis corresponding to the period T of the pulsed DC signal. In one embodiment, the scale of the time axis (time from the left end to the right end) of FIGS. 7A and 7B may be approximately 200 nsec to 1 μsec. In FIGS. 7A and 7B, "RF" indicates the power level of the source RF signal. "DC" indicates the voltage level of the pulsed DC signal. "RF reflected wave" indicates the power level of the reflected wave of the source RF signal propagating through the first transmission line TL1. "C52B" is the capacitance of the first high-speed matching circuit 52B. "C54B" is the capacitance of the second high-speed matching circuit 54B.

[0074] 7A shows an example in which the high-speed matching operation is not performed, i.e., step ST4 is not performed, and the capacitances of the first high-speed matching circuit 52B and the second high-speed matching circuit 54B are maintained constant. In this case, the power level of the reflected wave increases in synchronization with the voltage level of the pulsed DC signal. This is thought to be because, when the high-speed matching operation is not performed, intermodulation distortion (IMD) occurs due to fluctuations in the plasma load caused by the pulsed DC signal. When IMD occurs, mismatch occurs due to frequency modulation with the fundamental wave of the source RF signal, and the power level of the reflected wave of the source RF signal increases.

[0075] 7B shows an example of a case where a high-speed matching operation is performed, i.e., where step ST4 is performed and the capacitances of the first high-speed matching circuit 52B and the second high-speed matching circuit 54B are changed at high speed to follow the load fluctuations caused by the pulsed DC signal. In this case, the power level of the reflected wave is kept lower than in the case shown in FIG. 7A. This is thought to be because, when a high-speed matching operation is performed, the load fluctuations caused by the pulsed DC signal are suppressed, thereby suppressing the occurrence of IMD. In other words, this matching method can suppress IMD.

[0076] The impedance changes two-dimensionally across the load range in response to load fluctuations. Therefore, when there are two or more impedance adjustment means (knobs), the accuracy of the matching operation is further improved. According to this matching method, the capacitances of the first high-speed matching circuit 52B and the second high-speed matching circuit 54B can be changed independently in the high-speed matching operation of step ST4. In other words, the high-speed matching operation of step ST4 has two impedance adjustment means (knobs), which can improve the accuracy of the matching operation. This can further suppress IMD.

[0077] Furthermore, according to this matching method, a mechanical variable capacitor and an electronic variable capacitor can be selectively used depending on the load fluctuation range and speed. That is, the slow matching operation in step ST2 is performed using the first slow matching circuit 52A and the second slow matching circuit 54A. The load fluctuation range immediately after plasma ignition is larger than the load fluctuation range caused by the pulsed DC signal, but the speed of the load fluctuation is slow. Therefore, it is preferable to use the first slow matching circuit 52A and the second slow matching circuit 54A, which are configured with mechanical variable capacitors. On the other hand, the fast matching operation in step ST4 is performed using the first fast matching circuit 52B and the second fast matching circuit 54B. The speed of the load fluctuation caused by the pulsed DC signal is faster than the load fluctuation immediately after plasma ignition, but the load fluctuation range is small. Therefore, it is preferable to use the first fast matching circuit 52B and the second fast matching circuit 54B, which are configured with electronic variable capacitors.

[0078] <Modifications> Figures 8A to 8C are diagrams showing modifications of the configuration shown in Figure 3. Below, differences from the configuration shown in Figure 3 will be mainly described, and a description of the common configuration will be omitted.

[0079] In one embodiment, the impedance matching box 50 may not include the second matching circuit 54. For example, as shown in FIGS. 8A and 8C , the impedance matching box 50 may include a capacitor 56 instead of the second matching circuit 54. The capacitor 56 may be disposed on the first transmission line TL1. The capacitor 56 may be, for example, a vacuum capacitor. Note that the capacitor 56 may also be a mechanical variable capacitor (for example, a vacuum variable capacitor).

[0080] In the examples shown in FIGS. 8A and 8C , the first RF generating unit 31a may be configured to change the frequency of the RF signal it supplies. For example, the first RF generating unit 31a may be configured to change the frequency between a minimum frequency (e.g., −10% of the design frequency) and a maximum frequency (e.g., +10% of the design frequency). Then, in the high-speed matching operation of step ST4, the control unit 2 may change the capacitance of the first high-speed matching circuit 52B and change the frequency of the RF signal supplied from the first RF generating unit 31a so as to follow load fluctuations caused by the bias signal (pulsed DC signal or bias RF signal). In this case, the first RF generating unit 31a, together with the first high-speed matching circuit 52B, functions as an impedance adjustment means (knob) in the high-speed matching operation of step ST4.

[0081] In one embodiment, instead of or in addition to supplying the first DC signal as a bias signal to the lower electrode, a bias RF signal generated by the second RF generating unit 31b may be supplied to the lower electrode of the chamber 10. For example, as shown in FIGS. 8B and 8C , the second RF generating unit 31b may be electrically connected to the lower electrode of the chamber 10 via a third transmission line TL3. An impedance matching unit 70 is disposed on the third transmission line TL3. As shown in FIGS. 8B and 8C , the impedance matching unit 50 for the source RF signal may be provided with an RF filter 58. The RF filter 58 is configured to suppress the bias RF signal from entering the first RF generating unit 31a via the first transmission line TL1. Furthermore, the impedance matching unit 70 for the bias RF signal may be provided with an RF filter 72. The RF filter 72 is configured to suppress the bias RF signal from entering the second RF generating unit 31b via the third transmission line TL3. In the example shown in FIG. 8B, in the high-speed matching operation of step ST4, the control unit 2 may change the capacitance of the first high-speed matching circuit 52B and the second high-speed matching circuit 54B so as to follow the load fluctuation due to the bias RF signal.

[0082] The present disclosure may be implemented in a plasma processing apparatus 1 using any plasma source other than a capacitively coupled plasma processing apparatus. For example, the matching operation may be implemented in an inductively coupled plasma processing apparatus. In this case, the inductively coupled plasma processing apparatus includes a substrate support unit disposed in a chamber and including a lower electrode, and an antenna disposed above the chamber. The inductively coupled plasma processing apparatus may have a configuration similar to that described with reference to FIG. 3 and FIGS. 8A to 8C. The first RF generating unit 31a may be connected to the antenna via a first transmission line TL1, and the above-described impedance matching box 50 may be provided on the first transmission line TL1.

[0083] Embodiments of the present disclosure further include the following aspects.

[0084] an upper electrode disposed above the substrate support; a source RF generator configured to supply a source RF signal to the upper electrode or the lower electrode to generate plasma in the chamber; an impedance matching circuit electrically connected to a transmission line between the source RF generator and the upper electrode or the lower electrode, the impedance matching circuit including a first slow matching circuit and a first fast matching circuit connected in parallel; a bias generator configured to supply a bias signal to the lower electrode; and a control unit configured to perform a slow matching operation on the source RF signal by the first slow matching circuit during a first period, and to perform a fast matching operation on the source RF signal by the first fast matching circuit during a second period after the first period.

[0085] (Supplementary Note 2) The plasma processing apparatus according to Supplementary Note 1, wherein the first low-speed matching circuit includes a first mechanical variable capacitor, and the first high-speed matching circuit includes a first electronic variable capacitor, and the first electronic variable capacitor includes a plurality of first capacitor elements and a plurality of first switching elements electrically connected to the plurality of first capacitor elements, respectively.

[0086] (Supplementary Note 3) The plasma processing apparatus according to Supplementary Note 2, wherein the maximum capacitance of the first mechanical variable capacitor is 10 times or more the maximum capacitance of the first electronic variable capacitor.

[0087] (Appendix 4) The plasma processing apparatus according to any one of Appendices 1 to 3, wherein the first low-speed matching circuit is configured to perform the low-speed matching operation at a frequency of about once every 10 ms to several hundred ms, and the first high-speed matching circuit is configured to perform the high-speed matching operation at a frequency of about once every several tens of ns to several μs.

[0088] (Supplementary Note 5) The plasma processing apparatus according to any one of Supplementary Note 1 to Supplementary Note 4, wherein the first period is a period from when plasma generation starts in the chamber until the slow matching operation becomes stable.

[0089] (Supplementary Note 6) The plasma processing apparatus according to any one of Supplementary Note 1 to Supplementary Note 5, wherein the first low-speed matching circuit and the first high-speed matching circuit are arranged between the transmission line and a ground potential.

[0090] (Supplementary Note 7) The plasma processing apparatus according to any one of Supplementary Note 1 to Supplementary Note 6, wherein the impedance matching device includes a second low-speed matching circuit and a second high-speed matching circuit connected in parallel to each other, and the second low-speed matching circuit and the second high-speed matching circuit are arranged on the transmission line.

[0091] (Supplementary Note 8) The plasma processing apparatus of Supplementary Note 7, wherein the first slow matching circuit includes a first mechanical variable capacitor, the first fast matching circuit includes a first electronic variable capacitor, and the first electronic variable capacitor includes a plurality of first capacitor elements and a plurality of first switching elements electrically connected to the plurality of first capacitor elements, respectively, the second slow matching circuit includes a second mechanical variable capacitor, and the second fast matching circuit includes a second electronic variable capacitor, and the second electronic variable capacitor includes a plurality of second capacitor elements and a plurality of second switching elements electrically connected to the plurality of second capacitor elements, respectively.

[0092] (Supplementary Note 9) The plasma processing apparatus according to Supplementary Note 6, wherein the source RF generator is configured to be able to change a setting value of the frequency of the source RF signal.

[0093] (Supplementary Note 10) The plasma processing apparatus according to any one of Supplementary Note 1 to Supplementary Note 9, wherein the bias generator includes a bias RF generator configured to generate a bias RF signal.

[0094] (Supplementary Note 11) The plasma processing apparatus according to any one of Supplementary Note 1 to Supplementary Note 10, wherein the bias generator includes a bias DC generating unit configured to generate a bias DC signal, the bias DC signal having a sequence of voltage pulses.

[0095] (Supplementary Note 12) A plasma processing apparatus comprising: a chamber; a substrate support disposed within the chamber and including a lower electrode; an antenna disposed above the chamber; a source RF generator configured to supply a source RF signal to the antenna to generate plasma in the chamber; an impedance matching circuit electrically connected to a transmission line between the source RF generator and the antenna, the impedance matching circuit including a first slow matching circuit and a first fast matching circuit connected in parallel; a bias generator configured to supply a bias signal to the lower electrode; and a control unit configured to perform a slow matching operation on the source RF signal by the first slow matching circuit during a first period, and to perform a fast matching operation on the source RF signal by the first fast matching circuit during a second period after the first period.

[0096] (Supplementary Note 13) The plasma processing apparatus according to Supplementary Note 12, wherein the first low-speed matching circuit includes a first mechanical variable capacitor, and the first high-speed matching circuit includes a first electronic variable capacitor, and the first electronic variable capacitor includes a plurality of first capacitor elements and a plurality of first switching elements electrically connected to the plurality of first capacitor elements, respectively.

[0097] (Supplementary Note 14) The plasma processing apparatus according to Supplementary Note 12 or Supplementary Note 13, wherein the first low-speed matching circuit and the first high-speed matching circuit are arranged between the transmission line and a ground potential.

[0098] (Supplementary Note 15) The plasma processing apparatus according to any one of Supplementary Note 12 to Supplementary Note 14, wherein the impedance matching box includes a second low-speed matching circuit and a second high-speed matching circuit connected in parallel to each other, and the second low-speed matching circuit and the second high-speed matching circuit are arranged on the transmission line.

[0099] (Supplementary Note 16) The plasma processing apparatus of Supplementary Note 15, wherein the first slow matching circuit includes a first mechanical variable capacitor, the first fast matching circuit includes a first electronic variable capacitor, and the first electronic variable capacitor includes a plurality of first capacitor elements and a plurality of first switching elements electrically connected to the plurality of first capacitor elements, respectively, the second slow matching circuit includes a second mechanical variable capacitor, and the second fast matching circuit includes a second electronic variable capacitor, and the second electronic variable capacitor includes a plurality of second capacitor elements and a plurality of second switching elements electrically connected to the plurality of second capacitor elements, respectively.

[0100] (Supplementary Note 17) The plasma processing apparatus according to any one of Supplementary Note 14 to Supplementary Note 16, wherein the source RF generator is configured to be able to change the frequency of the source RF signal.

[0101] (Supplementary Note 18) An impedance matching method comprising: a step of supplying an RF signal from an RF generator to a load; a step of performing a slow matching operation on the RF signal by a first slow matching circuit during a first period; and a step of performing a fast matching operation on the RF signal by a first fast matching circuit connected in parallel to the first slow matching circuit during a second period after the first period.

[0102] (Supplementary Note 19) The impedance matching method according to Supplementary Note 18, wherein the first low-speed matching circuit includes a first mechanical variable capacitor, and the first high-speed matching circuit includes a first electronic variable capacitor, and the first electronic variable capacitor includes a plurality of first capacitor elements and a plurality of first switching elements electrically connected to the plurality of first capacitor elements, respectively.

[0103] The above embodiments are described for the purpose of explanation and are not intended to limit the scope of the present disclosure. Various modifications can be made to the above embodiments without departing from the scope and spirit of the present disclosure. For example, some components in one embodiment can be added to other embodiments. Also, some components in one embodiment can be replaced with corresponding components in other embodiments.

[0104] 1: Plasma processing apparatus, 2: Control unit, 10: Plasma processing chamber, 30: Power supply, 31a: First RF generating unit, 32a: First DC generating unit, 50: Impedance matching device, 52: First matching circuit, 52A: First low-speed matching circuit, 52B: First high-speed matching circuit, 54: Second matching circuit, 54A: Second low-speed matching circuit, 54B: Second high-speed matching circuit, 60: Waveform generating unit, 62: RF filter, TL1: First transmission line, TL2: Second transmission line

Claims

1. A plasma processing apparatus comprising: a chamber; a substrate support disposed within the chamber and including a lower electrode; an upper electrode disposed above the substrate support; a source RF generator configured to supply a source RF signal to the upper electrode or the lower electrode to generate plasma in the chamber; an impedance matching circuit electrically connected to a transmission line between the source RF generator and the upper electrode or the lower electrode, the impedance matching circuit including a first slow matching circuit and a first fast matching circuit connected in parallel to each other; a bias generator configured to supply a bias signal to the lower electrode; and a control unit configured to perform a slow matching operation on the source RF signal by the first slow matching circuit during a first period, and to perform a fast matching operation on the source RF signal by the first fast matching circuit during a second period after the first period.

2. The plasma processing apparatus of claim 1, wherein the first low-speed matching circuit includes a first mechanical variable capacitor; and the first high-speed matching circuit includes a first electronic variable capacitor, the first electronic variable capacitor including a plurality of first capacitor elements and a plurality of first switching elements electrically connected to the plurality of first capacitor elements, respectively.

3. The plasma processing apparatus according to claim 2, wherein the maximum capacitance of the first mechanical variable capacitor is 10 times or more the maximum capacitance of the first electronic variable capacitor.

4. A plasma processing apparatus as described in claim 3, wherein the first low-speed matching circuit is configured to perform the low-speed matching operation at a frequency of approximately once every 10 ms to several hundred ms, and the first high-speed matching circuit is configured to perform the high-speed matching operation at a frequency of approximately once every several tens of ns to several μs.

5. The plasma processing apparatus according to claim 1, wherein the first period is a period from when plasma starts to be generated in the chamber until the slow matching operation becomes stable.

6. The plasma processing apparatus of claim 1, wherein the first low-speed matching circuit and the first high-speed matching circuit are disposed between the transmission line and a ground potential.

7. The plasma processing apparatus according to claim 6, wherein the impedance matching circuit includes a second low-speed matching circuit and a second high-speed matching circuit connected in parallel with each other, and the second low-speed matching circuit and the second high-speed matching circuit are disposed on the transmission line.

8. The plasma processing apparatus of claim 7, wherein the first low-speed matching circuit includes a first mechanical variable capacitor; the first high-speed matching circuit includes a first electronic variable capacitor, the first electronic variable capacitor including a plurality of first capacitor elements and a plurality of first switching elements electrically connected to the plurality of first capacitor elements, respectively; the second low-speed matching circuit includes a second mechanical variable capacitor; the second high-speed matching circuit includes a second electronic variable capacitor, the second electronic variable capacitor including a plurality of second capacitor elements and a plurality of second switching elements electrically connected to the plurality of second capacitor elements, respectively.

9. The plasma processing apparatus according to claim 6, wherein the source RF generator is configured so that the set value of the frequency of the source RF signal can be changed.

10. The plasma processing apparatus of claim 1, wherein the bias generator comprises a bias RF generator configured to generate a bias RF signal.

11. The plasma processing apparatus of any one of claims 1 to 9, wherein the bias generator includes a bias DC generating section configured to generate a bias DC signal, the bias DC signal having a sequence of voltage pulses.

12. A plasma processing apparatus comprising: a chamber; a substrate support disposed within the chamber and including a lower electrode; an antenna disposed above the chamber; a source RF generator configured to supply a source RF signal to the antenna to generate plasma in the chamber; an impedance matching circuit electrically connected to a transmission line between the source RF generator and the antenna, the impedance matching circuit including a first slow matching circuit and a first fast matching circuit connected in parallel to each other; a bias generator configured to supply a bias signal to the lower electrode; and a control unit configured to perform a slow matching operation on the source RF signal by the first slow matching circuit during a first period, and to perform a fast matching operation on the source RF signal by the first fast matching circuit during a second period after the first period.

13. The plasma processing apparatus of claim 12, wherein the first low-speed matching circuit includes a first mechanical variable capacitor; and the first high-speed matching circuit includes a first electronic variable capacitor, the first electronic variable capacitor including a plurality of first capacitor elements and a plurality of first switching elements electrically connected to the plurality of first capacitor elements, respectively.

14. The plasma processing apparatus of claim 12, wherein the first low speed matching circuit and the first high speed matching circuit are disposed between the transmission line and a ground potential.

15. The plasma processing apparatus of claim 14, wherein the impedance matching circuit includes a second low-speed matching circuit and a second high-speed matching circuit connected in parallel to each other, and the second low-speed matching circuit and the second high-speed matching circuit are disposed on the transmission line.

16. The plasma processing apparatus of claim 15, wherein the first low-speed matching circuit includes a first mechanical variable capacitor; the first high-speed matching circuit includes a first electronic variable capacitor, the first electronic variable capacitor including a plurality of first capacitor elements and a plurality of first switching elements electrically connected to the plurality of first capacitor elements, respectively; the second low-speed matching circuit includes a second mechanical variable capacitor; and the second high-speed matching circuit includes a second electronic variable capacitor, the second electronic variable capacitor including a plurality of second capacitor elements and a plurality of second switching elements electrically connected to the plurality of second capacitor elements, respectively.

17. The plasma processing apparatus of claim 14, wherein the source RF generator is configured to be able to change the frequency of the source RF signal.

18. An impedance matching method comprising: supplying an RF signal from an RF generator to a load; performing a slow matching operation on the RF signal by a first slow matching circuit during a first period; and performing a fast matching operation on the RF signal by a first fast matching circuit connected in parallel to the first slow matching circuit during a second period after the first period.

19. The impedance matching method of claim 18, wherein the first low-speed matching circuit includes a first mechanically variable capacitor; and the first high-speed matching circuit includes a first electronically variable capacitor, the first electronically variable capacitor including a plurality of first capacitor elements and a plurality of first switching elements electrically connected to the plurality of first capacitor elements, respectively.

Images