Signal processing device and distance measuring sensor

Abstract

The present technology relates to a signal processing device and a distance measuring sensor that enable a more suitable improvement in distance measurement accuracy. The signal processing device according to the present technology is provided with a plurality of latch units that: hold data based on a light detection signal output from a light detecting unit that detects reflected light resulting from laser light being reflected by an object; output data in accordance with the light detection signal during an exposure period of the light detecting unit; and output data in accordance with a dummy pulse during periods other than the exposure period. The present technology can be applied, for example, to distance measuring sensors that employ a ToF method to measure the distance to an object being measured.

Description

Signal processing device and distance measuring sensor

[0001] The present technology relates to a signal processing device and a distance measuring sensor, and more particularly to a signal processing device and a distance measuring sensor that can more suitably improve distance measurement accuracy.

[0002] A distance sensor that measures the distance to an object using the ToF (Time-of-Flight) method is equipped with, for example, a two-phase TDC (Time-to-Digital Converter) that has two latches that hold data based on a light detection signal. Each time a light detection signal is input, the two-phase TDC operates in an interleaved manner by switching between one latch that holds data based on the light detection signal and another that outputs the held data to a counter.

[0003] By simultaneously holding data and outputting it to the counter, the time until the next photodetection signal can be input is shortened, so the two-phase TDC can reduce the number of photodetection signals missed.

[0004] The data held in the latch is not output to the counter until the next photodetection signal is input to the two-phase TDC. Since the data based on the last photodetection signal input to the two-phase TDC during the exposure period remains held in the latch and is not output to the counter, the number of counted data is one less than the number of photodetection signals input to the two-phase TDC.

[0005] When the background light is strong, even if the data based on the photodetection signal obtained from reflected light remains held in the latch, the photodetection signal obtained from the background light is input to the two-phase TDC, and therefore the data based on the photodetection signal obtained from reflected light is output to the counter. On the other hand, when the background light is weak, the photodetection signal obtained from the background light is not input to the two-phase TDC, and therefore the data based on the last photodetection signal obtained from reflected light during the exposure period remains held in the latch and is not output to the counter.

[0006] Since the number of light detection signals obtained from reflected light reflected by a distant object to be measured is small, even a decrease in the number of counted data points reduces the distance measurement accuracy and narrows the distance measurement range of the distance measurement sensor.

[0007] JP 2019-078690 A

[0008] Patent Document 1 describes a two-phase TDC that switches between holding data and outputting data to a counter using an external signal. In the two-phase TDC described in Patent Document 1, only one photodetection signal can be input to the two-phase TDC in one valid period, so if multiple photodetection signals are obtained in one valid period, some of the photodetection signals will be missed.

[0009] Furthermore, in the two-phase TDC described in Patent Document 1, switching between holding data and outputting data to the counter occurs even when no light detection signal is input, which may result in increased power consumption due to unnecessary switching.

[0010] The present technology has been made in view of such circumstances, and is intended to make it possible to more suitably improve distance measurement accuracy.

[0011] A signal processing device according to a first aspect of the present technology includes a plurality of latch units that hold data based on a photodetection signal output from a photodetection unit that detects reflected light of laser light reflected by an object, and that output the data in response to the photodetection signal during an exposure period of the photodetection unit, and output the data in response to a dummy pulse during a period other than the exposure period.

[0012] A ranging sensor according to a second aspect of the present technology includes a light detection unit that detects reflected light of laser light reflected by an object, a plurality of latch units that hold data based on a light detection signal output from the light detection unit, output the data in response to the light detection signal during an exposure period of the light detection unit, and output the data in response to a dummy pulse during periods other than the exposure period, and a counter that generates a histogram of the data output from the latch units.

[0013] In a first aspect of the present technology, data based on a photodetection signal output from a photodetector that detects reflected light of laser light reflected by an object is held, and during an exposure period of the photodetector, the data is output in response to the photodetection signal, and during periods other than the exposure period, the data is output in response to a dummy pulse.

[0014] In a second aspect of the present technology, a light detection unit detects reflected light of laser light reflected by an object, a plurality of latch units hold data based on a light detection signal output from the light detection unit, the data is output in response to the light detection signal during an exposure period, and the data is output in response to a dummy pulse during a period other than the exposure period, and a counter generates a histogram of the data output from the latch units.

[0015] 1 is a block diagram showing an example configuration of a distance measuring sensor according to an embodiment of the present technology. FIG. 2 is a circuit diagram showing an example configuration of a conventional TDC. FIG. 3 is a timing chart when a conventional TDC operates. FIG. 4 is a diagram for explaining the relationship between the amount of reflected light and the count number of a TDC code. FIG. 5 is a timing chart when a TDC according to the present technology operates. FIG. 6 is a circuit diagram showing an example configuration of a TDC according to a first embodiment. FIG. 7 is a timing chart when a TDC according to the first embodiment operates. FIG. 8 is a circuit diagram showing an example configuration of a TDC according to a second embodiment. FIG. 9 is a circuit diagram showing an example configuration of a TDC input signal generating unit. FIG. 10 is a circuit diagram showing an example configuration of a TDC input signal generating unit according to a third embodiment. FIG. 11 is a timing chart when a TDC according to the third embodiment operates. FIG. 12 is a circuit diagram showing an example configuration of a TDC input signal generating unit according to a fourth embodiment. FIG. 13 is a timing chart when a TDC according to the fourth embodiment operates. FIG. 14 is a circuit diagram showing an example configuration of a TDC according to a fifth embodiment. FIG. 15 is a circuit diagram showing an example configuration of a TDC input signal generating unit. FIG. 16 is a timing chart when a TDC according to the fifth embodiment operates. FIG. 17 is a circuit diagram showing an example configuration of a TDC according to a sixth embodiment. 13 is a circuit diagram showing a configuration example of a TDC input signal generating unit according to a sixth embodiment. 14 is a timing chart showing the operation of a TDC according to the sixth embodiment.

[0016] Hereinafter, embodiments of the present technology will be described in the following order: 1. Overview of distance measurement sensor 2. First embodiment 3. Second embodiment 4. Third embodiment 5. Fourth embodiment 6. Fifth embodiment 7. Sixth embodiment

[0017] 1. Overview of Distance Measuring Sensor FIG. 1 is a block diagram showing an example of the configuration of a distance measuring sensor 1 according to an embodiment of the present technology.

[0018] 1 is a sensor that measures the distance to an object using, for example, a ToF system. The distance measurement sensor 1 measures the distance to the object by, for example, irradiating a pulsed laser beam toward the object and measuring the time it takes for the laser beam to be reflected by the object and return, thereby receiving a pulse of reflected light. The laser beam may be emitted by the distance measurement sensor 1 itself or by a device external to the distance measurement sensor 1.

[0019] As shown in FIG. 1, the distance measuring sensor 1 is made up of a light detection unit 11, a TDC 12, a CNT 13, and a control unit .

[0020] The photodetector 11 includes, for example, a single photon avalanche diode (SPAD) as a photoelectric conversion element. The SPAD instantaneously detects a single photon by amplifying carriers generated by photoelectric conversion in a high-electric field PN junction region. When the photodetector 11 detects the incidence of a photon, it outputs a photodetection signal indicating that a photon has been detected to the TDC 12.

[0021] The TDC 12 is a TDC that includes multiple latches that hold data based on the light detection signal. The TDC 12 converts the time from when the laser light is emitted until the reflected light is detected by the light detection unit 11 into a digital value (data). Hereinafter, the digital value that indicates the time until the reflected light is detected by the light detection unit 11 will be referred to as the TDC code.

[0022] The TDC 12 receives a clock signal from the control unit 14, and counts up the TDC code in sequence based on the clock signal, starting from 0. The TDC 12 starts counting up the TDC code in synchronization with the start of a processing cycle, and outputs the TDC code to the CNT 13 at the timing of the pulse indicated by the photodetection signal supplied from the photodetector unit 11.

[0023] The CNT (counter) 13 functions as a histogram generating unit that generates a histogram of the TDC code and outputs the generated histogram to the control unit 14.

[0024] The control unit 14 controls the entire distance measuring sensor 1. For example, the control unit 14 controls the output timing of the TDC code from the TDC 12, and calculates the distance to the object to be measured based on the histogram input from the CNT 13.

[0025] FIG. 2 is a circuit diagram showing an example of the configuration of a conventional TDC 12.

[0026] As shown in FIG. 2, the conventional TDC 12 is composed of a first latch 21-1, a second latch 21-2, FFs (flip-flops) 22 and 23, inverters 24 and 26, NAND circuits 25-1 and 25-2, switches 27-1 and 27-2, a delay circuit 28, and an AND circuit 29.

[0027] When a light detection signal (pulse) is input to the TDC 12, a TDC input signal TDC_IN having the same waveform as the light detection signal is input to FFs 22 and 23, NAND circuits 25-1 and 25-2, and a delay circuit .

[0028] The first latch 21-1 and the second latch 21-2 start counting up the TDC code in synchronization with the start of the processing cycle and hold the TDC code at the timing of the pulses indicated by the latch input signals XLTIN_1 and XLTIN_2 input from the NAND circuits 25-1 and 25-2. The first latch 21-1 and the second latch 21-2 output a TDC output signal TDC_OUT indicating the TDC code to the AND circuit 29. The TDC code held by the first latch 21-1 and the second latch also includes the state of the enable signal EN. Based on the state of the enable signal EN, it is determined whether the TDC code is data input to the TDC 12 during the exposure period.

[0029] The FF 22, the inverter 24, and the NAND circuits 25-1 and 25-2 function as a selection unit that switches whether the TDC input signal TDC_IN (latch input signal) is input to the first latch 21-1 or the second latch 21-2, depending on the TDC input signal TDC_IN. Specifically, the FF 22, the inverter 24, and the NAND circuits 25-1 and 25-2 alternately switch the latch to which the TDC input signal TDC_IN is input, between the first latch 21-1 and the second latch 21-2, every time a light detection signal is input to the TDC.

[0030] The FF22 outputs an input switch control signal IN_SW, which is a signal for switching the latch that holds the TDC code, to the inverter 24 and the NAND circuit 25-1, and the inverter 24 inverts the input switch control signal IN_SW input from the FF22 and outputs it to the NAND circuit 25-2. In other words, the FF22 (and the inverter 24) outputs a High signal to one of the NAND circuits 25-1 and 25-2, and a Low signal to the other.

[0031] When a Low signal is input from FF22, the NAND circuit 25-1 outputs a latch input signal XLTIN_1 having the same waveform as the TDC input signal TDC_IN to the first latch 21-1, and when a Low signal is input from FF22 (inverter 24), the NAND circuit 25-2 outputs a latch input signal XLTIN_2 having the same waveform as the TDC input signal TDC_IN to the second latch 21-2.

[0032] The FF23, the inverter 26, and the switches 27-1 and 27-2 function as a selection unit that selects whether the TDC output signal TDC_OUT is to be output from the first latch 21-1 or the second latch 21-2, depending on the TDC input signal TDC_IN. Specifically, the FF23, the inverter 26, and the switches 27-1 and 27-2 select a latch other than the latch to which the TDC input signal TDC_IN is input, as the latch that will output the TDC output signal TDC_OUT.

[0033] The FF23 outputs an output switch control signal OUT_SW, which is a signal for selecting a latch that outputs a TDC code, to the inverter 26 and the switch 27-1, and the inverter 26 inverts the output switch control signal OUT_SW input from the FF23 and outputs it to the switch 27-2. In other words, the FF23 (and the inverter 26) turns on one of the switches 27-1 and 27-2 and turns off the other.

[0034] When the switch 27-1 is turned on, the first latch 21-1 outputs the TDC output signal TDC_OUT, and when the switch 27-2 is turned on, the second latch 21-2 outputs the TDC output signal TDC_OUT.

[0035] The delay circuit 28 generates a delayed signal OUT_EN by delaying the TDC input signal TDC_IN, and outputs the delayed signal OUT_EN to the AND circuit 29 .

[0036] The AND circuit 29 outputs a CNT input signal OUTPLS indicating the TDC code to the CNT 13 in response to the pulse indicated by the delayed signal OUT_EN.

[0037] An enable signal EN indicating the exposure period of the SPAD is input to the TDC 12, and only the light detection signals input during the exposure period are used to generate the histogram. Specifically, the state of the enable signal EN is also included (latched) in the TDC code, so only TDC code (valid data) for which the enable signal EN is latched to a high state is output to the CNT 13 as the CNT input signal OUTPLS.

[0038] The CNT 13 adds 1 to the frequency of the TDC code indicated by the CNT input signal OUTPLS. The CNT 13 outputs the histogram to the memory of the control unit 16 in response to a read signal CNT_READ input from the control unit 16, for example.

[0039] FIG. 3 is a timing chart showing the operation of the conventional TDC 12.

[0040] 3, after the photodetection signal (TDC input signal TDC_IN) rises at timing t1, output from the first latch 21-1 starts at timing t2. In response to the photodetection signal, the latch that holds the TDC code is switched to the second latch 21-2, and the TDC code based on the photodetection signal that rose at timing t1 is held in the second latch 21-2.

[0041] The rising edge of the photodetection signal at timing t1 is delayed by the delay circuit 28, and the delayed signal OUT_EN rises at timing t3, after which the CNT input signal OUTPLS rises at timing t4, which is delayed by the circuit delay of the AND circuit 29. At timing t4, the CNT 13 adds 1 to the frequency of the TDC code held in the first latch 21-1.

[0042] After the photodetection signal rises at timing t5, output from the second latch 21-2 starts at timing t6. In response to the photodetection signal, the latch that holds the TDC code is switched to the first latch 21-1, and the TDC code based on the photodetection signal that rose at timing t5 is held in the first latch 21-1.

[0043] The rising edge of the photodetection signal at timing t5 is delayed by the delay circuit 28, and the delayed signal OUT_EN rises at timing t7, after which the CNT input signal OUTPLS rises at timing t8, which is delayed by the circuit delay of the AND circuit 29. At timing t8, the CNT 13 adds 1 to the frequency of the TDC code that was held in the second latch 21-2 after timing t1.

[0044] When the exposure period ends, the enable signal EN falls at timing t9. After the exposure period ends, the read signal CNT_READ rises at timing t10, and the histogram is read out.

[0045] Here, the TDC code held in the first latch 21-1 after timing t5 is not output to the CNT 13 until the next photodetection signal is input to the TDC 12. In this way, the TDC code based on the photodetection signal last input to the TDC 12 during the exposure period remains held in the first latch 21-1 and is not output to the CNT 13. Therefore, the number of TDC codes counted is one less than the number of photodetection signals (pulses) input to the TDC 12.

[0046] When the background light is strong, even if the TDC code based on the photodetection signal obtained from the reflected light remains held in the first latch 21-1, the photodetection signal obtained from the background light is input to the TDC 12, and the TDC code based on the photodetection signal obtained from the reflected light is output to the CNT 13. On the other hand, when the background light is weak, the photodetection signal obtained from the background light is not input to the TDC 12, and the TDC code based on the last photodetection signal obtained from the reflected light during the exposure period remains held in the first latch 21-1 and is not output to the CNT 13.

[0047] 4 is a diagram for explaining the relationship between the amount of reflected light and the number of counts of the TDC code, in which the horizontal axis represents the amount of reflected light and the vertical axis represents the number of counts of the TDC code.

[0048] Generally, the amount of light reflected from a distant object is small, while the amount of light reflected from a close object is large. The smaller the amount of reflected light, the fewer the number of photodetection signals (pulses) obtained from the reflected light, and the fewer the TDC code counts.

[0049] It is desirable that the count number of the TDC code be the same as the number of photodetection signals obtained from reflected light (ideal count number), as shown in Fig. 4. In reality, the TDC code based on the last photodetection signal during the exposure period remains held in the latch, so the count number of the TDC code is one less than the ideal count number, as indicated by arrow A1.

[0050] As shown by arrow A2 in Figure 4, the number of light detection signals obtained from the light reflected from the object at a long distance is small, so the ratio of the decrease in the count number to the ideal count number is large. Therefore, the longer the distance to the object at a long distance, the lower the accuracy of the distance measurement, and as a result, the narrower the distance measurement range of the distance measurement sensor.

[0051] This technology was conceived with the above points in mind, and the first latch 21-1 and the second latch 21-2 hold a TDC code based on the photodetection signal output from the photodetection unit 11, output the data in response to the photodetection signal during the exposure period of the photodetection unit 11, and output the data in response to a dummy pulse during periods other than the exposure period, thereby reducing the loss of photodetection signals and more appropriately improving ranging accuracy.

[0052] 5 is a timing chart showing the operation of the TDC 12 according to the present technology. In FIG. 5, the operation of the TDC 12 at timings t1 to t9 is the same as the operation described with reference to FIG. 3, and therefore a description thereof will be omitted.

[0053] In the TDC 12 of the present technology, a dummy pulse DMYPLS is input so that the TDC code held in the first latch 21-1 is output (the CNT input signal OUTPLS rises) between timing t9 when the exposure period ends and timing t10 ​​when the histogram is read out.

[0054] After the enable signal EN falls at timing t9, the dummy pulse DMYPLS rises at timing t21. After the dummy pulse DMYPLS rises, output from the first latch 21-1 side starts at timing t22.

[0055] The rising edge of the dummy pulse DMYPLS at timing t21 is delayed by the delay circuit 28, causing the delay signal OUT_EN to rise at timing t23. Thereafter, at timing t24, delayed by the circuit delay of the AND circuit 29, the CNT input signal OUTPLS rises. At timing t24, the CNT 13 increments the frequency of the TDC code held in the first latch 21-1 after timing t5 by one. The TDC code based on the dummy pulse DMYPLS that rose at timing t21 has the enable signal EN latched low. Even if a photodetection signal is input to the TDC 12 between the input of the dummy pulse DMYPLS and the counter readout, the TDC code based on the dummy pulse DMYPLS has the enable signal EN latched low. Therefore, the CNT input signal OUTPLS indicating the TDC code is not output to the CNT 13, i.e., is not added to the histogram.

[0056] At timing t10, the read signal CNT_READ rises and the histogram is read out.

[0057] The TDC 12 is reset during the period from the end of the histogram readout (the falling edge of the readout signal CNT_READ) to the start of the next exposure period (the rising edge of the enable signal EN).

[0058] As described above, the TDC 12 of the present technology switches between the latch that holds the TDC code and the latch that outputs the TDC code based on the photodetection signal during the exposure period. Furthermore, the TDC 12 of the present technology switches between the latch that holds the TDC code and the latch that outputs the TDC code based on the dummy pulse during the period from the end of the exposure period to the start of histogram readout. This allows the TDC code that remains held in the latch after the exposure period to be output to the CNT 13, thereby reducing the number of photodetection signal drops.

[0059] Regardless of the intensity of background light, the TDC code that has been held in the latch after the exposure period is output to the CNT 13, so the count number of the TDC code becomes the ideal count number. Therefore, it is possible to prevent a decrease in the count number of the TDC code from causing a decrease in the distance measurement accuracy or a narrowing of the distance measurement range.

[0060] Furthermore, the latch that holds the TDC code and the latch that outputs the TDC code are switched only when the photodetection signal is input to the TDC 12, so unnecessary switching is not performed, and power consumption can be reduced.

[0061] 2. First Embodiment Fig. 6 is a circuit diagram showing an example of the configuration of the TDC 12 according to the first embodiment. In Fig. 6, the same components as those in Fig. 3 are denoted by the same reference numerals. Duplicate explanations will be omitted as appropriate.

[0062] The TDC 12 in FIG. 6 differs from the TDC 12 in FIG. 3 in that a TDC input signal TDC_IN is input from an OR circuit 51 .

[0063] The OR circuit 51 receives an optical detection signal from the optical detection unit 11 and, for example, a dummy pulse DMYPLS from the control unit 14. The OR circuit 51 outputs a TDC input signal TDC_IN having the same waveform as the optical detection signal or the dummy pulse DMYPLS to the first latch 21-1 or the second latch 21-2 (NAND circuits 25-1, 25-2), the FFs 22, 23, and the delay circuit 28.

[0064] 6, a TDC input signal TDC_IN having a waveform similar to that of a light detection signal is input to the first latch 21-1. Next, a TDC input signal TDC_IN having a waveform similar to that of a dummy pulse is input to the second latch 21-2, as indicated by the gray arrow. When the TDC input signal TDC_IN having a waveform similar to that of a dummy pulse is input to the FF 23, the switch 27-1 is turned on, and a TDC output signal TDC_OUT indicating a TDC code based on the light detection signal (TDC input signal TDC_IN) is output from the first latch 21-1.

[0065] Although the example in which the OR circuit 51 is provided outside the TDC 12 has been described with reference to FIG. 6, the OR circuit 51 may be provided inside the TDC 12 .

[0066] FIG. 7 is a timing chart showing the operation of the TDC 12 according to the first embodiment.

[0067] 7 , after the photodetection signal rises at timing t51, the TDC input signal TDC_IN rises at timing t52, which is delayed by the circuit delay of the OR circuit 51. After the TDC input signal TDC_IN rises, output from the first latch 21-1 begins at timing t53. In response to the photodetection signal, the latch that holds the TDC code is switched to the second latch 21-2, and the TDC code based on the photodetection signal that rose at timing t51 is held in the second latch 21-2.

[0068] The rising edge of the TDC input signal TDC_IN at timing t52 is delayed by the delay circuit 28, and the delayed signal OUT_EN rises at timing t54. Thereafter, the CNT input signal OUTPLS rises at timing t55, which is delayed by the circuit delay of the AND circuit 29. At timing t55, the CNT 13 adds 1 to the frequency of the TDC code held in the first latch 21-1.

[0069] After the photodetection signal rises at timing t56, the TDC input signal TDC_IN rises at timing t57, which is delayed by the circuit delay of the OR circuit 51. After the TDC input signal TDC_IN rises, output from the second latch 21-2 begins at timing t58. In response to the photodetection signal, the latch that holds the TDC code is switched to the first latch 21-1, and the TDC code based on the photodetection signal that rose at timing t56 is held in the first latch 21-1.

[0070] The rising edge of the TDC input signal TDC_IN at timing t57 is delayed by the delay circuit 28, and the delayed signal OUT_EN rises at timing t59. Thereafter, the CNT input signal OUTPLS rises at timing t60, which is delayed by the circuit delay of the AND circuit 29. At timing t60, the CNT 13 adds 1 to the frequency of the TDC code that was held in the first latch 21-1 after timing t51.

[0071] When the exposure period ends, the enable signal EN falls at timing t61, and the dummy pulse DMYPLS rises at timing t62. After the dummy pulse DMYPLS rises, the TDC input signal TDC_IN rises at timing t63, which is delayed by the circuit delay of the OR circuit 51.

[0072] After the TDC input signal TDC_IN rises, at timing t64, output from the first latch 21-1 side starts.

[0073] The rising edge of the TDC input signal TDC_IN at timing t63 is delayed by the delay circuit 28, and the delayed signal OUT_EN rises at timing t65. Thereafter, the CNT input signal OUTPLS rises at timing t66, delayed by the circuit delay of the AND circuit 29. At timing t66, the CNT 13 increments by 1 the frequency of the TDC code that was held in the first latch 21-1 after timing t56.

[0074] At timing t67, the read signal CNT_READ rises and the histogram is read out.

[0075] As described above, it is possible to switch between a latch that holds a TDC code and a latch that outputs a TDC code in response to a dummy pulse input from outside the TDC 12 (for example, from the control unit 14).

[0076] 3. Second Embodiment Fig. 8 is a circuit diagram showing an example of the configuration of the TDC 12 according to the second embodiment. In Fig. 8, the same components as those in Fig. 3 are denoted by the same reference numerals. Duplicate explanations will be omitted as appropriate.

[0077] The TDC 12 in FIG. 8 differs from the TDC 12 in FIG. 3 in that a TDC input signal generator 81 is provided.

[0078] The TDC input signal generation unit 81 receives the photodetection signal from the photodetection unit 11 and also receives the enable signal EN from, for example, the control unit 14. The TDC input signal generation unit 81 generates a dummy pulse DMYPLS based on the enable signal EN and outputs a TDC input signal TDC_IN having the same waveform as the photodetection signal or the dummy pulse DMYPLS to the first latch 21-1 or the second latch 21-2 (NAND circuits 25-1, 25-2), the FFs 22, 23, and the delay circuit 28.

[0079] FIG. 9 is a circuit diagram showing an example of the configuration of the TDC input signal generating unit 81. As shown in FIG.

[0080] As shown in FIG. 9, the TDC input signal generating unit 81 is composed of a dummy pulse generating circuit 91 and an OR circuit 92 .

[0081] The dummy pulse generating circuit 91 generates a dummy pulse DMYPLS using a level transition (falling edge) of the enable signal EN as a trigger, and outputs the dummy pulse DMYPLS to the OR circuit 92 .

[0082] The light detection signal and the dummy pulse DMYPLS are input to the OR circuit 92, and the OR circuit 92 outputs a TDC input signal TDC_IN having the same waveform as the light detection signal or the dummy pulse DMYPLS.

[0083] The flow of operation of the TDC 12 according to the second embodiment is substantially the same as the flow of operation of the TDC 12 according to the second embodiment explained with reference to the timing chart of FIG. 7, and therefore will not be explained again.

[0084] As described above, it is possible to generate a dummy pulse inside the TDC 12.

[0085] 4. Third Embodiment Fig. 10 is a circuit diagram showing an example of the configuration of a TDC input signal generator 81 according to a third embodiment. In Fig. 10, the same components as those in Fig. 9 are denoted by the same reference numerals. Duplicate explanations will be omitted where appropriate.

[0086] The TDC input signal generating section 81 in FIG. 10 differs from the TDC input signal generating section 81 in FIG. 9 in that an inverter 111, delay circuits 112 and 114, and a NOR circuit 113 are provided in a dummy pulse generating circuit 91.

[0087] The inverter 111 inverts the input enable signal and outputs the inverted signal to the delay circuit 112 .

[0088] The delay circuit 112 generates a delayed signal XEN_delay by delaying the inverted signal of the enable signal, and outputs the delayed signal XEN_delay to the NOR circuit 113 .

[0089] The enable signal EN and the delay signal XEN_delay are input to the NOR circuit 113. When the enable signal EN and the delay signal XEN_delay are both Low signals, the NOR circuit 113 generates a dummy pulse DMYPLS and outputs it to the OR circuit 92.

[0090] FIG. 11 is a timing chart showing the operation of the TDC 12 according to the third embodiment.

[0091] 11 , after the photodetection signal rises at timing t81, the TDC input signal TDC_IN rises at timing t82, which is delayed by the circuit delay of the OR circuit 92. After the TDC input signal TDC_IN rises, output from the first latch 21-1 begins at timing t83. In response to the photodetection signal, the latch that holds the TDC code is switched to the second latch 21-2, and the TDC code based on the photodetection signal that rose at timing t81 is held in the second latch 21-2.

[0092] The rising edge of the TDC input signal TDC_IN at timing t82 is delayed by the delay circuit 28, and the delayed signal OUT_EN rises at timing t84. Thereafter, the CNT input signal OUTPLS rises at timing t85, which is delayed by the circuit delay of the AND circuit 29. At timing t85, the CNT 13 adds 1 to the frequency of the TDC code held in the first latch 21-1.

[0093] After the photodetection signal rises at timing t86, the TDC input signal TDC_IN rises at timing t87, which is delayed by the circuit delay of the OR circuit 92. After the TDC input signal TDC_IN rises, output from the second latch 21-2 begins at timing t88. In response to the photodetection signal, the latch that holds the TDC code is switched to the first latch 21-1, and the TDC code based on the photodetection signal that rose at timing t86 is held in the first latch 21-1.

[0094] The rising edge of the TDC input signal TDC_IN at timing t87 is delayed by the delay circuit 28, and the delayed signal OUT_EN rises at timing t89. Thereafter, the CNT input signal OUTPLS rises at timing t90, which is delayed by the circuit delay of the AND circuit 29. At timing t90, the CNT 13 adds 1 to the frequency of the TDC code that was held in the first latch 21-1 after timing t81.

[0095] When the exposure period ends, the enable signal EN falls at timing t91. At timing t91, the delay signal XEN_delay is a low signal, so the dummy pulse DMYPLS rises at timing t92, which is delayed by the circuit delay of the NOR circuit 113. After the dummy pulse DMYPLS rises, the TDC input signal TDC_IN rises at timing t93, which is delayed by the circuit delay of the OR circuit 92.

[0096] After the TDC input signal TDC_IN rises, at timing t94, output from the first latch 21-1 side starts.

[0097] The rising edge of the TDC input signal TDC_IN at timing t93 is delayed by the delay circuit 28, and the delayed signal OUT_EN rises at timing t95. Thereafter, the CNT input signal OUTPLS rises at timing t97, which is delayed by the circuit delay of the AND circuit 29. At timing t97, the CNT 13 adds 1 to the frequency of the TDC code that was held in the first latch 21-1 after timing t86.

[0098] The falling edge of the enable signal EN at timing t91 (the rising edge of the inverted signal of the enable signal EN) is delayed by the delay circuit 112, and the delayed signal XEN_delay rises at timing t96. After the delayed signal XEN_delay rises, the dummy pulse DMYPLS falls at timing t98, which is delayed by the circuit delay of the NOR circuit 113.

[0099] At timing t99, the read signal CNT_READ rises and the histogram is read out.

[0100] As described above, it is possible to generate a dummy pulse based on the enable signal EN and the delayed signal XEN_delay obtained by delaying the enable signal EN (its inverted signal).

[0101] 5. Fourth Embodiment Fig. 12 is a circuit diagram showing an example of the configuration of a TDC input signal generator 81 according to a fourth embodiment. In Fig. 12, the same components as those in Fig. 10 are denoted by the same reference numerals. Duplicate explanations will be omitted as appropriate.

[0102] The TDC input signal generating section 81 in FIG. 12 differs from the TDC input signal generating section 81 in FIG. 10 in that a delay circuit 131 is provided between the NOR circuit 113 and the OR circuit 92 in the dummy pulse generating circuit 91 .

[0103] When the enable signal EN and the delay signal XEN_delay are both low signals, the NOR circuit 113 generates a pulse signal ENPLS and outputs it to the delay circuit 131 .

[0104] The delay circuit 131 delays the pulse signal ENPLS input from the NOR circuit 113 to generate a dummy pulse DMYPLS, and outputs the dummy pulse DMYPLS to the OR circuit 92. The delay circuit 131 functions as a delay unit that delays the dummy pulse DMYPLS.

[0105] 13 is a timing chart showing the operation of the TDC 12 according to the fourth embodiment. Note that the timings of the read signal CNT_READ, the TDC output signal TDC_OUT, the delay signal OUT_EN, and the CNT input signal OUTPLS are not shown in FIG.

[0106] 13 , after the photodetection signal rises at timing t111, the TDC input signal TDC_IN rises at timing t112, which is delayed by the circuit delay of the OR circuit 92. After the photodetection signal falls at timing t113, the TDC input signal TDC_IN falls at timing t114, which is delayed by the circuit delay of the OR circuit 92.

[0107] After the TDC input signal TDC_IN falls at timing t114, the input switch control signal IN_SW falls at timing t115, which is delayed by the circuit delay of the FF 22. After the input switch control signal IN_SW falls, the latch input signal XLTIN_1 is input to the first latch 21-1.

[0108] After the photodetection signal rises at timing t116, the TDC input signal TDC_IN rises at timing t117, which is delayed by the circuit delay of the OR circuit 92. After the photodetection signal falls at timing t118, the TDC input signal TDC_IN falls at timing t119, which is delayed by the circuit delay of the OR circuit 92.

[0109] When the exposure period ends, the enable signal EN falls at timing t120. Since the delay signal XEN_delay is a low signal at timing t120, the pulse signal ENPLS rises at timing t121, which is delayed by the circuit delay of the NOR circuit 113.

[0110] After the TDC input signal TDC_IN falls at timing t119, the input switch control signal IN_SW rises at timing t122, which is delayed by the circuit delay of the FF 22. After the input switch control signal IN_SW rises, the latch input signal XLTIN_2 is input to the second latch 21-2. In other words, the latch that holds the TDC code is switched to the second latch 21-2 in response to the photodetection signal.

[0111] The delay circuit 131 delays the rising edge of the pulse signal ENPLS at timing t121, so that the dummy pulse DMYPLS rises at timing t123 after timing t122 ​​when the input switch control signal IN_SW rises.

[0112] In order to prevent the TDC code held in the first latch 21-1 from being rewritten by the dummy pulse DMYPLS, it is preferable that the dummy pulse DMYPLS rises after the exposure period ends (after timing t120) and after the level of the input switch control signal IN_SW transitions in response to the last photodetection signal in the exposure period (the photodetection signal that rose at timing t116) (after timing t122).

[0113] The delay time in the delay circuit 131 is adjusted so that the rising edge of the dummy pulse DMYPLS occurs after the transition of the input switch control signal IN_SW.

[0114] After the dummy pulse DMYPLS rises at timing t123, the TDC input signal TDC_IN rises at timing t124, which is delayed by the circuit delay of the OR circuit 92.

[0115] The falling edge of the enable signal EN at timing t120 (the rising edge of the inverted signal of the enable signal EN) is delayed by the delay circuit 112, and the delayed signal XEN_delay rises at timing t125. After the delayed signal XEN_delay rises, the pulse signal ENPLS falls at timing t126, which is delayed by the circuit delay of the NOR circuit 113.

[0116] The falling edge of the pulse signal ENPLS at timing t126 is delayed by the delay circuit 131, and the dummy pulse DMYPLS falls at timing t127. Thereafter, at timing t128, which is delayed by the circuit delay of the OR circuit 92, the TDC input signal TDC_IN falls.

[0117] After the TDC input signal TDC_IN falls, the input switch control signal IN_SW falls at timing t129, which is delayed by the circuit delay of the FF 22. In other words, in response to the dummy pulse DMYPLS, the latch that holds the TDC code is switched to the first latch 21-1.

[0118] As described above, in order to prevent the TDC code held in the first latch 21-1 from being rewritten by the dummy pulse DMYPLS, it is possible to generate a dummy pulse after the exposure period ends and after the level of the input switch control signal IN_SW transitions in response to the last light detection signal in the exposure period.

[0119] 6. Fifth Embodiment Fig. 14 is a circuit diagram showing an example of the configuration of a TDC 12 according to a fifth embodiment. In Fig. 14, the same components as those in Fig. 3 are denoted by the same reference numerals. Duplicate explanations will be omitted as appropriate.

[0120] The TDC 12 in FIG. 14 differs from the TDC 12 in FIG. 3 in that a TDC input signal generator 151, an inverter 152, and a delay circuit 153 are provided.

[0121] The TDC input signal generator 151 receives an optical detection signal from the optical detector 11, and also receives an enable signal EN and an inverted signal XCNT_READ obtained by inverting the read signal CNT_READ from, for example, the controller .

[0122] The TDC input signal generation unit 151 generates a dummy pulse DMYPLS based on the light detection signal, the enable signal EN, and the inverted signal XCNT_READ. The TDC input signal generation unit 151 outputs a TDC input signal TDC_IN having a waveform similar to that of the light detection signal or the dummy pulse DMYPLS to the first latch 21-1 or the second latch 21-2 (NAND circuits 25-1, 25-2), the FFs 22, 23, and the delay circuit 28.

[0123] The inverter 152 inverts the input inverted signal XCNT_READ and outputs the inverted signal to the delay circuit 153 .

[0124] The delay circuit 153 delays the signal input from the inverter 152 to generate a read signal CNT_READ, and outputs it to the CNT 13 .

[0125] FIG. 15 is a circuit diagram showing an example of the configuration of the TDC input signal generating unit 151.

[0126] As shown in FIG. 15, the TDC input signal generating unit 151 is composed of a dummy pulse generating circuit 161 and an OR circuit 162 .

[0127] The dummy pulse generating circuit 91 includes a D flip-flop 181 , a delay circuit 182 , an inverter 183 , and AND circuits 184 and 185 .

[0128] A signal of a constant level (high signal) is input to the D terminal (first input terminal) of the D flip-flop 181, and a light detection signal is input to the clock input terminal (second input terminal). The output from the delay circuit 182 is input to the reset terminal of the D flip-flop 181.

[0129] The D flip-flop 181 stores the signal input to the D terminal at the rising edge of the photodetection signal, and outputs an inverted signal of the stored signal as a mask signal XMASK from the output terminal. This operation is repeated every time the D flip-flop 181 is reset by the output from the delay circuit 182. The mask signal XMASK is input to the delay circuit 182 and an AND circuit 185. The mask signal XMASK is a signal that restricts the dummy pulse DMYPLS from rising for a certain period of time after the photodetection signal is input to the TDC 12.

[0130] The delay circuit 182 delays the mask signal XMASK input from the D flip-flop 181 and outputs the delayed signal to the reset terminal of the D flip-flop 181 , thereby resetting the D flip-flop 181 .

[0131] The inverter 183 inverts the input enable signal EN and outputs it to the AND circuit 184 .

[0132] An inverted signal of the enable signal EN and an inverted signal XCNT_READ of the read signal CNT_READ are input to the AND circuit 184. When the inverted signal of the enable signal EN and the inverted signal XCNT_READ are both High signals, the AND circuit 184 outputs a High signal to the AND circuit 185.

[0133] When the mask signal XMASK from the D flip-flop 181 and the signal from the AND circuit 184 are both high signals, the AND circuit 185 outputs a dummy pulse DMYPLS to the OR circuit 162 .

[0134] The OR circuit 162 receives the light detection signal and the dummy pulse DMYPLS from the AND circuit 185, and outputs a TDC input signal TDC_IN having the same waveform as the light detection signal or the dummy pulse DMYPLS.

[0135] 16 is a timing chart showing the operation of the TDC 12 according to the fifth embodiment. Note that in FIG. 16, the timing of the delay signal OUT_EN and the CNT input signal OUTPLS is not described.

[0136] 16 , after the photodetection signal rises at timing t151, the TDC input signal TDC_IN rises at timing t152, which is delayed by the circuit delay of the OR circuit 162. In addition, after the photodetection signal rises at timing t151, the mask signal XMASK falls at timing t153, which is delayed by the circuit delay of the D flip-flop 181.

[0137] After the TDC input signal TDC_IN rises, the output switch control signal OUT_SW rises at timing t154, which is delayed by the circuit delay of FF23, and then, at timing t155, which is delayed by the circuit delay of switch 27-1, etc., output from the first latch 21-1 side begins.

[0138] After the photodetection signal falls at timing t156, the TDC input signal TDC_IN falls at timing t157, which is delayed by the circuit delay of the OR circuit 162, and then the input switch control signal IN_SW falls at timing t158, which is delayed by the circuit delay of the FF 22. After the input switch control signal IN_SW falls, the latch input signal XLTIN_1 is input to the first latch 21-1.

[0139] The delay circuit 182 delays the falling edge of the mask signal XMASK at timing t153, so that at timing t159, the D flip-flop 181 is reset and the mask signal XMASK rises.

[0140] After the photodetection signal rises at timing t160, the TDC input signal TDC_IN rises at timing t161, which is delayed by the circuit delay of the OR circuit 162. After the photodetection signal rises at timing t160, the mask signal XMASK falls at timing t162, which is delayed by the circuit delay of the D flip-flop 181. During the period when the mask signal XMASK is a low signal, the dummy pulse DMYPLS is restricted from rising.

[0141] After the TDC input signal TDC_IN rises, the output switch control signal OUT_SW falls at timing t163, which is delayed by the circuit delay of FF23, and then, at timing t164, which is delayed by the circuit delay of switch 27-2 and the like, output from the second latch 21-2 side begins.

[0142] When the exposure period ends, the enable signal EN falls at timing t165. At timing t165, the inverted signal of the enable signal EN and the inverted signal XCNT_READ are both High signals, so the dummy pulse DMYPLS should rise at timing t167, which is delayed by the circuit delay of the AND circuit 184. However, because the mask signal XMASK is Low, the dummy pulse DMYPLS does not rise.

[0143] After the TDC input signal TDC_IN falls at timing t166, the input switch control signal IN_SW rises at timing t168, which is delayed by the circuit delay of the FF 22. After the input switch control signal IN_SW rises, the latch input signal XLTIN_2 is input to the second latch 21-2.

[0144] The delay circuit 182 delays the falling edge of the mask signal XMASK at timing t162, so that the D flip-flop 181 is reset and the mask signal XMASK rises at timing t169. After the mask signal XMASK rises, the dummy pulse DMYPLS rises at timing t170, which is delayed by the circuit delay of the AND circuit 185.

[0145] As described above, in order to prevent the TDC code held in the first latch 21-1 from being rewritten by the dummy pulse DMYPLS, it is preferable that the dummy pulse DMYPLS rises after the exposure period ends (after timing t165) and after the level of the input switch control signal IN_SW transitions in response to the last photodetection signal in the exposure period (after timing t168).

[0146] In a fifth embodiment of the present technology, a predetermined period including the timing at which the level of the input switch control signal IN_SW transitions in response to the light detection signal is a period (mask period) during which the mask signal XMASK is a Low signal and the rising edge of the dummy pulse DMYPLS is restricted. The length of the mask period is determined by the delay time in the delay circuit 182. The delay time in the delay circuit 182 is adjusted so that the rising edge of the dummy pulse DMYPLS occurs after the transition of the input switch control signal IN_SW.

[0147] In the fifth embodiment, the input rate of the photodetection signal is determined by the reciprocal of the square of the mask period.

[0148] After the dummy pulse DMYPLS rises at timing t170, the TDC input signal TDC_IN rises at timing t171, which is delayed by the circuit delay of the OR circuit 162. After the TDC input signal TDC_IN rises, the output switch control signal OUT_SW rises at timing t172, which is delayed by the circuit delay of the FF 23, and then, at timing t173, which is delayed by the circuit delay of the switch 27-1 and the like, output from the first latch 21-1 side begins.

[0149] After the inversion signal XCNT_READ falls at timing t174, the dummy pulse DMYPLS falls at timing t175, which is delayed by the circuit delay of the AND circuit 184, and then the TDC input signal TDC_IN falls at timing t176, which is delayed by the circuit delay of the OR circuit 162.

[0150] Furthermore, the falling edge of the inverted signal XCNT_READ at timing t174 is delayed by the delay circuit 153, the read signal CNT_READ rises, and the histogram is read out.

[0151] After the TDC input signal TDC_IN falls at timing t176, the input switch control signal IN_SW falls at timing t177, which is delayed by the circuit delay of the FF 22.

[0152] As described above, by providing a mask period in which the rising of the dummy pulse is restricted, it is possible to generate a dummy pulse after the exposure period ends and after the level of the input switch control signal IN_SW transitions in response to the last photodetection signal in the exposure period.

[0153] 7. Sixth Embodiment Fig. 17 is a circuit diagram showing an example of the configuration of a TDC 12 according to a sixth embodiment. In Fig. 17, the same components as those in Fig. 14 are assigned the same reference numerals. Duplicate explanations will be omitted as appropriate.

[0154] The TDC 12 in FIG. 17 differs from the TDC 12 in FIG. 14 in that an input switch control signal IN_SW is input to a TDC input signal generator 151 .

[0155] The TDC input signal generating unit 151 generates a dummy pulse DMYPLS based on the light detection signal, the enable signal EN, the inverted signal XCNT_READ, and the input switch control signal IN_SW.

[0156] Fig. 18 is a circuit diagram showing an example of the configuration of a TDC input signal generator 151 according to the sixth embodiment. In Fig. 18, the same components as those in Fig. 15 are denoted by the same reference numerals. Duplicate explanations will be omitted where appropriate.

[0157] The TDC input signal generation unit 151 in FIG. 18 differs from the TDC input signal generation unit 151 in FIG. 15 in that a delay circuit 201 and an EX-OR circuit 202 are provided instead of the delay circuit 182 in the dummy pulse generation circuit 161.

[0158] The delay circuit 201 delays the input switch control signal IN_SW and outputs it to the EX-OR circuit 202 .

[0159] The input switch control signal IN_SW and the delayed input switch control signal IN_SW are input to the EX-OR circuit 202. If the input switch control signal IN_SW and the delayed input switch control signal IN_SW are exclusive inputs, the EX-OR circuit 202 outputs a reset signal FF_RST to the reset terminal of the D flip-flop 181.

[0160] In other words, the EX-OR circuit 202 generates a reset signal FF_RST based on the input switch control signal IN_SW, which becomes high during the delay time of the delay circuit 201, and inputs it to the reset terminal to reset the D flip-flop 181.

[0161] 19 is a timing chart showing the operation of the TDC 12 according to the sixth embodiment. Note that in FIG. 19, the timings of the delay signal OUT_EN, the CNT input signal OUTPLS, and the TDC output signal TDC_OUT are not shown.

[0162] 19 , after the photodetection signal rises at timing t201, the TDC input signal TDC_IN rises at timing t202, which is delayed by the circuit delay of the OR circuit 162. In addition, after the photodetection signal rises at timing t201, the mask signal XMASK falls at timing t203, which is delayed by the circuit delay of the D flip-flop 181.

[0163] After the TDC input signal TDC_IN rises, the output switch control signal OUT_SW rises at timing t204, which is delayed by the circuit delay of the FF 23.

[0164] After the photodetection signal falls at timing t205, the TDC input signal TDC_IN falls at timing t206, which is delayed by the circuit delay of the OR circuit 162, and then the input switch control signal IN_SW falls at timing t207, which is delayed by the circuit delay of the FF 22. After the input switch control signal IN_SW falls, the latch input signal XLTIN_1 is input to the first latch 21-1.

[0165] At timing t207, the input switch control signal IN_SW falls, but the input switch control signal IN_SW delayed by the delay circuit 201 has not yet fallen, so the reset signal FF_RST rises at timing t208, which is delayed by the circuit delay of the EX-OR circuit 202. In response to the reset signal FF_RST rising, the D flip-flop 181 is reset at timing t209, and the mask signal XMASK rises.

[0166] After the photodetection signal rises at timing t210, the TDC input signal TDC_IN rises at timing t211, which is delayed by the circuit delay of the OR circuit 162. Furthermore, after the photodetection signal rises at timing t210, the mask signal XMASK falls at timing t212, which is delayed by the circuit delay of the D flip-flop 181. During the period when the mask signal XMASK is a low signal, the dummy pulse DMYPLS is restricted from rising.

[0167] After the TDC input signal TDC_IN rises, the output switch control signal OUT_SW falls at timing t213, which is delayed by the circuit delay of the FF 23.

[0168] When the exposure period ends, the enable signal EN falls at timing t214. At timing t214, the inverted signal of the enable signal EN and the inverted signal XCNT_READ are both High signals, so the dummy pulse DMYPLS should rise at timing t216, which is delayed by the circuit delay of the AND circuit 184. However, because the mask signal XMASK is Low, the dummy pulse DMYPLS does not rise.

[0169] After the TDC input signal TDC_IN falls at timing t215, the input switch control signal IN_SW rises at timing t217, which is delayed by the circuit delay of the FF 22. After the input switch control signal IN_SW rises, the latch input signal XLTIN_2 is input to the second latch 21-2.

[0170] At timing t217, the input switch control signal IN_SW falls, but the input switch control signal IN_SW delayed by the delay circuit 201 has not yet fallen, so the reset signal FF_RST rises at timing t218, which is delayed by the circuit delay of the EX-OR circuit 202. In response to the reset signal FF_RST rising, the D flip-flop 181 is reset at timing t219, and the mask signal XMASK rises.

[0171] After the mask signal XMASK rises, the dummy pulse DMYPLS rises at timing t220, which is delayed by the circuit delay of the AND circuit 185.

[0172] As described above, in order to prevent the TDC code held in the first latch 21-1 from being rewritten by the dummy pulse DMYPLS, it is preferable that the dummy pulse DMYPLS rises after the exposure period ends (after timing t214) and after the level of the input switch control signal IN_SW transitions in response to the last photodetection signal in the exposure period (after timing t217).

[0173] In a sixth embodiment of the present technology, a predetermined period including a timing at which the level of the input switch control signal IN_SW transitions in response to a light detection signal is set as a mask period. The mask period corresponds to a period from when the last light detection signal is input in the exposure period until when the level of the input switch control signal IN_SW transitions.

[0174] After the dummy pulse DMYPLS rises at timing t220, the TDC input signal TDC_IN rises at timing t221, which is delayed by the circuit delay of the OR circuit 162, and then the output switch control signal OUT_SW rises at timing t222, which is delayed by the circuit delay of FF23.

[0175] After the inversion signal XCNT_READ falls at timing t223, the dummy pulse DMYPLS falls at timing t224, which is delayed by the circuit delay of the AND circuit 184, and then the TDC input signal TDC_IN falls at timing t225, which is delayed by the circuit delay of the OR circuit 162.

[0176] Furthermore, the falling edge of the inverted signal XCNT_READ at timing t223 is delayed by the delay circuit 153, the read signal CNT_READ rises, and the histogram is read out.

[0177] After the TDC input signal TDC_IN falls at timing t225, the input switch control signal IN_SW falls at timing t226, which is delayed by the circuit delay of the FF 22.

[0178] At timing t226, the input switch control signal IN_SW falls, but the input switch control signal IN_SW delayed by the delay circuit 201 has not yet fallen, so the reset signal FF_RST rises at timing t227, which is delayed by the circuit delay of the EX-OR circuit 202.

[0179] As described above, it is possible to set the mask period based on the timing at which the last light detection signal in the exposure period is input and the timing at which the level of the input switch control signal IN_SW transitions.

[0180] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0181] The embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present technology.

[0182] <Examples of Combinations of Configurations> The present technology can also have the following configurations.

[0183] (1) A signal processing device comprising a plurality of latch units that hold data based on a photodetection signal output from a photodetector that detects light reflected from an object, output the data in response to the photodetection signal during an exposure period of the photodetector, and output the data in response to a dummy pulse during periods other than the exposure period. (2) The signal processing device described in (1) above further comprises a generator that generates the dummy pulse. (3) The signal processing device described in (2) above, in which the generator generates the dummy pulse based on an enable signal indicating the exposure period. (4) The signal processing device described in (3) above further comprises a selector that switches the latch unit that holds the data among the plurality of latch units in response to the photodetection signal or the dummy pulse. (5) The signal processing device described in (4) above, in which the generator includes a flip-flop that outputs a mask signal that prevents the dummy pulse from rising during a predetermined period that includes a timing when the selector transitions the level of an input control signal for switching the latch unit that holds the data in response to the last photodetection signal during the exposure period. (6) The signal processing device according to (5), wherein the flip-flop stores a signal of a constant level input to a first input terminal at the rising edge of the photodetection signal input to a second input terminal, and outputs an inverted signal of the stored signal as the mask signal. (7) The signal processing device according to (5) or (6), wherein the generation unit resets the flip-flop by inputting a reset signal based on the input control signal to a reset terminal of the flip-flop. (8) The signal processing device according to (5) or (6), wherein the generation unit resets the flip-flop by delaying the mask signal and inputting it to the reset terminal of the flip-flop. (9) The signal processing device according to (4), wherein the generation unit includes a delay unit that delays the dummy pulse so that the dummy pulse rises after the selection unit transitions the level of the input control signal for switching the latch unit that holds the data in accordance with the last photodetection signal in the exposure period.(10) The signal processing device according to (3) or (4), wherein the generation unit generates the dummy pulse using a transition in the level of the enable signal as a trigger. (11) The signal processing device according to (3) or (4), wherein the generation unit generates the dummy pulse based on the enable signal and a signal obtained by delaying the enable signal. (12) The signal processing device according to (11), wherein the generation unit outputs the dummy pulse when the enable signal and a signal obtained by delaying an inverted version of the enable signal are both Low signals. (13) The signal processing device according to (1), wherein the latch unit outputs the data in response to the dummy pulse input from outside the signal processing device. (14) The signal processing device according to any one of (1) to (13), wherein the data is a TDC code indicating the timing at which the reflected light is detected by the light detection unit. (15) The signal processing device according to (14), wherein the plurality of latch units output the TDC code to a counter that generates a histogram of the TDC code. (16) The signal processing device according to (15), wherein at least one of the plurality of latch units outputs the data in response to the dummy pulse during a period from after the exposure period ends to before reading of the histogram from the counter starts. (17) A distance measuring sensor comprising: a light detection unit that detects reflected light of laser light reflected by an object, a plurality of latch units that hold data based on a light detection signal output from the light detection unit, and output the data in response to the light detection signal during an exposure period of the light detection unit and output the data in response to a dummy pulse during periods other than the exposure period, and a counter that generates a histogram of the data output from the latch units.

[0184] 1 Range finding sensor, 11 Light detection unit, 12 TDC, 13 CNT, 14 Control unit, 21-1 First latch, 21-2 Second latch, 22, 23 FF, 24 Inverter, 25-1, 25-2 NAND circuit, 26 Inverter, 27-1, 27-2 Switch, 28 Delay circuit, 29 AND circuit, 51 OR circuit, 81 TDC input signal generation unit, 91 Dummy pulse generation unit, 92 OR circuit, 111 Inverter, 112 Delay circuit, 113 NOR circuit, 131 Delay circuit, 151 TDC input signal generation unit, 152 Inverter, 153 Delay circuit, 161 Dummy pulse generation unit, 162 OR circuit, 181 D flip-flop, 182 Delay circuit, 183 Inverter, 184, 185 AND circuit, 201 delay circuit, 202 EX-OR circuit

Claims

1. A signal processing device comprising a plurality of latch units which hold data based on a photodetection signal output from a photodetection unit which detects reflected light of laser light reflected by an object, output the data in response to the photodetection signal during an exposure period of the photodetection unit, and output the data in response to a dummy pulse during periods other than the exposure period.

2. The signal processing device according to claim 1, further comprising a generating unit for generating the dummy pulse.

3. The signal processing device according to claim 2, wherein the generating section generates the dummy pulse based on an enable signal indicating the exposure period.

4. The signal processing device according to claim 3, further comprising a selection section that switches the latch section that holds the data among the plurality of latch sections in response to the light detection signal or the dummy pulse.

5. The signal processing device according to claim 4, wherein the generating section includes a flip-flop that outputs a mask signal that restricts the dummy pulse from rising during a predetermined period including the timing when the selecting section transitions the level of an input control signal for switching the latch section that holds the data in response to the last light detection signal in the exposure period.

6. The signal processing device according to claim 5, wherein the flip-flop stores a constant level signal input to a first input terminal at the rising edge of the photodetection signal input to a second input terminal, and outputs an inverted signal of the stored signal as the mask signal.

7. The signal processing device according to claim 5, wherein the generating section resets the flip-flop by inputting a reset signal based on the input control signal to a reset terminal of the flip-flop.

8. The signal processing device according to claim 5, wherein the generation section resets the flip-flop by delaying the mask signal and inputting it to a reset terminal of the flip-flop.

9. The signal processing device according to claim 4, wherein the generating section includes a delay section that delays the dummy pulse so that the dummy pulse rises after the selecting section transitions the level of an input control signal for switching the latch section that holds the data in response to the last light detection signal in the exposure period.

10. The signal processing device according to claim 3, wherein the generating section generates the dummy pulse using a transition in the level of the enable signal as a trigger.

11. The signal processing device according to claim 3, wherein the generating section generates the dummy pulse based on the enable signal and a signal obtained by delaying the enable signal.

12. The signal processing device according to claim 11, wherein the generating section outputs the dummy pulse when the enable signal and a signal obtained by delaying an inverted signal of the enable signal are both low signals.

13. The signal processing device according to claim 1, wherein the latch section outputs the data in response to the dummy pulse input from outside the signal processing device.

14. The signal processing device according to claim 1, wherein the data is a TDC code indicating the timing at which the reflected light is detected by the light detection section.

15. The signal processing device according to claim 14, wherein the plurality of latch sections output the TDC codes to a counter that generates a histogram of the TDC codes.

16. A signal processing device as described in claim 15, wherein at least one of the plurality of latch sections outputs the data in response to the dummy pulse during the period from after the exposure period ends until before reading of the histogram from the counter starts.

17. A distance measuring sensor comprising: a light detection unit that detects reflected light of laser light reflected by an object; a plurality of latch units that hold data based on a light detection signal output from the light detection unit, output the data in response to the light detection signal during an exposure period of the light detection unit, and output the data in response to a dummy pulse during periods other than the exposure period; and a counter that generates a histogram of the data output from the latch units.

Images