Logic gate circuit, adder circuit structure, and processor

Abstract

A logic gate circuit, an adder circuit structure, and a processor. The logic gate circuit is used for realizing an XOR or XNOR logic operation. The logic gate circuit comprises a first input port, a second input port, and a first output port. A transmission path from the first input port to the first output port is a first transmission path; a transmission path from the second input port to the first output port is a second transmission path; and a delay of the second transmission path is greater than that of the first transmission path.

Description

Logic gate circuit, adder circuit structure and processor Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, the field of computer technology, and in particular to a logic gate circuit, an adder circuit structure, and a processor. Background Art

[0002] Adders, as the most basic logical unit, are widely used in various types of processors. In circuit systems, adders are primarily responsible for calculations and indexing. Adders contain multiple circuit structures, and reducing their power consumption is a common requirement.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, an embodiment of the present disclosure provides a logic gate circuit for implementing exclusive-OR or exclusive-OR logical operations, wherein the logic gate circuit includes a first input port, a second input port, and a first output port, wherein the transmission path from the first input port to the first output port is a first transmission path, and the transmission path from the second input port to the first output port is a second transmission path, and the delay of the second transmission path is greater than the delay of the first transmission path.

[0006] In a second aspect, an embodiment of the present disclosure further provides a logic gate circuit for implementing a summation operation in an adder, wherein the logic gate circuit includes a first logic subcircuit and a second logic subcircuit, wherein:

[0007] The first logic sub-circuit is used to perform an exclusive-OR operation or an exclusive-OR operation, the first logic sub-circuit includes a first input bit, a second input bit and a first output bit, and the first output bit of the first logic sub-circuit is connected to the second input port of the second logic sub-circuit;

[0008] The second logic sub-circuit includes a first input port, a second input port, and a first output port. The first output port of the second logic sub-circuit outputs the result of the summation operation, wherein the transmission path from the first input port to the first output port is the first transmission path, the transmission path from the second input port to the first output port is the second transmission path, and the delay of the second transmission path is greater than the delay of the first transmission path.

[0009] In a third aspect, an embodiment of the present disclosure provides an adder circuit structure, including: for implementing addition operations on 2^n bits of data, where n is a positive integer greater than or equal to 3, the adder includes at least 2^n logic gate circuits as mentioned in the second aspect above.

[0010] In a fourth aspect, an embodiment of the present disclosure provides an adder circuit structure, including: for implementing an addition operation of 2^n bits of data, where n is a positive integer greater than or equal to 3, the adder includes: at least 2^n first-class circuit structures, at least 2 second-class circuit structures, at least 2^n-2 third-class circuit structures, and at least 2^n-1 fourth-class circuit structures, wherein: the first-class circuit structure receives the i-th bit of the input first data and the i-th bit of the second data, 0≥i≥2^n, and outputs the G logic result and the P logic result of the i-th bit; the second-class circuit structure receives the G logic result and the P logic result, and outputs a G logic result sub-combination and a P logic result sub-combination; the third-class circuit structure receives the G logic result and the P logic result, or receives the G logic result sub-combination and the P logic result sub-combination, and outputs a new G logic result sub-combination; the fourth-class circuit structure receives the P logic result and the G logic result, or receives the P logic result and the new G logic result sub-combination, and outputs a sum value, and the four-class circuit structures include the logic gate circuits mentioned in the first aspect above.

[0011] In a fifth aspect, an embodiment of the present disclosure provides a processor, comprising: the adder circuit structure as described above.

[0012] Other features and advantages of the present disclosure will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present disclosure. Other advantages of the present disclosure can be realized and obtained by the solutions described in the description, claims and drawings.

[0013] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0014] Summary of the Figures

[0015] The accompanying drawings are intended to facilitate understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0016] Figure 1 is a typical circuit diagram;

[0017] Figure 2 is a topological diagram of an 8-bit unsigned integer adder with carry;

[0018] FIG3A is a circuit diagram of a circuit structure S01;

[0019] FIG3B is a symbolic diagram of a circuit structure S01;

[0020] FIG4A is a circuit diagram of the second type circuit structure S02;

[0021] FIG4B is a symbolic diagram of the second type of circuit structure S02;

[0022] FIG5A is a circuit diagram of the third type of circuit structure S03;

[0023] FIG5B is a symbolic diagram of three types of circuit structures S03;

[0024] FIG6A is a circuit diagram of the fourth type of circuit structure S04;

[0025] FIG6B is a symbolic diagram of four types of circuit structures S04;

[0026] FIG7 is a topological structure diagram obtained by abstracting each Si path in FIG2;

[0027] FIG8A is a circuit diagram of an XOR gate;

[0028] FIG8B is another XOR gate circuit diagram;

[0029] FIG8C shows a Take the NOT gate circuit diagram as an example;

[0030] FIG8D is a transmission gate circuit diagram;

[0031] FIG9 is a circuit diagram of an XOR gate according to an embodiment of the present disclosure;

[0032] FIG10 is a circuit diagram of an XNOR gate according to an embodiment of the present disclosure;

[0033] FIG11 is a schematic diagram of another logic gate circuit provided by an embodiment of the present disclosure;

[0034] FIG12 is a circuit diagram of implementing the topology structure shown in FIG7 using an XOR gate according to an embodiment of the present disclosure;

[0035] FIG13 is a circuit diagram of implementing the topology structure shown in FIG7 using an XNOR gate according to an embodiment of the present disclosure;

[0036] FIG14 is another circuit diagram of implementing the topology shown in FIG7 using an XOR gate according to an embodiment of the present disclosure;

[0037] FIG15 is another circuit diagram of implementing the topology shown in FIG7 using an XNOR gate according to an embodiment of the present disclosure;

[0038] Figure 16 is a topological diagram of a 32-bit unsigned integer adder with carry.

[0039] Details

[0040] The present disclosure describes a number of embodiments, but this description is exemplary rather than restrictive, and it will be apparent to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present disclosure. Although many possible feature combinations are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0041] The term "and / or" in this article is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0042] The terms "first" and "second" and the like in the specification and drawings of the present disclosure are used to distinguish different objects, or to distinguish different processing of the same object, rather than to describe a specific order of objects. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein.

[0043] In the description of the present disclosure, unless otherwise specified, “plurality” means two or more, and “two or more” herein includes two.

[0044] The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The disclosed embodiments, features, and elements of the present disclosure may also be combined with any conventional features or elements to form a unique inventive solution defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any appropriate combination. Therefore, the embodiments are not subject to other limitations except for the limitations set forth in the appended claims and their equivalents. In addition, various modifications and changes may be made within the scope of protection of the appended claims.

[0045] A typical circuit diagram is shown in Figure 1, which includes a first register (reg1), a logic gate circuit (U1), and a second register (reg2). There are two paths from the output (Q) of reg1 to the input (D) of reg2: PathA (represented by the thick solid line in the figure) and PathB (represented by the thick dashed line in the figure). PathA's path is reg1 / Q → U1 / a → reg2 / D, while PathB's path is reg1 / Q → ... → U1 / b → reg2 / D. PathB has a deeper logic depth than PathA, so PathA has a timing margin. The circuit structure of U1 in this path can be optimized, for example, by adjusting the circuit in the path from U1 / a to U1 / o, including reconfiguring the logic or adjusting the transistor (MOSFET) size, to reduce U1's power consumption.

[0046] Figure 2 shows the topology of an 8-bit unsigned integer adder with carry. The figure involves four circuit structures (or circuit units): type 1, type 2, type 3, and type 4, represented below as circuit structures S01, S02, S03, and S04, respectively. All four circuit structures are composed of logic gates.

[0047] Figure 3A is a circuit diagram of circuit structure S01 (a type of circuit structure), and Figure 3B is a symbolic diagram of circuit structure S01. The circuit structure S01 consists of logic gates: an AND gate (and) and an XOR gate (xor). The input of circuit structure S01 is a i and b i , indicating the a and b of the i-th position, the output is G i and P i , represents the G (Generate, carry generation) logic result and P (Propagate, carry propagation) logic result of the i-th bit. G, P and a i 、b i The logical relationship is: G i =a i b i Formula 1

[0048] Figure 4A is a circuit diagram of circuit structure S02 (second type circuit structure), and Figure 4B is a symbolic diagram of circuit structure S02. The circuit structure S02 consists of logic gates: one AND gate (and) and one AND-OR gate (abbreviated as ao gate). The input of circuit structure S02 is P i:k , G i:k 、P k-1:j and G k-1:j , the output is G i:jand P i:j , that is, the G logical result subcombination and the P logical result subcombination, the relationship between i, j, k is: i>k>k-1>j. In some cases, i=k, or k=j, or k-1=j may appear. The logical relationship between P and G is: P i:j =P i:k ·P k-1:j Formula 3 G i:j =(P i:k ·G k-1:j )|G i:k Formula 4

[0049] When j=i-1, P i:i-1 =P i:i ·P i-1:i-1 =P i ·P i-1 Type 5G i:i-1 =(P i:i ·G i-1:i-1 )|G i:i =(P i ·G i-1 )|G i Formula 6

[0050] For example: If i=5, k=3, j=1, then P 5:1 =P 5:3 ·P 2:1 , G 5:1 =(P 5:3 ·G 2:1 )|G 5:3

[0051] Among them, P 5:3 =P 5:4 ·P 3:3 , G 5:3 =(P 5:4 ·G 3:3 )|G 5:4 , P 3:3 That is, P3, which can be obtained by the above formula 2, G 3:3 That is, G3, which can be obtained by the above formula 1, then P 5:3 =P 5:4 P3, G 5:3 =(P 5:4 ·G3)|G 5:4 Among them, P 5:4 =P 5:5 ·P 4:4 , G 5:4 =(P 5:5 ·G 4:4 )|G5:5 , P 5:5 That is, P5, P 4:4 That is, P4, G 5:5 That is G5, G 4:4 That is, G4, then P 5:4 =P5·P4,G 5:4 =(P5·G4)|G5; where P 2:1 =P 2:2 ·P 1:1 , G 2:1 =(P 2:2 ·G 1:1 )|G 2:2 , P 2:2 That is, P2, P 1:1 That is, P1, G 2:2 That is, G2, G 1:1 That is, G1, then P 2:1 =P2·P1,G 2:1 =(P2·G1)|G2.

[0052] Figure 5A is a circuit diagram of circuit structure S03 (type 3 circuit structure), and Figure 5B is a symbolic diagram of circuit structure S03. Circuit structure S03 consists of a logic gate: 1 ao gate. Compared with circuit structure S02, it has one less AND gate (and). The input of circuit structure S03 is P i:k , G i:k and G k-1:j , the output is G i:j , that is, the new G logical result sub-combination, the relationship between i, j, k is: i>k>k-1>j. In some cases, i=k, or k=j, or k-1=j may appear. The logical relationship between P and G is as follows, the same as formula 4: G i:j =(P i:k ·G k-1:j )|G i:k Formula 7 (same as Formula 4)

[0053] Figure 6A is a circuit diagram of circuit structure S04 (fourth type of circuit structure), and Figure 6B is a symbolic diagram of circuit structure S04. The circuit structure S04 consists of a logic gate: an exclusive OR gate (xor). The input of circuit structure S04 is P i and G i-1:0 , the output is S i , S i Represents S (sum, sum value) of the i-th position. The logical relationship between them is: S i =P i ·G i-1:0 Formula 8

[0054] In the examples herein, the circuit structure S01 is represented by a hexagon, the circuit structure S02 is represented by a square, the circuit structure S03 is represented by a circle, and the circuit structure S04 is represented by a triangle. These are merely examples and are not intended to limit the present application.

[0055] In the adder shown in Figure 2, the expression of the circuit structure of the last stage is: S i =function(P i ,G i-1:0 ), i is any integer from 0 to 7. The input term P in the formula i The signal comes from the logic output of the first-level circuit structure S01, and each S i After the circuit is abstracted, the topology diagram shown in Figure 7 is obtained, which shows the logical relationship between the last level and the first level in the adder. In the figure, the logic circuit U2 is the circuit structure S04, and the logic circuit U1 is the circuit structure S01. As shown in Figures 2 to 7, P i The logic is generated by an XOR gate (U1 in the figure), P i It will directly serve as the input of U2 and connect to the b port (pin) of U2. The a port of U2 is connected to other logic. The logic depth of this path is usually deep and it is a critical path. In some examples, based on the value of the input port, U2 can determine whether to use an exclusive-OR gate (xor) or an exclusive-Nor gate (xnr). The expression can be: S i =xor(G i-1:0 ,P i ), S i =xor(!G i-1:0 ,! P i ), S i =xnr(!G i-1:0 ,P i ), S i =xnr(G i-1:0 ,! P i ).

[0056] In one embodiment, the circuit implementation of the XOR gate (xor) can be shown in FIG8A , which is implemented using transistors. A total of 8+4=12 transistors are required, of which 8 transistors are shown in the figure. In addition, a is converted into Two transistors are needed (as shown in Figure 8C) to convert b into Requires 2 transistors, so 4 transistors are required. In order to reduce the number of transistors, in another embodiment, the XOR gate circuit is implemented using a NOT gate and a transmission gate, as shown in FIG8B , wherein As an example, the NOT gate circuit is shown in FIG8C , and the transmission gate circuit is shown in FIG8D . It can be seen that 10 transistors are still required to implement the XOR gate using the circuit shown in FIG8B .

[0057] Generally speaking, the delay from input port a to output port o and the delay from input port b to output port o in the XOR gate are basically the same. However, the inventors took into account that in the application scenario of the adder, as shown in the circuit diagram of Figure 7, since the path from input port b of U2 to output port o of U2 is a non-critical path, there is no requirement for the delay of this path, so the power consumption can be reduced by increasing the delay.

[0058] To this end, an embodiment of the present disclosure provides a logic gate circuit structure that can implement an exclusive-OR operation. As shown in Figure 9, the exclusive-OR gate circuit structure includes an input port a1 (hereinafter referred to as a1 port), an input port b1 (hereinafter referred to as b1 port), and an output port o1 (hereinafter referred to as o1 port), wherein the transmission path from port a1 to port o1 is a first transmission path, and the transmission path from port b1 to port o1 is a second transmission path. The first transmission path is asymmetric with the second transmission path. The delay of the second transmission path is different from the delay of the first transmission path. For example, the delay of the second transmission path is greater than the delay of the first transmission path. The exclusive-OR gate circuit is implemented by adopting a circuit with large delay but low power consumption. The output o1 of the exclusive-OR gate = xor(a1, b1).

[0059] For example, a transmission gate can be used to implement the XOR gate circuit. Port a1 is connected to the input of the first transmission gate TG1, and the output of the first transmission gate TG1 is connected to port o1 of the XOR gate circuit. Port a1 is also connected to the gates of the first transistor T1 and the second transistor T2, respectively, for controlling the on / off state of the first transistor T1 and the second transistor T2. Port b1 is connected to the first electrode of the first transistor T1, and the second electrode of the first transistor T1 is connected to port o1 of the XOR gate circuit. Port b1 is also connected to the first control terminal sb of the transmission gate TG1. Port b1 is also connected to the input of the first inverter D1, and the output of the first inverter D1 is connected to the second control terminal s of the first transmission gate TG1. The output of the first inverter D1 is also connected to the first electrode of the second transistor T2, and the second electrode of the second transistor T2 is connected to port o1 of the XOR gate circuit. In this XOR gate circuit, the signal at port b1 is used to control the on / off state of the first transmission gate TG1. In an exemplary embodiment, the first transistor T1 is a PMOS transistor, and the second transistor T2 is an NMOS transistor. In other embodiments, those skilled in the art may replace the transistors according to input.

[0060] The working process of the XOR gate circuit is introduced below.

[0061] When a1=0, b1=0, the first transistor T1 is turned off (Vgs does not meet the conduction requirement), the second transistor T2 is turned off, and the NOT gate D1 outputs the inverted signal of b1. Therefore, the control terminal sb=b1=0 of the transmission gate TG1. The output of the first transmission gate TG1 is equal to the input, so the XOR gate output o1 = a1 = 0;

[0062] When a1=1, b1=0, the output of NOT gate D1 is the inverted signal of b1. The Vgs of the second transistor T2 does not meet the conduction requirement, the first transistor T1 and the second transistor T2 are both turned off, and the control terminal of the transmission gate sb=b1=0, the transmission gate output is equal to the input, so the XOR gate output o1=a1=1;

[0063] When a1=0, b1=1, the transmission gate is closed and the output is high impedance, the first transistor T1 is turned on, the second transistor T2 is turned off, and the XOR gate outputs o1=b1=1;

[0064] When a1=1, b1=1, the transmission gate is closed, the first transistor is closed, the second transistor is open, and the XOR gate outputs

[0065] It can be seen that the output of the circuit shown in Figure 9 conforms to the input and output logic of the XOR gate, and the circuit only requires 6 transistors to realize the XOR gate logic function, which reduces the area of ​​the logic gate circuit structure and reduces the power consumption of the logic gate circuit.

[0066] Another embodiment of the present disclosure provides an XNOR gate circuit structure, as shown in Figure 10, the XNOR gate circuit structure includes an input port a2 (hereinafter referred to as a2 port), an input port b2 (hereinafter referred to as b2 port) and an output port o2 (hereinafter referred to as o2 port), wherein the transmission path from a2 port to o2 port is a first transmission path, and the transmission path from b2 port to o2 port is a second transmission path. The first transmission path is asymmetric with the second transmission path. The delay of the second transmission path is different from the delay of the first transmission path, for example, the delay of the second transmission path is greater than the delay of the first transmission path. The XNOR gate circuit is implemented by adopting a circuit with large delay but low power consumption. The output o2 of the XNOR gate = xnr(a2, b2).

[0067] For example, a transmission gate can be used to implement the X-OR circuit. Port a2 is connected to the input of the second transmission gate TG2, and the output of the second transmission gate TG2 is connected to port o2 of the X-OR circuit. Port a2 is also connected to the gates of the third and fourth transistors T3 and T4, respectively, for controlling the on / off switching of the third and fourth transistors T3 and T4. Port b2 is connected to the first electrode of the third transistor T3, and the second electrode of the third transistor T3 is connected to port o2 of the X-OR circuit. Port b2 is also connected to the second control terminal s of the second transmission gate TG2. Port b2 is also connected to the input of the second inverter D2, and the output of the second inverter D2 is connected to the first control terminal sb of the second transmission gate TG2. The output of the second inverter D2 is also connected to the first electrode of the fourth transistor T4, and the second electrode of the fourth transistor T4 is connected to port o2 of the X-OR circuit. In this X-OR circuit, the signal at port b2 is used to control the on / off switching of the second transmission gate TG2. In an exemplary embodiment, the third transistor T3 is an NMOS transistor, and the fourth transistor T4 is a PMOS transistor. In other embodiments, those skilled in the art may replace the transistors according to input.

[0068] The working process of the XOR gate circuit is introduced below.

[0069] When a2=0, b2=0, the output of NOT gate D2 is the inverted signal of b2. Therefore, the control terminal of the transmission gate TG2 s=b2=0, transmission gate TG2 is closed, output is high impedance, fourth transistor T4 is turned on, third transistor T3 is turned off, and the XOR gate output is

[0070] When a2=1, b2=0, the output of NOT gate D2 is the inverted signal of b2. The control terminal of the transmission gate s=b2=0, The transmission gate TG2 is closed, the third transistor T3 is turned on, and the fourth transistor T4 is turned off, so the XOR gate outputs o2 = b2 = 0;

[0071] When a2=0, b2=1, the third transistor T3 is turned off, the fourth transistor T4 is turned off, and the NOT gate D2 outputs the inverted signal of b2. The control terminal of the transmission gate s=b2=1, Transmission gate TG2 opens, output o = input i = a2 = 0, and the XOR gate output o2 = a2 = 0;

[0072] When a2=1, b2=1, the third transistor T3 is turned off, the fourth transistor T4 is turned off, and the NOT gate D2 outputs the inverted signal of b2. The control terminal of the transmission gate s=b2=1, Transmission gate TG2 opens, output o = input i = a2 = 1, and the XOR gate output o2 = a2 = 1.

[0073] It can be seen that the output of the circuit shown in Figure 10 conforms to the input and output logic of the XNOR gate, and the circuit also only requires 6 transistors to realize the XNOR gate logic function, which reduces the area of ​​the logic gate circuit structure and reduces the power consumption of the logic gate circuit.

[0074] When an adder is constructed using the aforementioned XOR or XNOR gate circuits, fewer transistors are used in the circuit structure, the area occupied by the adder circuit topology is reduced, and overall power consumption is lowered. Thus, the logic gate circuit structure provided in this embodiment, and an adder incorporating this logic gate circuit structure, can achieve a topology with a smaller area and lower power consumption, while also achieving a good balance between power consumption and speed.

[0075] As shown in FIG11 , an embodiment of the present disclosure provides a logic gate circuit for implementing a summation operation in an adder. The logic gate circuit includes a first logic subcircuit and a second logic subcircuit, wherein:

[0076] The first logic sub-circuit is used to perform an exclusive-OR operation or an exclusive-OR operation, the first logic sub-circuit includes a first input bit, a second input bit and a first output bit, and the first output bit of the first logic sub-circuit is connected to the second input port of the second logic sub-circuit;

[0077] The second logic subcircuit includes a first input port, a second input port, and a first output port. The first output port of the second logic subcircuit outputs the result of the summation operation. The transmission path from the first input port to the first output port is a first transmission path, and the transmission path from the second input port to the first output port is a second transmission path. The delay of the second transmission path is greater than the delay of the first transmission path. The second logic subcircuit can be implemented using the circuit shown in Figure 9 or Figure 10.

[0078] The above logic gate circuit uses the logic gate circuit shown in FIG9 to realize the XOR function, or uses the logic gate circuit shown in FIG10 to realize the XNOR function, thereby reducing the power consumption of the logic gate circuit and reducing the circuit area.

[0079] In an exemplary embodiment, the first logic subcircuit can be used to implement an exclusive-OR operation. To implement the circuit structure shown in FIG7 , the exclusive-OR gate circuit in FIG9 is used to replace U2 in FIG7 . That is, the exclusive-OR gate structure in FIG9 is used as the second logic subcircuit to implement the function of the logic gate circuit together with the first logic subcircuit. Combining FIG7 and FIG9 , a new circuit structure S04 shown in FIG12 can be obtained. The expression of this circuit structure is S i ,P i=func(a i ,b i ,G i-1:0 ), where a i is the first bit of the first data of the first input bit, b i The i-th bit of the second data of the second input bit is input, P i is the output of the first logic sub-circuit, that is, the first input of the second logic sub-circuit, G i-1:0 is the first G logic result, i.e., the second input of the second logic sub-circuit. Substituting this expression into the topology diagrams shown in FIG1 or FIG2 , it is possible to partially replace the original topology with a new circuit structure S04, thereby reducing circuit area and power consumption.

[0080] In an exemplary embodiment, the first logic subcircuit can be used to implement an exclusive-OR operation. To implement the circuit structure shown in FIG. 7 , the exclusive-OR gate in FIG. 10 can be used to replace U2 in FIG. 7 . That is, the exclusive-OR gate in FIG. 10 serves as the second logic subcircuit. To ensure the correct result of the entire logic gate circuit, the input terminal a of U2 in FIG. 7 is changed to !a. That is, the first input port of the second logic subcircuit inputs the second G logic result !G. i-1:0 , the second G logic result is the inverse of the first G logic result, and by combining FIG7 and FIG10 , a new circuit structure S04 shown in FIG13 can be obtained. The expression of this circuit structure is S i ,P i =func(a i ,b i ,! G i-1:0 ), where a i is the first bit of the first data of the first input bit, b i The i-th bit of the second data of the second input bit is input, P i is the output of the first logic sub-circuit, ie, the first input of the second logic sub-circuit! G i-1:0 is the second G logic result, i.e., the second input of the second logic sub-circuit. Substituting this expression into the topology diagrams shown in FIG1 or FIG2 , it is possible to partially replace the original topology with a new circuit structure S04, thereby reducing circuit area and power consumption.

[0081] In an exemplary embodiment, the first logic subcircuit can be used to implement an XOR operation, that is, the XOR gate U1 in the circuit structure shown in FIG7 is replaced by an XOR gate, and the second logic subcircuit can be implemented using the XOR gate circuit in FIG9 , that is, the XOR gate circuit in FIG9 replaces U2 in FIG7 . In order to ensure the correct result of the entire logic gate circuit, the input terminal a of U2 in FIG7 is changed to !a, that is, the first input port of the second logic subcircuit inputs the second G logic result !G i-1:0, combining FIG7 and FIG9, we can get the new circuit structure S04 shown in FIG14, the expression of the circuit structure is S i ,! P i =func(a i ,b i ,! G i-1:0 ), where a i is the first bit of the first data of the first input bit, b i The i-th bit of the second data of the second input bit is input,! P i is the output of the first logic sub-circuit, ie, the first input of the second logic sub-circuit! G i-1:0 is the second G logic result, i.e., the second input of the second logic sub-circuit. Substituting this expression into the topology diagrams shown in FIG1 or FIG2 , it is possible to partially replace the original topology with a new circuit structure S04, thereby reducing circuit area and power consumption.

[0082] In an exemplary embodiment, the first logic subcircuit can be used to implement an XOR operation, that is, the XOR gate U1 in the circuit structure shown in FIG7 can be replaced by an XOR gate, and the second logic subcircuit can be implemented by the XOR gate circuit in FIG10, that is, the XOR gate circuit in FIG10 replaces U2 in FIG7. Combining FIG7 and FIG10, a new circuit structure S04 shown in FIG15 can be obtained. The expression of this circuit structure is S i ,! P i =func(a i ,b i ,G i-1:0 ), where a i is the first bit of the first data of the first input bit, b i The i-th bit of the second data of the second input bit is input,! P i is the output of the first logic sub-circuit, that is, the first input of the second logic sub-circuit, G i-1:0 is the first G logic result, i.e., the second input of the second logic sub-circuit. Substituting this expression into the topology diagrams shown in FIG1 or FIG2 , it is possible to partially replace the original topology with a new circuit structure S04, thereby reducing circuit area and power consumption.

[0083] The logic gate circuits shown in FIG. 12 to FIG. 15 can be used to implement a summation operation in an adder. The logic gate circuit includes a first logic subcircuit and a second logic subcircuit. The first logic subcircuit includes a first input bit (a i ), the second input bit (b i ) and the first output bit (output P i or! P i), the result of the first output bit output of the first logic sub-circuit and the data inputted by the first input port (G i-1:0 or !G i-1:0 ) together as the input of the second logic sub-circuit, the output of the second logic sub-circuit is the result of the summation operation (Si), the first logic sub-circuit can be an XOR gate or an XNOR gate, and the second logic sub-circuit can be the logic gate circuit in Figure 9 or the logic gate circuit in Figure 10.

[0084] The embodiment of the present disclosure further provides an adder circuit structure including the XOR gate shown in FIG9 or the XNOR gate shown in FIG10, for implementing the addition operation of 2^n bits of data, where n is a positive integer greater than or equal to 3. The adder includes: at least 2^n first-class circuit structures (i.e., the aforementioned circuit structure S01), at least 2 second-class circuit structures (i.e., the aforementioned circuit structure S02), at least 2^n-2 third-class circuit structures (i.e., the aforementioned circuit structure S03), and at least 2^n-1 fourth-class circuit structures (i.e., the aforementioned new circuit structure S04, such as the XOR gate circuit shown in FIG9 or the XNOR gate circuit shown in FIG10). The following description will be made using an XOR gate circuit to implement the adder as an example. In the adder:

[0085] The circuit structure includes an AND gate and an XOR gate (or XNOR gate). It can be configured to receive the i-th bit of the first data and the i-th bit of the second data, 0≥i≥2^n, and output the carry of the i-th bit to generate a G logic result (G i ) and carry propagate P logical result (P i );

[0086] The second type of circuit structure includes an AND gate and an AND-OR gate. It can be configured to receive a G logic result and a P logic result, and output a G logic result sub-combination (G i:j ) and P logical result subcombination (P i:j );

[0087] The three types of circuit structures include an AND-OR gate. It can be configured to receive a G logic result and a P logic result or a G logic result sub-combination and a P logic result sub-combination, and output a new G logic result sub-combination (G i:0 );

[0088] The four types of circuit structures include an XOR gate as shown in Figure 9 (or an XNOR gate as shown in Figure 10), which is configured to receive a P logic result and a G logic result or a P logic result and a new G logic result sub-combination, and the output logic result is the sum value S.

[0089] In another embodiment, the adder can be implemented using any logic gate circuit shown in Figures 12 to 15, and the adder includes at least 2^n logic gate circuits shown in any logic gate circuit shown in Figures 12 to 15 to implement addition operations on 2^n bits of data.

[0090] The adder circuit structure provided in the embodiment of the present disclosure utilizes the above four circuit structures to construct an adder. Through reasonable design, the number of circuit structures used can be reduced, the power consumption of the adder can be reduced, and the area occupied by the overall topology structure can be reduced.

[0091] The reasonable design includes any one or more of the following:

[0092] ●The adder circuit structure includes at least 2^n vertical paths, and the vertical path is used to receive the i-th bit of the first data and the second data, and output the sum value of the i+1th bit. For example, the first vertical path receives the 0th bit of data and outputs the sum value of the 1st bit. The vertical path that receives the k-th bit of the first data and the second data includes a first-class circuit structure, a third-class circuit structure and a fourth-class circuit structure, k is an even number other than 0 in i, and the first-class circuit structure is used to receive the k-th bit of the first data and the second data. The output end of the first-class circuit structure is connected to the input end of the third-class circuit structure, and the input end of the third-class circuit structure is also connected to the output end of the first-class circuit structure in the previous vertical path for receiving the k-1-th bit of the first data and the second data. The output end of the third-class circuit structure is connected to the input end of the fourth-class circuit structure, and the input end of the fourth-class circuit structure is also connected to the output end of the first-class circuit structure in the next vertical path for receiving the k+1-th bit of the first data and the k+1-th bit of the second data. The fourth-class circuit structure outputs the sum value of the k+1th bit.

[0093] This design reduces the number of circuit structures by simplifying the circuit structure in the even-bit vertical path (requiring only one type 1 circuit, one type 3 circuit, and one type 4 circuit), lowers the power consumption of the adder, and reduces the area occupied by the overall topology.

[0094] The odd-numbered bit vertical path may adopt the following structure: the vertical path receiving the k+1th bit of the first data and the second data in the adder circuit structure includes one type I circuit structure, at least one type II circuit structure, one type III circuit structure, and one type IV circuit structure, where k is an even number other than 0 in i;

[0095] The first type of circuit structure is used to receive the kth bit of the first data and the second data. The output end of the first type of circuit structure is connected to the input end of the first type of circuit structure. The input end of the first type of circuit structure is also connected to the output end of the first type of circuit structure in the previous vertical path for receiving the kth bit of the first data and the second data. The output end of the last type of circuit structure is connected to the input end of the third type of circuit structure. The input end of the third type of circuit structure is also connected to the output end of the third type of circuit structure in the previous even-numbered vertical path. The output end of the third type of circuit structure is connected to the input end of the fourth type of circuit structure. The input end of the fourth type of circuit structure is also connected to the output end of the first type of circuit structure in the next vertical path for receiving the k+2th bit of the first data and the second data. The fourth type of circuit structure outputs the sum value of the k+2th bit.

[0096] With this design, the number of circuit structures is reduced by simplifying the circuit structure in the odd-bit vertical path, the power consumption of the adder is reduced, and the area occupied by the overall topology structure is reduced.

[0097] ● In the adder circuit structure, the output from a i 、b i to S i The path can be considered another vertical path, hereinafter referred to as a vertical path. The vertical paths include at least 2^n paths, and are used to receive the i-th bit of the first data and the second data and output the sum of the i-th bit. For example, the first vertical path receives the 0th bit of data and outputs the sum of the 0th bit. The starting circuit structure of the vertical path is an XOR gate, and the ending circuit structure is an XOR gate, or the starting circuit structure of the vertical path is an XOR gate and the ending circuit structure is an XOR gate, or the starting circuit structure of the vertical path is an XOR gate and the ending circuit structure is an XOR gate, or the starting circuit structure of the vertical path is an XOR gate and the ending circuit structure is an XOR gate, or the starting circuit structure of the vertical path is an XOR gate and the ending circuit structure is an XOR gate. See the examples of logic gate circuit structures shown in Figures 12 to 15.

[0098] By adopting this design, the number of transistors in the circuit structure can be reduced, the power consumption of the adder can be reduced, and the area occupied by the overall topology structure can be reduced.

[0099] In the adder circuit structure, two or more of the second-type circuit structures reuse the calculation result of one second-type circuit structure, or two or more of the third-type circuit structures reuse the calculation result of one third-type circuit structure.

[0100] With this design, the number of circuit structures can be reduced by reusing the calculation results of the circuit structures, the power consumption of the adders can be reduced, and the area occupied by the overall topology can be reduced.

[0101] The following describes how multiple circuit structures can reuse the calculation results of the same circuit structure.

[0102] As described above, the adder circuit structure includes 2^n input terminals for inputting 2^n bits and at least 2^n output terminals, the path from the i-th input terminal to the (i+1)-th output terminal is a vertical path, and each path (or path) from the input terminal to the output terminal is provided with one or more of the aforementioned type 1 circuit structure, type 2 circuit structure, type 3 circuit structure, and type 4 circuit structure;

[0103] In an exemplary embodiment, within each of eight adjacent vertical paths, the fourth circuit structure in the eighth vertical path and the third circuit structure in the sixth vertical path reuse the calculation results of the third circuit structure in the fourth vertical path. For example, each of the eight adjacent vertical paths may be: path 0 to path 7, path 8 to path 15, path 16 to path 23, path 24 to path 31, path 32 to path 39, path 40 to path 47, path 48 to path 55, path 56 to path 63, and so on. The fourth circuit structure in the eighth vertical path refers to the circuit result ranked fourth in the eighth vertical path, meaning there are three circuit structures preceding it. The fourth circuit structure may be referred to as a fourth-level circuit structure, representing the number of logic levels in that vertical path. The number of circuit structures, i.e., the total number of logic levels, in the longest path from the input to the output of the adder circuit structure is the logical depth of the adder circuit structure. Among them, the fourth circuit structure in the eighth longitudinal path, the third circuit structure in the sixth longitudinal path, and the third circuit structure in the fourth longitudinal path are all type II circuit structures or type III circuit structures.

[0104] In an exemplary embodiment, in every 16 adjacent vertical paths, the fifth circuit structure in the 16th vertical path, the fourth circuit structure in the 14th vertical path, the fourth circuit structure in the 12th vertical path, and the third circuit structure in the 10th vertical path reuse the calculation results of the fourth circuit structure in the 8th vertical path. For example, the 16 adjacent vertical paths are: paths 0 to 15, paths 16 to 31, paths 32 to 47, paths 48 to 63, and so on. The fifth circuit structure in the 16th vertical path, the fourth circuit structure in the 14th vertical path, the fourth circuit structure in the 12th vertical path, the third circuit structure in the 10th vertical path, and the fourth circuit structure in the 8th vertical path are all third-category circuit structures.

[0105] In an exemplary embodiment, in every 32 adjacent vertical paths, the sixth circuit structure in the 32nd vertical path, the fifth circuit structure in the 30th vertical path, the fifth circuit structure in the 28th vertical path, the fourth circuit structure in the 26th vertical path, the fifth circuit structure in the 24th vertical path, the fourth circuit structure in the 22nd vertical path, the fourth circuit structure in the 20th vertical path, and the third circuit structure in the 18th vertical path reuse the calculation result of the fifth circuit structure in the 16th vertical path. For example, the 32 adjacent vertical paths include: paths 0 to 31, paths 32 to 63, and so on. Among them, the sixth circuit structure in the thirty-second longitudinal pathway, the fifth circuit structure in the thirtieth longitudinal pathway, the fifth circuit structure in the twenty-eighth longitudinal pathway, the fourth circuit structure in the twenty-sixth longitudinal pathway, the fifth circuit structure in the twenty-fourth longitudinal pathway, the fourth circuit structure in the twenty-second longitudinal pathway, the fourth circuit structure in the twentieth longitudinal pathway, the third circuit structure in the eighteenth longitudinal pathway, and the fifth circuit structure in the sixteenth longitudinal pathway are all three types of circuit structures.

[0106] The following takes n=4 and n=5 as examples to illustrate the connection relationship of the circuit structure for implementing multiplexing in the odd-numbered bit vertical path.

[0107] In an exemplary embodiment, when n=4, the odd-numbered bit vertical path may adopt the following structure: the vertical path receiving the k+1th bit of the first data and the second data in the adder circuit structure includes one type I circuit structure, one, two, or three type II circuit structures, one type III circuit structure, and one type IV circuit structure, where k is an even number other than 0 in i;

[0108] The first type of circuit structure is used to receive the k-th bit of data in the first data and the second data, and the output end of the first type of circuit structure is connected to the input end of the first and second type of circuit structures;

[0109] The input end of the first-two-category circuit structure is also connected to the output end of the first-category circuit structure in the previous vertical path for receiving the k-th bit of the first data and the second data, and the output end of the first-two-category circuit structure (for example, the first-two-category circuit structure in the vertical path for receiving the 3rd bit of data, the 5th bit of data, and the 9th bit of data) is connected to the input end of the one of the three-category circuit structures; or the output end of the first-two-category circuit structure (for example, the first-two-category circuit structure in the vertical path for receiving the 7th bit of data, the 11th bit of data, and the 13th bit of data) is connected to the input end of the second-two-category circuit structure, and the input end of the second-two-category circuit structure is also connected to the output end of the first-two-category circuit structure in the first two vertical paths, and the output end of the second-two-category circuit structure is connected to the input end of the one of the three-category circuit structures; or the first-two-category circuit structure (for example, the first-two-category circuit structure in the vertical path for receiving the 15th bit of data) is connected to the input end of the second-two-category circuit structure. The output end of the second-class circuit structure is connected to the input end of the second-class circuit structure, the input end of the second-class circuit structure is also connected to the output end of the second-class circuit structure in the first two longitudinal paths, the output end of the second-class circuit structure is connected to the input end of the third-class circuit structure, the input end of the third-class circuit structure is also connected to the output end of the last second-class circuit structure (the second-class circuit structure) in the first four longitudinal paths, and the output end of the third-class circuit structure is connected to the input end of the one third-class circuit structure; the first second-class circuit structure in each longitudinal path is the first-class circuit structure, the second second-class circuit structure in each longitudinal path is the second-class circuit structure, the third second-class circuit structure in each longitudinal path is the third-class circuit structure, and so on; the above-mentioned 3rd, 5th, 7th, 9th, 11th, 13th, 15th, etc. all refer to bits starting from 0. Unless otherwise specified below, the i-th bit refers to the number of bits starting from 0;

[0110] The input end of the three-type circuit structure is also connected to the output end of the three-type circuit structure in the first even-numbered longitudinal paths, and the output end of the three-type circuit structure is connected to the input end of the four-type circuit structure;

[0111] The input ends of the four types of circuit structures are also connected to the output ends of a type of circuit structure in the next vertical path for receiving the k+2th bit of the first data and the second data, and the four types of circuit structures output the sum value of the k+2th bit.

[0112] In the above structure, the circuit structure calculation results can be reused in the following ways:

[0113] Reuse of the results of the second type of circuit structure:

[0114] The second-second type circuit structure in the fourteenth vertical path in the adder circuit structure that receives the 13th bit data and the third-second type circuit structure in the sixteenth vertical path in the adder circuit structure that receives the 15th bit data multiplex the calculation results of the second-second type circuit structure in the twelfth vertical path in the adder circuit structure that receives the 11th bit data.

[0115] Reuse of three types of circuit structure results:

[0116] The three types of circuit structures in the sixth vertical path of the adder circuit structure receiving the fifth-bit data and the three types of circuit structures in the eighth vertical path of the adder circuit structure receiving the seventh-bit data multiplex the calculation results of the three types of circuit structures in the fourth vertical path of the adder circuit structure receiving the third-bit data;

[0117] The three types of circuit structures in the tenth vertical path of the adder circuit structure that receives the 9th bit data, the three types of circuit structures in the twelfth vertical path that receives the 11th bit data, and the three types of circuit structures in the fourteenth vertical path that receives the 13th bit data, multiplex the calculation results of the three types of circuit structures in the eighth vertical path of the adder circuit structure that receives the 7th bit data.

[0118] When the output includes a carry result, the three types of circuit structures in the tenth vertical path of the adder circuit structure that receives the 9th bit data, the three types of circuit structures in the twelfth vertical path that receives the 11th bit data, the three types of circuit structures in the fourteenth vertical path that receives the 13th bit data, and the three types of circuit structures in the sixteenth vertical path that receives the 15th bit data multiplex the calculation results of the three types of circuit structures in the eighth vertical path of the adder circuit structure that receives the 7th bit data.

[0119] In an exemplary embodiment, when n=5, the odd-numbered bit vertical path may adopt the following structure: the vertical path receiving the k+1-th bit data in the first data and the second data in the adder circuit structure includes one type I circuit structure, one or two or three or four type II circuit structures, one type III circuit structure and one type IV circuit structure, where k is an even number other than 0 in i;

[0120] The first type of circuit structure is used to receive the k-th bit of data in the first data and the second data, and the output end of the first type of circuit structure is connected to the input end of the first and second type of circuit structures;

[0121] The input end of the first-class-two circuit structure is also connected to the output end of the first-class-two circuit structure in the previous vertical path for receiving the k-th bit of the first data and the second data, the output end of the first-class-two circuit structure (for example, the first-class-two circuit structure in the vertical path for receiving the 3rd bit of data, the 5th bit of data, the 9th bit of data, and the 17th bit of data starting from 0) is connected to the input end of the one of the three-class circuit structures, or the output end of the first-class-two circuit structure (for example, the first-class-two circuit structure in the vertical path for receiving the 7th bit of data, the 11th bit of data, the 13th bit of data, the 19th bit of data, the 21st bit of data, and the 25th bit of data) is connected to the input end of the second-class-two circuit structure, the input end of the second-class-two circuit structure is also connected to the output end of the first-class-two circuit structure in the second vertical path, and the output end of the second-class-two circuit structure is connected to the input end of the second-class-two circuit structure. The input end of the one of the three-type circuit structures is connected, or the output end of the first-type-two circuit structure (for example, the first-type-two circuit structure in the vertical path that receives the 15th-bit data, the 23rd-bit data, the 27th-bit data, and the 29th-bit data) is connected to the input end of the second-type-two circuit structure, the input end of the second-type-two circuit structure is further connected to the output end of the second-type-two circuit structure in the first two vertical paths, the output end of the second-type-two circuit structure is connected to the input end of the third-type-two circuit structure, the input end of the third-type-two circuit structure is further connected to the output end of the last-type-two circuit structure in the first fourth vertical path or the first sixth vertical path, the output end of the third-type-two circuit structure is connected to the input end of the one of the three-type circuit structures; or the first-type-two circuit structure (for example, the first-type-two circuit structure in the vertical path that receives the 31st-bit data) the output end of the second-class-II circuit structure is connected to the input end of the second-class-II circuit structure, the input end of the second-class-II circuit structure is further connected to the output end of the second-class-II circuit structure in the first two longitudinal paths, the output end of the second-class-II circuit structure is connected to the input end of the third-class-II circuit structure, the input end of the third-class-II circuit structure is further connected to the output end of the second-class-II circuit structure in the first fourth longitudinal path, the output end of the third-class-II circuit structure is connected to the input end of the fourth-class-II circuit structure, the input end of the fourth-class-II circuit structure is further connected to the output end of the last-class-II circuit structure (the third-class-II circuit structure) in the first eighth longitudinal path, and the output end of the fourth-class-II circuit structure is connected to the input end of the one third-class circuit structure;

[0122] The input end of the three-type circuit structure is also connected to the output end of the three-type circuit structure in the first even-numbered longitudinal path, and the output end of the three-type circuit structure is connected to the input end of the four-type circuit structure;

[0123] The input ends of the four types of circuit structures are also connected to the output ends of a type of circuit structure in the next vertical path for receiving the k+2th bit of the first data and the second data, and the four types of circuit structures output the sum value of the k+2th bit.

[0124] In the above structure, the circuit structure calculation results can be reused in the following ways:

[0125] Reuse of the results of the second type of circuit structure:

[0126] The second-second type circuit structure in the fourteenth vertical path of the adder circuit structure receiving the 13th bit of data and the third-second type circuit structure in the sixteenth vertical path of the adder circuit structure receiving the 15th bit of data multiplex the calculation result of the second-second type circuit structure in the twelfth vertical path of the adder circuit structure receiving the 11th bit of data;

[0127] The second-second type circuit structure in the twenty-second vertical path in the adder circuit structure that receives the 21st bit data and the third-second type circuit structure in the twenty-fourth vertical path in the adder circuit structure that receives the 23rd bit data multiplex the calculation results of the second-second type circuit structure in the twentieth vertical path in the adder circuit structure that receives the 19th bit data.

[0128] When the output includes a carry result, in addition to the above-mentioned structural multiplexing, the following structural multiplexing is also adopted: the second-class circuit structure in the 30th vertical path receiving the 29th bit data in the adder circuit structure and the third-class circuit structure in the 32nd vertical path receiving the 31st bit data in the adder circuit structure are multiplexed, and the calculation result of the second-class circuit structure in the 28th vertical path receiving the 27th bit data in the adder circuit structure is multiplexed.

[0129] Reuse of three types of circuit structure results:

[0130] The three types of circuit structures in the sixth vertical path of the adder circuit structure receiving the fifth-bit data and the three types of circuit structures in the eighth vertical path of the adder circuit structure receiving the seventh-bit data multiplex the calculation results of the three types of circuit structures in the fourth vertical path of the adder circuit structure receiving the third-bit data;

[0131] The three types of circuit structures in the tenth vertical path of the adder circuit structure receiving the 9th bit of data, the three types of circuit structures in the twelfth vertical path receiving the 11th bit of data, the three types of circuit structures in the fourteenth vertical path receiving the 13th bit of data, and the three types of circuit structures in the sixteenth vertical path receiving the 15th bit of data, and the calculation results of the three types of circuit structures in the eighth vertical path of the adder circuit structure receiving the 7th bit of data are multiplexed;

[0132] The three types of circuit structures in the eighteenth vertical path receiving the 17th-bit data in the adder circuit structure, the three types of circuit structures in the 20th vertical path receiving the 19th-bit data, the three types of circuit structures in the 22nd vertical path receiving the 21st-bit data, the three types of circuit structures in the 24th vertical path receiving the 23rd-bit data, the three types of circuit structures in the 26th vertical path receiving the 25th-bit data, the three types of circuit structures in the 28th vertical path receiving the 27th-bit data, and the three types of circuit structures in the 30th vertical path receiving the 29th-bit data, reuse the calculation results of the three types of circuit structures in the sixteenth vertical path receiving the 15th-bit data in the adder circuit structure.

[0133] When the output includes a carry result, in addition to the above-mentioned structural multiplexing, the following structural multiplexing is also adopted: the three types of circuit structures in the eighteenth vertical path receiving the 17th-bit data in the adder circuit structure, the three types of circuit structures in the 20th vertical path receiving the 19th-bit data, the three types of circuit structures in the 22nd vertical path receiving the 21st-bit data, the three types of circuit structures in the 24th vertical path receiving the 23rd-bit data, the three types of circuit structures in the 26th vertical path receiving the 25th-bit data, the three types of circuit structures in the 28th vertical path receiving the 27th-bit data, the three types of circuit structures in the 30th vertical path receiving the 29th-bit data, and the three types of circuit structures in the 32nd vertical path receiving the 31st-bit data, and the calculation results of the three types of circuit structures in the sixteenth vertical path receiving the 15th-bit data in the adder circuit structure are multiplexed.

[0134] The above examples illustrate the connection of even-numbered vertical paths and odd-numbered vertical paths of 3 or more. The following describes the vertical path for receiving the 0th bit data and the vertical path for receiving the 1st bit data.

[0135] In an exemplary embodiment, the first vertical path in the adder circuit structure is used to receive the i-th bit of the first data and the second data, i=0, and output the sum of the i-th bit and the i+1-th bit. The first vertical path includes a first-class circuit structure and a fourth-class circuit structure. The first-class circuit structure is used to receive the 0th bit of the first data and the second data, and output the G logic result and the P logic result of the 0th bit. The output end of the first-class circuit structure is connected to the input end of the fourth-class circuit structure. The input end of the fourth-class circuit structure is also connected to the output end of the first-class circuit structure in the latter vertical path for receiving the 1st bit of the first data and the second data. The fourth-class circuit structure outputs the sum of the 1st bit, and the P logic result of the 0th bit output by the first-class circuit structure is the sum of the 0th bit.

[0136] In an exemplary embodiment, the second vertical path in the adder circuit structure is used to receive the i-th bit of the first data and the second data, i=1, and output the sum of the i-th bit and the i+1-th bit. The first vertical path includes a first-class circuit structure, a third-class circuit structure, and a fourth-class circuit structure. The first-class circuit structure is used to receive the first-bit data of the first data and the second data. The output end of the first-class circuit structure is connected to the input end of the third-class circuit structure. The input end of the third-class circuit structure is also connected to the output end of the first-class circuit structure in the previous vertical path for receiving the 0th bit data of the first data and the second data. The output end of the third-class circuit structure is connected to the input end of the fourth-class circuit structure. The input end of the fourth-class circuit structure is also connected to the output end of the first-class circuit structure in the next vertical path for receiving the second-bit data of the first data and the second data. The fourth-class circuit structure outputs the sum of the second bit.

[0137] In an exemplary embodiment, the 2^nth vertical path is used as a path for calculating a carry value, and the path includes a first-class circuit structure, at least two second-class circuit structures, a third-class circuit structure, and a fourth-class circuit structure, wherein:

[0138] The first type of circuit structure is used to receive the 2^n-1th bit of the first data and the second data, and the output end of the first type of circuit structure is connected to the input end of the second type of circuit structure.

[0139] The at least two Class-II circuit structures are connected in sequence, wherein the input end of the first Class-II circuit structure is connected to the output end of the Class-II circuit structure in addition to being connected to the output end of the Class-I circuit structure, and is also connected to the output end of the Class-I circuit structure in the previous longitudinal path for receiving the 2^n-2th bit of the first data and the second data; the output end of the first Class-II circuit structure is connected to the input end of the one Class-III circuit structure, or is connected to the input end of the second Class-II circuit structure; the input end of the second Class-II circuit structure is also connected to the output end of the first Class-II circuit structure in the second previous longitudinal path; the output end of the second Class-II circuit structure is connected to the input end of the one Class-III circuit structure, or is connected to the input end of the third Class-II circuit structure; the input end of the third Class-II circuit structure is also connected to the output end of the second Class-II circuit structure in the fourth previous longitudinal path, or the input end of the third Class-II circuit structure is also connected to the output end of the third Class-II circuit structure in the eighth previous longitudinal path; the output end of the third Class-II circuit structure is connected to the input end of the one Class-III circuit structure;

[0140] The input end of the one three-type circuit structure is further connected to the output end of the three-type circuit structure in the front fourth vertical path, or the input end of the one three-type circuit structure is further connected to the output end of the three-type circuit structure in the front eighth vertical path, or the input end of the one three-type circuit structure is further connected to the output end of the three-type circuit structure in the front sixteenth vertical path, and the output end of the one three-type circuit structure is connected to the input end of the four-type circuit structure;

[0141] The input ends of the four types of circuit structures are also connected to the output ends of a type of circuit structure in the next vertical path for receiving the 2^n+1th bit data in the first data and the second data, and the four types of circuit structures output carry values.

[0142] In an exemplary embodiment, the adder circuit structure includes a data path for summing the values, and the data path for summing the values ​​includes one or more of the following data paths:

[0143] The first data path includes: a first type of circuit structure and a fourth type of circuit structure;

[0144] The second data path includes: a first-class circuit structure, a third-class circuit structure, and a fourth-class circuit structure;

[0145] The third data path includes: a first type circuit structure, a second type circuit structure, a third type circuit structure and a fourth type circuit structure.

[0146] In an exemplary embodiment, the adder circuit structure may further include a data path (fourth data path) for calculating a carry value, and the fourth data path includes: a first-type circuit structure, a second-type circuit structure, and a third-type circuit structure.

[0147] The adder can be used to implement an addition operation with or without a carry on 2^n bit input data, where n is a positive integer greater than or equal to 3.

[0148] When the data length of the first data and the second data is 2^n bits, and n=3, the adder includes 2^n=8 inputs and 2^n=8 summation outputs. The adder includes 2^n=8 first-class circuit structures, (2^(n-2)-1)*2=2 second-class circuit structures, (2^n)-2=6 third-class circuit structures, and (2^n)-1=7 fourth-class circuit structures, for a total of 8+2+6+7=23 circuit structures, with a maximum logic depth of 6 levels. The maximum logic depth can be understood as the maximum number of circuit structures passed through on the path from input to output. Alternatively, the adder includes 2^n=8 inputs, 2^n=8 summation outputs, and 1 carry output. The adder includes 2^n=8 first-class circuit structures, (2^(n-2)-1)*2+2=4 second-class circuit structures, (2^n)-1=7 third-class circuit structures, and (2^n)-1=7 fourth-class circuit structures, for a total of 8+4+7+7=26 circuit structures, which is 3 more circuit structures than an 8-bit adder excluding carry, and the maximum logic depth is still 6 levels.

[0149] When the data length of the first data and the second data is 2^n bits, and n=4, the adder includes 2^n=16 inputs and 2^n=16 summation outputs, and the adder includes 2^n=16 first-class circuit structures, (2^(n-2)-1)*3=9 second-class circuit structures, (2^n)-2=14 third-class circuit structures, and (2^n)-1=15 fourth-class circuit structures, for a total of 16+9+14+15=54 circuit structures, with a maximum logic depth of 7 levels; or The adder includes 2^n=16 inputs, 2^n=16 summation outputs and 1 carry output. The adder includes 2^n=16 first-class circuit structures, (2^(n-2)-1)*3+3=12 second-class circuit structures, (2^n)-1=15 third-class circuit structures and (2^n)-1=15 fourth-class circuit structures, totaling 16+12+15+15=58 circuit structures, which is 4 more circuit structures than a 16-bit adder without carry, and the maximum logic depth is still 7 levels.

[0150] When the data length of the first data and the second data is 2^n bits, and n=5, the adder includes 2^n=32 inputs and 2^n=32 summation outputs, the adder includes 2^n=32 first-class circuit structures, (2^(n-1)-1)+(2^(n-2)-1)*3-2^(n-2)=28 second-class circuit structures, (2^n)-2=30 third-class circuit structures, and (2^n)-1=31 fourth-class circuit structures, totaling 32+28+30+31=121 circuit structures, and a maximum logic depth of 8 levels; or The adder includes 2^n=32 inputs, 2^n=32 summation outputs and 1 carry output. The adder includes 2^n=32 first-class circuit structures, (2^(n-1)-1)+(2^(n-2)-1)*3-2^(n-2)+4=32 second-class circuit structures, (2^n)-1=31 third-class circuit structures and (2^n)-1=31 fourth-class circuit structures, totaling 32+32+31+31=126 circuit structures, which is 5 more circuit structures than a 32-bit adder without carry, and the maximum logic depth is still 8 levels.

[0151] When the data length of the first data and the second data is 2^n bits, and n=6, the adder includes 2^n=64 inputs and 2^n=64 summation outputs, the adder includes (2^n)=64 first-class circuit structures, (2^(n-1)-1)+(2^(n-2)-1)*3-2^(n-3)=68 second-class circuit structures, (2^n)-2=62 third-class circuit structures, and (2^n)-1=63 fourth-class circuit structures, totaling 64+68+62+63=257 circuit structures, and the maximum logic depth is 10 levels; or The adder includes 2^n=64 inputs, 2^n=64 summation outputs and 1 carry output. The adder includes 2^n=64 first-class circuit structures, (2^(n-1)-1)+(2^(n-2)-1)*3-2^(n-3)+4=72 second-class circuit structures, (2^n)-1=63 third-class circuit structures and (2^n)-1=63 fourth-class circuit structures, totaling 64+72+63+63=262 circuit structures, which is 5 more circuit structures than a 64-bit adder without carry, and the maximum logic depth is still 10 levels.

[0152] The adder circuit structures provided by the disclosed embodiments all have low maximum logic depths. The lower the maximum logic depth, the shorter the computation path and the faster the computation speed. This shows that the disclosed embodiments not only achieve low power consumption but also ensure high adder computation speeds, achieving a good balance between operating speed and power consumption.

[0153] The following example illustrates the topology of a 32-bit unsigned integer adder with carry built using the above four circuit structures. The expression of the adder is: {carry,sum[31:0]}=a[31:0]+b[31:0], where carry represents carry and sum represents sum. As shown in Figure 15, the adder includes 32 inputs and 33 outputs (only 32 outputs are required if the adder does not include the carry). In the figure, 0-31 represent inputs 0-31 (0-31 bits), and each input includes a and b. For example, input 0 represents a0 and b0, input 1 represents a1 and b1, and so on. S0-S 31 They represent 32 summation outputs, in addition to a carry output. In the figure, the path from input 0 to output S1 is the first vertical path, referred to as the first path. The path from input 1 to output S2 is the second vertical path, referred to as the second path. For ease of illustration, subscripts are not used in the figure. For clarity, the adder circuit structure and connection relationships are described below in units of paths. Unless otherwise specified, all paths refer to vertical paths.

[0154] The first path (path 0 in the figure) can be used to obtain the sum values ​​S0 and S1. The first path includes a circuit structure S01 (hereinafter referred to as S01-1, represented by 1-1 in the figure, and the number after "-" represents the sequence number) and a circuit structure S04 (hereinafter referred to as S04-1, represented by 4-1 in the figure) connected to the circuit structure S01-1. The circuit structure S01-1 is used to calculate G0 and P0, and the circuit structure S04-1 is used to calculate S1. Among them, the input of the circuit structure S01-1 is a0 and b0, and the output is G0 and P0. The expression of the circuit structure S01-1 is: G0 = a0·b0, The output P0 of circuit structure S01-1 is S0. The expression of circuit structure S04-1 is: S1 = P1·G0. Circuit structure S04-1 is connected to circuit structure S01-1 to obtain G0. Circuit structure S04-1 is also connected to the next circuit structure (second circuit) S01-2 to obtain P1. The output of circuit structure S04-1 is S1.

[0155] The second path (path 1 in the figure) can be used to obtain the sum S2. The second path includes a circuit structure S01 (hereinafter referred to as S01-2, represented by 1-2 in the figure), a circuit structure S03 (hereinafter referred to as S03-1, represented by 3-1 in the figure), and a circuit structure S04 (hereinafter referred to as S04-2, represented by 4-2 in the figure) connected in sequence. The circuit structure S01-2 is used to calculate G1 and P1, and the circuit structure S03-1 is used to calculate G 1:0, the circuit structure S04-2 is used to calculate S2. Wherein, the expression of the circuit structure S01-2 is: G1=a1·b1, The inputs of circuit structure S01-2 are a1 and b1, and the outputs are G1 and P1. The expression of circuit structure S03-1 is: G 1:0 =(P1·G0)|G1, the circuit structure S03-1 is connected to the circuit structure S01-2 to obtain G1 and P1, and the circuit structure S03-1 is also connected to the first circuit structure S01-1 to obtain G0. The output of the circuit structure S03-1 is G 1:0 The expression of circuit structure S04-2 is: S2=P2·G 1:0 , the circuit structure S04-2 is connected to the circuit structure S03-1 to obtain G 1:0 The circuit structure S04-2 is also connected to the circuit structure S01-3 of the next path (the third path) to obtain P2. The output of the circuit structure S04-2 is S2.

[0156] The third path (path 2 in the figure) can be used to obtain the sum S3. The third path includes a circuit structure S01 (hereinafter referred to as S01-3, represented by 1-3 in the figure), a circuit structure S03 (hereinafter referred to as S03-2, represented by 3-2 in the figure), and a circuit structure S04 (hereinafter referred to as S04-3, represented by 4-3 in the figure) connected in sequence. The circuit structure S01-3 is used to calculate G2 and P2, and the circuit structure S03-2 is used to calculate G 2:0 , the circuit structure S04-3 is used to calculate S3. Wherein, the expression of the circuit structure S01-3 is: G2=a2·b2, The inputs of circuit structure S01-3 are a2 and b2, and the outputs are G2 and P2. The expression of circuit structure S03-2 is: G 2:0 =(P2·G 1:0 )|G2, the circuit structure S03-2 is connected to the circuit structure S01-3 to obtain G2, P2, and the circuit structure S03-2 is also connected to the second circuit structure S03-1 to obtain G 1:0 , the output of circuit structure S03-2 is G 2:0 The expression of circuit structure S04-3 is: S3=P3·G 2:0 , the circuit structure S04-3 is connected to the circuit structure S03-2 to obtain G 2:0 The circuit structure S04-2 is also connected to the circuit structure S01-4 of the next path (the fourth path) to obtain P3. The output of the circuit structure S04-3 is S3.

[0157] The fourth path (path 3 in the figure) can be used to obtain the sum S4. The fourth path includes a circuit structure S01 (hereinafter referred to as S01-4, represented by 1-4 in the figure), a circuit structure S02 (hereinafter referred to as S02-1, represented by 2-1 in the figure), a circuit structure S03 (hereinafter referred to as S03-3, represented by 3-3 in the figure), and a circuit structure S04 (hereinafter referred to as S04-4, represented by 4-4 in the figure) connected in sequence. Circuit structure S01-4 is used to calculate G3 and P3, and circuit structure S02-1 is used to calculate P 3:2 and G 3:2 , circuit structure S03-3 is used to calculate G 3:0 , the circuit structure S04-4 is used to calculate S4. Wherein, the expression of the circuit structure S01-4 is: G3=a3·b3, The inputs of circuit structure S01-4 are a3 and b3, and the outputs are G3 and P3. The expression of circuit structure S02-1 is: P 3:2 =P3·P2,G 3:2 =(P3·G2)|G3, the circuit structure S02-1 is connected to the circuit structure S01-4 to obtain G3 and P3, and the circuit structure S02-1 is also connected to the third circuit structure S01-3 to obtain G2 and P2. The output of the circuit structure S02-1 is P 3:2 and G 3:2 The expression of circuit structure S03-3 is: G 3:0 =(P 3:2 ·G 1:0 )|G 3:2 , the circuit structure S03-3 is connected to the circuit structure S02-1 to obtain P 3:2 and G 3:2 The circuit structure S03-3 is also connected to the second circuit structure S03-1 to obtain P 3:2 and G 3:2 , the output of circuit structure S03-3 is G 3:0 The expression of circuit structure S04-4 is: S4=P4·G 3:0 , the circuit structure S04-4 is connected to the circuit structure S03-3 to obtain G 3:0 The circuit structure S04-4 is also connected to the circuit structure S01-5 of the next path (the fifth path) to obtain P4. The output of the circuit structure S04-4 is S4.

[0158] The fifth path (4th path in the figure) can be used to obtain the sum S5. The fifth path includes a circuit structure S01 (hereinafter referred to as S01-5, represented by 1-5 in the figure), a circuit structure S03 (hereinafter referred to as S03-4, represented by 3-4 in the figure), and a circuit structure S04 (hereinafter referred to as S04-5, represented by 4-5 in the figure) connected in sequence. The circuit structure S01-5 is used to calculate G4 and P4, and the circuit structure S03-4 is used to calculate G 4:0 , the circuit structure S04-5 is used to calculate S5. Wherein, the expression of the circuit structure S01-5 is: G4=a4·b4, The inputs of circuit structure S01-5 are a4 and b4, and the outputs are G4 and P4. The expression of circuit structure S03-4 is: G 4:0 =(P4·G 3:0 )|G4, the circuit structure S03-4 is connected to the circuit structure S01-5 to obtain G4 and P4, and the circuit structure S03-4 is also connected to the fourth circuit structure S03-3 to obtain G 3:0 , the output of circuit structure S03-4 is G 4:0 The expression of circuit structure S04-5 is: S5=P5·G 4:0 , the circuit structure S04-5 is connected to the circuit structure S03-4 to obtain G 4:0 The circuit structure S04-5 is also connected to the circuit structure S01-6 of the next path (the sixth path) to obtain P5. The output of the circuit structure S04-5 is S5.

[0159] The sixth path (path 5 in the figure) can be used to obtain the sum S6. The sixth path includes a circuit structure S01 (hereinafter referred to as S01-6, represented by 1-6 in the figure), a circuit structure S02 (hereinafter referred to as S02-2, represented by 2-2 in the figure), a circuit structure S03 (hereinafter referred to as S03-5, represented by 3-5 in the figure), and a circuit structure S04 (hereinafter referred to as S04-6, represented by 4-6 in the figure) connected in sequence. Circuit structure S01-6 is used to calculate G5 and P5, and circuit structure S02-2 is used to calculate P 5:4 and G 5:4 , circuit structure S03-5 is used to calculate G 5:0 , the circuit structure S04-6 is used to calculate S6. Wherein, the expression of the circuit structure S01-6 is: G5=a5·b5, The inputs of circuit structure S01-6 are a5 and b5, and the outputs are G5 and P5. The expression of circuit structure S02-2 is: P 5:4 =P5·P4,G 5:4=(P5·G4)|G5, the circuit structure S02-2 is connected to the circuit structure S01-6 to obtain G5 and P5, and the circuit structure S02-2 is also connected to the fifth circuit structure S01-5 to obtain G4 and P4. The output of the circuit structure S02-2 is P 5:4 and G 5:4 The expression of circuit structure S03-5 is: G 5:0 =(P 5:4 ·G 3:0 )|G 5:4 , the circuit structure S03-5 is connected to the circuit structure S02-2 to obtain P 5:4 and G 5:4 The circuit structure S03-5 is also connected to the fourth circuit structure S03-3 to obtain G 3:0 , the output of circuit structure S03-5 is G 5:0 The expression of circuit structure S04-6 is: S6=P6·G 5:0 , the circuit structure S04-6 is connected to the circuit structure S03-5 to obtain G 5:0 The circuit structure S04-6 is also connected to the circuit structure S01-7 of the next path (the seventh path) to obtain P6. The output of the circuit structure S04-6 is S6.

[0160] The seventh path (path 6 in the figure) can be used to obtain the sum S7. The seventh path includes a circuit structure S01 (hereinafter referred to as S01-7, represented by 1-7 in the figure), a circuit structure S03 (hereinafter referred to as S03-6, represented by 3-6 in the figure), and a circuit structure S04 (hereinafter referred to as S4-7, represented by 4-7 in the figure) connected in sequence. The circuit structure S01-7 is used to calculate G6 and P6, and the circuit structure S03-6 is used to calculate G 6:0 , the circuit structure S04-7 is used to calculate S7. Wherein, the expression of the circuit structure S01-7 is: G6=a6·b6, The inputs of circuit structure S01-7 are a6 and b6, and the outputs are G6 and P6. The expression of circuit structure S03-6 is: G 6:0 =(P6·G 5:0 )|G6, the circuit structure S03-6 is connected to the circuit structure S01-7 to obtain G6 and P6, and the circuit structure S03-6 is also connected to the circuit structure S03-5 of the sixth path to obtain G 5:0 , the output of circuit structure S03-6 is G 6:0 The expression of circuit structure S04-7 is: S7=P7·G 6:0 , the circuit structure S04-7 is connected to the circuit structure S03-6 to obtain G 6:0The circuit structure S04-7 is also connected to the circuit structure S01-8 of the next path (the eighth path) to obtain P7. The output of the circuit structure S04-7 is S7.

[0161] The eighth path (path 7 in the figure) can be used to obtain the sum value S8. The eighth path includes a circuit structure S01 (hereinafter referred to as S01-8, represented by 1-8 in the figure), two circuit structures S02 (including circuit structure S02-3 and circuit structure S02-4, represented by 2-3 and 2-4 in the figure), a circuit structure S03 (hereinafter referred to as S03-7, represented by 3-7 in the figure), and a circuit structure S04 (hereinafter referred to as S4-8, represented by 4-8 in the figure) connected in sequence. Circuit structure S01-8 is used to calculate G7 and P7, and circuit structure S02-3 is used to calculate P 7:6 and G 7:6 , circuit structure S02-4 is used to calculate P 7:4 and G 7:4 , circuit structure S03-7 is used to calculate G 7:0 , circuit structure S04-8 is used to calculate S8. Wherein, the expression of circuit structure S01-8 is: G7=a7·b7, The inputs of circuit structure S01-8 are a7 and b7, and the outputs are G7 and P7. The expression of circuit structure S02-3 is P 7:6 =P7·P6,G 7:6 =(P7·G6)|G7, the circuit structure S02-3 is connected to the circuit structure S01-8 to obtain G7 and P7, and the circuit structure S02-3 is also connected to the seventh circuit structure S01-7 to obtain G6 and P6. The output of the circuit structure S02-3 is G 7:6 and P 7:6 The expression of circuit structure S02-4 is P 7:4 =P 7:6 ·P 5:4 , G 7:4 =(P 7:6 ·G 5:4 )|G 7:6 , the circuit structure S02-4 is connected to the circuit structure S02-3 to obtain G 7:6 and P 7:6 The circuit structure S02-4 is also connected to the sixth circuit structure S02-2 to obtain G 5:4 and P 5:4 , the output of circuit structure S02-4 is G 7:4 and P 7:4 The expression of circuit structure S03-7 is G 7:0 =(P 7:4 ·G 3:0 )|G 7:4, the circuit structure S03-7 is connected to the circuit structure S02-4 to obtain G 7:4 and P 7:4 The circuit structure S03-7 is also connected to the fourth circuit structure S03-3 to obtain G 3:0 , the output of circuit structure S03-7 is G 7:0 The expression of circuit structure S04-8 is: S8=P8·G 7:0 , the circuit structure S04-8 is connected to the circuit structure S03-7 to obtain G 7:0 The circuit structure S04-8 is also connected to the circuit structure S01-9 of the next path (the ninth path) to obtain P8. The output of the circuit structure S04-8 is S8.

[0162] The ninth path (path 8 in the figure) can be used to obtain the sum S9. The ninth path includes a circuit structure S01 (hereinafter referred to as S01-9, represented by 1-9 in the figure), a circuit structure S03 (hereinafter referred to as S03-8, represented by 3-8 in the figure), and a circuit structure S04 (hereinafter referred to as S4-9, represented by 4-9 in the figure) connected in sequence. The circuit structure S01-9 is used to calculate G8 and P8, and the circuit structure S03-8 is used to calculate G 8:0 , the circuit structure S04-9 is used to calculate S9. Wherein, the expression of the circuit structure S01-9 is: G8=a8·b8, The inputs of circuit structure S01-9 are a8 and b8, and the outputs are G8 and P8. The expression of circuit structure S03-8 is: G 8:0 =(P8·G 7:0 )|G8, the circuit structure S03-8 is connected to the circuit structure S01-9 to obtain G8 and P8, and the circuit structure S03-8 is also connected to the circuit structure S03-7 of the eighth path to obtain G 7:0 , the output of circuit structure S03-8 is G 8:0 The expression of circuit structure S04-9 is: S9=P9·G 8:0 , the circuit structure S04-9 is connected to the circuit structure S03-8 to obtain G 8:0 The circuit structure S04-9 is also connected to the circuit structure S01-10 of the next path (the tenth path) to obtain P9. The output of the circuit structure S04-9 is S9.

[0163] The tenth path (9th path in the figure) can be used to obtain the sum value S 10The tenth path includes a circuit structure S01 (hereinafter referred to as S01-10, represented by 1-10 in the figure), a circuit structure S02 (hereinafter referred to as S02-5, represented by 2-5 in the figure), a circuit structure S03 (hereinafter referred to as S03-9, represented by 3-9 in the figure), and a circuit structure S04 (hereinafter referred to as S04-10, represented by 4-10 in the figure) connected in sequence. The circuit structure S01-10 is used to calculate G9 and P9, and the circuit structure S02-5 is used to calculate P 9:8 and G 9:8 , circuit structure S03-9 is used to calculate G 9:0 , circuit structure S04-10 is used to calculate S 10 Among them, the expression of circuit structure S01-10 is: G9=a9·b9, The inputs of circuit structure S01-10 are a9 and b9, and the outputs are G9 and P9. The expression of circuit structure S02-5 is: P 9:8 =P9·P8,G 9:8 =(P9·G8)|G9, the circuit structure S02-5 is connected to the circuit structure S01-10 to obtain G9 and P9, and the circuit structure S02-5 is also connected to the ninth circuit structure S01-9 to obtain G8 and P8. The output of the circuit structure S02-5 is P 9:8 and G 9:8 The expression of circuit structure S03-9 is: G 9:0 =(P 9:8 ·G 7:0 )|G 9:8 , the circuit structure S03-9 is connected to the circuit structure S02-5 to obtain G 9:8 and P 9:8 , the circuit structure S03-9 is also connected to the circuit structure S03-7 of the eighth path, for obtaining G 7:0 , the output of circuit structure S03-5 is G 9:0 The expression of circuit structure S04-10 is: S 10 =P 10 ·G 9:0 , the circuit structure S04-10 is connected to the circuit structure S03-9 to obtain G 9:0 The circuit structure S04-10 is also connected to the circuit structure S01-11 of the next path (the eleventh path) to obtain P 10 , the output of circuit structure S04-10 is S 10 .

[0164] The eleventh path (path 10 in the figure) can be used to obtain the sum value S 11The eleventh path includes a circuit structure S01 (hereinafter referred to as S01-11, represented by 1-11 in the figure), a circuit structure S03 (hereinafter referred to as S03-10, represented by 3-10 in the figure), and a circuit structure S04 (hereinafter referred to as S4-11, represented by 4-11 in the figure) connected in sequence. The circuit structure S01-11 is used to calculate G 10 and P 10 , circuit structure S03-10 is used to calculate G 10:0 , circuit structure S04-11 is used to calculate S 11 Among them, the expression of circuit structure S01-11 is: G 10 =a 10 b 10 , The input of circuit structure S01-11 is a 10 and b 10 , the output is G 10 and P 10 The expression of circuit structure S03-10 is: G 10:0 =(P 10 ·G 9:0 )|G 10 , the circuit structure S03-10 is connected to the circuit structure S01-11 to obtain G 10 and P 10 The circuit structure S03-10 is also connected to the circuit structure S03-9 of the tenth path to obtain G 9:0 , the output of circuit structure S03-10 is G 10:0 The expression of circuit structure S04-11 is: S 11 =P 11 ·G 10:0 , the circuit structure S04-11 is connected to the circuit structure S03-10 to obtain G 10:0 The circuit structure S04-11 is also connected to the circuit structure S01-12 of the next path (the twelfth path) to obtain P 11 , the output of circuit structure S04-11 is S 11 .

[0165] The twelfth path (path 11 in the figure) can be used to obtain the sum value S 12 The twelfth path includes a circuit structure S01 (hereinafter referred to as S01-12, represented by 1-12 in the figure), two circuit structures S02 (including circuit structure S02-6 and circuit structure S02-7, represented by 2-6 and 2-7 in the figure), a circuit structure S03 (hereinafter referred to as S03-11, represented by 3-11 in the figure) and a circuit structure S04 (hereinafter referred to as S4-12, represented by 4-12 in the figure). Circuit structure S01-12 is used to calculate G 11 and P11 , circuit structure S02-6 is used to calculate P 11:10 and G 11:10 , circuit structure S02-7 is used to calculate P 11:8 and G 11:8 , circuit structure S03-11 is used to calculate G 11:0 , circuit structure S04-12 is used to calculate S 12 Among them, the expression of circuit structure S01-12 is: G 11 =a 11 b 11 , The input of circuit structure S01-12 is a 11 and b 11 , the output is G 11 and P 11 The expression of circuit structure S02-6 is P 11:10 =P 11 ·P 10 , G 11:10 =(P 11 ·G 10 )|G 11 , the circuit structure S02-6 is connected to the circuit structure S01-12 to obtain G 11 and P 11 The circuit structure S02-6 is also connected to the circuit structure S01-11 of the eleventh path to obtain G 10 and P 10 , the output of circuit structure S02-6 is G 11:10 and P 11:10 The expression of circuit structure S02-7 is P 11:8 =P 11:10 ·P 9:8 , G 11:8 =(P 11:10 ·G 9:8 )|G 11:10 , the circuit structure S02-7 is connected to the circuit structure S02-6 to obtain G 11:10 and P 11:10 , the circuit structure S02-7 is also connected to the tenth circuit structure S02-5, for obtaining G 9:8 and P 9:8 , the output of circuit structure S02-7 is G 11:8 and P 11:8 The expression of circuit structure S03-11 is G 11:0 =(P 11:8 ·G 7:0 )|G 11:8 , the circuit structure S03-11 is connected to the circuit structure S02-7 to obtain G 11:8 and P11:8 The circuit structure S03-11 is also connected to the circuit structure S03-7 of the eighth path to obtain G 7:0 , the output of circuit structure S03-11 is G 11:0 The expression of circuit structure S04-12 is: S 12 =P 12 ·G 11:0 , the circuit structure S04-12 is connected to the circuit structure S03-11 to obtain G 11:0 The circuit structure S04-12 is also connected to the circuit structure S01-13 of the next path (the thirteenth path) to obtain P 12 The output of the circuit structure S04-8 is S 12 .

[0166] The thirteenth path (12th path in the figure) can be used to obtain the sum value S 13 The thirteenth path includes a circuit structure S01 (hereinafter referred to as S01-13, represented by 1-13 in the figure), a circuit structure S03 (hereinafter referred to as S03-12, represented by 3-12 in the figure), and a circuit structure S04 (hereinafter referred to as S4-13, represented by 4-13 in the figure) connected in sequence. The circuit structure S01-13 is used to calculate G 12 and P 12 , circuit structure S03-12 is used to calculate G 12:0 , circuit structure S04-13 is used to calculate S 13 Among them, the expression of circuit structure S01-13 is: G 12 =a 12 b 12 , The input of circuit structure S01-13 is a 12 and b 12 , the output is G 12 and P 12 The expression of circuit structure S03-12 is: G 12:0 =(P 12 ·G 11:0 )|G 12 , the circuit structure S03-12 is connected to the circuit structure S01-13 to obtain G 12 and P 12 The circuit structure S03-12 is also connected to the twelfth circuit structure S03-11 to obtain G 11:0 , the output of circuit structure S03-12 is G 12:0 The expression of circuit structure S04-13 is: S 13 =P 13 ·G 12:0 , the circuit structure S04-13 is connected to the circuit structure S03-12 to obtain G12:0 The circuit structure S04-13 is also connected to the circuit structure S01-14 of the next path (the fourteenth path) to obtain P 13 , the output of circuit structure S04-11 is S 13 .

[0167] The fourteenth path (path 13 in the figure) can be used to obtain the sum value S 14 The fourteenth path includes a circuit structure S01 (hereinafter referred to as S01-14, represented by 1-14 in the figure), two circuit structures S02 (including circuit structure S02-8 and circuit structure S02-9, represented by 2-8 and 2-9 in the figure), a circuit structure S03 (hereinafter referred to as S03-13, represented by 3-13 in the figure), and a circuit structure S04 (hereinafter referred to as S4-14, represented by 4-14 in the figure) connected in sequence. Circuit structure S01-14 is used to calculate G 13 and P 13 , circuit structure S02-8 is used to calculate P 13:12 and G 13:12 , circuit structure S02-9 is used to calculate P 13:8 and G 13:8 , circuit structure S03-13 is used to calculate G 13:0 , circuit structure S04-14 is used to calculate S 14 Among them, the expression of circuit structure S01-14 is: G 13 =a 13 b 13 , The input of circuit structure S01-14 is a 13 and b 13 , the output is G 13 and P 13 The expression of circuit structure S02-8 is P 13:12 =P 13 ·P 12 , G 13:12 =(P 13 ·G 12 )|G 13 , the circuit structure S02-8 is connected to the circuit structure S01-14 to obtain G 13 and P 13 , the circuit structure S02-8 is also connected to the thirteenth circuit structure S01-13, for obtaining G 12 and P 12 , the output of circuit structure S02-8 is G 13:12 and P 13:12 The expression of circuit structure S02-9 is P 13:8 =P 13:12 ·P 11:8 , G13:8 =(P 13:12 ·G 11:8 )|G 13:12 , the circuit structure S02-9 is connected to the circuit structure S02-8 to obtain G 13:12 and P 13:12 The circuit structure S02-9 is also connected to the twelfth circuit structure S02-7 to obtain G 11:8 and P 11:8 , the output of circuit structure S02-9 is G 13:8 and P 13:8 The expression of circuit structure S03-13 is G 13:0 =(P 13:8 ·G 7:0 )|G 13:8 , the circuit structure S03-13 is connected to the circuit structure S02-9 to obtain G 13:8 and P 13:8 , the circuit structure S03-13 is also connected to the circuit structure S03-7 of the eighth path, for obtaining G 7:0 , the output of circuit structure S03-13 is G 13:0 The expression of circuit structure S04-14 is: S 14 =P 14 ·G 13:0 , the circuit structure S04-14 is connected to the circuit structure S03-13 to obtain G 13:0 The circuit structure S04-14 is also connected to the circuit structure S01-15 of the next path (the fifteenth path) to obtain P 14 , the output of the circuit structure S04-14 is S 14 .

[0168] The 15th path (14th path in the figure) can be used to obtain the sum value S 15 The fifteenth path includes a circuit structure S01 (hereinafter referred to as S01-15, represented by 1-15 in the figure), a circuit structure S03 (hereinafter referred to as S03-14, represented by 3-14 in the figure), and a circuit structure S04 (hereinafter referred to as S4-15, represented by 4-15 in the figure) connected in sequence. The circuit structure S01-15 is used to calculate G 14 and P 14 , circuit structure S03-14 is used to calculate G 14:0 , circuit structure S04-15 is used to calculate S 15 Among them, the expression of circuit structure S01-15 is: G 14 =a 14 b 14 , The input of circuit structure S01-15 is a 14 and b14 , the output is G 14 and P 14 The expression of circuit structure S03-14 is: G 14:0 =(P 14 ·G 13:0 )|G 14 , the circuit structure S03-14 is connected to the circuit structure S01-15 to obtain G 14 and P 14 , the circuit structure S03-14 is also connected to the fourteenth circuit structure S03-13, for obtaining G 13:0 , the output of circuit structure S03-14 is G 14:0 The expression of circuit structure S04-15 is: S 15 =P 15 ·G 14:0 , the circuit structure S04-15 is connected to the circuit structure S03-14 to obtain G 14:0 The circuit structure S04-15 is also connected to the circuit structure S01-16 of the next path (the sixteenth path) to obtain P 15 , the output of circuit structure S04-15 is S 15 .

[0169] The sixteenth path (15th path in the figure) can be used to obtain the sum value S 16 The sixteenth path includes a circuit structure S01 (hereinafter referred to as S01-16, represented by 1-16 in the figure), three circuit structures S02 (including circuit structure S02-10, circuit structure S02-11 and circuit structure 2-12, represented by 2-10, 2-11 and 2-12 in the figure), a circuit structure S03 (hereinafter referred to as S03-15, represented by 3-15 in the figure) and a circuit structure S04 (hereinafter referred to as S4-16, represented by 4-16 in the figure) connected in sequence. Circuit structure S01-16 is used to calculate G 15 and P 15 , circuit structure S02-10 is used to calculate P 15:14 and G 15:14 , circuit structure S02-11 is used to calculate P 15:12 and G 15:12 , circuit structure S02-12 is used to calculate P 15:8 and G 15:8 , circuit structure S03-15 is used to calculate G 15:0 , circuit structure S04-16 is used to calculate S 16 Among them, the expression of circuit structure S01-16 is: G 15 =a 15 b 15 , The input of circuit structure S01-16 is a15 and b 15 , the output is G 15 and P 15 The expression of circuit structure S02-10 is P 15:14 =P 15 ·P 14 , G 15:14 =(P 15 ·G 14 )|G 15 , the circuit structure S02-10 is connected to the circuit structure S01-16 to obtain G 15 and P 15 , the circuit structure S02-10 is also connected to the circuit structure S01-15 of the fifteenth path, for obtaining G 14 and P 14 , the output of circuit structure S02-10 is G 15:14 and P 15:14 The expression of circuit structure S02-11 is P 15:12 =P 15:14 ·P 13:12 , G 15:12 =(P 15:14 ·G 13:12 )|G 15:14 , the circuit structure S02-11 is connected to the circuit structure S02-10 to obtain G 15:14 and P 15:14 , the circuit structure S02-11 is also connected to the fourteenth circuit structure S02-8, for obtaining G 13:12 and P 13:12 , the output of circuit structure S02-11 is G 15:12 and P 15:12 The expression of circuit structure S02-12 is P 15:8 =P 15:12 ·P 11:8 , G 15:8 =(P 15:12 ·G 11:8 )|G 15:12 , the circuit structure S02-12 is connected to the circuit structure S02-11 to obtain G 15:12 and P 15:12 The circuit structure S02-12 is also connected to the twelfth circuit structure S02-7 to obtain G 11:8 and P 11:8 , the output of circuit structure S02-12 is G 15:8 and P 15:8 The expression of circuit structure S03-15 is G 15:0 =(P 15:8 ·G 7:0 )|G 15:8, the circuit structure S03-15 is connected to the circuit structure S02-12 to obtain G 15:8 and P 15:8 , the circuit structure S03-15 is also connected to the circuit structure S03-7 of the eighth path, for obtaining G 7:0 , the output of circuit structure S03-15 is G 15:0 The expression of circuit structure S04-16 is: S 16 =P 16 ·G 15:0 , the circuit structure S04-16 is connected to the circuit structure S03-15 to obtain G 15:0 The circuit structure S04-16 is also connected to the circuit structure S01-17 of the next path (the seventeenth path) to obtain P 16 The output of the circuit structure S04-16 is S 16 .

[0170] The 17th path (16th path in the figure) can be used to obtain the sum value S 17 The seventeenth path includes a circuit structure S01 (hereinafter referred to as S01-17, represented by 1-17 in the figure), a circuit structure S03 (hereinafter referred to as S03-16, represented by 3-16 in the figure), and a circuit structure S04 (hereinafter referred to as S4-17, represented by 4-17 in the figure) connected in sequence. The circuit structure S01-17 is used to calculate G 16 and P 16 , circuit structure S03-16 is used to calculate G 16:0 , circuit structure S04-17 is used to calculate S 17 Among them, the expression of circuit structure S01-17 is: G 16 =a 16 b 16 , The input of circuit structure S01-17 is a 16 and b 16 , the output is G 16 and P 16 The expression of circuit structure S03-16 is: G 16:0 =(P 16 ·G 15:0 )|G 16 , the circuit structure S03-16 is connected to the circuit structure S01-17 to obtain G 16 and P 16 The circuit structure S03-16 is also connected to the circuit structure S03-15 of the sixteenth path, and is used to obtain G 15:0 , the output of circuit structure S03-16 is G 16:0 The expression of circuit structure S04-17 is: S 17 =P 17·G 16:0 , the circuit structure S04-17 is connected to the circuit structure S03-16 to obtain G 16:0 The circuit structure S04-17 is also connected to the circuit structure S01-18 of the next path (the eighteenth path) to obtain P 17 , the output of circuit structure S04-17 is S 17 .

[0171] The 18th path (17th path in the figure) can be used to obtain the sum value S 18 The eighteenth path includes a circuit structure S01 (hereinafter referred to as S01-18, represented by 1-18 in the figure), a circuit structure S02 (hereinafter referred to as S02-13, represented by 2-13 in the figure), a circuit structure S03 (hereinafter referred to as S03-17, represented by 3-17 in the figure), and a circuit structure S04 (hereinafter referred to as S04-18, represented by 4-18 in the figure) connected in sequence. The circuit structure S01-18 is used to calculate G 17 and P 17 , circuit structure S02-13 is used to calculate P 17:16 and G 17:16 , circuit structure S03-17 is used to calculate G 17:0 , circuit structure S04-18 is used to calculate S 18 Among them, the expression of circuit structure S01-18 is: G 17 =a 17 b 17 , The input of circuit structure S01-18 is a 17 and b 17 , the output is G 17 and P 17 The expression of circuit structure S02-13 is: P 17:16 =P 17 ·P 16 , G 17:16 =(P 17 ·G 16 )|G 17 , the circuit structure S02-13 is connected to the circuit structure S01-18 to obtain G 17 and P 17 , the circuit structure S02-13 is also connected to the circuit structure S01-17 of the seventeenth path, for obtaining G 16 and P 16 , the output of circuit structure S02-13 is P 17:16 and G 17:16 The expression of circuit structure S03-17 is: G 17:0 =(P 17:16 ·G 15:0 )|G17:16 , the circuit structure S03-17 is connected to the circuit structure S02-13 to obtain G 17:16 and P 17:16 , the circuit structure S03-17 is also connected to the circuit structure S03-15 of the sixteenth path, for obtaining G 15:0 , the output of circuit structure S03-17 is G 17:0 The expression of circuit structure S04-18 is: S 18 =P 18 ·G 17:0 , the circuit structure S04-18 is connected to the circuit structure S03-17 to obtain G 17:0 The circuit structure S04-18 is also connected to the circuit structure S01-19 of the next path (the nineteenth path) to obtain P 18 , the output of circuit structure S04-18 is S 18 .

[0172] The 19th path (18th path in the figure) can be used to obtain the sum value S 19 The nineteenth path includes a circuit structure S01 (hereinafter referred to as S01-19, represented by 1-19 in the figure), a circuit structure S03 (hereinafter referred to as S03-18, represented by 3-18 in the figure), and a circuit structure S04 (hereinafter referred to as S4-19, represented by 4-19 in the figure) connected in sequence. The circuit structure S01-19 is used to calculate G 18 and P 18 , circuit structure S03-18 is used to calculate G 18:0 , circuit structure S04-19 is used to calculate S 19 Among them, the expression of circuit structure S01-19 is: G 18 =a 18 b 18 , The input of circuit structure S01-19 is a 18 and b 18 , the output is G 18 and P 18 The expression of circuit structure S03-18 is: G 18:0 =(P 18 ·G 17:0 )|G 18 , the circuit structure S03-18 is connected to the circuit structure S01-19 to obtain G 18 and P 18 , the circuit structure S03-18 is also connected to the circuit structure S03-17 of the eighteenth path, for obtaining G 17:0 , the output of circuit structure S03-18 is G 18:0 The expression of circuit structure S04-19 is: S 19 =P19 ·G 18:0 , the circuit structure S04-19 is connected to the circuit structure S03-18 to obtain G 18:0 The circuit structure S04-19 is also connected to the circuit structure S01-20 of the next path (the 20th path) to obtain P 19 , the output of circuit structure S04-19 is S 19 .

[0173] The 20th path (19th path in the figure) can be used to obtain the sum value S 20 The twentieth path includes a circuit structure S01 (hereinafter referred to as S01-20, represented by 1-20 in the figure), two circuit structures S02 (including circuit structure S02-14 and circuit structure S02-15, represented by 2-14 and 2-15 in the figure), a circuit structure S03 (hereinafter referred to as S03-19, represented by 3-18 in the figure) and a circuit structure S04 (hereinafter referred to as S4-20, represented by 4-20 in the figure) connected in sequence. The circuit structure S01-20 is used to calculate G 19 and P 19 , circuit structure S02-14 is used to calculate P 19:18 and G 19:18 , circuit structure S02-15 is used to calculate P 19:16 and G 19:16 , circuit structure S03-19 is used to calculate G 19:0 , circuit structure S04-20 is used to calculate S 20 Among them, the expression of circuit structure S01-20 is: G 19 =a 19 b 19 , The input of circuit structure S01-20 is a 19 and b 19 , the output is G 19 and P 19 The expression of circuit structure S02-14 is P 19:18 =P 19 ·P 18 , G 19:18 =(P 19 ·G 18 )|G 19 , the circuit structure S02-14 is connected to the circuit structure S01-20 to obtain G 19 and P 19 , the circuit structure S02-14 is also connected to the circuit structure S01-19 of the nineteenth path, for obtaining G 18 and P 18 , the output of circuit structure S02-14 is G 19:18 and P 19:18The expression of circuit structure S02-15 is P 19:16 =P 19:18 ·P 17:16 , G 19:16 =(P 19:18 ·G 17:16 )|G 19:18 , the circuit structure S02-15 is connected to the circuit structure S02-14 to obtain G 19:18 and P 19:18 The circuit structure S02-15 is also connected to the circuit structure S02-13 of the eighteenth path to obtain G 17:16 and P 17:16 , the output of circuit structure S02-15 is G 19:16 and P 19:16 The expression of circuit structure S03-19 is G 19:0 =(P 19:16 ·G 15:0 )|G 19:16 , the circuit structure S03-19 is connected to the circuit structure S02-15 to obtain G 19:16 and P 19:16 The circuit structure S03-19 is also connected to the circuit structure S03-15 of the sixteenth path to obtain G 15:0 , the output of circuit structure S03-19 is G 19:0 The expression of circuit structure S04-20 is: S 20 =P 20 ·G 19:0 , the circuit structure S04-20 is connected to the circuit structure S03-19 to obtain G 19:0 The circuit structure S04-20 is also connected to the circuit structure S01-21 of the next path (the 21st path) to obtain P 20 , the output of the circuit structure S04-20 is S 20 .

[0174] The 21st path (20th path in the figure) can be used to obtain the sum value S 21 The twenty-first path includes a circuit structure S01 (hereinafter referred to as S01-21, represented by 1-21 in the figure), a circuit structure S03 (hereinafter referred to as S03-20, represented by 3-20 in the figure), and a circuit structure S04 (hereinafter referred to as S4-21, represented by 4-21 in the figure) connected in sequence. The circuit structure S01-21 is used to calculate G 20 and P 20 , circuit structure S03-20 is used to calculate G 20:0 , circuit structure S04-21 is used to calculate S 21 Among them, the expression of circuit structure S01-21 is: G 20 =a20 b 20 , The input of circuit structure S01-21 is a 20 and b 20 , the output is G 20 and P 20 The expression of circuit structure S03-20 is: G 20:0 =(P 20 ·G 19:0 )|G 20 , the circuit structure S03-20 is connected to the circuit structure S01-21 to obtain G 20 and P 20 The circuit structure S03-20 is also connected to the twentieth circuit structure S03-19 to obtain G 19:0 , the output of circuit structure S03-20 is G 20:0 The expression of circuit structure S04-21 is: S 21 =P 21 ·G 20:0 , the circuit structure S04-21 is connected to the circuit structure S03-20 to obtain G 20:0 The circuit structure S04-21 is also connected to the circuit structure S01-22 of the next path (the 22nd path) to obtain P 21 , the output of circuit structure S04-21 is S 21 .

[0175] The 22nd path (21st path in the figure) can be used to obtain the sum value S 22 The twenty-second path includes a circuit structure S01 (hereinafter referred to as S01-22, represented by 1-22 in the figure), two circuit structures S02 (including circuit structure S02-16 and circuit structure S02-17, represented by 2-16 and 2-17 in the figure), a circuit structure S03 (hereinafter referred to as S03-21, represented by 3-21 in the figure), and a circuit structure S04 (hereinafter referred to as S4-22, represented by 4-22 in the figure) connected in sequence. The circuit structure S01-22 is used to calculate G 21 and P 21 , circuit structure S02-16 is used to calculate P 21:20 and G 21:20 , circuit structure S02-17 is used to calculate P 21:16 and G 21:16 , circuit structure S03-21 is used to calculate G 21:0 , circuit structure S04-22 is used to calculate S 22 Among them, the expression of circuit structure S01-22 is: G 21 =a 21 b 21 , The input of circuit structure S01-22 is a 21 and b 21 , the output is G 21 and P 21 The expression of circuit structure S02-16 is P 21:20 =P 21 ·P 20 , G 21:20 =(P 21 ·G 20 )|G 21 , the circuit structure S02-16 is connected to the circuit structure S01-22 to obtain G 21 and P 21 The circuit structure S02-16 is also connected to the twenty-first circuit structure S01-21 to obtain G 20 and P 20 , the output of circuit structure S02-16 is G 21:20 and P 21:20 The expression of circuit structure S02-17 is P 21:16 =P 21:20 ·P 19:16 , G 21:16 =(P 21:20 ·G 19:16 )|G 21:20 , the circuit structure S02-17 is connected to the circuit structure S02-16 to obtain G 21:20 and P 21:20 , the circuit structure S02-17 is also connected to the twentieth circuit structure S02-15, for obtaining G 19:16 and P 19:16 , the output of circuit structure S02-17 is G 21:16 and P 21:16 The expression of circuit structure S03-21 is G 21:0 =(P 21:16 ·G 15:0 )|G 21:16 , the circuit structure S03-21 is connected to the circuit structure S02-17 to obtain G 21:16 and P 21:16 The circuit structure S03-21 is also connected to the circuit structure S03-15 of the sixteenth path to obtain G 15:0 , the output of circuit structure S03-21 is G 21:0 The expression of circuit structure S04-22 is: S 22 =P 22 ·G 21:0 , the circuit structure S04-22 is connected to the circuit structure S03-21 to obtain G 21:0The circuit structure S04-22 is also connected to the circuit structure S01-23 of the next path (the 23rd path) to obtain P 22 The output of the circuit structure S04-22 is S 22 .

[0176] The 23rd path (22nd path in the figure) can be used to obtain the sum value S 23 The twenty-third path includes a circuit structure S01 (hereinafter referred to as S01-21, represented by 1-23 in the figure), a circuit structure S03 (hereinafter referred to as S03-22, represented by 3-22 in the figure), and a circuit structure S04 (hereinafter referred to as S4-23, represented by 4-23 in the figure) connected in sequence. The circuit structure S01-23 is used to calculate G 22 and P 22 , circuit structure S03-22 is used to calculate G 22:0 , circuit structure S04-23 is used to calculate S 23 Among them, the expression of circuit structure S01-21 is: G 22 =a 22 b 22 , The input of circuit structure S01-23 is a 22 and b 22 , the output is G 22 and P 22 The expression of circuit structure S03-22 is: G 22:0 =(P 22 ·G 21:0 )|G 22 , the circuit structure S03-22 is connected to the circuit structure S01-23 to obtain G 22 and P 22 The circuit structure S03-22 is also connected to the twenty-second circuit structure S03-21 to obtain G 21:0 , the output of circuit structure S03-22 is G 22:0 The expression of circuit structure S04-23 is: S 23 =P 23 ·G 22:0 , the circuit structure S04-23 is connected to the circuit structure S03-22 to obtain G 22:0 The circuit structure S04-23 is also connected to the circuit structure S01-24 of the next path (the 24th path) to obtain P 23 , the output of circuit structure S04-23 is S 23 .

[0177] The 24th path (23rd path in the figure) can be used to obtain the sum value S 24The twenty-fourth path includes a circuit structure S01 (hereinafter referred to as S01-24, represented by 1-24 in the figure), three circuit structures S02 (including circuit structure S02-18, circuit structure S02-19 and circuit structure 2-20, represented by 2-18, 2-19 and 2-20 in the figure), a circuit structure S03 (hereinafter referred to as S03-23, represented by 3-23 in the figure) and a circuit structure S04 (hereinafter referred to as S4-24, represented by 4-24 in the figure) connected in sequence. The circuit structure S01-24 is used to calculate G 23 and P 23 , circuit structure S02-18 is used to calculate P 23:22 and G 23:22 , circuit structure S02-19 is used to calculate P 23:20 and G 23:20 , circuit structure S02-20 is used to calculate P 23:16 and G 23:16 , circuit structure S03-23 ​​is used to calculate G 23:0 , circuit structure S04-24 is used to calculate S 24 Among them, the expression of circuit structure S01-24 is: G 23 =a 23 b 23 , The input of circuit structure S01-24 is a 23 and b 23 , the output is G 23 and P 23 The expression of circuit structure S02-18 is P 23:22 =P 23 ·P 22 , G 23:22 =(P 23 ·G 22 )|G 23 , the circuit structure S02-18 is connected to the circuit structure S01-24 to obtain G 23 and P 23 , the circuit structure S02-18 is also connected to the twenty-third circuit structure S01-23, for obtaining G 22 and P 22 , the output of circuit structure S02-18 is G 23:22 and P 23:22 The expression of circuit structure S02-19 is P 23:20 =P 23:22 ·P 21:20 , G 23:20 =(P 23:22 ·G 21:20 )|G 23:22 , the circuit structure S02-19 is connected to the circuit structure S02-18 to obtain G23:22 and P 23:22 The circuit structure S02-19 is also connected to the twenty-second circuit structure S02-16 to obtain G 21:20 and P 21:20 , the output of circuit structure S02-19 is G 23:20 and P 23:20 The expression of circuit structure S02-20 is P 23:16 =P 23:20 ·P 19:16 , G 23:20 =(P 23:20 ·G 19:16 )|G 23:20 , the circuit structure S02-20 is connected to the circuit structure S02-19 to obtain G 23:20 and P 23:20 The circuit structure S02-20 is also connected to the twentieth circuit structure S02-15 to obtain G 19:16 and P 19:16 , the output of circuit structure S02-20 is G 23:16 and P 23:16 The expression of circuit structure S03-23 ​​is G 23:0 =(P 23:16 ·G 15:0 )|G 23:16 , the circuit structure S03-23 ​​is connected to the circuit structure S02-20 to obtain G 23:16 and P 23:16 , the circuit structure S03-23 ​​is also connected to the circuit structure S03-15 of the sixteenth path, for obtaining G 15:0 , the output of circuit structure S03-23 ​​is G 23:0 The expression of circuit structure S04-24 is: S 24 =P 24 ·G 23:0 , the circuit structure S04-24 is connected to the circuit structure S03-23 ​​to obtain G 23:0 The circuit structure S04-24 is also connected to the circuit structure S01-25 of the next path (the 25th path) to obtain P 24 The output of the circuit structure S04-24 is S 24 .

[0178] The 25th path (24th path in the figure) can be used to obtain the sum value S 25The twenty-fifth path includes a circuit structure S01 (hereinafter referred to as S01-25, represented by 1-25 in the figure), a circuit structure S03 (hereinafter referred to as S03-24, represented by 3-24 in the figure), and a circuit structure S04 (hereinafter referred to as S4-25, represented by 4-25 in the figure) connected in sequence. The circuit structure S01-25 is used to calculate G 24 and P 24 , circuit structure S03-24 is used to calculate G 24:0 , circuit structure S04-25 is used to calculate S 25 Among them, the expression of circuit structure S01-25 is: G 24 =a 24 b 24 , The input of circuit structure S01-25 is a 24 and b 24 , the output is G 24 and P 24 The expression of circuit structure S03-24 is: G 24:0 =(P 24 ·G 23:0 )|G 24 , the circuit structure S03-24 is connected to the circuit structure S01-25 to obtain G 24 and P 24 The circuit structure S03-24 is also connected to the twenty-fourth circuit structure S03-23 ​​to obtain G 23:0 , the output of circuit structure S03-24 is G 24:0 The expression of circuit structure S04-25 is: S 25 =P 25 ·G 24:0 , the circuit structure S04-25 is connected to the circuit structure S03-24 to obtain G 24:0 The circuit structure S04-25 is also connected to the circuit structure S01-26 of the next path (the 26th path) to obtain P 25 , the output of circuit structure S04-25 is S 25 .

[0179] The 26th path (25th path in the figure) can be used to obtain the sum value S 26 The twenty-sixth path includes a circuit structure S01 (hereinafter referred to as S01-26, represented by 1-26 in the figure), two circuit structures S02 (including circuit structure S02-21 and circuit structure S02-22, represented by 2-21 and 2-22 in the figure), a circuit structure S03 (hereinafter referred to as S03-25, represented by 3-25 in the figure), and a circuit structure S04 (hereinafter referred to as S4-26, represented by 4-26 in the figure) connected in sequence. The circuit structure S01-26 is used to calculate G25 and P 25 , circuit structure S02-21 is used to calculate P 25:24 and G 25:24 , circuit structure S02-22 is used to calculate P 25:16 and G 25:16 , circuit structure S03-25 is used to calculate G 25:0 , circuit structure S04-26 is used to calculate S 26 Among them, the circuit structure S01-26 is expressed as: G 25 =a 25 b 25 , The input of circuit structure S01-26 is a 25 and b 25 , the output is G 25 and P 25 The expression of circuit structure S02-21 is P 25:24 =P 25 ·P 24 , G 25:24 =(P 25 ·G 24 )|G 25 , the circuit structure S02-21 is connected to the circuit structure S01-26 to obtain G 25 and P 25 The circuit structure S02-21 is also connected to the twenty-fifth circuit structure S01-25 to obtain G 24 and P 24 , the output of circuit structure S02-21 is G 25:24 and P 25:24 The expression of circuit structure S02-22 is P 25:16 =P 25:24 ·P 23:16 , G 25:16 =(P 25:24 ·G 23:16 )|G 25:24 , the circuit structure S02-22 is connected to the circuit structure S02-21 to obtain G 25:24 and P 25:24 The circuit structure S02-22 is also connected to the twenty-fourth circuit structure S02-20 to obtain G 23:16 and P 23:16 , the output of circuit structure S02-22 is G 25:16 and P 25:16 The expression of circuit structure S03-25 is G 25:0 =(P 25:16 ·G 15:0 )|G 25:16, the circuit structure S03-25 is connected to the circuit structure S02-22 to obtain G 25:16 and P 25:16 The circuit structure S03-25 is also connected to the circuit structure S03-15 of the sixteenth path to obtain G 15:0 , the output of circuit structure S03-25 is G 25:0 The expression of circuit structure S04-26 is: S 26 =P 26 ·G 25:0 , the circuit structure S04-26 is connected to the circuit structure S03-25 to obtain G 25:0 The circuit structure S04-26 is also connected to the circuit structure S01-27 of the next path (the 27th path) to obtain P 26 The output of the circuit structure S04-26 is S 26 .

[0180] The 27th path (26th path in the figure) can be used to obtain the sum value S 27 The twenty-seventh path includes a circuit structure S01 (hereinafter referred to as S01-27, represented by 1-27 in the figure), a circuit structure S03 (hereinafter referred to as S03-26, represented by 3-26 in the figure), and a circuit structure S04 (hereinafter referred to as S4-27, represented by 4-27 in the figure) connected in sequence. The circuit structure S01-27 is used to calculate G 26 and P 26 , circuit structure S03-26 is used to calculate G 26:0 , circuit structure S04-27 is used to calculate S 27 Among them, the expression of circuit structure S01-27 is: G 26 =a 26 b 26 , The input of circuit structure S01-27 is a 26 and b 26 , the output is G 26 and P 26 The expression of circuit structure S03-26 is: G 26:0 =(P 26 ·G 25:0 )|G 26 , the circuit structure S03-26 is connected to the circuit structure S01-27 to obtain G 26 and P 26 The circuit structure S03-26 is also connected to the twenty-sixth circuit structure S03-25 to obtain G 25:0 , the output of circuit structure S03-26 is G 26:0 The expression of circuit structure S04-27 is: S 27 =P27 ·G 26:0 , the circuit structure S04-27 is connected to the circuit structure S03-26 to obtain G 26:0 The circuit structure S04-27 is also connected to the circuit structure S01-28 of the next path (the 28th path) to obtain P 27 , the output of circuit structure S04-27 is S 27 .

[0181] The 28th path (27th path in the figure) can be used to obtain the sum value S 28 The twenty-eighth path includes a circuit structure S01 (hereinafter referred to as S01-28, represented by 1-28 in the figure), three circuit structures S02 (including circuit structure S02-23, circuit structure S02-24 and circuit structure 2-25, represented by 2-23, 2-24 and 2-25 in the figure), a circuit structure S03 (hereinafter referred to as S03-27, represented by 3-27 in the figure) and a circuit structure S04 (hereinafter referred to as S4-28, represented by 4-28 in the figure). The circuit structure S01-28 is used to calculate G 27 and P 27 , circuit structure S02-23 is used to calculate P 27:26 and G 27:26 , circuit structure S02-24 is used to calculate P 27:24 and G 27:24 , circuit structure S02-25 is used to calculate P 27:16 and G 27:16 , circuit structure S03-27 is used to calculate G 27:0 , circuit structure S04-28 is used to calculate S 28 Among them, the expression of circuit structure S01-28 is: G 27 =a 27 b 27 , The input of circuit structure S01-28 is a 27 and b 27 , the output is G 27 and P 27 The expression of circuit structure S02-23 is P 27:26 =P 27 ·P 26 , G 27:26 =(P 27 ·G 26 )|G 27 , the circuit structure S02-23 is connected to the circuit structure S01-28 to obtain G 27 and P 27 The circuit structure S02-23 is also connected to the twenty-seventh circuit structure S01-27 to obtain G 26and P 26 , the output of circuit structure S02-23 is G 27:26 and P 27:26 The expression of circuit structure S02-24 is P 27:24 =P 27:26 ·P 25:24 , G 27:24 =(P 27:26 ·G 25:24 )|G 27:26 , the circuit structure S02-24 is connected to the circuit structure S02-23 to obtain G 27:26 and P 27:26 The circuit structure S02-24 is also connected to the twenty-sixth circuit structure S02-21 to obtain G 25:24 and P 25:24 , the output of circuit structure S02-24 is G 27:24 and P 27:24 The expression of circuit structure S02-25 is P 27:16 =P 27:24 ·P 23:16 , G 27:16 =(P 27:24 ·G 23:16 )|G 27:24 , the circuit structure S02-25 is connected to the circuit structure S02-24 to obtain G 27:24 and P 27:24 The circuit structure S02-25 is also connected to the twenty-fourth circuit structure S02-20 to obtain G 23:16 and P 23:16 , the output of circuit structure S02-25 is G 27:16 and P 27:16 The expression of circuit structure S03-27 is G 27:0 =(P 27:16 ·G 15:0 )|G 27:16 , the circuit structure S03-27 is connected to the circuit structure S02-25 to obtain G 27:16 and P 27:16 , the circuit structure S03-27 is also connected to the circuit structure S03-15 of the sixteenth path, for obtaining G 15:0 , the output of circuit structure S03-27 is G 27:0 The expression of circuit structure S04-28 is: S 28 =P 28 ·G 27:0 , the circuit structure S04-28 is connected to the circuit structure S03-27 to obtain G 27:0 The circuit structure S04-28 is also connected to the circuit structure S01-29 of the next path (the 29th path) to obtain P28 The output of the circuit structure S04-28 is S 28 .

[0182] The 29th path (28th path in the figure) can be used to obtain the sum value S 29 The 29th path includes a circuit structure S01 (hereinafter referred to as S01-29, represented by 1-29 in the figure), a circuit structure S03 (hereinafter referred to as S03-28, represented by 3-28 in the figure), and a circuit structure S04 (hereinafter referred to as S4-29, represented by 4-29 in the figure) connected in sequence. The circuit structure S01-29 is used to calculate G 28 and P 28 , circuit structure S03-28 is used to calculate G 28:0 , circuit structure S04-29 is used to calculate S 29 Among them, the expression of circuit structure S01-29 is: G 28 =a 28 b 28 , The input of circuit structure S01-29 is a 28 and b 28 , the output is G 28 and P 28 The expression of circuit structure S03-28 is: G 28:0 =(P 28 ·G 27:0 )|G 28 , the circuit structure S03-28 is connected to the circuit structure S01-29 to obtain G 28 and P 28 The circuit structure S03-28 is also connected to the twenty-eighth circuit structure S03-27 to obtain G 27:0 , the output of circuit structure S03-28 is G 28:0 The expression of circuit structure S04-29 is: S 29 =P 29 ·G 28:0 , the circuit structure S04-29 is connected to the circuit structure S03-28 to obtain G 28:0 The circuit structure S04-29 is also connected to the circuit structure S01-30 of the next path (the 30th path) to obtain P 29 , the output of circuit structure S04-29 is S 29 .

[0183] The 30th path (29th path in the figure) can be used to obtain the sum value S 30The 30th path includes a circuit structure S01 (hereinafter referred to as S01-30, represented by 1-30 in the figure), three circuit structures S02 (including circuit structure S02-26, circuit structure S02-27 and circuit structure 2-28, represented by 2-26, 2-27 and 2-28 in the figure), a circuit structure S03 (hereinafter referred to as S03-29, represented by 3-29 in the figure) and a circuit structure S04 (hereinafter referred to as S4-30, represented by 4-30 in the figure). The circuit structure S01-30 is used to calculate G 29 and P 29 , circuit structure S02-26 is used to calculate P 29:28 and G 29:28 , circuit structure S02-27 is used to calculate P 29:24 and G 29:24 , circuit structure S02-28 is used to calculate P 29:16 and G 29:16 , circuit structure S03-29 is used to calculate G 29:0 , circuit structure S04-30 is used to calculate S 30 Among them, the expression of circuit structure S01-30 is: G 29 =a 29 b 29 , The input of circuit structure S01-30 is a 29 and b 29 , the output is G 29 and P 29 The expression of circuit structure S02-26 is P 29:28 =P 29 ·P 28 , G 29:28 =(P 29 ·G 28 )|G 29 , the circuit structure S02-26 is connected to the circuit structure S01-30 to obtain G 29 and P 29 , the circuit structure S02-26 is also connected to the twenty-ninth circuit structure S01-29, for obtaining G 28 and P 28 , the output of circuit structure S02-26 is G 29:28 and P 29:28 The expression of circuit structure S02-27 is P 29:24 =P 29:28 ·P 27:24 , G 29:24 =(P 29:28 ·G 27:24 )|G 29:28 , the circuit structure S02-27 is connected to the circuit structure S02-26 to obtain G29:28 and P 29:28 The circuit structure S02-27 is also connected to the twenty-eighth circuit structure S02-24 to obtain G 27:24 and P 27:24 , the output of circuit structure S02-27 is G 29:24 and P 29:24 The expression of circuit structure S02-28 is P 29:16 =P 29:24 ·P 23:16 , G 29:16 =(P 29:24 ·G 23:16 )|G 29:24 , the circuit structure S02-28 is connected to the circuit structure S02-27 to obtain G 29:24 and P 29:24 The circuit structure S02-28 is also connected to the twenty-fourth circuit structure S02-20 to obtain G 23:16 and P 23:16 , the output of circuit structure S02-28 is G 29:16 and P 29:16 The expression of circuit structure S03-29 is G 29:0 =(P 29:16 ·G 15:0 )|G 29:16 , the circuit structure S03-29 is connected to the circuit structure S02-28 to obtain G 29:16 and P 29:16 The circuit structure S03-29 is also connected to the circuit structure S03-15 of the sixteenth path to obtain G 15:0 , the output of circuit structure S03-29 is G 29:0 The expression of circuit structure S04-30 is: S 30 =P 30 ·G 29:0 , the circuit structure S04-30 is connected to the circuit structure S03-29 to obtain G 29:0 The circuit structure S04-30 is also connected to the circuit structure S01-31 of the next path (the 31st path) to obtain P 30 , the output of the circuit structure S04-30 is S 30 .

[0184] The 31st path (30th path in the figure) can be used to obtain the sum value S 31The thirty-first path includes a circuit structure S01 (hereinafter referred to as S01-31, represented by 1-31 in the figure), a circuit structure S03 (hereinafter referred to as S03-30, represented by 3-30 in the figure), and a circuit structure S04 (hereinafter referred to as S4-31, represented by 4-31 in the figure) connected in sequence. The circuit structure S01-31 is used to calculate G 30 and P 30 , circuit structure S03-30 is used to calculate G 30:0 , circuit structure S04-31 is used to calculate S 31 Among them, the expression of circuit structure S01-31 is: G 30 =a 30 b 30 , The input of circuit structure S01-31 is a 30 and b 30 , the output is G 30 and P 30 The expression of circuit structure S03-30 is: G 30:0 =(P 30 ·G 29:0 )|G 30 , the circuit structure S03-30 is connected to the circuit structure S01-31 to obtain G 30 and P 30 The circuit structure S03-30 is also connected to the 30th circuit structure S03-29 to obtain G 29:0 , the output of circuit structure S03-30 is G 30:0 The expression of circuit structure S04-31 is: S 31 =P 31 ·G 30:0 , the circuit structure S04-31 is connected to the circuit structure S03-30 to obtain G 30:0 The circuit structure S04-31 is also connected to the circuit structure S01-32 of the next path (the 32nd path) to obtain P 31 , the output of circuit structure S04-31 is S 31 .

[0185] The 32nd path (31st path in the figure) can be used to obtain the carry value. The 32nd path includes a circuit structure S01 (hereinafter referred to as S01-32, represented by 1-32 in the figure), four circuit structures S02 (including circuit structure S02-29, circuit structure S02-30, circuit structure S02-31 and circuit structure 2-32, represented by 2-29, 2-30, 2-31 and 2-32 in the figure) and a circuit structure S03 (hereinafter referred to as S03-31, represented by 3-31 in the figure). The circuit structure S01-32 is used to calculate G 31 and P31 , circuit structure S02-29 is used to calculate P 31:30 and G 31:30 , circuit structure S02-30 is used to calculate P 31:28 and G 31:28 , circuit structure S02-31 is used to calculate P 31:24 and G 31:24 , circuit structure S02-32 is used to calculate P 31:16 and G 31:16 , circuit structure S03-31 is used to calculate G 31:0 Among them, the expression of circuit structure S01-32 is: G 31 =a 31 b 31 , The input of circuit structure S01-32 is a 31 and b 31 , the output is G 31 and P 31 The expression of circuit structure S02-29 is P 31:30 =P 31 ·P 30 , G 31:30 =(P 31 ·G 30 )|G 31 , the circuit structure S02-29 is connected to the circuit structure S01-32 to obtain G 31 and P 31 The circuit structure S02-29 is also connected to the thirty-first circuit structure S01-31 to obtain G 30 and P 30 , the output of circuit structure S02-29 is G 31:30 and P 31:30 The expression of circuit structure S02-30 is P 31:28 =P 31:30 ·P 29:28 , G 31:28 =(P 31:30 ·G 29:28 )|G 31:30 , the circuit structure S02-30 is connected to the circuit structure S02-29 to obtain G 31:30 and P 31:30 The circuit structure S02-30 is also connected to the 30th circuit structure S02-26 to obtain G 29:28 and P 29:28 , the output of circuit structure S02-30 is G 31:28 and P 31:28 The expression of circuit structure S02-31 is P 31:24 =P 31:28 ·P27:24 , G 31:24 =(P 31:28 ·G 27:24 )|G 31:28 , the circuit structure S02-31 is connected to the circuit structure S02-30 to obtain G 31:28 and P 31:28 The circuit structure S02-31 is also connected to the twenty-eighth circuit structure S02-24 to obtain G 27:24 and P 27:24 , the output of circuit structure S02-31 is G 31:24 and P 31:24 The expression of circuit structure S02-32 is P 31:16 =P 31:24 ·P 23:16 , G 31:16 =(P 31:24 ·G 23:16 )|G 31:16 , the circuit structure S02-32 is connected to the circuit structure S02-31 to obtain G 31:24 and P 31:24 The circuit structure S02-32 is also connected to the twenty-fourth circuit structure S02-20 to obtain G 23:16 and P 23:16 , the output of circuit structure S02-32 is G 31:16 and P 31:16 The expression of circuit structure S03-31 is G 31:0 =(P 31:16 ·G 15:0 )|G 31:16 , the circuit structure S03-31 is connected to the circuit structure S02-32 to obtain G 31:16 and P 31:16 The circuit structure S03-32 is also connected to the circuit structure S03-15 of the sixteenth path to obtain G 15:0 , the output G of circuit structure S03-31 31:0 This is the carry result.

[0186] In this embodiment, by designing circuit structures S02-31 and S02-27 to reuse the calculation result of circuit structure S02-24, circuit structures S02-20 and S02-17 to reuse the calculation result of circuit structure S02-15, circuit structures S02-12 and S02-9 to reuse the calculation result of circuit structure S02-7, and circuit structures S02-32, S02-28, S02-25 and S02-22 to reuse the calculation result of circuit structure S02-20, the circuit structures The calculation results of circuit structures S03-7 and S03-5 reuse the calculation results of circuit structure S03-3; circuit structures S03-15, S03-13, S03-11, and S03-9 reuse the calculation results of circuit structure S03-7; and circuit structures S03-31, S03-29, S03-27, S03-25, S03-23, S03-21, S03-19, and S03-17 reuse the calculation results of circuit structure S03-15. This reduces the number of circuit structures. This embodiment uses four circuit structures to implement a 32-bit adder with carry. Only 126 circuit structures are required to implement an adder with a logic depth of 8 levels, achieving a balance between low power consumption, high speed, and small area.

[0187] When implementing a 32-bit adder without carry, the 32nd path (31st path in the figure) can be used to obtain P 31 The 32nd path includes a circuit structure S01 (hereinafter referred to as S01-32, represented by 1-32 in the figure). The circuit structure S01-32 is used to calculate G 31 and P 31 The expression of circuit structure S01-32 is: G 31 =a 31 b 31 , The input of circuit structure S01-32 is a 31 and b 31 , the output is G 31 and P 31 .

[0188] The implementation of an 8-bit or 16-bit adder can refer to the 32-bit adder implementation, which will not be repeated here.

[0189] The above circuit structure can also be used to implement a 64-bit unsigned integer adder without carry or a 64-bit unsigned integer adder with carry. The circuit structure can be designed with reference to a 32-bit adder and will not be described in detail here.

[0190] A 32-bit carry-less KSA (Kogge Stone Adder) adder uses a total of 187 circuit structures, with a maximum logic depth of 7 levels. In contrast, the 32-bit carry-less adder in the disclosed embodiment uses only 121 circuit structures, with a maximum logic depth of 8 levels. Although the maximum logic depth increases by one level, 66 circuit structures are reduced, significantly reducing power consumption.

[0191] As can be seen, the adder circuit structure provided by the embodiments of the present disclosure has a relatively smaller overall circuit area. Since circuit area is directly proportional to power consumption, the adder circuit structure provided by the embodiments of the present disclosure has relatively lower power consumption. In practical applications, this adder can achieve a better balance between operating speed and power consumption.

[0192] An embodiment of the present disclosure further provides a processor, which may include the logic gate circuit or adder circuit structure in any of the above embodiments.

[0193] The above are only preferred embodiments of the present disclosure and the technical principles used. Those skilled in the art will understand that the present disclosure is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of this application. Therefore, although the present disclosure has been described in more detail through the above embodiments, the present disclosure is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present disclosure, and the scope of the present disclosure is determined by the scope of the appended claims.

Claims

1. A logic gate circuit for implementing an exclusive-OR or exclusive-OR logic operation, the logic gate circuit comprising a first input port, a second input port and a first output port, wherein a transmission path from the first input port to the first output port is a first transmission path, a transmission path from the second input port to the first output port is a second transmission path, and a delay of the second transmission path is greater than a delay of the first transmission path.

2. The logic gate circuit according to claim 1, wherein: The logic gate circuit is used to implement an exclusive-OR logic operation, and the logic gate circuit includes a first transmission gate, a first inverter, a first transistor and a second transistor, wherein: The first input port is connected to the input end of the first transmission gate, the output end of the first transmission gate is connected to the first output port of the logic gate circuit, the first input port is also connected to the gates of the first transistor and the second transistor respectively, the second input port is connected to the first electrode of the first transistor, the second electrode of the first transistor is connected to the first output port of the logic gate circuit, the second input port is also connected to the first control end of the first transmission gate, the second input port is also connected to the input end of the first inverter, the output end of the first inverter is connected to the second control end of the first transmission gate, the output end of the first inverter is also connected to the first electrode of the second transistor, and the second electrode of the second transistor is connected to the first output port of the logic gate circuit.

3. The logic gate circuit according to claim 2, wherein: The first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.

4. The logic gate circuit according to claim 1, wherein: The logic gate circuit is used to implement an XNOR logic operation, and the logic gate circuit includes a second transmission gate, a second inverter, a third transistor and a fourth transistor, wherein: The first input port is connected to the input end of the second transmission gate, the output end of the second transmission gate is connected to the first output port of the logic gate circuit, the first input port is also connected to the gates of the third transistor and the fourth transistor respectively, the second input port is connected to the first electrode of the third transistor, the second electrode of the third transistor is connected to the first output port of the logic gate circuit, the second input port is also connected to the second control end of the second transmission gate, the second input port is also connected to the input end of the second inverter, and the output end of the second inverter is connected to the first control end of the second transmission gate. A control terminal, the output terminal of the second inverter is also connected to the first electrode of the fourth transistor, and the second electrode of the fourth transistor is connected to the first output port of the logic gate circuit.

5. The logic gate circuit according to claim 4, wherein: The third transistor is an NMOS transistor, and the fourth transistor is a PMOS transistor.

6. A logic gate circuit for implementing a summation operation in an adder, the logic gate circuit comprising a first logic subcircuit and a second logic subcircuit, wherein: The first logic subcircuit is used to perform an XOR operation or an XNOR operation, the first logic subcircuit comprises a first input bit, a second input bit and a first output bit, and the first output bit of the first logic subcircuit is connected to the second input port of the second logic subcircuit; The second logic sub-circuit includes a first input port, a second input port and a first output port, the first output port of the second logic sub-circuit outputs the result of the summation operation, wherein the transmission path from the first input port to the first output port is the first transmission path, the transmission path from the second input port to the first output port is the second transmission path, and the delay of the second transmission path is greater than the delay of the first transmission path.

7. The logic gate circuit according to claim 6, wherein: The first logic sub-circuit is an XOR gate circuit or an XNOR gate circuit; The second logic subcircuit is used to implement an XOR operation, and the second logic subcircuit includes a first transmission gate, a first inverter, a first transistor and a second transistor, wherein: The first input port is connected to the input end of the first transmission gate, the output end of the first transmission gate is connected to the first output port of the second logic sub-circuit, the first input port is also connected to the gates of the first transistor and the second transistor respectively, the second input port is connected to the first electrode of the first transistor, the second electrode of the first transistor is connected to the first output port of the second logic sub-circuit, the second input port is also connected to the first control end of the first transmission gate, the second input port is also connected to the input end of the first inverter, the output end of the first inverter is connected to the second control end of the first transmission gate, the output end of the first inverter is also connected to the first electrode of the second transistor, and the second electrode of the second transistor is connected to the first output port of the second logic sub-circuit.

8. The logic gate circuit according to claim 7, wherein: The first logic subcircuit is an XOR gate circuit, the first input bit of the first logic subcircuit is used to input the i-th bit of the first data, the second input bit of the first logic subcircuit is used to input the i-th bit of the second data; the first input port of the second logic subcircuit is used to input the first G logic result G i-1:0 ;or The first logic subcircuit is an XNOR gate circuit, the first input bit of the first logic subcircuit is used to input the i-th bit of the first data, the second input bit of the first logic subcircuit is used to input the i-th bit of the second data; the first input port of the second logic subcircuit is used to input the second G logic result! G i-1:0 .

9. The logic gate circuit according to claim 6, wherein: The first logic sub-circuit is an XOR gate circuit or an XNOR gate circuit; The second logic sub-circuit is used to implement an XNOR logic operation, and the second logic sub-circuit includes a second transmission gate, a second inverter, a third transistor and a fourth transistor, wherein: The first input port is connected to the input end of the second transmission gate, the output end of the second transmission gate is connected to the first output port of the second logic sub-circuit, the first input port is also connected to the gates of the third transistor and the fourth transistor respectively, the second input port is connected to the first electrode of the third transistor, the second electrode of the third transistor is connected to the first output port of the second logic sub-circuit, the second input port is also connected to the second control end of the second transmission gate, the second input port is also connected to the input end of the second inverter, the output end of the second inverter is connected to the first control end of the second transmission gate, the output end of the second inverter is also connected to the first electrode of the fourth transistor, and the second electrode of the fourth transistor is connected to the first output port of the second logic sub-circuit.

10. The logic gate circuit according to claim 9, wherein: The first logic subcircuit is an XOR gate circuit, the first input bit of the first logic subcircuit is used to input the i-th bit of the first data, the second input bit of the first logic subcircuit is used to input the i-th bit of the second data; the first input port of the second logic subcircuit is used to input the second G logic result! G i-1:0 ;or The first logic subcircuit is an XNOR gate circuit, the first input bit of the first logic subcircuit is used to input the i-th bit of the first data, and the second input bit of the first logic subcircuit is used to input the i-th bit of the first data. The first input port of the second logic subcircuit is used to input the first G logic result G i-1:0 .

11. An adder circuit structure for implementing an addition operation of 2^n-bit data, where n is a positive integer greater than or equal to 3, and the adder comprises at least 2^n logic gate circuits as described in any one of claims 6 to 10.

12. An adder circuit structure for implementing an addition operation of 2^n-bit data, where n is a positive integer greater than or equal to 3, the adder comprising: At least 2^n first-class circuit structures, at least 2 second-class circuit structures, at least 2^n-2 third-class circuit structures and at least 2^n-1 fourth-class circuit structures, wherein: the first-class circuit structure receives the i-th bit of the first data and the i-th bit of the second data as input, 0≥i≥2^n, and outputs the G logic result and the P logic result of the i-th bit; the second-class circuit structure receives the G logic result and the P logic result, and outputs a sub-combination of the G logic result and a sub-combination of the P logic result; the third-class circuit structure receives the G logic result and the P logic result or receives the sub-combination of the G logic result and the P logic result, and outputs a new sub-combination of the G logic result; the fourth-class circuit structure receives the P logic result and the G logic result or receives the P logic result and the new sub-combination of the G logic result, and outputs a sum value, and the fourth-class circuit structure includes a logic gate circuit as described in any one of claims 1 to 5; In the adder circuit structure, two or more of the second-type circuit structures reuse the calculation result of one second-type circuit structure, or two or more of the three-type circuit structures reuse the calculation result of one three-type circuit structure.

13. The adder circuit structure according to claim 12, wherein: The adder circuit structure includes 2^n input terminals for inputting 2^n bits and at least 2^n output terminals, the path from the i-th input terminal to the i+1-th output terminal is a vertical path, 0≤i≤2^n, and one or more of the first-type circuit structure, the second-type circuit structure, the third-type circuit structure and the fourth-type circuit structure are arranged on each path from the input terminal to the output terminal; In every eight adjacent vertical paths, the fourth circuit structure in the eighth vertical path and the third circuit structure in the sixth vertical path reuse the calculation result of the third circuit structure in the fourth vertical path.

14. The adder circuit structure according to claim 13, wherein: The fourth circuit structure in the eighth longitudinal path, the third circuit structure in the sixth longitudinal path, and the third circuit structure in the fourth longitudinal path are all type II circuit structures or type III circuit structures.

15. The adder circuit structure according to claim 12 or 13, wherein: In every 16 adjacent vertical paths, the fifth circuit structure in the sixteenth vertical path, the fourth circuit structure in the fourteenth vertical path, the fourth circuit structure in the twelfth vertical path, and the third circuit structure in the tenth vertical path reuse the calculation results of the fourth circuit structure in the eighth vertical path.

16. The adder circuit structure according to claim 15, wherein: The fifth circuit structure in the sixteenth longitudinal path, the fourth circuit structure in the fourteenth longitudinal path, the fourth circuit structure in the twelfth longitudinal path, the third circuit structure in the tenth longitudinal path, and the fourth circuit structure in the eighth longitudinal path are all three types of circuit structures.

17. The adder circuit structure according to claim 15, wherein: In every 32 adjacent vertical paths, the sixth circuit structure in the thirty-second vertical path, the fifth circuit structure in the thirtieth vertical path, the fifth circuit structure in the twenty-eighth vertical path, the fourth circuit structure in the twenty-sixth vertical path, the fifth circuit structure in the twenty-fourth vertical path, the fourth circuit structure in the twenty-second vertical path, the fourth circuit structure in the twentieth vertical path, and the third circuit structure in the eighteenth vertical path reuse the calculation results of the fifth circuit structure in the sixteenth vertical path.

18. The adder circuit structure according to claim 17, wherein: The sixth circuit structure in the thirty-second longitudinal pathway, the fifth circuit structure in the thirtieth longitudinal pathway, the fifth circuit structure in the twenty-eighth longitudinal pathway, the fourth circuit structure in the twenty-sixth longitudinal pathway, the fifth circuit structure in the twenty-fourth longitudinal pathway, the fourth circuit structure in the twenty-second longitudinal pathway, the fourth circuit structure in the twentieth longitudinal pathway, the third circuit structure in the eighteenth longitudinal pathway, and the fifth circuit structure in the sixteenth longitudinal pathway are all three types of circuit structures.

19. A processor comprising: The logic gate circuit according to any one of claims 1 to 5, or the logic gate circuit according to any one of claims 6 to 10, or the adder circuit structure according to claim 11, or the adder circuit structure according to any one of claims 12 to 18.

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