Circuit board electroplating method and circuit board

Abstract

A circuit board electroplating method and a circuit board. The electroplating method comprises: removing partial layers at a target edge of a circuit board, so as to expose a target internal circuit layer (S1); and placing the circuit board in an electroplating solution, applying an electroplating current to the target internal circuit layer exposed at the target edge, and performing electroplating, so as to form on a surface metal layer a first metal layer having a uniform thickness, and form on the inner walls of holes included in a hole dense region on the surface of the circuit board a first metal layer connecting the surface metal layer and the target internal circuit layer (S2).

Description

Circuit board electroplating method and circuit board

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on September 5, 2023, with application number 202311142764.X. The entire contents of the above application are incorporated by reference into this application. Technical Field

[0002] The present application relates to electroplating technology, for example, to a circuit board electroplating method and a circuit board. Background Art

[0003] In the process of preparing a multi-layer circuit board, it is usually necessary to drill holes in the circuit board and electroplate a metal layer on the inner wall of the hole to electrically connect the circuit of the internal circuit layer of the circuit board with the metal layer on the surface of the circuit board. The metal layer on the surface of the circuit board is then processed to form a surface circuit layer, thereby achieving electrical connection between the internal circuit layer and the surface circuit layer.

[0004] During the electroplating process, the entire circuit board is immersed in the plating solution. Simultaneously, a metal layer forms on the inner walls of the holes and on the surface of the circuit board. In the hole-dense areas of the circuit board's surface, the higher specific surface area and lower current density result in a thinner metal layer in these areas after electroplating, while the thicker metal layer in other areas deteriorates. This leads to poor plating uniformity. A large disparity between the two can severely impact subsequent processing and, in severe cases, can even prevent the surface circuits from being etched, rendering the circuit board scrapped.

[0005] Summary of the Invention

[0006] The present application provides a circuit board electroplating method and a circuit board, which can increase the current density in the hole-dense area, thereby offsetting the effect of the lower current density due to the high specific surface area of ​​the hole-dense area. In this way, the thickness of the metal layer formed on the surface metal layer is uniform, thereby improving the quality of the circuit board and reducing the scrap rate.

[0007] In a first aspect, the present application provides a circuit board electroplating method, comprising:

[0008] Removing a portion of a layer at a target edge of a circuit board to expose a target internal circuit layer, wherein the target edge is one edge of the circuit board;

[0009] Placing the circuit board in an electroplating solution and applying an electroplating current to the target internal circuit layer exposed at the target edge to electroplate the circuit board, thereby forming a first metal layer of uniform thickness on the surface metal layer of the circuit board, and forming a first metal layer connecting the surface metal layer and the target internal circuit layer on the inner wall of each hole included in the hole-dense area on the surface of the circuit board;

[0010] In which, the circuit board includes a surface metal layer on the surface of the circuit board, a first insulating layer on the bottom surface of the circuit board, and at least one internal circuit layer located between the surface metal layer and the first insulating layer, a second insulating layer is arranged between adjacent internal circuit layers, and a third insulating layer is arranged between the surface metal layer and the internal circuit layer adjacent to the surface metal layer. The partial layers of the target edge of the circuit board are the surface metal layer and the third insulating layer at the target edge of the circuit board, and the target internal circuit layer is the internal circuit layer adjacent to the surface metal layer.

[0011] Optionally, before removing part of the layers at the target edge of the circuit board to expose the target internal circuit layer, the method further includes:

[0012] Immersing the circuit board in a deposition liquid, and depositing a second metal layer on the inner wall of each hole and the surface of the surface metal layer using a chemical deposition method, wherein the partial layer at the target edge also includes the second metal layer on the surface metal layer at the target edge;

[0013] Accordingly, the first metal layer with uniform thickness is formed on the surface metal layer of the circuit board, and the first metal layer connecting the surface metal layer and the target internal circuit layer is formed on the inner wall of each hole included in the hole-dense area on the surface of the circuit board, including:

[0014] A first metal layer with uniform thickness is formed on the second metal layer deposited on the surface metal layer, and a first metal layer connecting the surface metal layer and the target internal circuit layer is formed on the second metal layer deposited on the inner wall of each hole.

[0015] Optionally, after removing part of the layers at the target edge of the circuit board to expose the target internal circuit layer, the method further includes:

[0016] forming a groove parallel to the target edge on the surface metal layer, wherein the bottom of the groove exposes the target insulating layer located below the surface metal layer, wherein the target insulating layer is the third insulating layer, and the groove divides the surface metal layer into a first portion close to the target edge and a second portion away from the target edge, wherein the width of the first portion is smaller than the width of the second portion;

[0017] Immersing the circuit board in a deposition liquid, and depositing a second metal layer on the inner wall of each hole, the exposed surface of the target insulating layer, the first portion, and the second portion using a chemical deposition method;

[0018] removing the first portion and the second metal layer on the first portion to form an insulating isolation zone between the exposed target internal circuit layer and the surface metal layer;

[0019] Accordingly, a first metal layer having a uniform thickness is formed on the surface metal layer of the circuit board, and a first metal layer connecting the surface metal layer and the target internal circuit layer is formed on the inner wall of each hole included in the hole-dense area on the surface of the circuit board, comprising:

[0020] A first metal layer with uniform thickness is formed on the second metal layer deposited on the second portion, and a first metal layer connecting the surface metal layer and the target internal circuit layer is formed on the second metal layer deposited on the inner wall of each hole.

[0021] Optionally, forming a groove parallel to the target edge on the surface metal layer includes:

[0022] A groove parallel to the target edge is formed on the surface metal layer in a gong groove manner.

[0023] Optionally, after removing part of the layers at the target edge of the circuit board to expose the target internal circuit layer, the method further includes:

[0024] removing a surface metal layer near an edge of the target edge to expose a target insulating layer below the surface metal layer, wherein the target insulating layer is the third insulating layer;

[0025] Applying insulating tape to the exposed target insulation layer;

[0026] Immersing the circuit board in a deposition liquid, and depositing a second metal layer on the inner wall of each hole, the surface of the insulating tape, and the surface of the surface metal layer using a chemical deposition method;

[0027] Peeling off the insulating tape and the second metal layer deposited on the surface of the insulating tape to form an insulating isolation tape between the exposed target internal circuit layer and the surface metal layer;

[0028] Accordingly, a first metal layer having a uniform thickness is formed on the surface metal layer of the circuit board, and a first metal layer connecting the surface metal layer and the target internal circuit layer is formed on the inner wall of each hole included in the hole-dense area on the surface of the circuit board, comprising:

[0029] A first metal layer with uniform thickness is formed on the second metal layer deposited on the surface metal layer, and a first metal layer connecting the surface metal layer and the target internal circuit layer is formed on the second metal layer deposited on the inner wall of each hole.

[0030] Optionally, removing a portion of layers at a target edge of the circuit board to expose a target internal circuit layer includes:

[0031] A blind gong method is used to remove part of the layer at the target edge of the circuit board to expose the target internal circuit layer. The width of the blind gong ranges from 5mm to 12mm, and the length of the blind gong is the length of the target edge.

[0032] Optionally, removing a portion of layers at a target edge of the circuit board to expose a target internal circuit layer includes:

[0033] A portion of the target edge layer of the circuit board on the side where the surface metal layer is provided is removed to expose the target internal circuit layer.

[0034] Optionally, a non-target surface metal layer is formed on a side of the first insulating layer on the bottom surface of the circuit board away from the surface metal layer, and the surface metal layer on the surface of the circuit board is the target surface metal layer;

[0035] Removing a portion of the layers at the target edge of the circuit board to expose the target internal circuit layer includes:

[0036] Removing a portion of the target edge layer on one side of the target surface metal layer of the circuit board to expose the target internal circuit layer;

[0037] The non-target surface metal layer and the first insulating layer at the target edge of the circuit board on one side of the non-target surface metal layer are removed to expose the internal circuit layer on the side of the first insulating layer away from the non-target surface metal layer.

[0038] Optionally, placing the circuit board in a plating solution and applying a plating current to the target internal circuit layer exposed at the target edge to electroplate the circuit board includes:

[0039] Using a plurality of electroplating clips to clamp the target edge of the circuit board, the plurality of electroplating clips are evenly spaced along the target edge, and the plurality of electroplating clips are electrically connected to the target internal circuit layer exposed at the target edge;

[0040] placing the circuit board in a plating solution;

[0041] Electroplating of the circuit board is performed by applying an electroplating current to the target internal circuit layer exposed at the target edge through the multiple electroplating clamps.

[0042] Optionally, the metal layer is a copper layer.

[0043] In a second aspect, an embodiment of the present application further provides a circuit board, comprising:

[0044] a surface metal layer on the surface of the circuit board, a first insulating layer on the bottom surface of the circuit board, and at least one internal circuit layer located between the surface metal layer and the first insulating layer, a second insulating layer being provided between adjacent internal circuit layers, and a third insulating layer being provided between the surface metal layer and the internal circuit layer adjacent to the surface metal layer;

[0045] Wherein, a portion of the internal circuit layer adjacent to the surface metal layer at one edge of the circuit board is not covered by the third insulating layer and the surface metal layer, and the exposed portion of the internal circuit layer is the target internal circuit layer;

[0046] A first metal layer with uniform thickness is formed on the surface metal layer, and a first metal layer connecting the surface metal layer and the target internal circuit layer is formed on the inner wall of each hole included in the hole-dense area on the surface of the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The present application will be described below with reference to the accompanying drawings and embodiments.

[0048] FIG1 is a schematic structural diagram of a circuit board;

[0049] FIG2 is a schematic diagram of current flow in an electroplating method;

[0050] FIG3 is a schematic diagram of a process flow of a circuit board electroplating method;

[0051] FIG4 is a schematic diagram of a process for depositing a metal layer;

[0052] FIG5 is a front view of a circuit board with a portion of a layer at a target edge removed;

[0053] FIG6 is a cross-sectional view of FIG5 along section line AA;

[0054] FIG7 is a schematic diagram of electroplating a circuit board;

[0055] FIG8 is a cross-sectional view of a circuit board after electroplating along section line AA;

[0056] FIG9 is a schematic flow chart of another circuit board electroplating method;

[0057] FIG10 is a front view of another circuit board with a portion of a layer at a target edge removed;

[0058] FIG11 is a cross-sectional view of FIG10 along section line AA;

[0059] FIG12 is a front view of another circuit board after removing a portion of the layers at the target edge;

[0060] FIG13 is a cross-sectional view of FIG12 along section line AA;

[0061] FIG14 is a schematic diagram of the structure of a circuit board after depositing a metal layer;

[0062] FIG15 is a schematic structural diagram of the circuit board after removing the first portion and the metal layer on the first portion;

[0063] FIG16 is a schematic diagram of another method of electroplating a circuit board;

[0064] FIG17 is a cross-sectional view of another circuit board after electroplating along section line AA;

[0065] FIG18 is a schematic flow chart of another circuit board electroplating method;

[0066] FIG19 is a schematic diagram of the structure of a circuit board after removing the surface metal layer at the edge close to the target edge;

[0067] FIG20 is a schematic structural diagram of a circuit board after insulating tape is attached to the exposed target insulating layer;

[0068] FIG21 is a schematic diagram of the structure of another circuit board after depositing a metal layer;

[0069] FIG22 is a schematic diagram of the structure of the circuit board after the insulating tape is peeled off;

[0070] FIG23 is a cross-sectional view of another circuit board after electroplating along section line AA;

[0071] FIG. 24 is a schematic flow chart of another circuit board electroplating method. DETAILED DESCRIPTION

[0072] The following will illustrate the technical solutions of the embodiments of the present application with reference to the accompanying drawings. The embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0073] In the description of this application, unless otherwise expressly specified or limited, the terms "connected," "connected," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and can refer to internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0074] In this application, unless otherwise expressly specified and limited, a first feature being “above” or “below” a second feature may include the first feature and the second feature being in direct contact, or may include the first feature and the second feature being in contact not directly but through another feature between them. Moreover, a first feature being “above”, “above”, and “above” a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is at a higher level than the second feature. A first feature being “below”, “below”, and “below” a second feature includes the first feature being directly below and obliquely below the second feature, or simply indicates that the first feature is at a lower level than the second feature. In addition, the terms “first” and “second” are merely used to distinguish in description and have no special meaning.

[0075] FIG1 is a schematic diagram of the structure of a circuit board, and FIG2 is a schematic diagram of the current flow of an electroplating method. As shown in FIG1 , the circuit board includes a surface metal layer 10 and an internal circuit layer 20. An insulating layer 30 is provided between the surface metal layer 10 and the internal circuit layer 20. The internal circuit layer 20 is formed on the insulating layer 70. The surface metal layer 10 has not been etched to form a circuit, while the internal circuit layer 20 has been etched to form a circuit. A hole-dense area 40 is formed on the surface of the circuit board. The hole-dense area 40 includes at least one hole 41. The hole 41 is configured to electrically connect the surface metal layer 10 and the internal circuit layer 20. As shown in FIG1 , a very thin metal layer 50 is deposited on the inner wall of the hole 41. Since the metal layer 50 is very thin and has a high resistance, in order to reduce the resistance of the metal layer 50 and at the same time improve the connection stability between the surface metal layer 10 and the internal circuit layer 20, it is usually necessary to electroplate the circuit board to form a thicker metal layer on the surface metal layer 10 and the metal layer 50 on the inner wall of the hole 41. As shown in FIG2 , a circuit board is usually placed vertically in an electroplating tank filled with electroplating solution, and an electroplating current is applied to the surface metal layer 10 at the upper edge of the circuit board. Through electrochemical reaction, a thicker metal layer is formed on the surface metal layer 10 and the metal layer 50 on the inner wall of the hole 41. As shown in FIG2 , during the electroplating process, the current flows from the upper edge to the lower edge of the circuit board. When flowing through the hole-dense area 40, due to the high specific surface area of ​​the hole-dense area 40, the current density becomes smaller, resulting in a thinner metal layer formed in the hole-dense area 40 of the surface metal layer 10 after electroplating, and a thicker metal layer formed in other areas of the surface metal layer 10, resulting in poor electroplating uniformity. When the difference between the two is large, subsequent processing is seriously affected. In severe cases, it may even lead to the inability to etch the surface circuit, resulting in the scrapping of the circuit board.

[0076] An embodiment of the present application provides a circuit board electroplating method. FIG3 is a schematic flow chart of a circuit board electroplating method provided in an embodiment of the present application. As shown in FIG3 , the circuit board electroplating method includes the following steps:

[0077] S101, immersing the circuit board in a deposition liquid, and depositing a metal layer, ie, a second metal layer, on the inner wall of the hole by a chemical deposition method.

[0078] Figure 4 is a schematic diagram of the process of depositing a metal layer on the inner wall of a hole by a chemical deposition method according to an embodiment of the present application. As shown in Figure 4, before deposition, the circuit board includes a surface metal layer 110 and at least one internal circuit layer. This embodiment is described by taking two internal circuit layers 121 and 122 as an example. An insulating layer 131, i.e., a second insulating layer, is provided between adjacent internal circuit layers. An insulating layer 132, i.e., a third insulating layer, is provided between the surface metal layer 110 and the adjacent internal circuit layer 121. A hole-dense area 140 is formed on the surface of the circuit board, and the hole-dense area 140 includes at least one hole 141.

[0079] For example, in some embodiments of the present application, a very thin metal layer 151 is formed on the inner wall of hole 141 by chemical deposition. Metal layer 151 connects surface metal layer 110 and internal circuit layer 121. For example, after hole 141 is formed on the circuit board, the circuit board is immersed in a deposition solution, and metal layer 151 is deposited on the inner wall of hole 141 by chemical deposition. Metal layer 151 formed by chemical deposition is very thin, has high resistance, and has an unstable connection. At the same time, a very thin metal layer 153 is also formed on the surface of surface metal layer 110.

[0080] S102 , removing part of the layers at the target edge of the circuit board to expose the target internal circuit layer.

[0081] FIG5 is a front view of a circuit board with a portion of the layers at a target edge removed, and FIG6 is a cross-sectional view of FIG5 along section line AA. As shown in FIG5 and FIG6, in an embodiment of the present application, one edge of the circuit board is used as the target edge, and the target edge is processed to remove a portion of the layers at the target edge of the circuit board, exposing the target internal circuit layer 121. In the embodiment of the present application, the portion of the layers at the target edge of the circuit board is the surface metal layer and the third insulating layer at the target edge of the circuit board. In the embodiment of the present application, the internal circuit layer 121 connected to the surface metal layer 110 is referred to as the target internal circuit layer 121.

[0082] For example, in the embodiment of the present application, a blind gong method is used to remove a portion of the target edge layer of the circuit board (part of the surface metal layer 110 and part of the insulation layer 132 in Figure 6) by using a gong groove method to expose the target internal circuit layer 121. For example, the width of the blind gong ranges from 5mm to 12mm, and the length of the blind gong is the length of the target edge.

[0083] In this embodiment, the circuit board is provided with a surface metal layer 110 only on one side, and the other side is an insulating layer 133, i.e., a first insulating layer. Therefore, when removing part of the layer at the target edge of the circuit board, it is only necessary to remove part of the layer at the target edge on the side of the circuit board provided with the surface metal layer 110 to expose the target internal circuit layer 121, and the other side does not need to be processed.

[0084] Optionally, in some embodiments, surface metal layers are provided on opposite sides of the circuit board. For example, in Figure 6, a surface metal layer is also provided on the surface of the first insulating layer 133 away from the internal circuit layer 122. When removing part of the layers at the target edge of the circuit board, part of the surface metal layer 110 and part of the third insulating layer 132 are removed to expose the target internal circuit layer 121. At the same time, part of the surface metal layer on the other side of the circuit board and part of the first insulating layer 133 are removed to expose the target internal circuit layer 122 as a plated conductive layer.

[0085] S103. Place the circuit board in an electroplating solution and apply an electroplating current to the target internal circuit layer exposed at the target edge to perform electroplating to form a metal layer with uniform thickness on the surface metal layer, i.e., the first metal layer, and form a metal layer connecting the surface metal layer and the target internal circuit layer on the inner wall of the hole, i.e., the first metal layer.

[0086] FIG7 is a schematic diagram of a circuit board electroplating method provided in an embodiment of the present application. As shown in FIG7 , in an embodiment of the present application, the circuit board is placed vertically in an electrolytic tank containing an electrolyte, with the target edge facing upward, and a plating current is applied to the target internal circuit layer 121 exposed at the target edge for electroplating. FIG8 is a cross-sectional view of a circuit board after electroplating along section line AA. As shown in FIG8 , a metal layer 161 of uniform thickness is formed on the metal layer 153 on the surface metal layer 110, and a metal layer 162 connecting the surface metal layer 110 and the target internal circuit layer 121 is formed on the surface of the metal layer 151 on the inner wall of the hole 141. The metal layer 162 thickens the metal layer connecting the surface metal layer 110 and the target internal circuit layer 121, thereby reducing resistance and improving connection stability.

[0087] For example, in an embodiment of the present application, as shown in FIG7 , a plating clamp 170 is used to clamp the target edge of the circuit board. Multiple plating clamps 170 are evenly spaced along the target edge, and the plating clamps 170 are electrically connected to the target internal wiring layer 121 exposed at the target edge. After the circuit board is placed in the plating solution, multiple plating clamps 170 are energized simultaneously, and a plating current is applied to the target internal wiring layer 121 exposed at the target edge through the plating clamps 170 to perform plating, thereby improving current uniformity.

[0088] As shown in FIG7 , during the electroplating process, the current flows from the target internal circuit layer 121 through the inner wall of the hole 141 to the surface metal layer 110, and on the surface metal layer 110, the current flows divergently from the hole 141 to the surrounding area, thereby increasing the current density in the hole-dense area 140, thereby offsetting the effect of the lower current density due to the high specific surface area of ​​the hole-dense area 140. In this way, the metal layer 161 formed on the surface metal layer 110 has a uniform thickness, which improves the quality of the circuit board and reduces the scrap rate.

[0089] The material of the metal layer described in the above embodiment can be a conductive metal such as copper, which is not limited in the embodiment of the present application.

[0090] The embodiment of the present application provides a circuit board electroplating method, which includes a surface metal layer and at least one internal circuit layer, an insulating layer is provided between adjacent internal circuit layers, and an insulating layer is provided between the surface metal layer and the internal circuit layer. A hole-dense area is formed on the surface of the circuit board, and the hole-dense area includes at least one hole. Part of the layer at the target edge of the circuit board is removed to expose the target internal circuit layer, and the target edge is one of the edges of the circuit board. The circuit board is placed in a plating solution, and a plating current is applied to the target internal circuit layer exposed at the target edge for electroplating to form a metal layer of uniform thickness on the surface metal layer, and a metal layer connecting the surface metal layer and the target internal circuit layer is formed on the inner wall of the hole. During the electroplating process, the current on the surface metal layer is changed to flow divergently from the hole to the surrounding area, thereby increasing the current density in the hole-dense area, thereby offsetting the effect of the lower current density due to the high specific surface area of ​​the hole-dense area. In this way, the metal layer formed on the surface metal layer has a uniform thickness, which improves the quality of the circuit board and reduces the scrap rate.

[0091] This application provides another circuit board electroplating method that can avoid the problem of the process of removing a portion of the target layer at the edge of the circuit board, which takes a long time to expose the target internal circuit layer and the metal layer deposited on the inner wall of the hole is easily oxidized. This ensures that the metal layer is smoothly formed on the inner wall of the hole during the electroplating process, thereby improving the quality of the circuit board. Figure 9 is a schematic flow chart of another circuit board electroplating method provided in an embodiment of the present application. As shown in Figure 9, the circuit board electroplating method includes the following steps:

[0092] S201 , removing part of the layers at the target edge of the circuit board to expose the target internal circuit layer.

[0093] Figure 10 is a front view of another circuit board with part of the layer at the target edge removed, and Figure 11 is a cross-sectional view of Figure 10 along section line AA. As shown in Figures 10 and 11, the circuit board includes a surface metal layer 110 and at least one internal circuit layer. This embodiment is described by taking two internal circuit layers 121 and 122 as an example. An insulating layer 131 is provided between adjacent internal circuit layers, and an insulating layer 132 is provided between the surface metal layer 110 and the adjacent internal circuit layer 121. A hole-dense area 140 is formed on the surface of the circuit board, and the hole-dense area 140 includes at least one hole 141.

[0094] One edge of the circuit board is used as the target edge, and the target edge is processed. As shown in Figure 11, part of the layer at the target edge of the circuit board is removed to expose the target internal circuit layer 121. In the embodiment of the present application, the internal circuit layer 121 connected to the surface metal layer 110 is referred to as the target internal circuit layer.

[0095] For example, in an embodiment of the present application, a blind gong method is used to remove a portion of the target edge layer of the circuit board (surface metal layer 110 and insulation layer 132 in FIG. 11 ), exposing the target internal circuit layer 121. For example, the width of the blind gong ranges from 5 mm to 12 mm, and the length of the blind gong is the length of the target edge.

[0096] In this embodiment, the circuit board is provided with a surface metal layer 110 only on one side, and the other side is an insulating layer 133. Therefore, when removing part of the layer at the target edge of the circuit board, it is only necessary to remove part of the layer at the target edge on the side of the circuit board provided with the surface metal layer 110 to expose the target internal circuit layer 121, and the other side does not need to be processed.

[0097] Optionally, in this embodiment, surface metal layers are provided on both opposite sides of the circuit board. For example, in Figure 6, a surface metal layer is also provided on the surface of the first insulating layer 133 away from the internal circuit layer 122. When removing part of the layers at the target edge of the circuit board, part of the surface metal layer 110 and part of the third insulating layer 132 are removed to expose the target internal circuit layer 121. At the same time, part of the surface metal layer on the other side of the circuit board and part of the first insulating layer 133 are removed to expose the target internal circuit layer 122 as a plated conductive layer.

[0098] S202. A groove parallel to the target edge is formed on the surface metal layer, wherein the bottom of the groove exposes the target insulating layer below the surface metal layer, and the groove divides the surface metal layer into a first part close to the target edge and a second part away from the target edge, wherein the width of the first part is smaller than the width of the second part.

[0099] FIG12 is a front view of another circuit board after partial layer removal at the target edge, and FIG13 is a cross-sectional view of FIG12 along section line AA. As shown in FIG12 and FIG13 , a groove 111 is formed on the surface metal layer 110, parallel to the target edge. The bottom of groove 111 exposes the target insulating layer (insulating layer 132) located below the surface metal layer 110. Groove 111 divides the surface metal layer 110 into a first portion 112 close to the target edge and a second portion 113 away from the target edge. The width of the first portion 112 is smaller than the width of the second portion 113. Exemplarily, the width of the first portion 112 is much smaller than the width of the second portion 113, and the width of the first portion 112 is very small, approximately several millimeters.

[0100] For example, in some embodiments of the present application, a groove 111 parallel to the target edge is formed on the surface metal layer 110 by a grooving method, and the bottom of the groove 111 exposes the target insulating layer below the surface metal layer 110 .

[0101] S203, immersing the circuit board in a deposition liquid, and depositing a metal layer on the inner wall of the hole and the surface of the exposed target insulating layer by a chemical deposition method.

[0102] Figure 14 is a schematic structural diagram of a circuit board after depositing a metal layer. As shown in Figure 14, the circuit board processed in the aforementioned step S202 is immersed in a deposition liquid, and a very thin metal layer 151 is deposited on the inner wall of the hole 141 by chemical deposition, and a very thin metal layer 152 is deposited on the surface of the exposed target insulating layer, and a very thin metal layer 153 is deposited on the surface of the surface metal layer 110 (including the surface of the first part 112 and the surface of the second part 113).

[0103] S204 , removing the first portion and the metal layer on the first portion, and forming an insulating isolation zone between the exposed target internal circuit layer and the surface metal layer.

[0104] FIG15 is a schematic diagram of the structure of the circuit board after the first portion and the metal layer on the first portion have been removed. As shown in FIG15 , the first portion 112 and the metal layer 153 on the first portion 112 have been removed, forming an insulating isolation zone 114 between the exposed target internal circuit layer 121 and the surface metal layer 110. In the embodiment of the present application, since the first portion 112 is very narrow, the first portion 112 and the metal layer 153 on the first portion 112 can be removed by directly tearing them off, which is a simple and time-saving process.

[0105] S205. Place the circuit board in an electroplating solution, and apply an electroplating current to the target internal circuit layer exposed at the target edge to perform electroplating, thereby forming a metal layer with uniform thickness on the surface metal layer, and forming a metal layer connecting the surface metal layer and the target internal circuit layer on the inner wall of the hole.

[0106] FIG16 is a schematic diagram of another method for electroplating a circuit board provided in an embodiment of the present application. As shown in FIG16 , in an embodiment of the present application, the circuit board treated in step S204 is placed vertically in an electrolytic bath containing an electrolyte, with the target edge facing upward, and a plating current is applied to the target internal circuit layer 121 exposed at the target edge for electroplating. Because step S204 uses a direct tearing method to remove the first portion 112 and the metal layer 153 on the first portion 112, an insulating isolation zone 114 is formed between the exposed target internal circuit layer 121 and the surface metal layer 110. The process is simple and time-consuming. Therefore, the metal layer 151 deposited on the inner wall of the hole can be prevented from being oxidized, thereby improving the quality of the metal layer formed on the metal layer on the inner wall of the hole during the electroplating process, thereby improving the quality of the circuit board. In addition, due to the presence of the insulating isolation zone 114, the plating current is prevented from flowing directly from the exposed target internal circuit layer 121 to the surface metal layer 110.

[0107] For example, in an embodiment of the present application, as shown in FIG16 , a plating clamp 170 is used to clamp the target edge of the circuit board. Multiple plating clamps 170 are evenly spaced along the target edge, and the plating clamps 170 are electrically connected to the target internal wiring layer 121 exposed at the target edge. After the circuit board is placed in the plating solution, multiple plating clamps 170 are simultaneously energized, applying a plating current to the target internal wiring layer 121 exposed at the target edge through the plating clamps 170 to perform plating, thereby improving current uniformity.

[0108] As shown in Figure 16, during the electroplating process, the current flows from the target internal circuit layer 121 through the inner wall of the hole 141 to the surface metal layer 110, and on the surface metal layer 110, the current flows divergently from the hole 141 to the surrounding area, increasing the current density in the hole-dense area 140, thereby offsetting the effect of the lower current density due to the high specific surface area of ​​the hole-dense area 140. In this way, the metal layer 161 formed on the surface metal layer 110 has a uniform thickness, which improves the quality of the circuit board and reduces the scrap rate.

[0109] Figure 17 is a cross-sectional view of another circuit board after electroplating along the section line AA. As shown in Figure 17, a metal layer 161 with uniform thickness is formed on the surface metal layer 110 (the surface of the metal layer 153), and a metal layer 162 connecting the surface metal layer 110 and the target internal circuit layer 121 is formed on the inner wall of the hole 141 (the surface of the metal layer 151). The metal layer 162 makes the metal layer connecting the surface metal layer 110 and the target internal circuit layer 121 thicker, reduces the resistance, and improves the connection stability.

[0110] FIG18 is a schematic flow chart of another circuit board electroplating method provided in an embodiment of the present application. As shown in FIG18 , the circuit board electroplating method includes the following steps:

[0111] S301 , removing part of the layers at the target edge of the circuit board to expose the target internal circuit layer.

[0112] Referring to Figures 10 and 11 , one edge of the circuit board is treated as a target edge. This target edge is processed to remove a portion of the layers at the target edge of the circuit board, exposing the target internal wiring layer 121. In this embodiment of the present application, the internal wiring layer 121 connected to the surface metal layer 110 is referred to as the target internal wiring layer. The structure of the circuit board has been described in detail in the previous embodiment and will not be repeated here.

[0113] S302 , removing the surface metal layer near the edge of the target to expose the target insulating layer below the surface metal layer.

[0114] Figure 19 is a schematic structural diagram of the circuit board after the surface metal layer at the edge close to the target edge is removed. As shown in Figure 19, part of the surface metal layer 110 at the edge close to the target edge is removed to expose the target insulating layer under the surface metal layer 110.

[0115] S303: Attaching insulating tape to the exposed target insulating layer.

[0116] FIG20 is a schematic diagram of the structure of a circuit board after insulating tape is attached to the exposed target insulating layer. As shown in FIG20 , insulating tape 180 is attached to the surface of the exposed target insulating layer. The thickness of insulating tape 180 is not limited herein. For example, as shown in FIG20 , the thickness of insulating tape 180 is the same as the thickness of surface metal layer 110, that is, the surface of insulating tape 180 is flush with the surface of surface metal layer 110.

[0117] S304, immersing the circuit board in a deposition liquid, and depositing a metal layer on the inner wall of the hole, the surface of the insulating tape, and the surface of the surface metal layer using a chemical deposition method.

[0118] Figure 21 is a schematic structural diagram of another circuit board after depositing a metal layer. As shown in Figure 21, the circuit board processed in the aforementioned step S303 is immersed in a deposition liquid, and a very thin metal layer 151 is deposited on the inner wall of the hole 141 by chemical deposition, and a very thin metal layer 153 is deposited on the surface of the insulating tape 180 and the surface of the surface metal layer 110.

[0119] S305 , peeling off the insulating tape to form an insulating isolation tape between the exposed target internal circuit layer and the surface metal layer.

[0120] FIG22 is a schematic diagram of the structure of a circuit board after the insulating tape is removed. As shown in FIG22 , the insulating tape 180 is removed, and the metal layer on the surface of the insulating tape 180 is removed, forming an insulating isolation band 114 between the exposed target internal circuit layer and the surface metal layer. In this embodiment of the present application, the insulating tape 180 is easy to remove, the process is simple, and the time consumption is short.

[0121] S306. Place the circuit board in an electroplating solution and apply an electroplating current to the target internal circuit layer exposed at the target edge to perform electroplating to form a metal layer with uniform thickness on the surface metal layer, and form a metal layer connecting the surface metal layer and the target internal circuit layer on the inner wall of the hole.

[0122] The circuit board processed in step S305 is placed vertically in an electrolytic bath containing an electrolyte, with the target edge facing upward. A plating current is applied to the target internal circuit layer 121 exposed at the target edge to perform electroplating. Since step S305 can directly peel off the insulating tape 180 and simultaneously remove the metal layer on the surface of the insulating tape 180, forming an insulating isolation zone 114 between the exposed target internal circuit layer and the surface metal layer, the process is simple and time-efficient. Therefore, oxidation of the metal layer 151 deposited on the inner wall of the hole can be avoided, thereby improving the quality of the metal layer formed on the metal layer on the inner wall of the hole during the electroplating process, thereby improving the quality of the circuit board. Furthermore, the presence of the insulating isolation zone 114 prevents the plating current from flowing directly from the exposed target internal circuit layer 121 to the surface metal layer 110.

[0123] During the electroplating process, the current flows from the target internal circuit layer 121 through the inner wall of the hole 141 to the surface metal layer 110, and on the surface metal layer 110, the current diverges from the hole 141 to the surrounding area, increasing the current density in the hole-dense area 140, thereby offsetting the effect of the lower current density due to the high specific surface area of ​​the hole-dense area 140. In this way, the metal layer 161 formed on the surface metal layer 110 has a uniform thickness, which improves the quality of the circuit board and reduces the scrap rate.

[0124] Figure 23 is a cross-sectional view of another circuit board after electroplating along the section line AA. As shown in Figure 23, a metal layer 161 with uniform thickness is formed on the surface metal layer 110 (the surface of the metal layer 153), and a metal layer 162 connecting the surface metal layer 110 and the target internal circuit layer 121 is formed on the inner wall of the hole 141 (the surface of the metal layer 151). The metal layer 162 makes the metal layer connecting the surface metal layer 110 and the target internal circuit layer 121 thicker, reduces the resistance, and improves the connection stability.

[0125] An embodiment of the present application also provides a circuit board, which is prepared using the circuit board electroplating method provided in any of the aforementioned embodiments of the present application and has the corresponding effect.

[0126] The circuit board comprises:

[0127] a surface metal layer on the surface of the circuit board, a first insulating layer on the bottom surface of the circuit board, and at least one internal circuit layer located between the surface metal layer and the first insulating layer, a second insulating layer being provided between adjacent internal circuit layers, and a third insulating layer being provided between the surface metal layer and the internal circuit layer adjacent to the surface metal layer;

[0128] Wherein, a portion of the internal circuit layer adjacent to the surface metal layer at one edge of the circuit board is not covered by the third insulating layer and the surface metal layer, and the exposed portion of the internal circuit layer is the target internal circuit layer;

[0129] A first metal layer with uniform thickness is formed on the surface metal layer, and a first metal layer connecting the surface metal layer and the target internal circuit layer is formed on the inner wall of each hole included in the hole-dense area on the surface of the circuit board.

[0130] As shown in FIG24 , a circuit board electroplating method includes:

[0131] S1. Remove part of the layer at a target edge of the circuit board to expose a target internal circuit layer, where the target edge is one edge of the circuit board;

[0132] S2. Placing the circuit board in an electroplating solution and applying an electroplating current to the target internal circuit layer exposed at the target edge to electroplate the circuit board, thereby forming a first metal layer of uniform thickness on the surface metal layer of the circuit board, and forming a first metal layer connecting the surface metal layer and the target internal circuit layer on the inner wall of each hole included in the hole-dense area on the surface of the circuit board;

[0133] In which, the circuit board includes a surface metal layer on the surface of the circuit board, a first insulating layer on the bottom surface of the circuit board, and at least one internal circuit layer located between the surface metal layer and the first insulating layer, a second insulating layer is arranged between adjacent internal circuit layers, and a third insulating layer is arranged between the surface metal layer and the internal circuit layer adjacent to the surface metal layer. The partial layers of the target edge of the circuit board are the surface metal layer and the third insulating layer at the target edge of the circuit board, and the target internal circuit layer is the internal circuit layer adjacent to the surface metal layer.

Claims

1. A circuit board electroplating method, comprising: Removing a portion of the layer at a target edge of the circuit board to expose a target internal circuit layer, wherein the target edge is one edge of the circuit board; Placing the circuit board in a plating solution, and applying a plating current to the target internal circuit layer exposed at the target edge, electroplating the circuit board, forming a first metal layer with uniform thickness on the surface metal layer of the circuit board, and forming a first metal layer connecting the surface metal layer and the target internal circuit layer on the inner wall of each hole included in the hole-dense area on the surface of the circuit board; Among them, the circuit board includes a surface metal layer on the surface of the circuit board, a first insulating layer on the bottom of the circuit board, and at least one internal circuit layer located between the surface metal layer and the first insulating layer, a second insulating layer is arranged between adjacent internal circuit layers, a third insulating layer is arranged between the surface metal layer and the internal circuit layer adjacent to the surface metal layer, the partial layers of the target edge of the circuit board are the surface metal layer and the third insulating layer at the target edge of the circuit board, and the target internal circuit layer is the internal circuit layer adjacent to the surface metal layer.

2. The circuit board electroplating method according to claim 1, before removing part of the layers at the target edge of the circuit board to expose the target internal circuit layer, further comprising: Immersing the circuit board in a deposition liquid, and depositing a second metal layer on the inner wall of each hole and the surface of the surface metal layer by a chemical deposition method, wherein the partial layer at the target edge also includes the second metal layer on the surface metal layer at the target edge; The method comprises: forming a first metal layer with uniform thickness on the surface metal layer of the circuit board, and forming a first metal layer connecting the surface metal layer and the target internal circuit layer on the inner wall of each hole included in the hole-dense area on the surface of the circuit board. A first metal layer with uniform thickness is formed on the second metal layer deposited on the surface metal layer, and a first metal layer connecting the surface metal layer and the target internal circuit layer is formed on the second metal layer deposited on the inner wall of each hole.

3. The circuit board electroplating method according to claim 1, after removing part of the layers at the target edge of the circuit board to expose the target internal circuit layer, further comprising: A groove parallel to the target edge is formed on the surface metal layer, the bottom of the groove exposes the target insulating layer below the surface metal layer, wherein the target insulating layer is the third insulating layer, the groove divides the surface metal layer into a first part close to the target edge and a second part away from the target edge, and the width of the first part is smaller than the width of the second part; The circuit board is immersed in a deposition liquid, and a chemical deposition method is used to deposit the inner wall of each hole and the exposed Depositing a second metal layer on a surface of the target insulating layer, the first portion, and the second portion; removing the first portion and the second metal layer on the first portion to form an insulating isolation zone between the exposed target internal circuit layer and the surface metal layer; Forming a first metal layer with uniform thickness on the surface metal layer of the circuit board, and forming a first metal layer connecting the surface metal layer and the target internal circuit layer on the inner wall of each hole included in the hole-dense area on the surface of the circuit board, comprising: A first metal layer with uniform thickness is formed on the second metal layer deposited on the second portion, and a first metal layer connecting the surface metal layer and the target internal circuit layer is formed on the second metal layer deposited on the inner wall of each hole.

4. The circuit board electroplating method according to claim 3, wherein: Forming a groove parallel to the target edge on the surface metal layer, comprising: A groove parallel to the target edge is formed on the surface metal layer in a gong groove manner.

5. The circuit board electroplating method according to claim 1, after removing part of the layers at the target edge of the circuit board to expose the target internal circuit layer, further comprising: Removing a surface metal layer near an edge of the target edge to expose a target insulating layer under the surface metal layer, wherein the target insulating layer is the third insulating layer; Applying insulating tape to the exposed target insulation layer; Immersing the circuit board in a deposition liquid, and depositing a second metal layer on the inner wall of each hole, the surface of the insulating tape, and the surface of the surface metal layer by a chemical deposition method; Stripping the insulating tape and the second metal layer deposited on the surface of the insulating tape to form an insulating isolation zone between the exposed target internal circuit layer and the surface metal layer; Forming a first metal layer with uniform thickness on the surface metal layer of the circuit board, and forming a first metal layer connecting the surface metal layer and the target internal circuit layer on the inner wall of each hole included in the hole-dense area on the surface of the circuit board, comprising: A first metal layer with uniform thickness is formed on the second metal layer deposited on the surface metal layer, and a first metal layer connecting the surface metal layer and the target internal circuit layer is formed on the second metal layer deposited on the inner wall of each hole.

6. The circuit board electroplating method according to any one of claims 1 to 5, wherein: Removing a portion of the layers at the target edge of the circuit board to expose the target internal circuit layer, including: The blind gong method is used to remove part of the layer at the target edge of the circuit board to expose the target internal circuit layer, the width of the blind gong ranges from 5mm to 12mm, and the length of the blind gong is the length of the target edge.

7. The circuit board electroplating method according to any one of claims 1 to 5, wherein removing a portion of the target edge layer of the circuit board to expose the target internal circuit layer comprises: A portion of the target edge layer on the side of the circuit board where the surface metal layer is provided is removed to expose the target internal circuit layer.

8. The circuit board electroplating method according to any one of claims 1 to 5, wherein: A non-target surface metal layer is formed on the side of the first insulating layer on the bottom surface of the circuit board away from the surface metal layer, and the surface metal layer on the surface of the circuit board is the target surface metal layer; The step of removing a portion of the layers at the target edge of the circuit board to expose the target internal circuit layer comprises: Removing a portion of the target edge layer on one side of the target surface metal layer of the circuit board to expose the target internal circuit layer; The non-target surface metal layer and the first insulating layer at the target edge of the non-target surface metal layer side of the circuit board are removed to expose the internal circuit layer located on the side of the first insulating layer away from the non-target surface metal.

9. The circuit board electroplating method according to any one of claims 1 to 5, wherein: Placing the circuit board in a plating solution and applying a plating current to the target internal circuit layer exposed at the target edge to electroplate the circuit board, including: clamping the target edge of the circuit board with a plurality of plating clamps, the plurality of plating clamps being evenly spaced along the target edge, and the plurality of plating clamps being electrically connected to the target internal circuit layer exposed at the target edge; placing the circuit board in a plating solution; The circuit board is electroplated by applying a plating current to the target internal circuit layer exposed at the target edge through the multiple plating clamps.

10. A circuit board, comprising: The surface metal layer on the surface of the circuit board, the first insulating layer on the bottom surface of the circuit board, and at least one internal circuit layer between the surface metal layer and the first insulating layer, a second insulating layer is arranged between adjacent internal circuit layers, and a third insulating layer is arranged between the surface metal layer and the internal circuit layer adjacent to the surface metal layer; wherein, part of the internal circuit layer adjacent to the surface metal layer at one edge of the circuit board is not covered with the third insulating layer and the surface metal layer, and the exposed part of the internal circuit layer is the target internal circuit layer; A first metal layer with uniform thickness is formed on the surface metal layer, and a first metal layer connecting the surface metal layer and the target internal circuit layer is formed on the inner wall of each hole included in the hole-dense area on the surface of the circuit board.

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