Failure analysis method and apparatus for chip, chip design method and apparatus, and device and medium

Abstract

Provided in the embodiments of the present disclosure are a failure analysis method and apparatus for a chip, a chip design method and apparatus, and a device and a medium. The failure analysis method comprises: acquiring a local failure analysis result of a chip, wherein the local failure analysis result comprises a local failure position where a failure anomaly occurs in the chip, and a process reason corresponding to the failure anomaly occurring at the local failure position; on the basis of the local failure position, determining a suspected failure position of the chip; at the suspected failure position, simulating the process reason; checking whether a failure anomaly has occurred after the process reason is simulated at the suspected failure position, so as to obtain a check report; and on the basis of the check report, generating a failure analysis result of the chip. The embodiments of the present disclosure can broaden the coverage of failure analysis on a chip, provide a relatively comprehensive direction and evidence for improving the chip in production, manufacturing and design stages, and provide a basis for increasing the yield of the chip and reducing the probability of a failure anomaly occurring in the chip.

Description

Chip failure analysis method, chip design method, device, equipment and medium

[0001] This application claims priority to Chinese Patent Application No. 202311197359.8 filed on September 15, 2023. The contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] The embodiments of the present disclosure relate to a chip failure analysis method, a chip design method, an apparatus, a device, and a medium. Background Art

[0003] Chips such as SOCs (System on Chips) often experience failure anomalies such as short circuits, open circuits, and functional failures, necessitating failure analysis (FA) of the chips. However, current FAs focus on localized failure anomalies within a chip, resulting in a relatively low coverage of FAs across the entire chip. Therefore, providing a chip failure analysis solution to improve its coverage has become a pressing technical challenge for those skilled in the art.

[0004] Summary of the Invention

[0005] In view of this, the embodiments of the present disclosure provide a chip failure analysis method, chip design method, device, equipment and medium to improve the coverage of failure analysis on chips; further, the embodiments of the present disclosure can perform chip inspections in the chip design stage based on failure analysis, thereby avoiding failure anomalies through design modifications in advance in the chip design stage.

[0006] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions.

[0007] The present disclosure provides a chip failure analysis method, including:

[0008] Obtaining a local failure analysis result of the chip, wherein the local failure analysis result includes a local failure location where the chip fails abnormally and a process cause corresponding to the failure abnormality at the local failure location;

[0009] Determining a suspected failure location of the chip based on the local failure location, where the suspected failure location is a chip location suspected of having a failure anomaly due to process reasons;

[0010] Simulate process causes at the suspected failure location;

[0011] Checking whether a failure anomaly occurs at the suspected failure location after simulating the process cause, and obtaining an inspection report; and

[0012] Generate chip failure analysis results based on the inspection report.

[0013] The present disclosure provides a chip design method, including:

[0014] Obtain the chip's phased design results;

[0015] Invoking a chip inspection tool, the chip inspection tool recording a chip failure analysis result, the failure analysis result indicating a chip location at which a chip has a failure anomaly risk and a corresponding process cause; wherein the failure analysis result is obtained according to the chip failure analysis method described in the first aspect above;

[0016] Using a chip inspection tool to check whether the phased design results have any failure anomalies at the chip location; and

[0017] If a failure anomaly occurs in the chip position in the phased design result, the phased design result is modified according to the process reason corresponding to the chip position until the modified phased design result does not fail anomaly in the chip position.

[0018] The present disclosure provides a chip failure analysis device, comprising:

[0019] A local result acquisition module is configured to acquire a local failure analysis result of the chip, wherein the local failure analysis result includes a local failure location where the chip fails abnormally and a process cause corresponding to the failure abnormality at the local failure location;

[0020] a suspected location determination module configured to determine a suspected failure location of the chip based on the local failure location, wherein the suspected failure location is a chip location suspected of having a failure anomaly due to process reasons;

[0021] a simulation module configured to simulate a process cause at the suspected failure location;

[0022] An inspection module configured to inspect whether a failure anomaly occurs at the suspected failure location after simulating a process cause, and obtain an inspection report;

[0023] The result generation module is configured to generate a failure analysis result of the chip according to the inspection report.

[0024] An embodiment of the present disclosure provides a chip design device, including:

[0025] A phased result acquisition module configured to acquire the phased design results of the chip;

[0026] a calling module configured to call a chip inspection tool, the chip inspection tool recording a chip failure analysis result, the failure analysis result indicating a chip location at risk of failure anomaly and a corresponding process cause; wherein the failure analysis result is obtained according to the chip failure analysis method described in the first aspect above;

[0027] A design checking module configured to use a chip checking tool to check whether a failure anomaly occurs in a phased design result at the chip location;

[0028] The design modification module is configured to modify the stage design result according to the process reasons corresponding to the chip position if the judgment result of the design check module is that the stage design result has a failure abnormality at the chip position, until the modified stage design result does not have a failure abnormality at the chip position.

[0029] An embodiment of the present disclosure provides a computer device comprising at least one memory and at least one processor, wherein the at least one memory stores one or more computer-executable instructions, and the at least one processor calls the one or more computer-executable instructions to execute a chip failure analysis method as provided in any of the above embodiments, or to execute a chip design method as provided in any of the above embodiments.

[0030] An embodiment of the present disclosure provides a storage medium storing one or more computer-executable instructions. When the one or more computer-executable instructions are executed, the chip failure analysis method provided in any of the above embodiments is implemented, or the chip design method provided in any of the above embodiments is implemented.

[0031] The chip failure analysis method provided by the embodiment of the present disclosure can obtain the local failure analysis results of the chip. The local failure analysis results include the local failure location where the chip failure anomaly occurs and the process cause corresponding to the failure anomaly at the local failure location. Thus, based on the local failure location, the suspected failure location of the chip is determined. The suspected failure location is the chip location suspected of having a failure anomaly due to process reasons. In other words, the embodiment of the present disclosure can determine a wider range of suspected failure locations in the chip that may have a failure anomaly due to process reasons based on the local failure analysis results of the chip. The suspected failure locations are suspected objects that may have a failure anomaly in the chip. To check whether the suspected failure location may have a failure anomaly due to process reasons, the embodiment of the present disclosure can simulate the process cause at the suspected failure location and check whether the failure anomaly occurs after the suspected failure location simulates the process cause, thereby obtaining an inspection report. If the suspected failure location fails after simulating the process cause, it indicates that the suspected failure location has a risk of failure anomaly due to process reasons. Then, the embodiment of the present disclosure can generate the chip failure analysis results based on the inspection report, so that the chip failure analysis results can cover the suspected failure locations with a risk of failure anomaly and the process cause of the suspected failure location.

[0032] The disclosed embodiments can improve the coverage of failure analysis on chips by conducting a comprehensive and detailed investigation of the local failure locations and process causes of actual chip failure anomalies, as well as the suspected failure locations and process causes of chip failure anomalies. This provides a more comprehensive direction and evidence for chip improvements in production, manufacturing, and design, and lays a foundation for improving chip yields and reducing the probability of chip failure anomalies. Furthermore, the disclosed embodiments can perform chip inspections during the chip design phase based on failure analysis, thereby avoiding failure anomalies through design modifications in advance during the chip design phase. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are merely embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0034] FIG1 is a flow chart of a chip failure analysis method provided by an embodiment of the present disclosure;

[0035] FIG2A is an example diagram showing a short circuit between metal layers;

[0036] FIG2B is an example diagram showing a short circuit between metal patterns;

[0037] FIG3A is an example diagram of chip layout inspection using an LVS tool;

[0038] FIG3B is an example diagram of chip layout checking using a DRC tool;

[0039] FIG4A is an example diagram of checking a simplified chip layout using an LVS tool;

[0040] FIG4B is an example diagram of checking a simplified chip layout using a DRC tool;

[0041] FIG5 is a comparative example diagram of simulation results;

[0042] FIG6 is an example diagram showing the matching between the eFA layout check result, the simulation result, and the test result;

[0043] FIG7A is an example diagram of current and voltage when a chip pin is short-circuited;

[0044] FIG7B is an example diagram of current and voltage after the chip pins have been cut off from the short-circuit area;

[0045] FIG8 is an example diagram of stages of chip failure analysis according to an embodiment of the present disclosure;

[0046] FIG9 is a flow chart of a chip design method provided by an embodiment of the present disclosure;

[0047] FIG10 is a block diagram of a chip failure analysis device provided by an embodiment of the present disclosure;

[0048] FIG11 is a block diagram of a chip design apparatus provided by an embodiment of the present disclosure; and

[0049] FIG12 is a block diagram of a computing device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0051] In chip manufacturing, wafers are thinned and cut to form numerous dies, which are then packaged into chips. Once the chips are obtained, they undergo testing to distinguish good from defective products. Good products that meet certain reliability standards are released to the market, while defective products are scrapped. To ensure chip quality and reliability, the yield rate must be continuously improved. Therefore, failure analysis is required for defective or abnormally failing chips. This helps identify the location and cause of the failure, providing direction and evidence for improvements in chip manufacturing and design. Therefore, performing failure analysis on chips is crucial.

[0052] It should be noted that failure analysis refers to the use of various electrical, physical, chemical and other equipment and methods to conduct electrical analysis, failure location, physical dissection and analysis on failed samples with failure anomalies, to find the location and cause of the failure anomaly, thereby providing direction and evidence for improvements in production and design.

[0053] In the chip field, the cause of chip failure anomalies may be process problems existing in the actual chip process engineering (for example, chip failure anomalies are caused by chip process problems). Therefore, chip failure analysis can be: locating the failure position where the chip failure anomaly occurs (for example, locating the chip position where failure anomalies such as short circuit, open circuit, and functional failure occur), and analyzing the process reasons corresponding to the failure anomalies at the failure position (the reasons for chip process problems are referred to as process reasons for short); then, verifying the failure position and the corresponding process reasons (for example, verifying whether the failure position is caused by the analyzed process reasons), and then, if the verification is passed, providing direction and evidence for improvement of chip production and design based on the failure analysis results (such as the failure position and the corresponding process reasons).

[0054] Chips can actually have complex failure anomalies (for example, a large chip may have a large number of failure anomalies of various types). Therefore, ideally, a detailed and comprehensive failure analysis of the chip is required for each type of failure anomaly. For example, for each type of failure anomaly, the failure location where the failure anomaly may occur in the chip is determined, as well as the process reasons for the failure anomaly at the failure location, so that the failure analysis can cover the entire chip area. Furthermore, the detailed and comprehensive failure analysis results for each type of failure anomaly provide direction and evidence for improvements in chip manufacturing and design, reducing the risk of chip failure anomalies.

[0055] However, there is currently a lack of technology to conduct more detailed and comprehensive failure analysis on chips. The current failure analysis method mainly focuses on failure analysis of local chip failure anomalies (for example, failure analysis is performed on failure anomalies that occur locally on the chip, and the location and cause of the local failure anomaly on the chip are defined). This results in relatively low coverage of failure analysis on the chip, making it impossible to perform a more comprehensive failure analysis on the chip.

[0056] Based on this, the embodiments of the present disclosure provide a new chip failure analysis solution, which is based on the local failure analysis results of the chip, combined with the relevant analysis of the program or script, extending from the local failure analysis of the chip to a more comprehensive failure analysis of the chip, thereby performing a more detailed and comprehensive failure analysis of the chip and improving the coverage of failure analysis on the chip.

[0057] As an optional implementation, FIG1 exemplarily illustrates an optional flowchart of a chip failure analysis method provided by an embodiment of the present disclosure. This method flow can be executed by a computer device, which can be a computer device running a failure analysis program. The present disclosure does not limit the computer device to whether it is a terminal device or a server device. Referring to FIG1 , this method flow may include the following steps.

[0058] In step S110 , a local failure analysis result of the chip is obtained, where the local failure analysis result includes a local failure location where the chip fails abnormally and a process cause corresponding to the failure abnormality at the local failure location.

[0059] For defective products or chips with failure anomalies, the embodiments of the present disclosure can perform a preliminary failure analysis on the chip. The preliminary failure analysis is a failure analysis of the local failure anomalies of the chip, so the embodiments of the present disclosure can obtain the local failure analysis results of the chip. The local failure analysis results of the chip can include the local failure location where the chip failure anomaly occurs, and the process reasons corresponding to the failure anomaly at the local failure location. For example, when a chip has a failure anomaly, the embodiments of the present disclosure can perform a preliminary failure analysis to determine the local failure location where the chip failure anomaly occurs, and the process reasons corresponding to the failure anomaly at the local failure location.

[0060] In an optional implementation, when conducting preliminary chip failure analysis, the disclosed embodiments can be expanded from multiple dimensions. For example, using experimental equipment to locate the local failure location of the chip failure anomaly, then analyzing the chip yield data, modeling the failure anomaly, and analyzing the assembly equipment involved in chip manufacturing to determine the process cause corresponding to the failure anomaly at the local failure location of the chip.

[0061] It should be noted that, in a possible implementation, a chip may have at least one type of failure anomaly (one type of failure anomaly or multiple types of failure anomalies). The disclosed embodiments can perform a preliminary failure analysis on the chip for each type of failure anomaly, thereby determining the local failure locations of each type of failure anomaly on the chip, as well as the corresponding process causes of the local failure locations. For example, the results of a local failure analysis of a chip can indicate at least one type of failure anomaly on the chip, as well as the local failure locations of each type of failure anomaly on the chip and the corresponding process causes.

[0062] The preliminary failure analysis aims to locate the failure position of the chip where the failure anomaly occurs locally (i.e., the local failure position), as well as the process problem cause of the failure anomaly at the local failure position (i.e., the process cause), and obtain the local failure analysis results of the chip, thereby providing a basis for subsequent detailed and comprehensive failure analysis of the chip; therefore, the embodiments of the present disclosure do not limit the specific implementation means of the preliminary failure analysis, and any method that can locate the local failure position and process cause of the chip failure anomaly can be applied.

[0063] In an optional implementation, the local failure location where the chip failure anomaly occurs may include: the local physical layer location where the chip failure anomaly occurs; and the process cause of the local failure location may be the process cause of the local physical layer location of the chip failure anomaly. In other words, the local failure analysis result of the chip can indicate the local failure location where the failure anomaly occurs from the perspective of the chip's physical layer; and indicate the process cause of the local failure location from the perspective of process defects in the physical layer.

[0064] In an optional implementation example, the physical layer position may be a position between physical layers, or a position inside the physical layer. For example, the physical layer of a chip may be a metal layer of the chip; accordingly, the physical layer position may be a position between metal layers, or a position inside the metal layer (such as a position between metal patterns inside the metal layer, or a position of a certain metal pattern inside the metal layer). Based on this, in an optional implementation, a chip failure anomaly may be a failure anomaly between metal layers, or a failure anomaly between metal patterns of a metal layer, or a failure anomaly inside a metal pattern of a metal layer, etc.; accordingly, the local physical layer position where the chip failure anomaly occurs may include any of the following: a position between local metal layers, a position between local metal patterns, a position of a local metal pattern, etc.

[0065] It should be noted that the positions between the metal layers of the chip involve multiple metal layers of the chip. Therefore, the failure anomalies occurring between the metal layers belong to the failure anomalies occurring in the vertical space of the chip, that is, the chip space corresponding to the failure anomaly is the vertical space; the metal graphics of the chip or the inside of the metal graphics involve the internal conditions of the metal layer. Therefore, the failure anomalies between the metal graphics or the inside of the metal graphics belong to the failure anomalies occurring in the horizontal space of the chip, that is, the chip space corresponding to the failure anomaly is the horizontal space.

[0066] For ease of understanding, taking the failure anomaly of chip short circuit as an example, through preliminary failure analysis, the embodiment of the present disclosure can obtain the local physical layer location where the chip short circuit occurs, and obtain the process reason for the short circuit at the local physical layer location.

[0067] For example, in the vertical space of the chip, a short circuit occurs between metal layers due to process problems. Through preliminary failure analysis, the embodiment of the present disclosure can obtain the location between the local metal layers where the short circuit occurs, as well as the process reasons for the short circuit between the local metal layers.

[0068] In one example, assuming that in the vertical space of the chip, a short circuit occurs between metal layers due to a process defect of insufficient thickness of the isolation layer between the metal layers, then through preliminary failure analysis, the location between the local metal layers where the short circuit occurs can be obtained, and the process reason for the short circuit at the location between the local metal layers is: insufficient thickness of the isolation layer between the local metal layers. For example, FIG2A exemplarily shows an example diagram of a short circuit between metal layers. As shown in FIG2A , in the vertical space of the chip, a short circuit occurs between metal layer 210 and metal layer 220. Then, through preliminary failure analysis, the location between the local metal layers where the short circuit occurs can be located in the vertical space of the chip: the location between metal layer 210 and metal layer 220; at the same time, the process reason for the short circuit at the location between the local metal layers is obtained: insufficient thickness of the isolation layer between metal layer 210 and metal layer 220.

[0069] For example, in the horizontal space of the chip, a short circuit occurs between metal patterns due to process problems. Through preliminary failure analysis, the embodiment of the present disclosure can obtain the location between the local metal patterns where the short circuit occurs, as well as the process reasons for the short circuit between the local metal patterns.

[0070] In one example, assuming that in the horizontal space of the chip, a short circuit occurs between metal patterns due to a process defect of a small spacing between metal patterns, then through preliminary failure analysis, the position between the local metal patterns where the short circuit occurs can be obtained, and the process reason for the short circuit at the position between the local metal patterns is: the spacing between the local metal patterns is small. For example, FIG2B exemplarily shows an example diagram of a short circuit between metal patterns. As shown in FIG2B , in the horizontal space of the chip, a short circuit occurs between metal pattern 201 and metal pattern 202. Then, through preliminary failure analysis, the position between the local metal patterns where the short circuit occurs can be located in the horizontal space of the chip: the position between metal pattern 201 and metal pattern 202; at the same time, the process reason for the short circuit at the position between the local metal patterns is obtained: the spacing between metal pattern 201 and metal pattern 202 is small.

[0071] Taking a chip failure anomaly such as a short circuit (i.e., an open circuit) as an example, through preliminary failure analysis, the disclosed embodiments can determine the local physical layer location of the chip short circuit and the process cause of the short circuit at that local physical layer location. For example, in the horizontal space of the chip, a short circuit may occur within the metal pattern due to process reasons such as the small spacing between metal patterns. Accordingly, through preliminary failure analysis, the disclosed embodiments can locate the location of the local metal pattern where the short circuit occurs in the horizontal space of the chip and determine that the process cause of the short circuit at that local metal pattern location is the small spacing between metal patterns in the horizontal space.

[0072] In step S120 , the suspected failure location of the chip is determined according to the local failure location.

[0073] Different from manually searching for suspected locations of possible failure anomalies in the chip layout based on experience, the embodiment of the present disclosure can determine the suspected failure locations of possible failure anomalies in the chip based on the local failure locations after obtaining the local failure analysis results of the chip, so as to realize the automated search for chip locations of suspected possible failure anomalies in the chip layout. It should be explained that the local failure location is the actual location of the chip failure anomaly located by preliminary failure analysis, while the suspected failure location can be regarded as the chip location suspected by the embodiment of the present disclosure as possibly having failure anomalies due to process reasons (i.e., the suspected failure location is a suspected object of possible failure anomalies); for example, the suspected failure location may have failure anomalies due to process reasons, or may not have failure anomalies due to process reasons, and needs to be checked later.

[0074] In an optional implementation, the embodiment of the present disclosure may search for a location in the chip that corresponds to the location attribute of the local failure location based on the location attribute of the local failure location, and use the location as the suspected failure location of the chip.

[0075] Optionally, the local failure location may be a local physical layer location where the chip failure anomaly occurs, such as any of the following: a location between local metal layers, a location between local metal patterns, a location at a local metal pattern, etc. Accordingly, the suspected failure location may be a suspected physical layer location in the chip where the failure anomaly is suspected to occur, such as any of the following: a location between suspected metal layers, a location between suspected metal patterns, a location at a suspected metal pattern, etc.

[0076] In an optional implementation, to facilitate the search for suspected failure locations, the disclosed embodiment may set the location attributes of the local failure location to: the chip space corresponding to the local physical layer location, and the physical layer type of the local physical layer. Thus, in an optional implementation, the disclosed embodiment may search for a location in the chip corresponding to the physical layer type of the local physical layer based on the chip space corresponding to the local physical layer location, thereby obtaining a suspected physical layer location in the chip where a failure anomaly may occur. Optionally, the corresponding physical layer type may be, for example, the same physical layer type or a similar physical layer type (the standard for similar physical layer types may be set according to actual conditions).

[0077] In an implementation example, taking the case where the thickness of the isolation layer between local metal layers is insufficient, resulting in a short circuit between the local metal layers as an example (such as shown in the example of FIG2A ), the local failure position may be the position between the local metal layers where the short circuit occurs, and the position attribute may indicate the vertical space of the chip, as well as the type of the local metal layer; thus, the embodiment of the present disclosure may search for suspected metal layers corresponding to the type of the local metal layer (for example, search for suspected metal layers of the same or similar type as the local metal layer) in the vertical space of the chip based on the position attribute of the position between the local metal layers, and use the position between the found suspected metal layers as the suspected physical layer position. For example, when the local failure analysis result indicates that a short circuit occurs between two local metal layers, the embodiment of the present disclosure may search for other two metal layers of corresponding type in the vertical space of the chip based on the type of the two local metal layers where the short circuit occurs, and regard the position between the other two metal layers found as the position between the suspected metal layers where a short circuit may occur.

[0078] In another implementation example, taking the case where the spacing between local metal patterns is small, resulting in a short circuit between the local metal patterns as an example (such as shown in the example of FIG2B ), the local failure position can be the position between the local metal patterns where the short circuit occurs, and the position attribute can indicate the horizontal space of the chip and the type of the local metal pattern; thus, the embodiment of the present disclosure can search for suspected metal patterns corresponding to the type of the local metal patterns (for example, searching for suspected metal patterns of the same or similar type as the local metal patterns) in the horizontal space of the chip based on the position attribute of the position between the local metal patterns, and use the position between the found suspected metal patterns as the suspected physical layer position. For example, when the local failure analysis result indicates that a short circuit occurs between two local metal patterns, the embodiment of the present disclosure can search for other two metal patterns of corresponding types in the horizontal space of the chip based on the types of the two local metal patterns where the short circuit occurs, and regard the position between the other two metal patterns found as the position between the suspected metal patterns where a short circuit is suspected to occur.

[0079] In another implementation example, taking the case where the spacing between local metal patterns is small, resulting in a short circuit inside the local metal pattern, the embodiment of the present disclosure can search for suspected metal patterns with suspected short circuits in the horizontal space of the chip according to the type of local metal patterns with short circuits inside, and obtain the suspected physical layer position.

[0080] It should be noted that the above description uses short circuits between metal layers, between metal patterns, and within metal patterns as examples to illustrate chip failure anomalies. In practice, other types of failure anomalies may occur between metal layers, between metal patterns, or within metal patterns, and are not limited to these examples. In other words, chip failure anomalies may occur between metal layers, between metal patterns, or within metal patterns. The disclosed embodiments do not limit the types of failure anomalies occurring in these locations, and the specific types depend on the specific circumstances.

[0081] In step S130 , process causes are simulated at suspected failure locations of the chip.

[0082] In step S140 , it is checked whether a failure anomaly occurs after simulating the process cause at the suspected failure location, and an inspection report is obtained.

[0083] After determining the suspected failure location of the chip, in order to conduct a more detailed and comprehensive failure analysis of the chip, the embodiment of the present disclosure can simulate the process cause at the suspected failure location, and check whether the suspected failure location will cause a failure anomaly after simulating the process cause; if the suspected failure location causes a failure anomaly after simulating the process cause, it indicates that there is a risk of failure anomaly due to process reasons at the suspected failure location. The suspected failure location and the process cause simulated at the suspected failure location can be written into the failure analysis results of the chip, so as to avoid introducing process defects that may cause failure anomalies at the suspected failure location during chip production and design.

[0084] That is to say, the significance of simulating the process reasons at the suspected failure locations of the chip in the embodiment of the present disclosure is to comprehensively check the locations where failure anomalies may occur in the chip (such as suspected failure locations), and when there is a risk of failure anomalies due to process reasons at the suspected failure locations, the failure analysis results indicate such risk, so that the chip can avoid such risk during the production and design stages. The embodiment of the present disclosure can improve the coverage of failure analysis on the chip by conducting a comprehensive and detailed investigation of the local failure locations and process reasons where actual failure anomalies of the chip occur, as well as the suspected failure locations and process reasons where there is a risk of failure anomalies of the chip, provide a more comprehensive direction and evidence for the improvement of the chip in the production and design stages, and provide a basis for improving the yield rate of the chip and reducing the probability of failure anomalies of the chip.

[0085] In an optional implementation, the disclosed embodiments can modify the inspection rules for suspected failure locations in the code file of a chip inspection tool to simulate the design corresponding to the process cause at the suspected failure location, thereby simulating the process cause at the suspected failure location. Optionally, the chip inspection tool can be used to perform a layout inspection on the chip. Furthermore, the chip inspection tool can be used to perform a chip layout inspection to check whether a failure anomaly occurs at the suspected failure location during the chip layout inspection process, and obtain an inspection report.

[0086] It should be noted that the chip inspection tool that performs layout inspection on the chip has a code file for executing the layout inspection, and the code file expresses the inspection rules for inspecting the chip layout (such as inspection code, rule critical values ​​of chip layout positions, etc.); wherein, the inspection code of the code file can describe the inspection position of the chip (for example, the metal layer that needs to be inspected, etc.) and the inspection logic of the inspection position (for example, checking whether the metal layer is connected, whether the spacing between the metal layers is too close, etc.). Therefore, the embodiment of the present disclosure can modify the inspection rules of the suspected failure position in the code file of the chip inspection tool according to the process cause that needs to be simulated at the suspected failure position (for example, finding the process cause corresponding to the local failure position based on which the suspected failure position is based), so as to simulate the design corresponding to the process cause at the suspected failure position, thereby simulating the process cause at the suspected failure position.

[0087] In one example, the chip inspection tool for performing layout inspection can be, for example, an LVS (Layout Verse Schematic) tool, a DRC (Design Rule Check) tool, an ERC (Electrical Rule Checking) tool, an ESD (Electro Static Discharge) tool, etc. It should be noted that the LVS tool is used to verify the consistency between the connection relationship of the devices in the chip layout and the schematic diagram, and to verify the consistency between the properties of the devices in the chip layout and the schematic diagram. The DRC tool is used to check whether the graphic spacing, size, overlap, etc. in the chip layout meet the process requirements. Inspections can be performed on the geometric figures of the chip layout to ensure that the layout data can be produced and a higher yield can be obtained on a given integrated circuit process technology. The ERC tool is used to check whether there are electrical connection problems in the chip layout.

[0088] In an optional implementation, the embodiment of the present disclosure can simulate the process cause at the suspected failure location by adding a new inspection code for the suspected failure location in the code file of the chip inspection tool without changing the original design of the suspected failure location, and the newly added inspection code expresses that the suspected failure location has a design corresponding to the process cause.

[0089] In an implementation example, taking the suspected failure position as the position between the suspected metal layers as an example, the embodiment of the present disclosure can add a new inspection code between the suspected metal layers in the code file of the chip inspection tool, and the newly added inspection code expresses that the suspected metal layers have a connection relationship corresponding to the process reason, thereby simulating the process reason at the position between the suspected metal layers. For example, assuming that the local failure analysis result indicates that the thickness of the isolation layer between the local metal layers is insufficient, resulting in a short circuit at the position between the local metal layers, the embodiment of the present disclosure can add a new inspection code between the suspected metal layers in the code file of the chip inspection tool after finding the position between the suspected metal layers where the short circuit may occur, and the newly added inspection code expresses that the suspected metal layers have a connection relationship with the connection layer, thereby simulating the process reason of insufficient thickness of the isolation layer between the suspected metal layers.

[0090] For ease of understanding, it is assumed that the position between the suspected metal layers is the position between the metal layer M1 and the metal layer M2 (that is, it is suspected that a short circuit will occur between the metal layer M1 and the metal layer M2 due to a process defect of insufficient isolation layer thickness). If the original connection design of the metal layer M1 and the metal layer M2 is that the metal layer M1 and the metal layer M2 are connected through vias, for example, the metal layer M1 and the metal layer M2 are connected through through-holes (Via), then in order to simulate the process defect of insufficient isolation layer thickness between the metal layer M1 and the metal layer M2, the embodiment of the present disclosure can add an inspection code between the metal layer M1 and the metal layer M2 in the code file of the chip inspection tool, and the newly added inspection code expresses that the metal layer M1 and the metal layer M2 are connected through a connection layer. In other words, the metal layer M1 and the metal layer M2 were originally connected through a through-hole (Via). The embodiment of the present disclosure can, on the basis of the original connection relationship, add an inspection code so that the metal layer M1 and the metal layer M2 have a connection relationship through a connection layer in addition to the connection relationship through the through-hole. In one example, the embodiment of the present disclosure can add a new checking code in the code file of the LVS tool to add a connection relationship between the metal layer M1 and the metal layer M2 that are suspected of having a short circuit.

[0091] In another optional implementation, if the suspected failure location is inside the metal layer, the embodiment of the present disclosure can modify the rule critical value of the metal layer in the code file of the chip inspection tool based on process reasons to simulate the process reasons inside the metal layer. In an implementation example, taking the suspected failure location as the position between suspected metal patterns, or the position of a suspected metal pattern as an example, since the suspected failure location is the dimension of the suspected metal pattern (such as the position between suspected metal patterns, or the position of a suspected metal pattern), it is suspected that the location where the failure anomaly exists is inside the metal layer, so that the embodiment of the present disclosure can simulate the process reasons by modifying the rule critical value of the metal layer where the suspected metal pattern is located in the code file of the chip inspection tool based on process reasons.

[0092] For example, the disclosed embodiments can modify the rule critical values ​​of the metal layer where the suspected metal pattern is located in the code file of the chip inspection tool to simulate the process cause at the location between the suspected metal layers, or to simulate the process cause at the location of the suspected metal pattern. For example, if it is suspected that there is a short circuit between the metal patterns, or if it is suspected that there is a break inside the metal pattern, the rule critical values ​​related to the space of the metal layer where the metal pattern is located can be modified, thereby adjusting the internal space design of the metal layer, and simulating the process cause between the metal patterns inside the metal layer, or inside a certain metal pattern.

[0093] It should be noted that chip inspection tools such as LVS and DRC have code files for inspecting chip layouts, and these code files contain inspection code. By adjusting and modifying the code files of chip inspection tools such as LVS and DRC, it is possible to simulate process causes at suspected failure locations. Furthermore, during the chip layout inspection process, it is possible to check whether corresponding failure anomalies occur after simulating process causes at suspected failure locations. Based on this concept, the embodiments of the present disclosure do not limit the modification of code files of chip inspection tools such as LVS and DRC to simulate process causes at suspected failure locations. The simulation methods described above from the perspective of metal layers and metal patterns are provided only as optional examples.

[0094] After simulating the process cause at the suspected failure location, the embodiment of the present disclosure can check whether a failure anomaly occurs at the suspected failure location and obtain an inspection report. The inspection report can indicate the process cause simulated at the suspected failure location and whether a failure anomaly occurs at the suspected failure location. In an optional implementation, the embodiment of the present disclosure can utilize chip inspection tools such as LVS and DRC to perform a chip layout inspection after simulating the process cause at the suspected failure location, thereby checking whether a failure anomaly occurs at the suspected failure location and obtaining an inspection report. For example, after adding a connection layer between suspected metal layers suspected of short circuit, a chip layout inspection is performed to check whether a short circuit occurs between the suspected metal layers.

[0095] In an optional implementation, the disclosed embodiments can utilize chip inspection tools such as LVS and DRC to perform chip layout checks after simulating process causes at suspected failure locations. Inspection reports can then be generated using reporting tools in electronic design assistance software, such as signoff tools. Signoff is a crucial concept in chip design, serving as a marker of successful completion of all chip design checks.

[0096] In a further implementation example, step S120 and step S130 can be implemented by a program or script. For example, by writing a relevant program or script, after obtaining the local failure analysis result of the chip, the local failure analysis result of the chip is input into the program or script, so as to automatically determine the suspected failure position of the chip through the program or script, and modify the code files of chip inspection tools such as LVS and DRC through the program or script to simulate process reasons at the suspected failure position of the chip; then, the chip layout inspection is performed through chip inspection tools such as LVS and DRC to check whether failure anomalies occur at the suspected failure position, and the inspection report is output using the Signoff tool.

[0097] It should be noted that the embodiment of the present disclosure is based on the preliminary failure analysis, and uses a program or script to determine a more comprehensive list of suspected failure locations in the chip that may have a risk of failure anomalies, and simulates the process reasons at the suspected failure locations, and then performs chip layout inspection through chip inspection tools such as LVS and DRC to check whether the suspected failure locations have failure anomalies after simulating the process reasons. Therefore, in the embodiment of the present disclosure, chip inspection tools such as LVS and DRC can perform a more comprehensive and detailed failure analysis when performing chip layout inspection, that is, they can more comprehensively and detailedly check whether the suspected failure locations will have failure anomalies when there are process reasons, and derive a more comprehensive and detailed relationship between the suspected failure locations, process reasons and failure anomalies, thereby improving the coverage of failure analysis on the chip. Based on this, the chip layout inspection performed by chip inspection tools such as LVS and DRC in the embodiment of the present disclosure can also be called eFA (electrical failure analysis) layout inspection. eFA can be understood as chip failure analysis through non-destructive means such as electrical analysis.

[0098] It should be further explained that, as an optional implementation, there may be multiple suspected failure locations for a given type of failure anomaly. For any given type of failure anomaly, the embodiments of the present disclosure can modify the inspection rules for each suspected failure location in the code file of the chip inspection tool, simulate the design corresponding to the process cause at each suspected failure location, and check each suspected failure location for failure anomalies. In other words, for any given type of failure anomaly, when determining multiple suspected failure locations for that type of failure anomaly, the embodiments of the present disclosure can modify the inspection rules one by one in the code file of the chip inspection tool and check each suspected failure location for failure anomalies.

[0099] In step S150 , a failure analysis result of the chip is generated according to the inspection report.

[0100] After checking whether a suspected failure location has experienced an anomaly, embodiments of the present disclosure can generate an inspection report. The inspection report can indicate each suspected failure location, the process cause simulated for each suspected failure location, and whether each suspected failure location has experienced an anomaly. If the inspection report indicates that a suspected failure location has experienced an anomaly after simulating the process cause, it can be confirmed that the suspected failure location has a risk of an anomaly due to the process issue corresponding to the process cause.

[0101] In an optional implementation, the disclosed embodiments can generate a chip failure analysis result based on the suspected failure location where the failure anomaly occurred, as indicated in the inspection report, and the simulated process cause of the suspected failure location. In other words, the chip failure analysis result can indicate the suspected failure location where the failure anomaly occurred, as well as the simulated process cause of the suspected failure location, to avoid introducing process defects that could cause the failure anomaly at the suspected failure location during chip manufacturing and design.

[0102] In another optional implementation, the disclosed embodiments can combine the local failure analysis results of the chip, as well as the suspected failure locations where the failure anomaly occurred as indicated in the inspection report, and the process causes simulated at the suspected failure locations, to generate a failure analysis result for the chip. In other words, the chip failure analysis result can indicate the local failure locations where the failure anomaly occurred, the process causes corresponding to the local failure locations, as well as the suspected failure locations where the failure anomaly occurred as indicated in the inspection report, and the process causes simulated at the suspected failure locations, thereby providing a failure analysis result that combines preliminary failure analysis with eFA layout inspection, making the failure analysis result more comprehensive and detailed.

[0103] In a further optional implementation, the embodiment of the present disclosure may generate a chip failure analysis result based on the inspection report if the inspection report passes the accuracy verification and / or the rationality verification. For example, after obtaining the inspection report, the embodiment of the present disclosure may verify the accuracy of the inspection report; if the inspection report passes the accuracy verification, then execute step S150. For another example, after obtaining the inspection report, the embodiment of the present disclosure may verify the rationality of the inspection report; if the inspection report passes the rationality verification, then execute step S150. For another example, after obtaining the inspection report, the embodiment of the present disclosure may verify the accuracy and rationality of the inspection report; if the inspection report passes the accuracy verification and the rationality verification, then execute step S150.

[0104] In an optional implementation, the accuracy of the inspection report can be verified by testing, simulation, etc. For example, the inspection report is compared with the test results and / or simulation results, and when the inspection report matches the test results and / or simulation results, it is confirmed that the inspection report has passed the accuracy verification. It should be noted that the inspection report is obtained through the eFA layout inspection process of chip inspection tools such as LVS and DRC, and the inspection report can indicate the suspected failure location where the failure anomaly occurs and the process reason simulated by the suspected failure location; thus, based on the suspected failure location and process reason of the failure anomaly indicated by the inspection report, it can be verified from the perspectives of testing, simulation, etc. whether the suspected failure location will correspondingly cause a failure anomaly in the presence of a process reason, and then the accuracy of the inspection report can be verified from multiple dimensions. There can be many ways to verify the accuracy of the inspection report, and the embodiments of the present disclosure are not limited thereto.

[0105] In an optional implementation, the embodiment of the present disclosure can perform failure analysis (FA) on the chip based on the suspected failure location where the failure anomaly occurs as indicated in the inspection report to verify the rationality of the inspection report; for example, it is determined whether the failure anomaly at the suspected failure location disappears after the design corresponding to the process cause is eliminated to determine the rationality of the inspection report.

[0106] The chip failure analysis method provided by the embodiment of the present disclosure can obtain the local failure analysis results of the chip. The local failure analysis results include the local failure location where the chip failure anomaly occurs and the process cause corresponding to the failure anomaly at the local failure location. Thus, based on the local failure location, the suspected failure location of the chip is determined. The suspected failure location is the chip location suspected of having a failure anomaly due to process reasons. In other words, the embodiment of the present disclosure can determine a wider range of suspected failure locations in the chip that may have a failure anomaly due to process reasons based on the local failure analysis results of the chip. The suspected failure locations are suspected objects that may have a failure anomaly in the chip. To check whether the suspected failure location may have a failure anomaly due to process reasons, the embodiment of the present disclosure can simulate the process cause at the suspected failure location and check whether the failure anomaly occurs after the suspected failure location simulates the process cause, thereby obtaining an inspection report. If the suspected failure location fails after simulating the process cause, it indicates that the suspected failure location has a risk of failure anomaly due to process reasons. Then, the embodiment of the present disclosure can generate the chip failure analysis results based on the inspection report, so that the chip failure analysis results can cover the suspected failure locations with a risk of failure anomaly and the process cause of the suspected failure location.

[0107] It can be seen that the embodiments of the present disclosure can improve the coverage of failure analysis on chips by conducting comprehensive and detailed investigations of the local failure locations and process causes of actual chip failure anomalies, as well as the suspected failure locations and process causes of chip failure anomalies, provide a more comprehensive direction and evidence for chip improvements in production, manufacturing and design, and lay a foundation for improving the chip yield and reducing the probability of chip failure anomalies.

[0108] As an optional implementation, after determining the suspected failure position of the chip, the suspected failure position of the chip may be a position between suspected metal layers in the vertical space of the chip. With respect to the vertical space of the chip, the embodiment of the present disclosure can use the LVS tool to perform chip layout inspection, so that the embodiment of the present disclosure can add a new inspection code in the code file of the LVS tool, and express the design corresponding to the process reasons between the suspected metal layers through the newly added inspection code, and use the LVS tool to check whether failure anomalies occur between the suspected metal layers to obtain an inspection report; for example, by adding a new inspection code in the code file of the LVS tool, a new connection relationship is added between the suspected metal layers suspected of having a short circuit, and the LVS tool is used to check whether a short circuit occurs between the suspected metal layers.

[0109] For example, Figure 3A exemplarily shows an example diagram of chip layout check using the LVS tool. As shown in Figure 3A, GDS (Graphic Data System) is the layout data file of the chip, and the GDS can be checked by the LVS tool to realize layout check of the chip; LVSDECK is the parameter configuration file of the LVS tool, which records the code file of the LVS tool; by modifying LVSDECK, the code file of the LVS tool can be modified; thus, the embodiment of the present disclosure can modify LVSDECK to realize adding a new inspection code to the code file of the LVS tool, and express the design corresponding to the process reason between the suspected metal layers through the newly added inspection code; further, by using the LVS tool with the modified LVSDECK to check the GDS, it can be checked whether failure anomalies occur between the suspected metal layers after simulating the design corresponding to the process reason during the layout check of the chip.

[0110] As another optional implementation, the suspected failure location of the chip may be between suspected metal patterns in the horizontal space of the chip, or at the location of the suspected metal patterns, that is, the suspected failure location is located within the metal layer. With respect to the horizontal space of the chip, the embodiments of the present disclosure can utilize a DRC tool to perform chip layout inspection. Thus, the embodiments of the present disclosure can modify the rule thresholds of the metal layer in the code file of the DRC tool to simulate process reasons between metal patterns within the metal layer, or to simulate process reasons within the metal patterns within the metal layer.

[0111] For example, FIG3B exemplarily shows an example diagram of chip layout checking using a DRC tool. As shown in FIG3B , DRC DECK is a parameter configuration file of the DRC tool, which records the code file of the DRC tool. The code file of the DRC tool can be modified by modifying the DRC DECK. Thus, the embodiment of the present disclosure can modify the rule critical value of the metal layer in the code file of the DRC tool by modifying the DRC DECK. Furthermore, by using the DRC tool that modifies the DRC DECK to check the GDS, it is possible to check whether failure anomalies occur between the metal patterns inside the metal layer or after the metal patterns are designed corresponding to the simulation process reasons during the layout inspection of the chip.

[0112] In a further optional implementation, if the amount of data involved in the chip layout inspection is large, the embodiment of the present disclosure can streamline the chip layout data to reduce the amount of data when chip inspection tools such as LVS and DRC perform chip layout inspections, thereby improving processing efficiency. For example, before executing step S140 (i.e., before executing the step of checking whether a failure anomaly occurs after simulating the process cause of the suspected failure location), the embodiment of the present disclosure can streamline the chip layout data to obtain streamlined chip layout data; thus, step S140 can be performed based on the streamlined chip layout data (i.e., checking whether a failure anomaly occurs after simulating the process cause of the suspected failure location can be performed based on the streamlined chip layout data).

[0113] As an optional implementation, when streamlining the chip layout data, portions of the chip layout data that are not related to the suspected failure location can be deleted. For example, embodiments of the present disclosure can delete metal layers from the chip layout data that are not related to the suspected failure location, and delete portions of the circuit layout from the chip layout data that are not related to the suspected failure location. Portions of the chip layout data that are not related to the suspected failure location can be considered portions of the chip layout data that are not listed as suspected failure anomalies.

[0114] As an optional implementation, the embodiment of the present disclosure can also divide the chip layout data into multiple sub-layout data (i.e., divide the large chip layout data into multiple small sub-layout data), and then perform chip layout inspection on each sub-layout data to reduce the amount of data during one inspection by chip inspection tools such as LVS and DRC.

[0115] In an optional implementation example, deleting the portion of the chip layout data that is not related to the suspected failure location and dividing the chip layout data into multiple sub-layout data can be used in combination, or one of them can be selected for use, both of which can achieve the effect of streamlining the chip layout data.

[0116] For example, FIG4A exemplarily shows an example diagram of using the LVS tool to check a simplified chip layout. In combination with FIG3A and FIG4A , the GDS can be simplified by deleting parts that are not related to the suspected failure location and / or dividing it into multiple sub-layout data; thus, after modifying the LVSDECK, the LVS tool that modified the LVSDECK can be used to check the simplified GDS.

[0117] For example, FIG4B exemplarily shows an example diagram of checking a simplified chip layout using a DRC tool. In combination with FIG3B and FIG4B , the GDS can be simplified by deleting parts that are not related to the suspected failure location and / or dividing it into multiple sub-layout data; thus, after modifying the DRC DECK, the simplified GDS can be checked using the DRC tool that modified the DRC DECK.

[0118] In a further optional implementation, after obtaining the inspection report, the embodiment of the present disclosure can further verify the accuracy of the inspection report. Optionally, the embodiment of the present disclosure can verify the accuracy of the inspection report through testing, simulation, etc.

[0119] As an optional implementation, the test can be, for example, an abnormal failure test. In the embodiment of the present disclosure, a design corresponding to the process cause can be introduced at the suspected failure location, and the suspected failure location can be tested to see whether the failure anomaly actually occurs to obtain the test result. Thus, the inspection report can be compared with the test results. If the inspection report and the test results match, the inspection report is deemed to have passed the accuracy verification of the test results. For example, if the suspected failure location and process cause of the failure anomaly indicated in the inspection report match the test results, the inspection report is deemed to have passed the accuracy verification of the test results.

[0120] In one example, abnormal failure tests include short circuit tests, open circuit tests, functional tests, and the like. For example, assuming that the inspection report indicates that the position between the metal layer M1 and the metal layer M2 is the position between the suspected metal layers where a short circuit exists, and the process reason is that the thickness of the isolation layer between the metal layer M1 and the metal layer M2 is insufficient, the embodiment of the present disclosure can perform a short circuit test on the metal layer M1 and the metal layer M2; for example, when performing a short circuit test, the embodiment of the present disclosure can introduce a connection layer between the metal layer M1 and the metal layer M2, and test whether a short circuit actually occurs between the metal layer M1 and the metal layer M2 to obtain a short circuit test result. If the short circuit test result indicates that a short circuit actually occurs between the metal layer M1 and the metal layer M2, the short circuit test result is deemed to match the inspection report.

[0121] Optionally, the test tools used for the test (eg, abnormal failure test) may include, but are not limited to: ATE (Automatic Test Equipment) test system, test source meter, etc., which is not limited in the embodiment of the present disclosure.

[0122] As an optional implementation, simulation can be performed using a simulation tool to simulate the electrical characteristics corresponding to the process cause at the suspected failure location, and simulate whether the suspected failure location has a failure anomaly to obtain a simulation result. The inspection report can then be compared with the simulation results. If the inspection report and the simulation results match, the inspection report is considered to have passed the accuracy verification of the simulation results. For example, if the suspected failure location and process cause of the failure anomaly indicated in the inspection report match the simulation results, the inspection report is considered to have passed the accuracy verification of the simulation results.

[0123] In one example, assuming that the inspection report indicates that the location between metal layer M1 and metal layer M2 is the location between metal layers suspected of having a short circuit, and the process reason is that the thickness of the isolation layer between metal layer M1 and metal layer M2 is insufficient, the embodiments of the present disclosure can use a simulation tool to simulate the connection layer between metal layer M1 and metal layer M2, thereby performing corresponding electrical characteristic simulation between metal layer M1 and metal layer M2, and simulating whether a short circuit exists between metal layer M1 and metal layer M2 to obtain a simulation result. If the simulation result indicates that a short circuit exists between metal layer M1 and metal layer M2, the simulation result is considered to match the inspection report. For example, FIG5 exemplarily shows a comparative example diagram of the simulation results. As shown in FIG5 , the solid line in FIG5 represents the simulation curve of the current and voltage after the electrical characteristic simulation is introduced between the metal layer M1 and the metal layer M2 (for example, the simulation curve of the current and voltage after the connection layer is simulated between the metal layer M1 and the metal layer M2), and the dotted line in FIG5 represents the simulation curve of the current and voltage before the electrical characteristic simulation is introduced between the metal layer M1 and the metal layer M2 (for example, the simulation curve of the current and voltage before the connection layer is simulated between the metal layer M1 and the metal layer M2). It can be seen that after the electrical characteristic simulation is introduced between the metal layer M1 and the metal layer M2, a short circuit occurs between the metal layer M1 and the metal layer M2.

[0124] In an optional implementation, if the inspection report of the embodiment of the present disclosure matches the test results and / or simulation results, it can be considered that the inspection report has passed the accuracy verification. For example, the embodiment of the present disclosure can confirm that the inspection report has passed the accuracy verification when the inspection report matches both the test results and the simulation results. For example, based on the fact that the inspection report is the result of the eFA layout inspection, when the simulation results, the eFA layout inspection results, and the test results match each other, the embodiment of the present disclosure can confirm that the result of the eFA layout inspection (i.e., the inspection report) has passed the accuracy verification. Taking the short-circuit failure anomaly of the chip pin (PIN) as an example, Figure 6 exemplifies an example diagram of the mutual matching of the eFA layout inspection results, simulation results, and test results, which can be used for reference.

[0125] In a further optional implementation, after obtaining the inspection report, the embodiment of the present disclosure can further verify the rationality of the inspection report. Optionally, the inspection report can indicate the suspected failure location where the failure anomaly occurred and the corresponding process cause, so that based on the suspected failure location where the failure anomaly occurred and the corresponding process cause indicated in the inspection report, the embodiment of the present disclosure can perform actual FA processing. For example, the embodiment of the present disclosure can eliminate the design corresponding to the process cause at the suspected failure location of the chip, and determine whether the failure anomaly at the suspected failure location of the chip is eliminated; if the failure anomaly at the suspected failure location is eliminated after the design corresponding to the process cause is eliminated at the suspected failure location of the chip, it means that the failure anomaly at the suspected failure location is actually caused by the design corresponding to the process cause, and the inspection report is reasonable; thus, the embodiment of the present disclosure can confirm that the inspection report has passed the rationality verification.

[0126] In an optional implementation, the embodiment of the present disclosure may first verify the accuracy of the inspection report, and then perform rationality verification on the inspection report after the inspection report passes the accuracy verification; if the inspection report passes the rationality verification, step S150 shown in Figure 1 may be executed (i.e., generating a failure analysis result of the chip based on the inspection report).

[0127] For example, taking the failure anomaly of a short circuit in a chip pin indicated in the inspection report as an example, the voltage and current of the chip pin when the process reason indicated in the inspection report exists can be measured through testing, simulation, etc. to verify whether the chip pin has a short circuit. Correspondingly, Figure 7A exemplarily shows an example diagram of the current and voltage of a chip pin short circuit. It can be seen from Figure 7A that when the pin has the process reason indicated in the inspection report, the voltage and current of the test and simulation show that the pin is short-circuited. In order to verify the rationality of the inspection report, the design corresponding to the short-circuit area of ​​the chip pin indicated in the inspection report can be eliminated, such as using FIB (Focused Ion Beam) to cut off the short-circuit area of ​​the chip pin (the short-circuit area can correspond to the process reason for the short circuit of the chip pin indicated in the inspection report), and then measure the voltage and current of the pin; accordingly, Figure 7B exemplarily shows an example diagram of the current and voltage after the short-circuit area of ​​the chip pin is cut off. It can be seen from Figure 7B that after the short-circuit area is cut off, the voltage and current of the pin return to normal from the short circuit; thereby, the rationality of the short circuit of the chip pin indicated in the inspection report and the corresponding process reason can be verified.

[0128] In an optional implementation, the chip failure analysis solution provided by the embodiment of the present disclosure may involve the stages shown in Figure 8, thereby ensuring accuracy and rationality while improving the coverage of the failure analysis on the chip. Optionally, Figure 8 exemplarily illustrates an example diagram of the stages of chip failure analysis provided by the embodiment of the present disclosure. As shown in Figure 8, the chip failure analysis may include the following stages.

[0129] Preliminary failure analysis stage 801. In the preliminary failure analysis stage 801, the embodiment of the present disclosure can perform preliminary failure analysis on defective products or chips with failure anomalies, so as to obtain local failure analysis results of the chips. The local failure analysis results include the local failure location where the chip failure anomaly occurs, and the process reasons corresponding to the local failure location.

[0130] During the eFA layout check phase 802, embodiments of the present disclosure can automatically determine suspected chip failure locations based on local failure locations by programming a program or script. Within the code file of the chip check tool, the check rules for the suspected failure locations are modified to simulate process causes at the suspected failure locations. Furthermore, the chip check tool performs a chip layout check to determine whether failure anomalies have occurred at the suspected failure locations and generate an inspection report. Furthermore, prior to performing the chip layout check, embodiments of the present disclosure can streamline the chip layout data, thereby reducing the amount of data required for the chip layout check.

[0131] Accuracy verification stage 803. In the accuracy verification stage 803, the embodiment of the present disclosure can verify the accuracy of the inspection report through testing, simulation, etc.; for example, the inspection report is data-checked with the test results and simulation results, and the accuracy of the inspection report is verified by determining whether the inspection report matches the test results and simulation results.

[0132] In the rationality verification stage 804, the embodiment of the present disclosure may perform actual FA verification on the chip according to the instructions of the inspection report, thereby verifying the rationality of the inspection report. Optionally, the embodiment of the present disclosure may further verify the rationality of the inspection report if the inspection report passes the accuracy verification.

[0133] Failure analysis result generation stage 805: In this stage, embodiments of the present disclosure can generate chip failure analysis results based on the inspection report, providing comprehensive direction and evidence for chip improvements in manufacturing and design. Optionally, embodiments of the present disclosure can generate chip failure analysis results based on the inspection report after the inspection report has passed accuracy and rationality verification.

[0134] The optional implementation methods of each stage of the example in Figure 8 can be referred to the description of the corresponding parts in the previous text and will not be repeated here.

[0135] Optionally, the failure analysis solution provided by the embodiment of the present disclosure is to analyze defective chips or chips that have failure anomalies due to process problems during chip production and manufacturing, and to perform failure analysis in the chip production and manufacturing link after chip design. Furthermore, based on the idea of ​​the failure analysis solution provided by the embodiment of the present disclosure, the embodiment of the present disclosure can improve the chip inspection process in the chip design stage, so as to avoid failure anomalies through design modifications in advance in the chip design stage; that is, the embodiment of the present disclosure can avoid similar failure anomalies in the failure analysis stage from recurring through inspection means in the chip design stage. As an optional implementation, Figure 9 exemplifies an optional flow chart of the chip design method provided by the embodiment of the present disclosure. The method can be executed and implemented by a computer device equipped with chip design auxiliary software. As shown in Figure 9, the method flow may include the following steps.

[0136] In step S910 , the phased design results of the chip are obtained.

[0137] Chip design has multiple design phases. The disclosed embodiments can obtain interim design results for a chip after the chip completes a set design phase. Examples of interim design results include the netlist result after the chip completes the netlist design phase, or the layout design result after the chip completes the layout design phase.

[0138] In step S911, a chip inspection tool is called, and the chip inspection tool records a failure analysis result of the chip. The failure analysis result indicates the chip location where there is a risk of abnormal failure of the chip and the corresponding process reason.

[0139] After obtaining the interim design results of the chip, the embodiment of the present disclosure can call a chip inspection tool based on failure analysis (such as an LVS tool, a DRC tool, etc.) to perform chip design inspection using the chip inspection tool based on failure analysis, thereby checking whether the chip has a failure anomaly at a chip position where there is a risk of failure anomaly. In the embodiment of the present disclosure, chip inspection tools such as LVS tools and DRC tools can record the failure analysis results of the chip, and the failure analysis results of the chip can be obtained according to the chip failure analysis method provided by the embodiment of the present disclosure. The optional method of obtaining the failure analysis results of the chip can refer to the description of the corresponding part above.

[0140] In an optional implementation, the chip failure analysis results recorded by the chip inspection tool can indicate the chip locations at risk of failure anomalies and the corresponding process causes; the chip locations at risk of failure anomalies can correspond to the suspected failure locations in the inspection report that has been verified for accuracy and rationality. For example, after the inspection report has been verified for accuracy and rationality, the embodiments of the present disclosure can apply the suspected failure locations and corresponding process causes indicated in the inspection report to the chip design inspection process, thereby avoiding chip failure anomalies in advance during the chip design stage.

[0141] In step S912, a chip inspection tool is used to check whether the phased design result has a failure anomaly at the chip position; if so, step S913 is executed; if not, step S914 is executed.

[0142] The disclosed embodiments can utilize chip inspection tools such as LVS tools and DRC tools to inspect the chip's phased design results during the chip design phase, and utilize the failure analysis results to indicate chip locations with failure anomaly risks and the corresponding process reasons during the inspection.

[0143] If a failure occurs at a chip location where there is a risk of failure during the inspection of the phased design results, it means that if subsequent chip production and manufacturing is carried out according to the phased design results, there is a high probability that the chip at that chip location will have a risk of failure due to process reasons. In this case, the phased design results need to be modified to avoid the risk.

[0144] If no failure occurs at a chip location with a risk of failure during inspection of the phased design results, it means that subsequent chip production and manufacturing will be carried out in accordance with the phased design results, and there is a high probability that there will be no risk of failure at that chip location. The phased design results can be confirmed to have passed the inspection.

[0145] In step S913, the phased design result is modified according to the process reasons corresponding to the chip position, and the process returns to step S912.

[0146] When a staged design result fails abnormally at a chip location that is at risk of failure abnormality, the embodiment of the present disclosure can modify the staged design result based on the process reasons corresponding to the chip location to attempt to overcome the failure abnormality problem at the chip location. For the modified staged design result, the embodiment of the present disclosure can return to execute step S912 and recheck whether the modified staged design result fails abnormally at the chip location until the modified staged design result (which may have been modified once or multiple times) does not fail abnormally at the chip location, thereby allowing the design with the failure abnormality risk in the staged design result to be repaired.

[0147] In step S914, it is confirmed that the phased design results have passed the inspection.

[0148] It can be seen that the embodiments of the present disclosure can apply the chip failure analysis results to the inspection link of chip design, thereby avoiding chip failure anomalies in advance in the chip design stage and improving chip design performance and production yield.

[0149] In an optional implementation, failure anomalies caused by process reasons of the chip can be overcome in the process link of chip production and manufacturing; if the failure anomalies caused by process reasons cannot be overcome in the process link of chip production and manufacturing, the inspection process of the chip design stage can be adjusted in the chip design stage, and guidance can be provided for modifying the phased design results of the chip, so as to avoid failure anomalies in the chip design stage.

[0150] The solution provided by the embodiment of the present disclosure can conduct a comprehensive and detailed investigation of the local failure location and process reasons of the actual failure anomaly of the chip, as well as the suspected failure location and process reasons of the chip with the risk of failure anomaly. It can improve the coverage of failure analysis on the chip, provide a more comprehensive direction and evidence for the improvement of the chip in the production, manufacturing and design links, and provide a basis for improving the yield rate of the chip and reducing the probability of failure anomaly of the chip. Optionally, the solution provided by the embodiment of the present disclosure can be implemented by writing a program or script, and the inspection efficiency of the failure analysis is relatively high. Furthermore, the embodiment of the present disclosure can apply the failure analysis results to the inspection process of the chip stage design, so as to avoid failure anomaly problems in advance in the chip design stage and improve the chip design performance.

[0151] The following describes the chip failure analysis device provided in the embodiments of the present disclosure. The description of the failure analysis device below can be considered the functional modules required by a computer device to implement the failure analysis method provided in the embodiments of the present disclosure. The description below can be used in conjunction with the description above.

[0152] As an optional implementation, FIG10 exemplarily shows an optional block diagram of a chip failure analysis device provided by an embodiment of the present disclosure. As shown in FIG10 , the device may include:

[0153] The local result acquisition module 101 is used to obtain the local failure analysis results of the chip, wherein the local failure analysis results include the local failure location where the chip failure anomaly occurs and the process cause corresponding to the failure anomaly at the local failure location;

[0154] A suspected location determination module 102 is configured to determine a suspected failure location of a chip based on the local failure location, wherein the suspected failure location is a chip location suspected of having a failure anomaly due to process reasons;

[0155] A simulation module 103 is used to simulate the process cause at the suspected failure location;

[0156] An inspection module 104 is configured to inspect whether a failure anomaly occurs at the suspected failure location after simulating the process cause, and obtain an inspection report;

[0157] The result generation module 105 is used to generate a failure analysis result of the chip according to the inspection report.

[0158] Optionally, the local result acquisition module 101, the suspected position determination module 102, the simulation module 103 and the result generation module 105 can be implemented by writing programs or scripts, and the inspection module 104 can be implemented by chip inspection tools such as LVS tools and DRC tools.

[0159] Optionally, the simulation module 103 is configured to simulate the process cause at the suspected failure location, including:

[0160] In a code file of a chip inspection tool, the inspection rules of the suspected failure location are modified to simulate a design corresponding to the process cause at the suspected failure location; wherein the chip inspection tool is used to perform layout inspection on the chip.

[0161] Optionally, in one aspect, the simulation module 103 is configured to modify the inspection rules of the suspected failure location in the code file of the chip inspection tool to simulate the design corresponding to the process cause at the suspected failure location, including:

[0162] In the code file of the chip inspection tool, an inspection code for the suspected failure position is added, and the newly added inspection code expresses that the suspected failure position has a design corresponding to the process reason.

[0163] Optionally, the simulation module 103 is configured to add a check code for a suspected failure location in a code file of a chip inspection tool, wherein the newly added check code expresses that the suspected failure location has a design corresponding to a process cause, including:

[0164] If the suspected failure location is between suspected metal layers, a new inspection code between the suspected metal layers is added to the code file of the chip inspection tool, and the newly added inspection code expresses that the suspected metal layers have a connection relationship corresponding to the process reason;

[0165] The positions between the suspected metal layers are determined according to the positions between the local metal layers where the chip failure anomaly occurs.

[0166] Optionally, on the other hand, the simulation module 103 is configured to modify the inspection rules of the suspected failure location in the code file of the chip inspection tool to simulate the design corresponding to the process cause at the suspected failure location, including:

[0167] If the suspected failure location is inside the metal layer, the rule threshold of the metal layer is modified in the code file of the chip inspection tool based on process reasons.

[0168] Optionally, the simulation module 103 is configured to modify the rule threshold of the metal layer in the code file of the chip inspection tool according to process reasons if the suspected failure location is inside the metal layer, including:

[0169] If the suspected failure location is between suspected metal patterns or at the location of suspected metal patterns, then based on process reasons, modify the rule threshold value of the metal layer where the suspected metal pattern is located in the code file of the chip inspection tool;

[0170] The positions of the suspected metal patterns are determined according to the positions of the local metal patterns where the chip fails abnormally, and the positions of the suspected metal patterns are determined according to the positions of the local metal patterns where the chip fails abnormally.

[0171] Optionally, the suspected location determining module 102 is configured to determine the suspected failure location of the chip according to the local failure location, including:

[0172] According to the location attribute of the local failure location, a location corresponding to the location attribute of the local failure location is searched in the chip as the suspected failure location of the chip.

[0173] Optionally, the local failure location includes a local physical layer location; the suspected failure location includes: a suspected physical layer location; the location attributes of the local failure location include: a chip space corresponding to the local physical layer location, and a physical layer type of the local physical layer;

[0174] The suspected location determination module 102 is configured to search for a location in the chip that corresponds to the location attribute of the local failure location based on the location attribute of the local failure location. The suspected failure location of the chip includes:

[0175] Based on the chip space corresponding to the local physical layer position, a position corresponding to the physical layer type of the local physical layer is searched in the chip to obtain a suspected physical layer position.

[0176] Optionally, the local physical layer position includes any one of the following: the position between local metal layers, the position between local metal patterns, and the position of local metal patterns; the suspected physical layer position includes any one of the following: the position between suspected metal layers, the position between suspected metal patterns, and the position of suspected metal patterns.

[0177] Optionally, the inspection module 104 is configured to inspect whether a failure anomaly occurs at the suspected failure location after simulating the process cause, and obtain an inspection report including:

[0178] After simulating the process cause at the suspected failure location, a chip layout inspection is performed using a chip inspection tool to check whether a failure anomaly occurs at the suspected failure location and obtain an inspection report.

[0179] Optionally, the inspection module 104 may obtain an inspection report through a Signoff tool.

[0180] In a further optional implementation, in combination with FIG10 , the apparatus may further include:

[0181] A streamlining module 106 is configured to streamline the chip layout data to obtain streamlined chip layout data before the checking module 104 performs the step of checking whether a failure anomaly occurs after simulating a process cause at the suspected failure location;

[0182] The checking module 104 performs the step of checking whether a failure anomaly occurs after simulating the process cause at the suspected failure location based on the simplified chip layout data.

[0183] Optionally, the streamlining module 106 is configured to streamline the chip layout data, including:

[0184] Delete the portion of the chip layout data that is not related to the suspected failure location;

[0185] And / or, dividing the chip layout data into a plurality of sub-layout data.

[0186] Optionally, the result generation module 105 is configured to generate a chip failure analysis result based on the inspection report, including:

[0187] Form a chip failure analysis result based on the suspected failure location where the failure anomaly occurred as indicated in the inspection report and the process cause simulated at the suspected failure location;

[0188] Alternatively, a failure analysis result of the chip is formed based on the local failure analysis result, the suspected failure location where the failure anomaly occurs indicated in the inspection report, and the process cause simulated at the suspected failure location.

[0189] In a further optional implementation, in combination with FIG10 , the apparatus may further include:

[0190] The accuracy verification module 107 is configured to verify the accuracy of the inspection report before the result generation module 105 performs the step of generating the chip failure analysis result based on the inspection report.

[0191] Optionally, the accuracy verification module 107 is configured to verify the accuracy of the inspection report, including:

[0192] Compare inspection reports with test results and / or simulation results;

[0193] If the inspection report matches the test results and / or simulation results, confirming that the inspection report passes the accuracy verification;

[0194] Among them, for the suspected failure location where the failure anomaly occurs as indicated by the inspection report, the test result is obtained by introducing the design corresponding to the process cause at the suspected failure location, and testing whether the failure anomaly actually occurs at the suspected failure location; for the suspected failure location where the failure anomaly occurs as indicated by the inspection report, the simulation result is obtained by performing electrical characteristic simulation corresponding to the process cause at the suspected failure location through a simulation tool, and performing a simulation test to determine whether the failure anomaly occurs at the suspected failure location.

[0195] In a further optional implementation, in combination with FIG10 , the apparatus may further include:

[0196] The rationality verification module 108 is used to verify the rationality of the inspection report before the result generation module 105 performs the step of generating the chip failure analysis result based on the inspection report.

[0197] Optionally, the rationality verification module 108 is configured to verify the rationality of the inspection report, including:

[0198] Based on the suspected failure locations and corresponding process causes indicated in the inspection report, actual failure analysis is performed to determine whether the failure anomaly at the suspected failure location of the chip has been eliminated after eliminating the design corresponding to the process cause;

[0199] If yes, confirm that the inspection report passes the rationality verification.

[0200] The following describes the chip design apparatus provided in the embodiments of the present disclosure. The chip design apparatus described below can be considered to be the functional modules required by a computer device (e.g., one that has chip design assistance software installed) for implementing the chip design method provided in the embodiments of the present disclosure. The following description can be cross-referenced with the above description.

[0201] As an optional implementation, FIG11 exemplarily shows an optional block diagram of a chip design apparatus provided by an embodiment of the present disclosure. As shown in FIG11 , the apparatus may include:

[0202] The interim result acquisition module 011 is used to acquire the interim design results of the chip;

[0203] A calling module 012 is configured to call a chip inspection tool, wherein the chip inspection tool records a chip failure analysis result, wherein the failure analysis result indicates a chip location at which a chip has a failure anomaly risk and a corresponding process cause; wherein the failure analysis result is obtained according to the chip failure analysis method provided in an embodiment of the present disclosure;

[0204] The design checking module 013 is used to check whether the phased design results have any failure anomalies at the chip location using a chip checking tool;

[0205] The design modification module 014 is configured to modify the phased design result according to the process reasons corresponding to the chip position if the judgment result of the design check module is yes, until the modified phased design result does not cause failure anomalies at the chip position.

[0206] The present disclosure also provides a computer device that can execute the chip failure analysis method or chip design method provided in the present disclosure. As an optional implementation, FIG12 exemplarily illustrates an optional block diagram of a computing device provided in the present disclosure. As shown in FIG12 , the computer device may include: at least one processor 1, at least one communication interface 2, at least one memory 3, and at least one communication bus 4.

[0207] In the embodiment of the present disclosure, there is at least one processor 1 , communication interface 2 , memory 3 , and communication bus 4 , and the processor 1 , communication interface 2 , and memory 3 communicate with each other through the communication bus 4 .

[0208] Optionally, the communication interface 2 may be an interface of a communication module for performing network communication.

[0209] Optionally, processor 1 may be a CPU (central processing unit), a GPU (Graphics Processing Unit), an NPU (embedded neural network processor), an FPGA (Field Programmable Gate Array), a TPU (tensor processing unit), an AI chip, an application-specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present disclosure.

[0210] The memory 3 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0211] The memory 3 stores one or more computer-executable instructions, and the processor 1 calls the one or more computer-executable instructions to execute the chip failure analysis method or chip design method provided by the embodiment of the present disclosure.

[0212] An embodiment of the present disclosure further provides a storage medium storing one or more computer-executable instructions. When the one or more computer-executable instructions are executed, the chip failure analysis method or chip design method provided in the embodiment of the present disclosure is implemented.

[0213] The above describes multiple embodiment schemes provided by the embodiments of the present disclosure. The various optional methods introduced in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiment schemes, which can all be considered as embodiment schemes disclosed and disclosed by the embodiments of the present disclosure.

[0214] Although the embodiments of the present disclosure are disclosed above, the present disclosure is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be based on the scope defined by the claims.

Claims

1. A chip failure analysis method, comprising: Obtaining a local failure analysis result of the chip, the local failure analysis result including a local failure position where a failure anomaly occurs in the chip, and a process cause corresponding to the failure anomaly occurring at the local failure position; Determining a suspected failure position of the chip according to the local failure position, wherein the suspected failure position is a chip position suspected to have the failure anomaly due to the process reason; At the suspected failure location, simulating the process cause; Checking whether the failure abnormality occurs at the suspected failure position after simulating the process cause, and obtaining an inspection report; as well as A failure analysis result of the chip is generated according to the inspection report.

2. The method according to claim 1, wherein: The simulating the process cause at the suspected failure location includes: In a code file of a chip inspection tool, the inspection rules of the suspected failure location are modified to simulate a design corresponding to the process cause at the suspected failure location; wherein the chip inspection tool is used to perform layout inspection on the chip.

3. The method according to claim 2, wherein: The step of modifying the inspection rule of the suspected failure location in the code file of the chip inspection tool to simulate the design corresponding to the process cause at the suspected failure location includes: In the code file of the chip inspection tool, an inspection code for the suspected failure position is newly added, and the newly added inspection code expresses that the suspected failure position has a design corresponding to the process cause.

4. The method of claim 3, wherein: In the code file of the chip inspection tool, a new inspection code for the suspected failure position is added, and the newly added inspection code expresses that the suspected failure position has a design corresponding to the process cause, including: If the suspected failure position is a position between suspected metal layers, in the code file of the chip inspection tool, a new inspection code between the suspected metal layers is added, and the newly added inspection code expresses that the suspected metal layers have a connection relationship corresponding to the process reason; The positions between the suspected metal layers are determined according to the location of the chip where the failure anomaly occurs. The position between the metal layers is determined.

5. The method according to claim 2, wherein: The step of modifying the inspection rule of the suspected failure location in the code file of the chip inspection tool to simulate the design corresponding to the process cause at the suspected failure location includes: If the suspected failure location is inside the metal layer, then based on the process reasons, the rule critical value of the metal layer is modified in the code file of the chip inspection tool.

6. The method according to claim 5, wherein: If the suspected failure location is inside the metal layer, then according to the process reason, in the code file of the chip inspection tool, modifying the rule critical value of the metal layer includes: If the suspected failure position is a position between suspected metal patterns, or a position of the suspected metal pattern, then according to the process reason, in the code file of the chip inspection tool, modify the rule critical value of the metal layer where the suspected metal pattern is located; The positions between the suspected metal patterns are determined according to the positions between the local metal patterns where the failure anomaly occurs in the chip, and the positions of the suspected metal patterns are determined according to the positions of the local metal patterns where the failure anomaly occurs in the chip.

7. The method according to any one of claims 1 to 6, wherein: The determining the suspected failure position of the chip according to the local failure position includes: According to the location attribute of the local failure location, a location corresponding to the location attribute of the local failure location is searched in the chip as the suspected failure location of the chip.

8. The method according to claim 7, wherein: The local failure location includes a local physical layer location; The suspected failure position includes: a suspected physical layer position; the position attribute of the local failure position includes: a chip space corresponding to the local physical layer position, and a physical layer type of the local physical layer; The step of searching, according to the location attribute of the local failure location, for a location in the chip corresponding to the location attribute of the local failure location as the suspected failure location of the chip includes: Based on the chip space corresponding to the local physical layer position, a position corresponding to the physical layer type of the local physical layer is searched in the chip to obtain the suspected physical layer position.

9. The method according to claim 8, wherein: The local physical layer position includes any one of the following: the position between local metal layers, the position between local metal patterns and the position of the local metal pattern; the suspected physical layer position includes any one of the following: the position between suspected metal layers, the position between suspected metal patterns and the position of the suspected metal pattern.

10. The method according to claim 1, wherein: The checking whether the failure abnormality occurs after simulating the process cause at the suspected failure position to obtain an inspection report includes: After simulating the process cause at the suspected failure location, a chip layout check is performed using a chip inspection tool to check whether the failure anomaly occurs at the suspected failure location to obtain the inspection report.

11. The method according to claim 10, wherein: The obtaining of the inspection report includes: obtaining the inspection report through a Signoff tool.

12. The method according to claim 1, wherein: Before executing the step of checking whether the failure anomaly occurs after simulating the process cause at the suspected failure location, the method further includes: The chip layout data is simplified to obtain simplified chip layout data; wherein the step of checking whether the failure anomaly occurs after simulating the process cause at the suspected failure position is performed based on the simplified chip layout data.

13. The method according to claim 12, wherein: The streamlining of the chip layout data includes: Deleting the portion of the chip layout data that is not related to the suspected failure location; and / or The chip layout data is divided into a plurality of sub-layout data.

14. The method according to claim 1, wherein: Generating the failure analysis result of the chip according to the inspection report includes: forming a failure analysis result of the chip according to the suspected failure location where the failure anomaly occurs and the process cause of the suspected failure location indicated in the inspection report; or A failure analysis result of the chip is formed according to the local failure analysis result, the suspected failure location where the failure anomaly occurs indicated in the inspection report, and the process cause of the suspected failure location.

15. The method according to claim 1 or 14, wherein: Before executing the step of generating a failure analysis result of the chip according to the inspection report, the method further includes: Verify the accuracy of said inspection report.

16. The method according to claim 15, wherein: The verification of the accuracy of the inspection report includes: comparing the inspection report with the test results and / or simulation results; and If the inspection report matches the test result and / or the simulation result, confirming that the inspection report passes the accuracy verification; Among them, for the suspected failure location where the failure anomaly occurs as indicated by the inspection report, the test result is obtained by introducing the design corresponding to the process cause at the suspected failure location, and testing whether the failure anomaly actually occurs at the suspected failure location; for the suspected failure location where the failure anomaly occurs as indicated by the inspection report, the simulation result is obtained by using a simulation tool to simulate the electrical characteristics corresponding to the process cause at the suspected failure location, and performing a simulation test to determine whether the failure anomaly occurs at the suspected failure location.

17. The method according to claim 1 or 14, wherein: Before executing the step of generating a failure analysis result of the chip according to the inspection report, the method further includes: Verify the rationality of the inspection report.

18. The method according to claim 17, wherein: The verification of the rationality of the inspection report includes: Based on the suspected failure location where the failure anomaly occurs and the corresponding process cause indicated in the inspection report, actual failure analysis processing is performed to determine whether the failure anomaly at the suspected failure location of the chip is eliminated after the design corresponding to the process cause is eliminated; If the failure anomaly at the suspected failure location is eliminated, it is confirmed that the inspection report has passed the rationality verification.

19. A chip design method, comprising: Obtain the interim design results of the chip; Calling a chip inspection tool, wherein the chip inspection tool records a failure analysis result of the chip, wherein the failure analysis result indicates a chip location where the chip has a risk of failure abnormality and a corresponding process reason; wherein the failure analysis result is obtained according to the chip failure analysis method according to any one of claims 1 to 18; Using the chip inspection tool, inspecting whether the phased design result has a failure anomaly at the chip position; and If the failure anomaly occurs in the chip position in the phased design result, the phased design result is modified according to the process reason corresponding to the chip position until the modified phased design result is As a result of the calculation, the failure abnormality does not occur at the chip position.

20. A chip failure analysis device, comprising: A local result acquisition module, configured to acquire a local failure analysis result of the chip, wherein the local failure analysis result includes a local failure position where a failure anomaly occurs in the chip, and a process cause corresponding to the failure anomaly occurring at the local failure position; a suspected position determination module, configured to determine a suspected failure position of the chip according to the local failure position, wherein the suspected failure position is a chip position suspected of having the failure anomaly due to the process reason; A simulation module configured to simulate the process cause at the suspected failure location; An inspection module configured to inspect whether the failure anomaly occurs at the suspected failure position after simulating the process cause, and obtain an inspection report; as well as The result generating module is configured to generate a failure analysis result of the chip according to the inspection report.

21. A chip design device, comprising: A phased result acquisition module, configured to acquire the phased design results of the chip; A calling module configured to call a chip inspection tool, wherein the chip inspection tool records a failure analysis result of the chip, wherein the failure analysis result indicates a chip location where the chip has a risk of failure anomaly and a corresponding process reason; wherein the failure analysis result is obtained according to the chip failure analysis method according to any one of claims 1 to 18; A design checking module configured to use the chip checking tool to check whether the phased design result has a failure anomaly at the chip position; and The design modification module is configured to modify the staged design result according to the process reasons corresponding to the chip position if the judgment result of the design check module is that the failure anomaly occurs in the staged design result at the chip position, until the modified staged design result does not occur the failure anomaly at the chip position.

22. A computer device comprising: at least one memory and at least one processor, The at least one memory stores one or more computer executable instructions, and the at least one processor calls the one or more computer executable instructions to execute the chip failure analysis method according to any one of claims 1 to 18, or to execute the chip design method according to claim 19. method.

23. A storage medium, wherein: The storage medium stores one or more computer executable instructions, and when the one or more computer executable instructions are executed, the failure analysis method of the chip described in any one of claims 1 to 18 is implemented, or the chip design method described in claim 19 is implemented.

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