Selective summation latch circuit for decision feedback equalizer

Abstract

Provided in the present invention is a selective summation latch circuit for a decision feedback equalizer, comprising a selective summer, a latch amplifier, a sampler and a reset unit. The selective summer is used for alternatively select, when a sampling clock is at a high level, on the basis of logic levels of a selection signal positive terminal and a selection signal negative terminal, a positive reference voltage or a negative reference voltage to sum same and an input signal, so as to obtain a summation result; the latch amplifier is used for performing, when the sampling clock is at the high level, latching and amplification on the summation result, and outputting an output result to an output signal positive terminal and an output signal negative terminal; the sampler is used for performing, when the sampling clock is at the high level, sampling on the selective summer; and the reset unit is used for resetting, when the sampling clock is at a low level, the output signal positive terminal and the output signal negative terminal. The present invention reduces the overall power consumption, reduces the overall latency and improves the circuit performance.

Description

A selective summing latch circuit for decision feedback equalizer Technical Field

[0001] The present invention relates to the technical field of electronic signal processing circuits, and in particular to a selective summing latch circuit for a decision feedback equalizer. Background Art

[0002] Decision feedback equalization (DFEQ) technology can be used to improve signal reception quality and ensure accurate data reception. As shown in Figure 1, in a typical DFEQ application, the main functional components are typically implemented by a cascade of two summers, two latches, and a selector. The input signal from input signal interface 11 and the positive reference voltage from positive reference voltage interface 12 are summed in the first summer, while the input signal from input signal interface 11 and the negative reference voltage from negative reference voltage interface 13 are summed in the second summer.

[0003] The summation result is then sent to two latches via the first summation result interface 37 and the second summation result interface 38, and sampled by the sampling clock 15. The sampling result is sent to the two input terminals of the selector via the first sampling result interface 39 and the second sampling result interface 40, respectively.

[0004] The selector has two selection signals: a positive selection signal terminal 21 and a negative selection signal terminal 22. The logic levels of the positive selection signal terminal 21 and the negative selection signal terminal 22 are opposite. Based on the positive selection signal terminal 21 and the negative selection signal terminal 22, the selector selectively selects either the input signal of the first sampling result interface 39 or the input signal of the second sampling result interface 40. The selector includes two output signals, which are output to the positive output signal terminal 19 and the negative output signal terminal 20. The logic levels of the positive output signal terminal 19 and the negative output signal terminal 20 are opposite.

[0005] Since the decision feedback equalizer has many circuit stages connected in series, the delay from input to output is large, which will limit its operating speed and thus affect the operating frequency of the decision feedback equalizer. In addition, there are many circuit modules and the overall circuit power consumption is also relatively large.

[0006] Summary of the Invention

[0007] In order to solve the problems in the prior art of decision feedback equalizers, such as the large number of circuit stages connected in series, the large input-to-output delay, the limited operating speed, the impact on the operating frequency, and the high overall circuit power consumption, an object of the present invention is to provide a selective summing latch circuit for a decision feedback equalizer, the selective summing latch circuit comprising: a selective summer, a latch amplifier, a sampler, and a resetter;

[0008] The selection summer is used to select a positive reference voltage or a negative reference voltage to be summed with the input signal to obtain a summation result according to the logic levels of the positive end of the selection signal and the negative end of the selection signal when the sampling clock is at a high level;

[0009] The latch amplifier is used to latch and amplify the summation result when the sampling clock is at a high level, and output the output result to the output signal positive terminal and the output signal negative terminal;

[0010] The sampler is used to sample the selected summer when the sampling clock is at a high level;

[0011] The resetter is used to reset the positive end of the output signal and the negative end of the output signal when the sampling clock is at a low level.

[0012] Preferably, the selection summer includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor;

[0013] The second NMOS transistor and the fourth NMOS transistor are connected in series to form a first branch, and the third NMOS transistor and the fifth NMOS transistor are connected in series to form a second branch.

[0014] The first NMOS transistor is connected in parallel with the first branch, and the first NMOS transistor is connected in parallel with the second branch.

[0015] Preferably, the gate of the first NMOS transistor is connected to the input signal interface; the gate of the second NMOS transistor is connected to the positive reference voltage interface; the gate of the third NMOS transistor is connected to the negative reference voltage interface; the gate of the fourth NMOS transistor is connected to the positive terminal of the selection signal; and the gate of the fifth NMOS transistor is connected to the negative terminal of the selection signal.

[0016] The logic levels of the positive end of the selection signal and the negative end of the selection signal are opposite.

[0017] Preferably, the drain of the first NMOS transistor, the drain of the second NMOS transistor, and the drain of the third NMOS transistor are connected to each other and to the summation result interface;

[0018] The source of the first NMOS transistor, the source of the fourth NMOS transistor, and the source of the fifth NMOS transistor are connected to each other and to a summing source interface;

[0019] The source of the second NMOS tube is connected to the drain of the fourth NMOS tube; the source of the third NMOS tube is connected to the drain of the fifth NMOS tube.

[0020] Preferably, the drain of the first NMOS transistor, the drain of the fourth NMOS transistor, and the drain of the fifth NMOS transistor are connected to each other and to the summation result interface;

[0021] The source of the first NMOS transistor, the source of the second NMOS transistor, and the source of the third NMOS transistor are connected to each other and to a summing source interface;

[0022] The drain of the second NMOS tube is connected to the source of the fourth NMOS tube; the drain of the third NMOS tube is connected to the source of the fifth NMOS tube.

[0023] Preferably, the sampler is connected to the selection summer via a summing source interface;

[0024] The sampler includes one or more first sampling MOS transistors, wherein the gates of the first sampling MOS transistors are connected to a sampling clock;

[0025] When the sampling clock is at a high level, the first sampling MOS transistor samples the selected summer through the summing source interface.

[0026] Preferably, the drain of the first sampling MOS transistor is connected to the summing source interface, and the source of the first sampling MOS transistor is connected to the ground point VSS.

[0027] Preferably, the source of the first sampling MOS transistor is connected to the summing source interface, and the drain of the first sampling MOS transistor is connected to the ground point VSS.

[0028] Preferably, the latch amplifier is connected to the selection summer via a summation result interface;

[0029] The latch amplifier includes a first latch MOS transistor, a second latch MOS transistor, a third latch MOS transistor, a fourth latch MOS transistor and a second sampling MOS transistor;

[0030] The first latch MOS transistor and the third latch MOS transistor are connected in series to form a first latch branch, and the second sampling MOS transistor, the second latch MOS transistor and the fourth latch MOS transistor are connected in series to form a second latch branch;

[0031] The first latch branch and the second latch branch are connected in parallel, the gate of the second sampling MOS transistor is connected to the sampling clock, and the third latch MOS transistor is connected to the summing result interface;

[0032] The first latch branch is connected to the positive end of the output signal, and the second latch branch is connected to the negative end of the output signal;

[0033] The second latch branch is connected to the positive end of the output signal, and the second latch branch is connected to the negative end of the output signal.

[0034] Preferably, when the sampling clock is at a high level, the second sampling MOS transistor is turned on, and the first latch MOS transistor, the second latch MOS transistor, the third latch MOS transistor, and the fourth latch MOS transistor form a positive feedback loop, latching and amplifying the summation result through the summation result interface, and outputting the output result to the output signal positive terminal and the output signal negative terminal;

[0035] When the sampling clock is at a low level, the second sampling MOS transistor, the second latch MOS transistor and the fourth latch MOS transistor are all turned off.

[0036] Preferably, the source of the second sampling MOS transistor is connected to the ground point VSS; the drain of the second sampling MOS transistor is connected to the source of the fourth latch MOS transistor; the drain of the fourth latch MOS transistor is connected to the drain of the second latch MOS transistor;

[0037] The source of the third latch MOS transistor is connected to the summation result interface; the drain of the third latch MOS transistor is connected to the drain of the first latch MOS transistor;

[0038] The source of the second latch MOS transistor and the source of the first latch MOS transistor are connected to a power supply VDD.

[0039] Preferably, the drain of the second sampling MOS transistor is connected to the ground point VSS; the source of the second sampling MOS transistor is connected to the drain of the fourth latch MOS transistor; the source of the fourth latch MOS transistor is connected to the source of the second latch MOS transistor;

[0040] The drain of the third latch MOS transistor is connected to the summation result interface; the source of the third latch MOS transistor is connected to the source of the first latch MOS transistor;

[0041] The drain of the second latch MOS transistor and the drain of the first latch MOS transistor are connected to a power supply VDD.

[0042] Preferably, the resetter includes a first reset MOS transistor, a second reset MOS transistor and a third reset MOS transistor;

[0043] The gate of the first reset MOS transistor, the gate of the second reset MOS transistor and the gate of the third reset MOS transistor are respectively connected to a sampling clock;

[0044] The first reset MOS transistor and the second reset MOS transistor are connected in parallel, the positive end of the output signal is connected to the first reset MOS transistor, and the negative end of the output signal is connected to the second reset MOS transistor; the first reset MOS transistor is connected to the power supply VDD, and the second reset MOS transistor is connected to the power supply VDD;

[0045] The third reset MOS transistor is connected to the output signal positive terminal and the output signal negative terminal.

[0046] Preferably, when the sampling clock is at a low level, the first reset MOS transistor, the second reset MOS transistor and the third reset MOS transistor are all turned on to reset the positive end of the output signal and the negative end of the output signal;

[0047] When the sampling clock is at a high level, the first reset MOS transistor, the second reset MOS transistor and the third reset MOS transistor are all turned off.

[0048] Preferably, the drain of the first reset MOS transistor is connected to the positive terminal of the output signal, and the source of the third reset MOS transistor is connected to the positive terminal of the output signal;

[0049] The drain of the second reset MOS transistor is connected to the negative terminal of the output signal, and the drain of the third reset MOS transistor is connected to the negative terminal of the output signal;

[0050] The source of the first reset MOS transistor is connected to the power supply VDD, and the source of the second reset MOS transistor is connected to the power supply VDD.

[0051] Preferably, the source of the first reset MOS transistor is connected to the positive terminal of the output signal, and the drain of the third reset MOS transistor is connected to the positive terminal of the output signal;

[0052] The source of the second reset MOS transistor is connected to the negative end of the output signal, and the source of the third reset MOS transistor is connected to the negative end of the output signal;

[0053] The drain of the first reset MOS transistor is connected to the power supply VDD, and the drain of the second reset MOS transistor is connected to the power supply VDD.

[0054] Another object of the present invention is to provide a decision feedback equalizer, which includes a latch and the selective summing latch circuit provided by the present invention.

[0055] Preferably, the output signal positive terminal and the output signal negative terminal of the selection summing latch circuit are connected to the latch;

[0056] The output end of the latch is connected to the selection signal positive end and the selection signal negative end of the selection summing latch circuit;

[0057] The latch includes a latch clock, and the latch clock and the sampling clock are inverted signals.

[0058] The present invention provides a selection summing latch circuit for a decision feedback equalizer and a decision feedback equalizer, which reduces the delay and power consumption of a selector, a summer and a sampler in the decision feedback equalizer and improves the performance of the decision feedback equalizer.

[0059] The present invention provides a selection summing latch circuit for a decision feedback equalizer and a decision feedback equalizer, which integrates the summing function, selection function, sampling and latching functions used in the decision feedback equalizer into the selection summing latch circuit, thereby reducing overall power consumption, reducing overall delay, and improving circuit performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0061] FIG1 schematically shows a connection block diagram of a summer, a latch, and a selector used in a decision feedback equalizer in the prior art.

[0062] FIG2 shows an overall block diagram of a selective summing latch circuit for a decision feedback equalizer according to the present invention.

[0063] FIG3 shows a circuit diagram of a selection summer according to the present invention.

[0064] FIG4 shows a circuit diagram of a sampler according to the present invention.

[0065] FIG5 shows a circuit diagram of a latch amplifier according to the present invention.

[0066] FIG6 shows a circuit diagram of the resetter of the present invention.

[0067] FIG7 shows an overall block diagram of the decision feedback equalizer of the present invention.

[0068] The meanings of the reference numerals in the accompanying drawings are as follows: 100, selection summing latch circuit; 101, selection summing device; 102, latch amplifier; 103, sampler; 104, resetter; 201, latch; 11, input signal interface; 12, positive reference voltage interface; 13, negative reference voltage interface; 15, sampling clock; 16, summing source interface; 17, summing result interface; 19, output signal positive terminal; 20, output signal negative terminal; 21, selection signal positive terminal; 22, selection signal negative terminal; 23, latch clock; 37, first summing result interface; 38, second summing result interface; 39, first sampling result interface; 40, second sampling result interface; M1, first NMOS transistor; M2, second NMOS transistor; M3, third NMOS transistor; M4, fourth NMOS transistor; M5, fifth NMOS transistor; M31, first sampling MOS transistor; M41, first latch MOS tube; M42, second latch MOS tube; M43, third latch MOS tube; M44, fourth latch MOS tube; M45, second sampling MOS tube; M51, first reset MOS tube; M52, second reset MOS tube; M53, third reset MOS tube. DETAILED DESCRIPTION

[0069] In order to make the above and other features and advantages of the present invention more clear, the present invention is further described below with reference to the accompanying drawings. It should be understood that the specific embodiments given herein are for the purpose of explaining to those skilled in the art and are only exemplary and not restrictive.

[0070] As shown in FIG2 , according to an embodiment of the present invention, a selective summing latch circuit 100 for a decision feedback equalizer is provided. The selective summing latch circuit 100 includes a selective summer 101 , a latch amplifier 102 , a sampler 103 and a resetter 104 .

[0071] The selective summer 101 is connected to the latch amplifier 102, the selective summer 101 is connected to the sampler 103, and the sampler 103 is connected to the resetter 104. The latch amplifier 102, the sampler 103 and the resetter 104 are connected to the sampling clock 15 respectively.

[0072] The selection summer 101 is connected to the input signal interface 11 , the positive reference voltage interface 12 , the negative reference voltage interface 13 , the selection signal positive terminal 21 and the selection signal negative terminal 22 .

[0073] The input signal is input into the selection summer 101 through the input signal interface 11, the positive reference voltage is input into the selection summer 101 through the positive reference voltage interface 12, the negative reference voltage is input into the selection summer 101 through the negative reference voltage interface 13, and the selection signal positive terminal 21 and the selection signal negative terminal 22 provide logic levels to the selection summer 101.

[0074] The selection summer 101 is used to select the positive reference voltage input from the positive reference voltage interface 12 or the negative reference voltage input from the negative reference voltage interface 13 and the input signal input from the input signal interface 11 to sum the selected reference voltage and the input signal when the sampling clock 15 is at a high level, according to the logic levels of the selection signal positive terminal 21 and the selection signal negative terminal 22, to obtain a summation result.

[0075] The logic levels of the selection signal positive terminal 21 and the selection signal negative terminal 22 are opposite. When the selection signal positive terminal 21 is at a high level and the selection signal negative terminal 22 is at a low level, the positive reference voltage input from the positive reference voltage interface 12 is selected and summed with the input signal input from the input signal interface 11 in the selection summer 101 to obtain a summation result.

[0076] When the selection signal positive terminal 21 is at a low level and the selection signal negative terminal 22 is at a high level, the negative reference voltage input from the negative reference voltage interface 13 is selected and summed with the input signal input from the input signal interface 11 in the selection summer 101 to obtain a summation result.

[0077] The sampler 103 is connected to the ground point VSS and is connected to the selected summer 101 via the summing source interface 16 . The latch amplifier 102 is connected to the power supply VDD and is connected to the selected summer 101 via the summing result interface 17 .

[0078] The latch amplifier 102 includes an output signal positive terminal 19 and an output signal negative terminal 20 , and the output signal positive terminal 19 and the output signal negative terminal 20 of the latch amplifier 102 are connected to the reset device 104 .

[0079] The sampler 103 is configured to sample the selected summer 101 via the summing source interface 16 when the sampling clock 15 is at a high level.

[0080] The latch amplifier 102 is used to latch and amplify the summing result of the selected summer 101 through the summing result interface 17 when the sampling clock 15 is at a high level, and output the output result to the output signal positive terminal 19 and the output signal negative terminal 20.

[0081] The resetter 104 is used to reset the output signal positive terminal 19 and the output signal negative terminal 20 when the sampling clock 15 is at a low level.

[0082] As shown in FIG3 , according to an embodiment of the present invention, the selection summer 101 includes a first NMOS transistor M1 , a second NMOS transistor M2 , a third NMOS transistor M3 , a fourth NMOS transistor M4 and a fifth NMOS transistor M5 .

[0083] The second NMOS transistor M2 and the fourth NMOS transistor M4 are connected in series to form a first branch, the third NMOS transistor M3 and the fifth NMOS transistor M5 are connected in series to form a second branch, and the first NMOS transistor M1 is connected in parallel to the first branch and the second branch.

[0084] The gate of the first NMOS transistor M1 is connected to the input signal interface 11; the gate of the second NMOS transistor M2 is connected to the positive reference voltage interface 12; the gate of the third NMOS transistor M3 is connected to the negative reference voltage interface 13; the gate of the fourth NMOS transistor M4 is connected to the selection signal positive terminal 21; and the gate of the fifth NMOS transistor M5 is connected to the selection signal negative terminal 22.

[0085] The logic levels of the select signal positive terminal 21 and the select signal negative terminal 22 are opposite. When the select signal positive terminal 21 is at a high level and the select signal negative terminal 22 is at a low level, the fourth NMOS transistor M4 turns on and the fifth NMOS transistor M5 turns off, thereby selecting the first branch (the second NMOS transistor M2 and the fourth NMOS transistor M4) through the fourth NMOS transistor M4. The positive reference voltage input from the positive reference voltage interface 12 is selected and connected in parallel with the input signal input from the input signal interface 11 to the selection summer 101 for summation. The summation result is output to the latch amplifier 102 via the summation result interface 17.

[0086] When the positive terminal 21 of the selection signal is at a low level and the negative terminal 22 of the selection signal is at a high level, the fourth NMOS transistor M4 is turned off and the fifth NMOS transistor M5 is turned on, thereby selecting the second branch (the third NMOS transistor M3 and the fifth NMOS transistor M5) through the fifth NMOS transistor M5. The negative reference voltage input from the negative reference voltage interface 13 is selected and connected in parallel with the input signal input from the input signal interface 11 to be summed in the selection summer 101. The summed result is output to the latch amplifier 102 via the summation result interface 17.

[0087] The selection summer 101 selects the positive reference voltage input from the positive reference voltage interface 12 or the negative reference voltage input from the negative reference voltage interface 13 and the input signal input from the input signal interface 11 to sum the selected reference voltage and the input signal when the sampling clock 15 is at a high level, according to the logic levels of the selection signal positive terminal 21 and the selection signal negative terminal 22, and obtains a summation result.

[0088] In some embodiments, the drain of the first NMOS transistor M1, the drain of the second NMOS transistor M2, and the drain of the third NMOS transistor M3 are interconnected and connected to the summation result interface 17. The source of the first NMOS transistor M1, the source of the fourth NMOS transistor M4, and the source of the fifth NMOS transistor M5 are interconnected and connected to the summation source interface. The source of the second NMOS transistor M2 is connected to the drain of the fourth NMOS transistor M4; the source of the third NMOS transistor M3 is connected to the drain of the fifth NMOS transistor M5.

[0089] In some embodiments, the drain of the first NMOS transistor M1, the drain of the fourth NMOS transistor M4, and the drain of the fifth NMOS transistor M5 are interconnected and connected to the summation result interface 17. The source of the first NMOS transistor M1, the source of the second NMOS transistor M2, and the source of the third NMOS transistor M3 are interconnected and connected to the summation source interface 16. The drain of the second NMOS transistor M2 is connected to the source of the fourth NMOS transistor M4; the drain of the third NMOS transistor M3 is connected to the source of the fifth NMOS transistor M5.

[0090] According to an embodiment of the present invention, the sampler 103 is connected to the selected summer 101 via the summing source interface 16 , and the sampling clock 15 is connected to the sampler 103 .

[0091] As shown in FIG. 4 , the sampler 103 includes one or more first sampling MOS transistors M31 , and the gates of the first sampling MOS transistors M31 are connected to the sampling clock 15 .

[0092] When the sampling clock 15 is at a high level, the first sampling MOS transistor M31 samples the selected summer 101 through the summing source interface.

[0093] In some embodiments, the drain of the first sampling MOS transistor M31 is connected to the summing source interface 16 , and the source of the first sampling MOS transistor M31 is connected to the ground point VSS.

[0094] In some embodiments, the source of the first sampling MOS transistor M31 is connected to the summing source interface 16 , and the drain of the first sampling MOS transistor M31 is connected to the ground point VSS.

[0095] According to an embodiment of the present invention, the latch amplifier 102 is connected to the selection summer 101 via the summation result interface 17 , and the sampling clock 15 is connected to the latch amplifier 102 .

[0096] As shown in FIG5 , the latch amplifier 102 includes a first latch MOS transistor M41 , a second latch MOS transistor M42 , a third latch MOS transistor M43 , a fourth latch MOS transistor M44 and a second sampling MOS transistor M45 .

[0097] The first latch MOS transistor M41 and the third latch MOS transistor M43 are connected in series to form a first latch branch. The second sampling MOS transistor M45, the second latch MOS transistor M42, and the fourth latch MOS transistor M44 are connected in series to form a second latch branch. The first latch branch and the second latch branch are connected in parallel. The gate of the second sampling MOS transistor M45 is connected to the sampling clock 15, and the third latch MOS transistor M43 is connected to the summation result interface 17.

[0098] The first latch branch (the first latch MOS transistor M41 and the third latch MOS transistor M43 ) is connected to the output signal positive terminal 19 , and the first latch branch (the first latch MOS transistor M41 and the third latch MOS transistor M43 ) is connected to the output signal negative terminal 20 .

[0099] The second latch branch (the second latch MOS transistor M42 and the fourth latch MOS transistor M44) is connected to the output signal positive terminal 19, and the second latch branch (the second latch MOS transistor M42 and the fourth latch MOS transistor M44) is connected to the output signal negative terminal 20.

[0100] When the sampling clock 15 is at a high level, the second sampling MOS transistor M45 is turned on, and the first latch MOS transistor M41, the second latch MOS transistor M42, the third latch MOS transistor M43, and the fourth latch MOS transistor M44 form a positive feedback loop. The summation result is latched and amplified through the summation result interface 17, and the output result is output to the output signal positive terminal 19 and the output signal negative terminal 20.

[0101] When the sampling clock 15 is at a low level, the second sampling MOS transistor M45 , the second latch MOS transistor M42 and the fourth latch MOS transistor M44 are all off, and the output signal positive terminal 19 and the output signal negative terminal 20 are not controlled by the latch amplifier 102 .

[0102] In some embodiments, the source of the second sampling MOS transistor M45 is connected to the ground point VSS; the drain of the second sampling MOS transistor M45 is connected to the source of the fourth latch MOS transistor M44; and the drain of the fourth latch MOS transistor M44 is connected to the drain of the second latch MOS transistor M42.

[0103] The source of the third latch MOS transistor M43 is connected to the summing result interface 17 ; the drain of the third latch MOS transistor M43 is connected to the drain of the first latch MOS transistor M41 .

[0104] The source of the second latch MOS transistor M42 and the source of the first latch MOS transistor M41 are connected to the power supply VDD.

[0105] In some embodiments, the drain of the second sampling MOS transistor M45 is connected to the ground point VSS; the source of the second sampling MOS transistor M45 is connected to the drain of the fourth latch MOS transistor M44; and the source of the fourth latch MOS transistor M44 is connected to the source of the second latch MOS transistor M42.

[0106] The drain of the third latch MOS transistor M43 is connected to the summing result interface 17; the source of the third latch MOS transistor M43 is connected to the source of the first latch MOS transistor M41;

[0107] The drain of the second latch MOS transistor M42 and the drain of the first latch MOS transistor M41 are connected to the power supply VDD.

[0108] According to an embodiment of the present invention, the output signal positive terminal 19 and the output signal negative terminal 20 of the latch amplifier 102 are connected to the resetter 104 , and the sampling clock 15 is connected to the resetter 104 .

[0109] As shown in FIG6 , the resetter 104 includes a first reset MOS transistor M51 , a second reset MOS transistor M52 , and a third reset MOS transistor M53 .

[0110] The gates of the first reset MOS transistor M51 , the second reset MOS transistor M52 and the third reset MOS transistor M53 are connected to the sampling clock 15 respectively.

[0111] A first reset MOS transistor M51 and a second reset MOS transistor M52 are connected in parallel. The positive output signal terminal 19 of the latch amplifier 102 is connected to the first reset MOS transistor M51, and the negative output signal terminal 20 of the latch amplifier 102 is connected to the second reset MOS transistor M52. The first reset MOS transistor M51 is connected to the power supply VDD, and the second reset MOS transistor M52 is connected to the power supply VDD. A third reset MOS transistor M53 is connected to the positive output signal terminal 19 and the negative output signal terminal 20 of the latch amplifier 102.

[0112] When the sampling clock 15 is at a low level, the first reset MOS transistor M51, the second reset MOS transistor M52, and the third reset MOS transistor M53 are all turned on, and the output signal positive terminal 19 and the output signal negative terminal 20 of the latch amplifier 102 are connected to the power supply VDD through the first reset MOS transistor M51 and the second reset MOS transistor M52. At the same time, the third reset MOS transistor M53 turns on the first reset MOS transistor M51 and the second reset MOS transistor M52, thereby resetting the output signal positive terminal 19 and the output signal negative terminal 20 of the latch amplifier 102.

[0113] When the sampling clock 15 is at a high level, the first reset MOS transistor M51 , the second reset MOS transistor M52 and the third reset MOS transistor M53 are all turned off, and the operation of other circuits is not affected.

[0114] In some embodiments, the drain of the first reset MOS transistor M51 is connected to the output signal positive terminal 19 , and the source of the third reset MOS transistor M53 is connected to the output signal positive terminal 19 .

[0115] The drain of the second reset MOS transistor M52 is connected to the output signal negative terminal 20 , and the drain of the third reset MOS transistor M53 is connected to the output signal negative terminal 20 .

[0116] The source of the first reset MOS transistor M51 is connected to the power supply VDD, and the source of the second reset MOS transistor M52 is connected to the power supply VDD.

[0117] In some embodiments, the source of the first reset MOS transistor M51 is connected to the output signal positive terminal 19 , and the drain of the third reset MOS transistor M53 is connected to the output signal positive terminal 19 .

[0118] The source of the second reset MOS transistor M52 is connected to the output signal negative terminal 20 , and the source of the third reset MOS transistor M53 is connected to the output signal negative terminal 20 .

[0119] The drain of the first reset MOS transistor M51 is connected to the power supply VDD, and the drain of the second reset MOS transistor M52 is connected to the power supply VDD.

[0120] As shown in Figure 7, according to an embodiment of the present invention, a decision feedback equalizer is provided, including a latch 201 and a selection and summation latch circuit 100. The selection and summation latch circuit 100 is the selection and summation latch circuit 100 provided in the above embodiment of the present invention, and will not be described in detail here.

[0121] Latch 201 includes a latch clock 23, which is an inverted signal of sampling clock 15. The positive output signal terminal 19 and the negative output signal terminal 20 of the selection and summing latch circuit 100 are connected to latch 201. The output terminal of latch 201 is connected to the positive selection signal terminal 21 and the negative selection signal terminal 22 of the selection and summing latch circuit 100, forming a closed-loop decision feedback equalizer. This integrates the summing, selection, sampling, and latching functions used in the decision feedback equalizer into the selection and summing latch circuit, reducing overall power consumption, lowering overall delay, and improving circuit performance.

[0122] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. Any changes, modifications, substitutions and variations of the above embodiments made by a person skilled in the art within the scope of the present invention shall fall within the scope of protection of the present invention.

Claims

1. A selective summing latch circuit for a decision feedback equalizer, characterized in that: The selection and summation latch circuit comprises: a selection summer, a latch amplifier, a sampler and a resetter; The selection summer is used to select a positive reference voltage or a negative reference voltage to sum with the input signal to obtain a summation result according to the logic levels of the positive end of the selection signal and the negative end of the selection signal when the sampling clock is at a high level; The latch amplifier is used to latch and amplify the summation result when the sampling clock is at a high level, and output the output result to the output signal positive terminal and the output signal negative terminal; The sampler is used to sample the selected summer when the sampling clock is at a high level; The resetter is used to reset the positive end of the output signal and the negative end of the output signal when the sampling clock is at a low level.

2. The selective summing latch circuit according to claim 1, characterized in that: The selection summer includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube; Wherein, the second NMOS tube and the fourth NMOS tube are connected in series to form a first branch, and the third NMOS tube and the fifth NMOS tube are connected in series to form a second branch; The first NMOS transistor is connected in parallel with the first branch, and the first NMOS transistor is connected in parallel with the second branch.

3. The selective summing latch circuit according to claim 2, characterized in that: The gate of the first NMOS tube is connected to the input signal interface; the gate of the second NMOS tube is connected to the positive reference voltage interface; the gate of the third NMOS tube is connected to the negative reference voltage interface; the gate of the fourth NMOS tube is connected to the positive end of the selection signal; the gate of the fifth NMOS tube is connected to the negative end of the selection signal; The logic levels of the positive end of the selection signal and the negative end of the selection signal are opposite.

4. The selective summing latch circuit according to claim 2, characterized in that: The drain of the first NMOS tube, the drain of the second NMOS tube and the drain of the third NMOS tube are connected to each other and to the summing result interface; The source of the first NMOS tube, the source of the fourth NMOS tube and the source of the fifth NMOS tube are connected to each other and to the summing source interface; The source of the second NMOS tube is connected to the drain of the fourth NMOS tube; the source of the third NMOS tube is connected to the drain of the fifth NMOS tube.

5. The selective summing latch circuit according to claim 2, characterized in that: The drain of the first NMOS tube, the drain of the fourth NMOS tube and the drain of the fifth NMOS tube are connected to each other and to the summing result interface; The source of the first NMOS tube, the source of the second NMOS tube and the source of the third NMOS tube are connected to each other and to the summing source interface; The drain of the second NMOS tube is connected to the source of the fourth NMOS tube; the drain of the third NMOS tube is connected to the source of the fifth NMOS tube.

6. The selective summing latch circuit according to claim 1, characterized in that: The sampler is connected to the selection summer via a summing source interface; The sampler comprises one or more first sampling MOS tubes, and the gate of the first sampling MOS tube is connected to the sampling clock; When the sampling clock is at a high level, the first sampling MOS tube samples the selection summer through the summing source interface.

7. The selective summing latch circuit according to claim 6, characterized in that: The drain of the first sampling MOS tube is connected to the summing source interface, and the source of the first sampling MOS tube is connected to the ground point VSS.

8. The selective summing latch circuit according to claim 6, characterized in that: The source of the first sampling MOS tube is connected to the summing source interface, and the drain of the first sampling MOS tube is connected to the ground point VSS.

9. The selective summing latch circuit according to claim 1, characterized in that: The latch amplifier is connected to the selection summer via a summing result interface; The latch amplifier comprises a first latch MOS tube, a second latch MOS tube, a third latch MOS tube, a fourth latch MOS tube and a second sampling MOS tube; The first latch MOS tube and the third latch MOS tube are connected in series to form a first latch branch, and the second sampling MOS tube, the second latch MOS tube and the fourth latch MOS tube are connected in series to form a second latch branch; The first latch branch and the second latch branch are connected in parallel, the gate of the second sampling MOS tube is connected to the sampling clock, and the third latch MOS tube is connected to the summing result interface; The first latch branch is connected to the positive end of the output signal, and the first latch branch is connected to the negative end of the output signal; The second latch branch is connected to the positive end of the output signal, and the second latch branch is connected to the negative end of the output signal.

10. The selective summing latch circuit according to claim 9, characterized in that: When the sampling clock is at a high level, the second sampling MOS transistor is turned on, the first latch MOS transistor, the second latch MOS transistor, the third latch MOS transistor and the fourth latch MOS transistor form a positive feedback loop, the summation result is latched and amplified through the summation result interface, and the output result is output to the output signal positive terminal and the output signal negative terminal; When the sampling clock is at a low level, the second sampling MOS tube, the second latch MOS tube and the fourth latch MOS tube are all turned off.

11. The selective summing latch circuit according to claim 9, characterized in that: The source of the second sampling MOS tube is connected to the ground point VSS; the drain of the second sampling MOS tube is connected to the source of the fourth latch MOS tube; the drain of the fourth latch MOS tube is connected to the drain of the second latch MOS tube; The source of the third latch MOS tube is connected to the summing result interface; The drain of the transistor is connected to the drain of the first latch MOS transistor; The source of the second latch MOS tube and the source of the first latch MOS tube are connected to a power source VDD.

12. The selective summing latch circuit according to claim 9, characterized in that: The drain of the second sampling MOS tube is connected to the ground point VSS; the source of the second sampling MOS tube is connected to the drain of the fourth latch MOS tube; the source of the fourth latch MOS tube is connected to the source of the second latch MOS tube; The drain of the third latch MOS tube is connected to the summing result interface; the source of the third latch MOS tube is connected to the source of the first latch MOS tube; The drain of the second latch MOS tube and the drain of the first latch MOS tube are connected to a power source VDD.

13. The selective summing latch circuit according to claim 1, characterized in that: The resetter comprises a first reset MOS tube, a second reset MOS tube and a third reset MOS tube; The gate of the first reset MOS tube, the gate of the second reset MOS tube and the gate of the third reset MOS tube are respectively connected to the sampling clock; The first reset MOS tube and the second reset MOS tube are connected in parallel, the positive end of the output signal is connected to the first reset MOS tube, and the negative end of the output signal is connected to the second reset MOS tube; the first reset MOS tube is connected to the power supply VDD, and the second reset MOS tube is connected to the power supply VDD; The third reset MOS tube is connected to the output signal positive terminal and the output signal negative terminal.

14. The selective summing latch circuit according to claim 13, characterized in that: When the sampling clock is at a low level, the first reset MOS tube, the second reset MOS tube and the third reset MOS tube are all turned on to reset the positive end of the output signal and the negative end of the output signal; When the sampling clock is at a high level, the first reset MOS tube, the second reset MOS tube and the third reset MOS tube are all turned off.

15. The selective summing latch circuit according to claim 13, characterized in that: The drain of the first reset MOS tube is connected to the positive end of the output signal, and the source of the third reset MOS tube is connected to the positive end of the output signal; The drain of the second reset MOS tube is connected to the negative end of the output signal, and the drain of the third reset MOS tube is connected to the negative end of the output signal; The source of the first reset MOS tube is connected to the power supply VDD, and the source of the second reset MOS tube is connected to the power supply VDD.

16. The selective summing latch circuit according to claim 13, characterized in that: The source of the first reset MOS tube is connected to the positive end of the output signal, and the drain of the third reset MOS tube is connected to the positive end of the output signal; The source of the second reset MOS tube is connected to the negative end of the output signal, and the source of the third reset MOS tube is connected to the negative end of the output signal; The drain of the first reset MOS tube is connected to the power supply VDD, and the drain of the second reset MOS tube is connected to the power supply VDD.

17. A decision feedback equalizer, characterized in that: The decision feedback equalizer comprises a latch, and the selection and summing latch circuit as claimed in any one of claims 1 to 16.

18. The decision feedback equalizer according to claim 17, characterized in that: The output signal positive terminal and the output signal negative terminal of the selection summing latch circuit are connected to the latch; The output end of the latch is connected to the selection signal positive end and the selection signal negative end of the selection summing latch circuit; The latch comprises a latch clock, and the latch clock and the sampling clock are inverse phase signals to each other.

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