Flat panel detector and detection device
By optimizing the thin-film transistor structure and photoelectric conversion layer design, the leakage current problem of thin-film transistors was solved, the fill rate and response speed of the flat panel detector were improved, the image quality and quantum detection efficiency were enhanced, and the X-ray radiation was reduced.
Patent Information
- Application Number
- PCT/CN2023/120297
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-09-21
- Publication Date
- 2026-01-02
AI Technical Summary
In existing flat panel detectors, thin-film transistors are prone to leakage current when they are off, which leads to signal loss in the photosensitive unit, affecting image quality and detector performance.
By optimizing the structural design of thin-film transistors, reducing the area difference between the first and second overlapping regions, increasing the area of the photoelectric conversion layer, adopting an asymmetric semiconductor layer design, setting recesses and insulating layers to reduce the coupling electric field, optimizing the overlapping relationship of metal layers, reducing parasitic capacitance, and improving the flatness of the signal transmission path.
It effectively reduces the leakage current of thin-film transistors, improves the fill rate and response speed of detectors, enhances image quality and quantum detection efficiency, reduces X-ray radiation, and improves the overall performance of the detection substrate.
Smart Images
Figure CN2023120297_02012026_PF_FP_ABST
Abstract
Description
Flat panel detector and detection device TECHNICAL FIELD
[0001] The present application relates to the field of detection technology, and in particular to a flat panel detector and detection device. BACKGROUND
[0002] X-ray detection technology is widely used in industrial non-destructive testing, container scanning, circuit board inspection, medical treatment, security, industry and other fields, and has broad application prospects. Traditional X-ray imaging technology belongs to analog signal imaging, and has low resolution and poor image quality. The X-ray digital imaging technology (Digital Radio Graphy, DR) appeared in the late 1990s directly converts X images into digital images by using an X-ray flat panel detector. Since the converted digital images are clear, have high resolution, and are easy to save and transmit, the X-ray digital imaging technology has become a research hotspot. According to the different structures, the X-ray flat panel detector is divided into a direct type (Direct DR) and an indirect type (Indirect DR). Among them, the indirect type X-ray flat panel detector technology is relatively mature, has relatively low cost, high detective quantum efficiency (DQE), good reliability and other advantages, and has been widely developed and applied.
[0003] Generally, the flat panel detector includes a scintillator, a detection substrate, a control module, a signal processing module and a communication module. The scintillator absorbs X-rays and converts them into visible light; the detection substrate is composed of a pixel array of a photodiode and a TFT switch (Thin Film Transistor), under the driving of a control circuit, the photodiode converts the visible light generated by the scintillator into an electrical signal, and the TFT switch transmits the electrical signal to a scanning line; the signal processing module amplifies the electrical signal and converts it into a digital signal through an analog-to-digital converter, and forms an image after correction compensation processing.
[0004] However, the thin film transistor of the current detector is prone to generate a leakage current in an off state, and therefore, the current detection substrate, manufacturing method thereof and detector still need to be improved.
[0005] SUMMARY
[0006] The present application aims to at least solve one of the technical problems in the related art to some extent.
[0007] A detection substrate, comprising:
[0008] a substrate substrate;
[0009] a gate line, disposed on a first side of the substrate substrate, and extending along a first direction;
[0010] a scan line disposed on the first side of the substrate and extending along a second direction, the first direction intersecting the second direction; and
[0011] at least one pixel unit defined by the intersection of the gate line and the scan line,
[0012] the at least one pixel unit comprises:
[0013] a thin film transistor disposed on the first side of the substrate, the thin film transistor comprising: a semiconductor layer; a first electrode electrically connected with the semiconductor layer at a first overlap region; a second electrode electrically connected with the semiconductor layer at a second overlap region, the second overlap region having a larger area of a footprint on the substrate than the first overlap region;
[0014] a photoelectric converter disposed on a side of the thin film transistor facing away from the substrate, the photoelectric converter comprising: a bottom electrode electrically connected with the first electrode through a first via; a photoelectric conversion layer disposed on a side of the bottom electrode facing away from the substrate; and a top electrode disposed on a side of the photoelectric conversion layer facing away from the substrate;
[0015] wherein, in the at least one pixel unit, a minimum distance between a footprint on the substrate of the first via and a footprint on the substrate of the scan line closest to the first via is a first distance, and a maximum distance between a footprint on the substrate of the semiconductor layer and a footprint on the substrate of the scan line closest to the first via is a second distance, the second distance being greater than or equal to the first distance.
[0016] wherein,
[0017] the footprint on the substrate of the first electrode has a number of symmetry axes greater than or equal to 3;
[0018] the footprint on the substrate of the first via covers an intersection of at least 2 of the symmetry axes.
[0019] wherein, the footprint on the substrate of the first electrode has a center point, and the footprint on the substrate of the bottom electrode covers the center point.
[0020] wherein, the footprint on the substrate of the first electrode is at least partially conformal with the footprint on the substrate of the first via.
[0021] wherein, the footprint on the substrate of the semiconductor layer partially overlaps with the footprint on the substrate of the bottom electrode.
[0022] The second insulating layer is arranged on the side of the first electrode away from the substrate, and is arranged on the side of the bottom electrode close to the substrate.
[0023] The projection of the semiconductor layer on the substrate is spaced apart from the projection of the bottom electrode on the substrate.
[0024] The projection of the first via on the substrate partially overlaps the projection of the semiconductor layer on the substrate.
[0025] The semiconductor layer is provided with a first recess close to the first via.
[0026] The semiconductor layer partially surrounds the first via.
[0027] The maximum size of the first overlap region in the second direction is greater than or equal to the maximum size of the first via in the second direction.
[0028] The projection of the semiconductor layer in the first direction overlaps the projection of the first via in the first direction.
[0029] The semiconductor layer includes a channel region, and the projection of the bottom electrode on the substrate does not overlap the projection of the channel region on the substrate.
[0030] The projection of the bottom electrode on the substrate at least partially borders flush with the projection of the first electrode on the substrate.
[0031] The first electrode is an N-sided polygon, and N is greater than or equal to 5.
[0032] A second recess is arranged on at least one side of the second electrode in the second direction connected to the scan line.
[0033] The projection of the semiconductor layer on the substrate does not overlap the projection of the second recess on the substrate.
[0034] The bias line is electrically connected to the photoelectric converter through a second via,
[0035] The projection of the bias line on the substrate covers the projection of the first via on the substrate.
[0036] The thin film transistor further includes a gate electrode, and the gate electrode is provided with a fourth recess on the side close to the first via in the first direction.
[0037] The interlayer insulating layer has a third via hole, and the scan line and the second electrode are electrically connected through the third via hole. BRIEF DESCRIPTION OF DRAWINGS
[0038] Fig. 1 is a schematic diagram of a pixel structure of a flat panel detector provided in the related art.
[0039] Fig. 2A is a schematic diagram of a pixel structure of a flat panel detector provided in the present disclosure.
[0040] Fig. 2B is a partial enlarged view of Fig. 2A.
[0041] Fig. 3 is a sectional view along the section line A-A’ of Fig. 2B.
[0042] Fig. 4A is a schematic diagram of a pixel structure of a flat panel detector provided in the present disclosure.
[0043] Fig. 4B is a partial enlarged view of Fig. 4A.
[0044] Fig. 4C is a partial enlarged view of Fig. 4A.
[0045] Fig. 5 is a sectional view along the section line A-A’ of Fig. 4B.
[0046] Fig. 6A is a schematic diagram of a pixel structure of a flat panel detector provided in the present disclosure.
[0047] Fig. 6B is a partial enlarged view of Fig. 6A.
[0048] Fig. 7 is a sectional view along the section line A-A’ of Fig. 6B.
[0049] Fig. 8 is a schematic diagram of a first electrode structure provided in the present disclosure.
[0050] Fig. 9 is a schematic diagram of a pixel structure of a flat panel detector provided in the present disclosure.
[0051] Fig. 10A is a schematic diagram of a pixel structure of a flat panel detector provided in the present disclosure.
[0052] Fig. 10B is a sectional view along the section line A’-A of Fig. 10A.
[0053] Fig. 11 is a schematic diagram of a flat panel detector provided in the present disclosure.
[0054] Fig. 12A is a schematic diagram of an intermediate product formed in step S1 of a process flow for manufacturing a flat panel detector provided in the present disclosure.
[0055] Fig. 12B is a schematic diagram of an intermediate product formed in step S2 of a process flow for manufacturing a flat panel detector provided in the present disclosure.
[0056] Fig. 12C is a schematic view of an intermediate product formed in step S4 of a flat panel detector manufacturing process according to the present disclosure.
[0057] Fig. 12D is a schematic view of an intermediate product formed in step S5 of a flat panel detector manufacturing process according to the present disclosure.
[0058] Fig. 13 is a schematic block diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION
[0059] For the purpose of making the objects, technical solutions and advantages of the present disclosure clearer, below, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The embodiments can be implemented in multiple different forms. One of ordinary skill in the art can easily understand that the manners and contents can be changed into one or more forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict.
[0060] The proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the width-length ratio of the channel region, the thickness and interval of each film layer, and the width and interval of each scanning line can be adjusted according to actual needs. The number of pixels in the optoelectronic substrate and the number of sub-pixels in each pixel are also not limited to the numbers shown in the drawings. The drawings described in the present disclosure are only schematic views, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.
[0061] The ordinal numbers "first", "second", "third" and the like in the present disclosure are set in order to avoid confusion of the components, and are not intended to be limited in terms of numbers. The "multiple" in the present disclosure includes two and more than two numbers.
[0062] The words "equal", "approximately equal", "equal to" and the like in the present disclosure are intended for convenience in writing, and are not intended to be limited in terms of values. The "equal" in the present disclosure includes two values that differ by no more than 10% to 20%.
[0063] In the present disclosure, the words of "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the positional or locational relationship are used to refer to the positional relationship of the components with reference to the drawings for the purpose of convenience and simplicity of the description and the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which the components are described. Therefore, it is not limited to the words described in the specification, and can be appropriately replaced according to the situation.
[0064] In the present disclosure, unless explicitly specified and limited otherwise, the terms "mount", "connect", "connection" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or the communication inside two elements. The above-mentioned terms in the present disclosure can be understood according to the situation by those skilled in the art.
[0065] In the present disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.
[0066] In the present disclosure, the first electrode can be a drain electrode, and the second electrode can be a source electrode, or the first electrode can be a source electrode, and the second electrode can be a drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in the circuit operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in the present disclosure, "source electrode" and "drain electrode" can be exchanged with each other.
[0067] In the present disclosure, "electrically connected" includes the case where the components are connected together through an element having a certain electrical effect. The element having a certain electrical effect is not particularly limited as long as it can perform the transmission and reception of electrical signals between the connected components. Examples of the element having a certain electrical effect include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having one or more functions, and the like.
[0068] As shown in FIG. 1, the flat panel detector sensor of the related art includes a detection substrate including a substrate substrate 10, at least one thin film transistor 3 (TFT) disposed on the substrate substrate 10, at least one scan line 2, and at least one gate line 1; the at least one thin film transistor 3 includes a gate 31, a semiconductor layer 32, and a first electrode 33 and a second electrode 34 connected to the semiconductor layer 32, the gate 31 is disposed on the substrate substrate 10, the semiconductor layer 32 is disposed on the gate 31 insulating layer covering the gate 31, the first electrode 33 is disposed on the semiconductor layer 32 close to one end of the second electrode 34, the first electrode 33 is electrically connected to the scan line 2 away from the other end of the second electrode 34, the second electrode 34 is disposed on the semiconductor layer 32 close to one end of the first electrode 33; the second electrode 34 is electrically connected to the bottom electrode 6 of the photoelectric conversion layer 5 away from the other end of the first electrode 33; the photoelectric conversion layer 5 is provided with a top electrode 7 on the side away from the substrate substrate 10, and the top electrode 7 is electrically connected to the bias line 8.
[0069] Under X-ray irradiation, the scintillator layer or the fluorescent layer in the light conversion layer converts X-ray photons into visible light and is incident to the detection substrate. The bias line 8 and the top electrode 7 in the detection substrate apply a bias to the photoelectric conversion layer 5, so that the photoelectric conversion layer 5 converts the photons of the visible light into carriers (electrons) and integrates, and the integrated electrons are transported to the first electrode 33 by the bottom electrode 6, and the electrical signal is output to the scan line 2 through the thin film transistor 3, and then the digital image is formed by subsequent analog-to-digital conversion and image processing. The thin film transistor 3 reads the electrical signal to the scan line 2 and outputs the electrical signal to obtain a display image.
[0070] In the related art, the first electrode 33 of the thin film transistor 3 has a large overlapping area with the semiconductor layer 32, so when the potential on the first electrode 33 side is high, a leakage current may flow between the first electrode 33 / second electrode 34 when the thin film transistor 3 is cut off (in a state where the gate voltage Vg applied to the gate 31 is less than the threshold voltage Vth).
[0071] It can be considered that when the detection substrate is working, a voltage is applied on the first electrode 33 side during the cut-off of the thin film transistor 3, and electrostatic capacitive coupling is generated between the semiconductor layer 32 and the first electrode 33 to activate the semiconductor layer 32, thereby increasing the leakage current, causing the loss of the integrated electrical signal in the photosensitive unit, affecting the final read integrated signal, and finally reducing the photoelectric properties of the flat panel detector.
[0072] In order to reduce the leakage current of the thin film transistor 3 in the off state of the flat panel detector sensor, the channel region 321 of the thin film transistor 3 can be considered to be narrowed in width and length, or the overlap area of the first electrode 33 and the semiconductor layer 32, i.e. the first overlap region 331, or the overlap area of the second electrode 34 and the semiconductor layer 32, i.e. the second overlap region 341, can be considered to be reduced.
[0073] In view of the above technical problems, the present disclosure provides a novel detection substrate of a flat panel detector. The more specific structure of the detection substrate of the present disclosure will be described below in combination with the specific embodiments.
[0074] In some embodiments, as shown in FIGS. 2-3 (for the convenience of showing the structure of the thin film transistor 3, the photoelectric conversion layer 5 is not shown). The detection substrate comprises a substrate 10, a gate line 1 extending in a first direction, and a scan line 2 extending in a second direction; the gate line 1 and the scan line 2 divide a plurality of pixel units arranged in an array; the pixel unit comprises: a thin film transistor 3 disposed on the first side of the substrate 10; a photoelectric converter disposed on the side of the thin film transistor away from the substrate; the photoelectric converter comprises: a bottom electrode 6, the bottom electrode is electrically connected to the first electrode through a first via; a photoelectric conversion layer 5, the photoelectric conversion layer 5 is disposed on the side of the bottom electrode 6 away from the substrate; a top electrode 7, disposed on the side of the photoelectric conversion layer away from the substrate; the thin film transistor 3 comprises a first electrode 33, a second electrode 34, and a semiconductor layer 32; the first electrode 33 is connected to the semiconductor layer 32 at a first overlap region 331, the second electrode 34 is connected to the semiconductor layer 32 at a second overlap region 341, and the area of the second overlap region 341 on the substrate 10 is greater than the area of the first overlap region 331 on the substrate 10; the photoelectric conversion layer 5 comprises a bottom electrode 6, and the bottom electrode 6 is electrically connected to the first electrode 33 through a first via 9.
[0075] It should be noted that the area of the first overlap region 331 of the semiconductor layer 32 of the thin film transistor 3 is smaller than the area of the second overlap region 341. When the gate 311 is energized, due to the larger area of the second overlap region 341 than the first overlap region 331, the semiconductor layer 32 of the second overlap region 341 has more carrier accumulation, and the semiconductor layer 32 of the first overlap region 331 has less carrier accumulation, resulting in a reduction in the leakage current of the thin film transistor 3 in the off state.
[0076] Further, in some embodiments, the area of the semiconductor layer 32 at the position of the first overlap region 331 is also reduced, i.e., the orthographic projection of the semiconductor layer 32 on the substrate 10 is in the shape of a trapezoid or a pattern of two trapezoids connected along the bottom sides. Due to the coupling electric field between the first electrode 33 or the second electrode 34 and the gate 31, the semiconductor layer 32 at the position near the first overlap region 331 or the second overlap region 341 can be activated, increasing the leakage current. Therefore, in these embodiments, through the asymmetric design of the semiconductor layer 32, the number of carriers activated at the two sides of the thin film transistor 3 is made different, so as to reduce the leakage current.
[0077] In a flat panel detector, the larger the area of the photoelectric conversion layer 5 in the detection substrate, i.e., the higher the fill factor, the higher the photoelectric conversion efficiency of the flat panel detector, and the amount of X-rays required will be reduced, and in the field of medical imaging, the amount of X-ray radiation received by the patient will be reduced. Therefore, the fill factor of the flat panel detector is a parameter that needs to be improved.
[0078] With continued reference to FIGS. 2-3, in the case of only changing the structure of the channel region 321, due to the increase in the size of the thin film transistor 3, the orthographic projection area of the photoelectric conversion layer 5 in the substrate 100 in the photosensitive pixel will be reduced, thereby affecting the effective response area of the detection substrate, affecting the quantum detection efficiency and modulation transfer function of the radiation detector, and degrading the performance of the detection substrate. It should be noted that the effective response area of the detection substrate described above can be the area where the photoelectric conversion layer 5 is arranged opposite the scintillator, i.e., the area of the surface for responding to or receiving light converted by the scintillator.
[0079] Therefore, in some examples, as shown in FIG. 2B (the photoelectric conversion layer 5 is not shown in the figure, since the photoelectric conversion layer 5 is arranged on the bottom electrode 6, when the area of the bottom electrode 6 increases, the area of the photoelectric conversion layer 5 that can be arranged also increases), in the first direction, the shortest distance between the orthographic projection of the first via 9 on the substrate 10 and the orthographic projection of the scan line 2 on the substrate 10 is L1, and the maximum distance between the orthographic projection of the semiconductor layer 32 on the substrate 10 and the orthographic projection of the scan line 2 on the substrate 10 is L2, L2 is greater than or equal to L1.
[0080] It is to be noted that when L2 is greater than or equal to L1, the distance between the first via hole 9 and the scanning line 2 is reduced. In the photosensitive unit, the area of the bottom electrode 6 on the substrate 10 is increased, and thus the area of the photoelectric conversion layer 5 arranged on the side of the bottom electrode 6 away from the substrate 10 is increased, and the filling rate is correspondingly improved, thereby improving or enhancing the performance of the detection substrate. Further, when L2 is greater than or equal to L1, the shortest distance between the first via hole 9 and the thin film transistor 3 is reduced, and thus the embodiment can reduce the transmission distance of the signal and the resistance on the transmission path, thereby enhancing the response speed of the detection substrate.
[0081] With reference to FIG. 2B, in some embodiments, the first via hole 9 is partially overlapped with the projection of the semiconductor layer 32 on the substrate 10. In this case, the pattern complexity of the patterning process in the preparation process of the semiconductor layer 32 is small, the topography of the obtained semiconductor layer 32 is good, and the requirement of the patterning process of the semiconductor layer 32 in the preparation process is low, and the preparation process is simplified.
[0082] It is to be noted that in these embodiments, since the semiconductor layer 32 is partially arranged in the first via hole 9, the flatness inside the first via hole is reduced, which may cause macroscopic defects on the appearance of the final flat panel detector.
[0083] In some embodiments, as shown in FIGS. 4A-4B, the semiconductor layer 32 is provided with a first recess 13 near the first via hole 9; that is, the projection of the semiconductor layer 32 in the first direction is overlapped with the projection of the first via hole 9 in the first direction; that is, the semiconductor layer 32 partially surrounds the first via hole 9 at the position near the first via hole 9. Or the maximum size L3 of the first overlap area 331 in the second direction is greater than the maximum size L4 of the first via hole 9 in the second direction.
[0084] That is, as shown in FIG. 4C, the first overlap area 331 has a first side edge 3311, a second side edge 3312, a third side edge 3313, and a fourth side edge 3314. The second side edge and the fourth side edge extend along the second direction. The partial surrounding means that, in the first direction, the first side edge 3311 and the third side edge 3313 are arranged on both sides of the first via hole 9, and the projection 9’ of the first via hole in the first direction is overlapped with the projection 331’ of the first overlap area 331 in the first direction.
[0085] In these embodiments, with reference to FIG. 5, since the semiconductor layer 32 is not arranged in the first via hole 9, the flatness inside the first via hole 9 is improved, which is beneficial to solve the macroscopic defects caused by the unevenness.
[0086] Further, the design can reduce the overlap area of the semiconductor layer 32 and the first electrode 33, and further reduce the leakage current when the thin film transistor 3 is off.
[0087] Further, in the design, the first via 9 can be closer to the thin film transistor 3 while reducing the overlap area of the semiconductor layer 32 and the first overlap region 331, thereby further improving the fill factor of the light sensing unit.
[0088] In the thin film transistor 3, if there is a large overlap between the metal layers, a large parasitic capacitance will be introduced, which may affect the performance of the thin film transistor 3. Therefore, this problem should also be considered when designing the thin film transistor 3.
[0089] In the above embodiment, as shown in FIG. 4A, since the semiconductor layer 32 is provided with the first recess 13, the overlap area of the semiconductor layer 32 and the bottom electrode 6 is reduced, thereby reducing the leakage current and increasing the fill factor. In addition, the design of the semiconductor layer 32 provided with the first recess 13 can also reduce the overlap area of the semiconductor layer 32 and the bottom electrode 6, so that the interference on the thin film transistor 3 is reduced.
[0090] In addition to the semiconductor layer 32, the bottom electrode 6 can also be designed to reduce the parasitic capacitance. In some embodiments, as shown in FIG. 2A and FIG. 4A, the orthographic projection of the bottom electrode 6 on the substrate 10 is flush with at least part of the boundary of the orthographic projection of the first electrode 33 on the substrate 10. That is, the orthographic projection of the bottom electrode 6 on the substrate 10 does not overlap with the orthographic projection of the channel region 321 on the substrate 10. At this time, the bottom electrode 6 and the channel region 321 of the thin film transistor 3 have no orthographic projection overlap relationship or have a small orthographic projection overlap, so that the coupling effect of the bottom electrode 6 on the channel region 321 of the thin film transistor 3 can be reduced or prevented, and the accuracy of the signal transmission of the thin film transistor 3 is improved.
[0091] It should be noted that the flush refers to the orthographic projection of the bottom electrode 6 on the substrate 10 and the orthographic projection of the first electrode 33 on the substrate 10, at least part of the outline lines coincide.
[0092] In some embodiments, as shown in FIG. 3 and FIG. 5, the orthographic projection of the semiconductor layer 32 on the substrate 10 partially overlaps with the orthographic projection of the bottom electrode 6 on the substrate 10. The detection substrate further comprises a second insulating layer 42, which is arranged on the side of the first electrode 33 facing away from the substrate 10, and is arranged on the side of the bottom electrode 6 close to the substrate 10; the orthographic projection of the second insulating layer 42 on the substrate 10 overlaps with the first overlapping area 331. That is, in the first overlapping area 331, from the substrate 10 to the photoelectric conversion layer 5, the semiconductor layer 32, the first electrode 33, the second insulating layer 42, and the bottom electrode 6 are arranged in sequence; the orthographic projection of the bottom electrode 6 on the substrate 10 does not completely cover the orthographic projection of the first electrode 33 on the substrate 10.
[0093] When the second insulating layer 42 is not arranged, and the orthographic projection of the bottom electrode 6 on the substrate 10 overlaps with the orthographic projection of the channel area 321 on the substrate 10, coupling or electric field may be generated, which interferes with the signal transmission of the thin film transistor 3 or increases the leakage current of the thin film transistor 3. Therefore, by arranging the second insulating layer 42, the distance between the bottom electrode 6 and the semiconductor layer 32 is increased, and the interference of the bottom electrode 6 on the thin film transistor 3 is reduced or avoided.
[0094] In addition, due to the thickness of the second insulating layer 42 itself, a certain thickness of the boss 12 is formed on the surface of the first interlayer insulating layer 161, which can increase the surface roughness of the first interlayer insulating layer 101, increase the contact force of the interlayer insulating layer 10, reduce the probability of the flat layer falling off or prevent such adverse events from occurring, and improve the yield of the detection substrate.
[0095] In order to further reduce the overlapping area of the bottom electrode 6 and the semiconductor layer 32, the area of the bottom electrode 6 can be further reduced. In some embodiments, as shown in FIG. 6-7, the bottom electrode 6 does not extend and completely cover the first electrode 33, the orthographic projection of the semiconductor layer 32 on the substrate 10 is spaced apart from the orthographic projection of the bottom electrode 6 on the substrate 10, and the orthographic projection of the bottom electrode 6 on the substrate 10 completely covers the orthographic projection of the first via 9 on the substrate 10. In this embodiment, the bottom electrode 6 can realize good electrical connection with the first via 9, and in addition, since the bottom electrode 6 and the semiconductor layer 32 have no overlapping area, the parasitic capacitance between them is correspondingly reduced, and the performance of the flat panel detector is improved.
[0096] In some embodiments, as shown in FIG. 8, the first electrode 33 has a projection on the substrate 10 with a symmetry axis, and the number of symmetry axes is greater than or equal to 3, so that the first electrode 33 has a contour similar to a regular polygon, thereby ensuring the area of the first via 9, making the electrical connection between the first electrode 33 and the bottom electrode 6 more sufficient, and reducing the loss of the scanning line readout signal.
[0097] Further, the first via 9 has a projection on the substrate 10 covering at least two intersection points of the symmetry axes, i.e., the projection of the bottom electrode 6 on the substrate 10 covers the center point of the first electrode 33. In some embodiments, the projection of the first electrode 33 on the substrate 10 is at least partially conformal to the projection of the first via 9 on the substrate 10. This can make the electrical connection position close to the centroid of the first electrode 33, and the signal transmission more uniform.
[0098] As shown in FIG. 8, the symmetry axis refers to the axis of symmetry or rotational symmetry of a figure, which is a straight line that makes the figure axisymmetric or rotationally symmetric. The symmetry axis can be an axisymmetric symmetry axis or a center symmetric symmetry axis.
[0099] The center point of the first electrode 33 can be one of the centroid of the first electrode 33, the centroid of the projection on the substrate 10, and the geometric center of the projection on the substrate 10.
[0100] The conformality refers to the similarity of two or more figures. In the embodiments of the present disclosure, the at least partially conformal refers to that at least part of the contour of the projection of the first electrode 33 on the substrate 10 is similar to at least part of the contour of the projection of the first via 9 on the substrate 10, i.e., the extension direction and the bending angle are the same, or the two contour lines are parallel to each other.
[0101] Further, the first electrode 33 can be an N-polygon with N greater than or equal to 5. Near the thin film transistor 3 of the detection substrate, the figure of the photoelectric conversion layer 5 is conformal to the figure of the first electrode 33. When the figure of the first electrode 33 has an increased curvature, the photoelectric conversion layer 5 can have a nonlinear continuous sidewall, which optimizes and improves the surface quality and morphology of the sidewall, and effectively reduces or avoids the occurrence of the leakage current phenomenon of the photoelectric conversion layer 5. When N is greater than or equal to 5, as shown in FIG. 9, the first electrode 33 can adaptively rotate in a direction to make the corresponding photoelectric conversion layer 5 have better sidewall quality and morphology, which is not described herein.
[0102] In some embodiments, continuing to refer to FIG. 9, the second electrode 34 is provided with at least one second recess 14 at the position where the second electrode 34 is connected to the scan line 2. Due to the second recess 14 provided on the scan line 2, the overlapping capacitance between the second electrode 34 and the gate 31 is reduced, which can reduce the noise of the thin film transistor 3, improve the signal-to-noise ratio of the product, and enhance the quality of the image. Further, the semiconductor layer 32 and the second electrode 34 have a conformal portion, in this embodiment, the orthographic projection of the semiconductor layer 32 on the substrate 10 does not overlap with the orthographic projection of the second recess 14 on the substrate 10, that is, the semiconductor layer 32 is provided with a third recess 15 at both ends of the semiconductor layer 32 in the second direction close to the adjacent scan line 2. This will cause the circumference of the semiconductor layer 32 to be smaller, thereby reducing the area of the side surface of the semiconductor layer 32. Since the performance defects of the semiconductor layer 32 in the thin film transistor 3 are mainly concentrated on the side surface, the reduction of the area of the side surface also reduces the defects of the thin film transistor 3, which is beneficial to reduce the overall performance of the flat panel detector.
[0103] Continuing to refer to FIG. 10, the interlayer insulating layer is provided with a third via hole 17, and the scan line 2 and the second electrode 34 are electrically connected through the third via hole 17, and the scan line 2 and the bias line 8 are in the same layer. In this embodiment, since the scan line 2 and the gate line 1 have the interlayer insulating layer 10 therebetween, the scan line 2 in the detection substrate is farther away from the gate line 1, and the coupling capacitance of the overlapping area 21 between the scan line 2 and the gate line 1 is reduced. Therefore, the interference received by the signal during transmission can be reduced, and the quality of the image can be ensured.
[0104] The same layer means that the bias line 8 and the scan line 2 are prepared in the same step in the preparation process, that is, the material of the bias line 8 is the same as that of the scan line 2. In addition, the same layer can also mean that the material of the bias line 8 is different from that of the scan line 2, but the bias line 8 and the scan line 2 are arranged in the same layer, that is, the distance between the main body part of the bias line 8 and the main body part of the scan line 2 and the substrate 100 in the direction perpendicular to the substrate 100 is equal.
[0105] In addition, continuing to refer to FIG. 10, in this embodiment, in the detection substrate, whether it is the connecting part of the third via hole 17 or the extension part of the scan line 2, the distance between the scan line 2 and the bottom electrode 6 is increased, and therefore the coupling capacitance between the scan line 2 and the bottom electrode 6 is reduced, thereby ensuring the accuracy of the electrical signal generated by the photoelectric conversion layer 5, so as to ensure the quality of the generated image.
[0106] In some embodiments, the detection substrate further comprises a bias line 8. As shown in FIG. 11, the bias line 8 is electrically connected to the photoelectric conversion layer 5 through the second via hole 11 to provide a bias voltage for the photoelectric conversion layer 5. In addition, the bias line 8 can also act as a light shielding layer. In the embodiments of the present disclosure, the distance between the first via hole 9 and the thin film transistor 3 is small, and when the bias line 8 acts as a light shielding layer for the thin film transistor 3, the bias line 8 can only shield part of the first via hole 9. Due to the difference in flatness inside the via hole, the reflection intensity is different, so in this case, the detection substrate will have macro defects.
[0107] To solve the above problems, in the embodiments of the present disclosure, the bias line 8 covers the first via hole 9 in the orthographic projection of the substrate 10. This makes the bias line 8 completely shield the first via hole 9, thereby reducing or even solving the macro defects.
[0108] Further, the thin film transistor 3 further comprises a gate 31, and the gate 31 is provided with a fourth recess 16 on the side close to the first via hole 9 in the first direction. In this way, the overlapping area of the second electrode 34 and the gate 31 can be reduced, and thus the parasitic capacitance between the gate 31 and the second electrode 34 can be reduced.
[0109] Based on the same inventive concept, as shown in FIG. 12, the present disclosure further provides a preparation method of the detection substrate as described in any one of the above embodiments, comprising:
[0110] S1: As shown in FIG. 12A, the gate 31 of the thin film transistor 3, the first insulating layer 41, the semiconductor layer 32, and the first electrode 33 and the second electrode 34 are sequentially formed on the substrate 10 by a patterning process.
[0111] In this embodiment, the substrate 10 is made of transparent material such as glass and is pre-cleaned. Specifically, first, a gate metal film layer is formed on the substrate 10 by sputtering, thermal evaporation, plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), or electron cyclotron resonance chemical vapor deposition (ECR-CVD). Then, a pattern of the gate 31 is formed by a patterning process (film formation, exposure, development, wet etching or dry etching) using a half tone mask (HTM) or a gray tone mask (GTM). The gate 31 can be made of conductive material such as metal or metal alloy, e.g., molybdenum, molybdenum-niobium alloy, aluminum, aluminum-neodymium alloy, titanium, or copper.
[0112] Next, a first insulating layer 41 is formed above the gate 31 by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition, or sputtering.
[0113] Then, an amorphous silicon film is deposited by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, etc., and is crystallized, and a pattern of the semiconductor layer 32 is formed by a patterning process.
[0114] Finally, a source-drain metal film layer is formed by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition, or sputtering, and a pattern including the first electrode 33 and the second electrode 34 is formed by a one-time patterning process.
[0115] S2: As shown in FIG. 12B, a second insulating layer 42 is formed by a patterning process, and a first via hole 9 is formed at a position corresponding to the first electrode 33 in the second insulating layer 42.
[0116] Specifically, in this step, a passivation film layer can be deposited by a plasma enhanced chemical vapor deposition method, a low pressure chemical vapor deposition method, an atmospheric pressure chemical vapor deposition method, or an electron cyclotron resonance chemical vapor deposition method, and a first via hole 9 is formed by a patterning process such as a mask and dry etching. The material of the passivation film layer can include silicon nitride, silicon oxide, or the like.
[0117] A pattern of the bottom electrode 6 of the photoelectric conversion layer 5 is formed by a patterning process, and the pattern is connected to the first electrode 33 of the thin film transistor 3 through the first via hole 9.
[0118] Similarly to the process of forming the first electrode 33 and the second electrode 34 of the thin film transistor 3, in this step, a first metal film layer can be deposited on the passivation layer 3 by a plasma enhanced chemical vapor deposition method, a low pressure chemical vapor deposition method, an atmospheric pressure chemical vapor deposition method, an electron cyclotron resonance chemical vapor deposition method, or a sputtering method, and a pattern of the bottom electrode 6 of the photoelectric conversion layer 5 is formed by a patterning process such as a mask and wet etching.
[0119] The material of the first metal film layer can be a conductive material such as a metal or a metal alloy, for example, molybdenum, molybdenum-niobium alloy, aluminum, aluminum-neodymium alloy, titanium, or copper.
[0120] In some examples, the bottom electrode 6 of the photoelectric conversion layer 5 is electrically connected to the first electrode 33 through the first via hole 9. This is because, in the preparation of the detection substrate, the first electrode 33 is usually deposited and patterned first, and then the second insulating layer 42 is prepared to protect the channel region 321 of the thin film transistor 3 through the second insulating layer 42, so as to reduce or prevent the channel region 321 of the thin film transistor 3 from being disturbed or damaged in subsequent processes. At this time, the first electrode 33 is completely covered by the second insulating layer 42, and if it is required to be used as the bottom electrode 6 of the photoelectric conversion layer 5, the second insulating layer 42 needs to be etched to expose the first electrode 33. However, the etching process can cause the surface flatness of the first electrode 33 to decrease or the second insulating layer 42 to remain, which affects the electrical connection between the photoelectric conversion layer 5 prepared in the subsequent process and the first electrode 33, and reduces the photoelectric conversion performance of the flat panel detector. Therefore, the bottom electrode 6 layer is deposited and patterned on the second insulating layer 42, and the photoelectric conversion layer 5 is deposited and prepared on the bottom electrode 6 layer with a lower defect degree or no defect, so as to improve the performance of the flat panel detector.
[0121] S4: As shown in FIG. 12C, a photoelectric conversion layer 5 is deposited on the substrate 10, and a pattern is formed by a patterning process.
[0122] In this embodiment, the detection substrate includes a photoelectric conversion layer 5 region, and the thickness of the photoelectric conversion layer 5 layer can be 10000A. Specifically, the photoelectric conversion layer 5 layer can include an N-type semiconductor material layer, an I-type semiconductor material layer, and a P-type semiconductor material layer.
[0123] Specifically, the step S4 can include the following steps:
[0124] S41, depositing a semiconductor material on the substrate 10 with the bottom electrode 6 by sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance chemical vapor deposition.
[0125] S42, forming the photoelectric conversion layer 5 by dry etching processes such as plasma etching (PE), reactive ion etching (RIE), enhanced capacitive coupled plasma etching (ECCP) and inductively coupled plasma etching (ICP).
[0126] In order to make the photoelectric conversion layer 5 and the bias line 8 to be formed to have a good ohmic contact, a transparent conductive layer can be formed on the semiconductor material after the semiconductor material in S41 is formed; then, the transparent conductive layer is etched first to form the bias line 8. The material of the bias line 8 can be ITO, IGZO, etc.
[0127] S5, as shown in FIG. 12D, forming the interlayer insulating layer 10 on the substrate 10 with the semiconductor layer 32 of the photoelectric conversion layer 5, and forming the second via hole 11 in the interlayer insulating layer 10.
[0128] The material of the interlayer insulating layer 10 includes resin, and the thickness is large to play a role of planarization of the flat panel detector substrate. Specifically, in this step, the plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance chemical vapor deposition can be used to deposit the interlayer insulating material film layer, and the second via hole 11 is formed in the position corresponding to the photoelectric conversion layer 5 through the patterning process such as mask and etching.
[0129] Further, since the single-layer resin material interlayer insulating layer 10 has a large thickness and is easy to fall off, in order to further ensure the performance of the product, the interlayer insulating layer 10 preferably includes a first interlayer insulating layer 101, a second interlayer insulating layer 102 and a third interlayer insulating layer 103 arranged in sequence. The materials of the first interlayer insulating layer 101 and the third interlayer insulating layer 103 can include silicon nitride and silicon oxide layer material, and the material of the second interlayer insulating layer 102 includes resin. The thickness of the second interlayer insulating layer 102 is larger than the thickness of the first interlayer insulating layer 101 and the third interlayer insulating layer 103.
[0130] The pattern of the bias voltage line 8 is formed by a patterning process.
[0131] In this step, a second metal film layer is deposited on the interlayer insulating layer 10 by a plasma-enhanced chemical vapor deposition method, a low-pressure chemical vapor deposition method, an atmospheric pressure chemical vapor deposition method, an electron cyclotron resonance chemical vapor deposition method, or a sputtering method, and a pattern of the bias voltage line 8 is formed by a patterning process such as a mask, wet etching, or the like. The second metal film layer can be made of a metal or a metal alloy, such as molybdenum, molybdenum-niobium alloy, aluminum, aluminum-neodymium alloy, titanium, or copper.
[0132] That is, the light photoelectric conversion layer 5 is connected to the thin film transistor 3 by the bottom electrode 6 of the light photoelectric conversion layer 5 and the first electrode 33 of the thin film transistor 3, so that the detection of the collected light signal of the light photoelectric conversion layer 5 is realized by controlling the on-off state of the thin film transistor 3.
[0133] Thus, the preparation of the thin film transistor 3 and the photodiode in the flat panel detector substrate is completed.
[0134] It should be noted that the bottom electrode 6 in this embodiment can be directly connected to the first electrode 33 of the thin film transistor 3, and thus the step S21 can specifically include:
[0135] The gate 31 of the thin film transistor 3, the first insulating layer 41, the semiconductor layer 32, the first electrode 33, the second electrode 34, and the bottom electrode 6 of the light photoelectric conversion layer 5 are sequentially formed on the substrate 10 by a patterning process.
[0136] The gate 31 of the thin film transistor 3, the gate insulating layer, and the semiconductor layer 32 are prepared by the same process as described above, and thus will not be described again. When the first electrode 33 and the second electrode 34 are formed, the pattern of the first electrode 33, the second electrode 34, and the bottom electrode 6 is formed at the same time by one patterning process. The first electrode 33 and the bottom electrode 6 are integrally formed, that is, the extended part of the first electrode 33 can be used as the bottom electrode 6.
[0137] After the step S1, the light photoelectric conversion layer 5, the interlayer insulating layer 10, the bias voltage line 8, and other structures are sequentially formed according to the steps S3, S4, and S5, and thus will not be described again.
[0138] In this embodiment, the first electrode 33 of the thin film transistor 3 is used as the bottom electrode 6, which can further improve the filling rate and the performance of the flat panel detector.
[0139] A schematic block diagram 13 of an electronic device 200 is provided. The electronic device 200 includes the radiation detector described in any of the previous embodiments. Examples of the electronic device 200 include medical diagnostic devices, industrial inspection devices, geological exploration devices, etc. The electronic device 200 has the same advantages as the radiation detector embodiments.
[0140] The present disclosure also includes a flat panel detector comprising the detection substrate described above and a non-visible light conversion layer covering the array substrate, the non-visible light conversion layer being configured to convert non-visible light into visible light.
[0141] It can be understood that the above embodiments are only exemplary embodiments adopted for illustrating the principles of the present application, and the present application is not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and principle of the present application, and these modifications and improvements are also considered to be within the scope of protection of the present application.
Claims
1. A detection substrate, comprising: Substrate; A gate line is disposed on a first side of the substrate and extends along a first direction; A scan line is disposed on a first side of the substrate and extends along a second direction, wherein the first direction intersects the second direction; and, At least one pixel unit is defined by the intersection of the gate line and the scan line. The at least one pixel unit includes: A thin-film transistor, disposed on a first side of the substrate, includes: a semiconductor layer; a first electrode electrically connected to the semiconductor layer in a first overlap region; a second electrode electrically connected to the semiconductor layer in a second overlap region, wherein the projected area of the second overlap region on the substrate is larger than the projected area of the first overlap region on the substrate; and... A photoelectric converter is disposed on the side of the thin-film transistor away from the substrate; the photoelectric converter includes: a bottom electrode, which is electrically connected to the first electrode through a first via; a photoelectric conversion layer, which is disposed on the side of the bottom electrode away from the substrate; and a top electrode, which is disposed on the side of the photoelectric conversion layer away from the substrate. Wherein, in the at least one pixel unit, the minimum distance between the orthographic projection of the first via on the substrate and the orthographic projection of the scan line closest to the first via on the substrate is a first distance, and the maximum distance between the orthographic projection of the semiconductor layer on the substrate and the orthographic projection of the scan line closest to the first via on the substrate is a second distance, and the second distance is greater than or equal to the first distance.
2. The detection substrate as described in claim 1, wherein, The orthographic projection of the first electrode onto the substrate has an axis of symmetry, and the number of the axes of symmetry is greater than or equal to 3. The orthographic projection of the first via onto the substrate covers at least two intersections of the axes of symmetry.
3. The detection substrate as described in claim 1, wherein, The orthographic projection of the first electrode onto the substrate has a center point, and the orthographic projection of the bottom electrode onto the substrate covers the center point.
4. The detector substrate as claimed in claim 1, wherein, The orthographic projection of the first electrode on the substrate is at least partially conformal to the orthographic projection of the first via on the substrate.
5. The detector substrate as described in any one of claims 1-4, wherein, The orthographic projection of the semiconductor layer on the substrate overlaps with the orthographic projection of the bottom electrode on the substrate.
6. The detector substrate as described in any one of claims 1-4, wherein, It also includes a second insulating layer, which is disposed on the side of the first electrode away from the substrate and on the side of the bottom electrode close to the substrate; the orthographic projection of the second insulating layer on the substrate partially overlaps with the first overlapping area.
7. The detector substrate as described in any one of claims 1-4, wherein, The orthographic projection of the semiconductor layer on the substrate and the orthographic projection of the bottom electrode on the substrate are spaced apart from each other.
8. The detector substrate as described in any one of claims 1-4, wherein, The orthographic projection of the first via onto the substrate overlaps with the orthographic projection of the semiconductor layer onto the substrate.
9. The detector substrate as described in any one of claims 1-4, wherein, The semiconductor layer has a first recess near the first via.
10. The detector substrate as claimed in claim 9, wherein, The semiconductor layer partially surrounds the first via.
11. The detector substrate as claimed in claim 9, wherein, The maximum dimension of the first overlapping region in the second direction is greater than or equal to the maximum dimension of the first via in the second direction.
12. The detector substrate as claimed in claim 11, wherein, The projection of the semiconductor layer in the first direction overlaps with the projection of the first via in the first direction.
13. The detector substrate as claimed in claim 12, wherein, The semiconductor layer includes a channel region, and the orthographic projection of the bottom electrode onto the substrate does not overlap with the orthographic projection of the channel region onto the substrate.
14. The detector substrate according to any one of claims 1-4, wherein, The orthographic projection of the bottom electrode onto the substrate is at least partially flush with the orthographic projection of the first electrode onto the substrate.
15. The detector substrate according to any one of claims 1-14, wherein, The first electrode is an N-sided polygon, where N is greater than or equal to 5.
16. The detector substrate according to any one of claims 1-14, wherein, A second recess is provided on at least one side of the second electrode in the second direction in which the second electrode is connected to the scan line.
17. The detector substrate as claimed in claim 16, wherein, The orthographic projection of the semiconductor layer on the substrate does not overlap with the orthographic projection of the second recess on the substrate.
18. The detector substrate according to any one of claims 1-14, wherein, It also includes a bias line, which is electrically connected to the photoelectric converter through a second via. The orthogonal projection of the bias line onto the substrate covers the orthogonal projection of the first via onto the substrate.
19. The detector substrate as described in any one of claims 1-4, wherein, The thin-film transistor also includes a gate, and the gate has a fourth recess on the side near the first via in a first direction.
20. The detector substrate according to any one of claims 1-4, wherein, An interlayer insulating layer is provided between the thin-film transistor and the bias line, and the interlayer insulating layer has a third via. The scan line is electrically connected to the second electrode through the third via.
21. The probe substrate of claim 20, wherein the scan line and the bias line are on the same layer.
22. A flat panel detector, wherein, Includes a detector substrate as described in any one of claims 1-21 and a non-visible light conversion layer covering the array substrate, the non-visible light conversion layer being configured to convert non-visible light into visible light.