Integrated circuit and preparation method therefor, and memory and electronic device

Abstract

An integrated circuit and a preparation method therefor, and a memory and an electronic device. The integrated circuit comprises a memory array having semi-floating gate transistors (T) as memory cells. Each semi-floating gate transistor (T) comprises a substrate (30), a first gate dielectric layer (33), floating gates (31) and control gates (32), wherein the substrate (30) comprises a lower surface (R1) and an upper surface (R2) which are arranged opposite each other in the direction of the thickness of the substrate; the first gate dielectric layer (33) is arranged on the upper surface of the substrate (30), and a via hole (h) is formed in the first gate dielectric layer (33); the floating gates (31) are arranged on the first gate dielectric layer (33), each floating gate (31) being electrically connected to the substrate (30) through the via hole (h) in the first gate dielectric layer (33); and each control gate (32) is arranged on the floating gate (31). The floating gate (31) comprises an end portion (A) far away from the lower surface of the substrate (30), and on a section cutting plane of the semi-floating gate transistor (T), the end portion (A) of the floating gate (31) is embedded in the control gate (32).

Description

Integrated circuit and manufacturing method thereof, memory, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on September 19, 2023, with application number 202311215871.0 and application name “Integrated Circuit and Its Manufacturing Method, Memory, Electronic Device”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to an integrated circuit and a manufacturing method thereof, a memory, and an electronic device. Background Art

[0003] A semi-floating gate transistor (SFGT) is a microelectronic device that can replace a memory cell in a dynamic random access memory (DRAM) to prepare a semi-floating gate transistor memory.

[0004] Unlike traditional floating-gate transistors, semi-floating-gate transistors have a via in the gate dielectric layer between the floating gate and the substrate. This via serves as a window for charge transfer between the floating gate and the substrate. The floating gate is used to store charge, and a coupling capacitor is generated between the control gate and the floating gate to store data. The capacitance of this coupling capacitor directly affects its data retention capability.

[0005] Typically, the control gate and the floating gate are facing each other in one direction (the surfaces facing the control gate and the floating gate extend along the plane direction), but as the planar size of the device shrinks, the facing area between the control gate and the floating gate is decreasing, resulting in a decrease in the capacitance value of the coupling capacitor, and thus a decrease in data retention capability.

[0006] Summary of the Invention

[0007] The present application provides an integrated circuit and a method for manufacturing the same, a memory, and an electronic device, aiming to improve the data retention capability of the device.

[0008] To achieve the above objectives, this application adopts the following technical solutions:

[0009] In a first aspect, an integrated circuit is provided, comprising spaced-apart semi-floating gate transistors. The integrated circuit may be a memory array using the semi-floating gate transistors as memory cells. Each semi-floating gate transistor comprises a substrate, a first gate dielectric layer, a floating gate, and a control gate. The substrate comprises a lower surface and an upper surface opposing each other along its thickness. The first gate dielectric layer is disposed on the upper surface of the substrate, and a via is provided in the first gate dielectric layer. A floating gate is disposed on the first gate dielectric layer, and each floating gate is electrically connected to the substrate via a via in the first gate dielectric layer. A control gate is disposed on the floating gate, and the floating gate includes an end portion remote from the lower surface of the substrate. In a cross-sectional view of the semi-floating gate transistor, the end portion of the floating gate is embedded within the control gate.

[0010] The integrated circuit provided in the present application includes a plurality of spaced-apart semi-floating gate transistors. In each semi-floating gate transistor, a floating gate is disposed on a first gate dielectric layer and electrically connected to a substrate via a via in the first gate dielectric layer. A control gate stack is disposed on the floating gate. In a cross-sectional view of the semi-floating gate transistor, an end of the floating gate, which is away from the lower surface of the substrate, is embedded within the control gate. The control gate and the floating gate are not only surface-facing in the stacking direction, but also surface-facing in the spacing direction of the plurality of semi-floating gate transistors. This ensures surface-facing between the control gate and the floating gate in multiple directions, increases the effective facing area between the control gate and the floating gate, and facilitates increasing the coupling capacitance between the control gate and the floating gate, thereby improving the data retention capability of the device and reducing the refresh power consumption of the device.

[0011] In one possible implementation, the integrated circuit further includes multiple shallow trench isolation structures disposed on the substrate, each shallow trench isolation structure being located between the floating gates of two adjacent half-floating gate transistors. With the lower surface of the substrate serving as a reference plane, the shallow trench isolation structure includes a first surface distal from the reference plane, and the floating gate includes a second surface distal from the reference plane, with the first surface being lower than the second surface relative to the reference plane. The shallow trench isolation structure and the two floating gates located on either side form a groove, with at least a portion of the control gate embedded within the groove.

[0012] The first surface of the shallow trench isolation structure is the top surface of the shallow trench isolation structure, and the second surface of the floating gate is the top surface of the floating gate. By setting the top surface of the shallow trench isolation structure lower than the top surface of the floating gate, the shallow trench isolation structure can form a groove with the floating gates located on both sides thereof. The control gate can be partially embedded in the groove. Along the spacing direction of the multiple half-floating gate transistors, the portion of the control gate embedded in the groove directly faces the floating gate surface, which helps to increase the effective facing area between the control gate and the floating gate, thereby increasing the coupling capacitance between the control gate and the floating gate.

[0013] In a possible implementation, the portion of the control gate embedded in the groove includes a third surface close to the reference plane, and the third surface contacts the first surface.

[0014] It can be understood that, with the surface of the substrate close to the control gate as the upper surface of the substrate, when part of the shallow trench isolation structure is located in the substrate and the top surface of the shallow trench isolation structure is higher than the upper surface of the substrate relative to the reference plane, the part of the control gate embedded in the groove can be in direct contact with the shallow trench isolation structure, and there will be no electrical contact between the control gate and the substrate to generate a short circuit.

[0015] In another possible implementation, the integrated circuit further includes a second gate dielectric layer, the portion of the control gate embedded in the groove includes a third surface close to the reference plane, the third surface is lower than the second surface relative to the reference plane, and a portion of the second gate dielectric layer is located between the third surface and the first surface.

[0016] It is understood that if the shallow trench isolation structure is located within the substrate, the first surface of the shallow trench isolation structure is flush with the upper surface of the substrate, and the portion of the control gate embedded in the recess is in direct contact with the shallow trench isolation structure, there is a possibility of electrical contact between the control gate and the substrate. By providing a second gate dielectric layer between the third surface of the control gate and the first surface of the shallow trench isolation structure, the vertical distance between the control gate and the shallow trench isolation structure can be increased, and further the distance between the control gate and the upper surface of the substrate can be increased, thereby reducing the risk of electrical contact between the control gate and the substrate and causing a short circuit.

[0017] In one possible implementation, a portion of the first gate dielectric layer is located between the second gate dielectric layer and the first surface. A second gate dielectric layer is disposed between the third surface of the control gate and the first surface of the shallow trench isolation structure. In this case, the addition of the first gate dielectric layer between the second gate dielectric layer and the first surface can further increase the vertical distance between the control gate and the shallow trench isolation structure, further increasing the distance between the control gate and the upper surface of the substrate, thereby reducing the risk of electrical contact between the control gate and the substrate and causing a short circuit.

[0018] In a possible implementation, the integrated circuit further includes an insulating layer, and the insulating layer is located between the third surface and the second gate dielectric layer.

[0019] On the basis of setting a first gate dielectric layer and a second gate dielectric layer between the third surface of the control gate and the first surface of the shallow trench isolation structure, an insulating layer is added between the third surface of the control gate and the second gate dielectric layer, which can further increase the vertical distance between the control gate and the shallow trench isolation structure, increase the distance between the control gate and the upper surface of the substrate, and reduce the risk of short circuit due to electrical contact between the control gate and the substrate.

[0020] In one possible implementation, a first gate dielectric layer is located between the floating gate and the shallow trench isolation structure, and extends into the control gate. Along the arrangement direction of the plurality of floating gates, the first gate dielectric layer is also located between the floating gate and the control gate. A second gate dielectric layer is located on a side of the floating gate away from the reference plane, and is also located between the floating gate and the control gate.

[0021] The floating gate and the control gate are insulated by the first gate dielectric layer and the second gate dielectric layer. The first gate dielectric layer and the second gate dielectric layer can serve as dielectrics for the coupling capacitor formed by the floating gate and the control gate. The first gate dielectric layer and the second gate dielectric layer can both be made of materials with high dielectric constants, for example, at least one of hafnium oxide, zirconium oxide, or hafnium zirconium oxide, which is beneficial to increasing the coupling capacitance value between the control gate and the floating gate.

[0022] In another possible implementation, a second gate dielectric layer extends into the control gate. The second gate dielectric layer includes a first portion and a second portion. Along the arrangement direction of the multiple floating gates, the first portion is located between the floating gate and the control gate. The second portion is located on the side of the floating gate away from the reference plane and is also located between the floating gate and the control gate. That is, the second gate dielectric layer covers the top surface and the portion of the sidewall adjacent to the top surface of the floating gate, thereby insulating the floating gate from the control gate. The second gate dielectric layer can serve as the dielectric for the coupling capacitance formed by the floating gate and the control gate. The second gate dielectric layer can be made of a material with a high dielectric constant, for example, at least one of hafnium oxide, zirconium oxide, or hafnium zirconium oxide, which can help increase the coupling capacitance between the control gate and the floating gate.

[0023] In a possible implementation, the dielectric constant of the material of the first gate dielectric layer is in the range of 4-100, and the dielectric constant of the material of the second gate dielectric layer is in the range of 4-100.

[0024] In a possible implementation, the material of the control gate includes at least one of tungsten, aluminum, titanium nitride, or tantalum nitride. These materials have low resistance and can reduce the resistance of the control gate.

[0025] Of the two opposite ends of the control gate along its extension direction, one end receives a voltage signal, which can also be called the "proximal end" of the control gate, and the other end is called the "distal end". The voltage signal is transmitted from the proximal end to the distal end of the control gate. By reducing the resistance of the control gate, the voltage drop generated by the voltage signal being transmitted on the control gate can be reduced. In this way, on the premise that the actual operating voltage received by the distal end of the control gate reaches the rated operating voltage, it is beneficial to increase the number of semi-floating gate transistors corresponding to the same control gate, thereby helping to improve the storage density of the memory array.

[0026] In a second aspect, a method for fabricating an integrated circuit is provided. The integrated circuit includes spaced-apart semi-floating gate transistors. The method comprises: forming a first gate dielectric layer on the upper surface of a substrate, the first gate dielectric layer having a via formed therein, the via exposing the upper surface of the substrate; forming a floating gate on the first gate dielectric layer, the floating gate electrically connected to the substrate via the via; and forming a control gate on the floating gate. The floating gate includes an end portion remote from a reference plane, such that, in a cross-section of the semi-floating gate transistor, the end portion of the floating gate is embedded within the control gate.

[0027] The fabrication method provided herein forms a floating gate on a first gate dielectric layer, electrically connected to a substrate via vias in the first gate dielectric layer. A control gate is also formed on the floating gate. In a cross-sectional view of a semi-floating gate transistor, the end of the floating gate, facing away from a reference plane, is embedded within the control gate. This allows the control gate and the floating gate to face each other not only in the stacking direction but also in the direction in which the multiple semi-floating gate transistors are spaced apart. This ensures that the control gate and the floating gate face each other in multiple directions, increasing the effective facing area between the control gate and the floating gate, and facilitating an increase in the coupling capacitance between the control gate and the floating gate. This improves the device's data retention capability and reduces the device's refresh power consumption.

[0028] In one possible implementation, before forming the first gate dielectric layer, a shallow trench isolation structure is formed on the substrate. The shallow trench isolation structure is partially located within the substrate, and the first surface of the shallow trench isolation structure is higher than the upper surface of the substrate. After forming a plurality of spaced floating gates, the shallow trench isolation structure is located between two adjacent floating gates. The shallow trench isolation structure is etched so that the first surface is lower than the second surface and higher than the upper surface of the substrate relative to a reference plane. A recess is formed between the shallow trench isolation structure and the two floating gates located on either side. Finally, a control gate is formed within the recess.

[0029] The method involves first forming a shallow trench isolation structure, then forming floating gates on both sides of the shallow trench isolation structure, etching the shallow trench isolation structure so that the top surface of the shallow trench isolation structure is lower than the top surface of the floating gate, and forming a groove between the shallow trench isolation structure and the floating gate. Finally, the groove is filled with a control gate material, so that the control gate is embedded in the groove. The portion of the control gate embedded in the groove faces the surface of the floating gate, which helps increase the effective facing area between the control gate and the floating gate, and increases the coupling capacitance between the control gate and the floating gate, thereby improving the data retention capability of the device and reducing the refresh power consumption of the device.

[0030] In one possible implementation, a first gate dielectric layer covers the shallow trench isolation structure. During the etching of the shallow trench isolation structure, the first gate dielectric layer is also etched to expose the floating gate. Then, a second gate dielectric layer is formed covering the floating gate to insulate the floating gate from the control gate.

[0031] The first gate dielectric layer and the shallow trench isolation structure are made of the same material. By selectively etching the first gate dielectric layer and the shallow trench isolation structure, the portion of the side wall of the floating gate adjacent to the top surface can be exposed, so that the top surface of the shallow trench isolation structure is lower than the top surface of the floating gate. The top surface of the shallow trench isolation structure can form a groove with the floating gates on both adjacent sides.

[0032] In another possible implementation, the first gate dielectric layer includes a third portion and a fourth portion, the third portion covers the first surface of the shallow trench isolation structure, and the fourth portion covers the sidewall of the shallow trench isolation structure. During the etching of the shallow trench isolation structure, the third portion is also etched, leaving the fourth portion, which covers the sidewall of the floating gate and exposes the second surface of the floating gate. Then, a second gate dielectric layer is formed covering the second surface of the floating gate. The fourth portion of the first gate dielectric layer and the second gate dielectric layer achieve insulation between the floating gate and the control gate. In addition, when the material of the floating gate includes polysilicon, a thermal oxidation process can be used to form an oxide layer on the second surface of the floating gate, and the oxide layer is used as the second gate dielectric layer, avoiding the use of a thin film deposition process to form the second gate dielectric layer, thereby simplifying the preparation process.

[0033] In one possible implementation, before forming the first gate dielectric layer, a shallow trench isolation structure is formed on the substrate. The shallow trench isolation structure is located within the substrate, and the first surface of the shallow trench isolation structure is flush with the upper surface of the substrate. A floating gate layer is then formed, located on the substrate and the shallow trench isolation structure. The portion of the floating gate layer located on the shallow trench isolation structure is removed to form a plurality of floating gates arranged in an interval. The shallow trench isolation structure is located between two adjacent floating gates, and the first surface is lower than the second surface relative to a reference plane. The shallow trench isolation structure and the two floating gates located on either side form a groove. Finally, a control gate is formed within the groove.

[0034] A floating gate layer is formed overlying the shallow trench isolation structure, with the top surface of the floating gate layer being higher than the top surface of the shallow trench isolation structure. The portion of the floating gate layer located above the shallow trench isolation structure is then etched away to form a recess in the floating gate layer. Finally, a control gate material is filled into the recess, embedding the control gate within the recess. The portion of the control gate embedded within the recess faces the surface of the floating gate, increasing the effective facing area between the control gate and the floating gate, and thus increasing the coupling capacitance between the control gate and the floating gate. This improves the device's data retention capability and reduces the device's refresh power consumption.

[0035] In one possible implementation, a second gate dielectric layer covering the floating gate is formed before forming the control gate. An insulating layer is formed on the first surface of the shallow trench isolation structure, with the surface of the insulating layer distal to the reference plane being lower than the second surface of the floating gate relative to the reference plane to prevent the insulating layer from filling the groove. The insulating layer increases the vertical distance between the control gate and the shallow trench isolation structure, and increases the distance between the control gate and the upper surface of the substrate, thereby reducing the risk of electrical contact between the control gate and the substrate and causing a short circuit.

[0036] In a third aspect, a memory is provided, which includes a controller and the above-mentioned integrated circuit, and the integrated circuit is electrically connected to the controller.

[0037] In a fourth aspect, an electronic device is provided, which includes a circuit board and the above-mentioned memory, and the memory is electrically connected to the circuit board.

[0038] It can be understood that the beneficial effects that can be achieved by the memory and electronic device provided in this application can refer to the beneficial effects of the integrated circuit mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] FIG1 is a schematic diagram of the structure of the server provided by this application;

[0040] FIG2 is an architectural diagram of the memory provided by this application;

[0041] FIG3 is a partial structural diagram of a storage array provided by the present application;

[0042] FIG4 is a schematic diagram of a half-floating gate transistor performing a write operation;

[0043] FIG5 is a schematic diagram of an erase operation of a half-floating gate transistor;

[0044] FIG6 is a partial enlarged view of the memory array at position M in FIG3 ;

[0045] 7A to 7K are diagrams showing the steps of preparing a memory array provided by the present application;

[0046] FIG8 is a partial structural diagram of another storage array provided by the present application;

[0047] 9A to 9K are diagrams showing the steps of preparing a memory array provided by the present application;

[0048] FIG10 is a partial structural diagram of another storage array provided by the present application;

[0049] 11A to 11J are diagrams showing steps of preparing a memory array according to the present application;

[0050] FIG12 is a partial structural diagram of another storage array provided by the present application;

[0051] 13A to 13L are diagrams showing the steps of preparing a memory array provided in this application. DETAILED DESCRIPTION

[0052] In order to solve the problem in the prior art that as the planar size of the semi-floating gate transistor is miniaturized, the facing area between the control gate and the floating gate is reduced, resulting in a decrease in the coupling capacitance value and a decrease in the data retention ability of the device, the present application proposes a semi-floating gate transistor, which adopts a design method of embedding the control gate at the top of the floating gate, thereby increasing the effective facing area between the control gate and the floating gate, which is beneficial to increase the coupling capacitance value between the control gate and the floating gate, thereby improving the data retention ability of the device and reducing the refresh power consumption of the device.

[0053] The present application provides an electronic device, which may be, for example, a server, a mobile phone, a tablet computer, a personal computer (PC), a vehicle-mounted electronic product, etc. The present application does not impose any special restrictions on the specific type of the electronic device.

[0054] FIG1 is a schematic diagram of the structure of the server provided in this application.

[0055] 1 , a server 1 includes a cabinet 11, a circuit board 12 disposed in the cabinet 11, and a chip 13 disposed on the circuit board 12. The chip 13 is electrically connected to the circuit board 12. The circuit board 12 includes but is not limited to a printed circuit board (PCB).

[0056] The chip 13 may be a memory chip, and the memory may include, for example, dynamic random access memory (DRAM), static random access memory (SRAM), etc. In terms of packaging form, the memory may include a registered dual in-line memory module (RDIMM), a small outline dual in-line memory module (SO-DIMM), a high bandwidth memory (HBM), etc.

[0057] Taking DRAM as an example, FIG2 is an architecture diagram of the memory provided in this application.

[0058] 2 , the memory 2 includes a memory array 21 , a row decoder 22 , a column decoder 23 , a controller 24 , a read / write control circuit 25 , and a sense amplifier 26 .

[0059] The memory array 21 includes a plurality of memory cells 210 arranged in an array, wherein the plurality of memory cells 210 include a plurality of rows arranged along a first direction X and a plurality of columns arranged along a second direction Y. The first direction X and the second direction Y intersect, for example, are perpendicular to each other.

[0060] The controller 24 is electrically connected to the row decoder 22 , the column decoder 23 , the memory array 21 , the read / write control circuit 25 , and the sense amplifier 26 , respectively. The controller 24 is configured to control each circuit.

[0061] The row decoder 22 is electrically connected to the memory array 21 . The row decoder 22 is configured to select the memory cells 210 in the corresponding row according to the row address so as to address the memory cells 210 in the corresponding row.

[0062] The column decoder 23 is electrically connected to the memory array 21. After the memory cells 210 of the corresponding row are selected, the column decoder 23 is configured to address the memory cells 210 of the corresponding column according to the column address, thereby selecting the memory cells 210 that need to be read or written.

[0063] The read / write control circuit 25 is electrically connected to the memory array 21 , and is configured to control the selected memory cell 210 to perform a read operation or a write operation.

[0064] The sense amplifier 26 is electrically connected to the memory array 21 and is configured to read, amplify and output the data information stored in the selected memory cell 210 to implement a data read operation; or, input a data signal to the selected memory cell 210 to implement a data write operation.

[0065] In traditional DRAM, the memory cell 210 is based on a transistor and storage capacitor architecture. As devices become smaller, this architecture faces numerous challenges. For example, transistor drive current decreases, leakage current increases, and the storage capacitor's capacity decreases, leading to decreased data retention and increased power consumption. Furthermore, the device's manufacturing process becomes complex, leading to a sharp increase in cost. Therefore, a new type of memory is urgently needed to replace DRAM.

[0066] A semi-floating gate transistor (SFGT) is a microelectronic device that can replace the memory cell 210 in a DRAM to produce a SFGT memory. The SFGT memory is compatible with the DRAM controller 24 and control instructions. Specifically, the DRAM controller 24 and control instructions can be used to perform read and write operations on the SFGT memory. This minimizes any impact on the original functions or structures of other DRAM-related hardware circuits when the SFGT memory is used to replace the DRAM, thereby reducing the cost and complexity of the DRAM replacement.

[0067] The difference from DRAM is that in the semi-floating gate transistor memory, the storage cell includes a semi-floating gate transistor, and the storage cell does not have a storage capacitor. The semi-floating gate transistor memory has the characteristics of low operating (read / write) voltage, fast operating speed, unlimited erasable times, small device size and high storage density. In addition, the preparation process of the semi-floating gate transistor is compatible with the currently mature complementary metal oxide semiconductor (CMOS) process, making the preparation process of the semi-floating gate transistor memory simple and low-cost.

[0068] The present application provides a memory array using half-floating gate transistors as memory cells. FIG3 is a partial structural diagram of a memory array provided by the present application. The left side of FIG3 is a main view of the memory array, and the right side is a cross-sectional view of the left main view along the section line AA', which shows the "cross-sectional surface of multiple half-floating gate transistors."

[0069] 3 , a partial structural diagram of the memory array 3 shows 2 rows×5 columns of half-floating-gate transistors T. The half-floating-gate transistors T in each row are arranged along a first direction X, and the half-floating-gate transistors T in each column are arranged along a second direction Y. This application does not impose any limitation on this.

[0070] 3 , the memory array 3 includes a substrate 30 , and a source S, a drain D, a floating gate (Semi-Floating Gate, SFG) 31 and a control gate (Controlling Gate, CG) 32 disposed on the substrate 30 .

[0071] Exemplarily, the thickness direction of the substrate 30 may be along the third direction Z. The substrate 30 includes a lower surface R1 and an upper surface R2 that are opposite to each other along the third direction Z. The substrate 30 includes a p-well 30a and an n-well 30b disposed on the p-well 30a. The material of the p-well 30a includes a p-type semiconductor material, and the material of the n-well 30b includes an n-type semiconductor material. The source S and the drain D are located in the n-well 30b.

[0072] 3 , the memory array 3 further includes a first gate dielectric layer 33 disposed on the upper surface R2 of the substrate 30. A via h is defined in the first gate dielectric layer 33. A plurality of floating gates 31 are spaced apart and arranged on the first gate dielectric layer 33 along a first direction X. Each floating gate 31 is electrically connected to the substrate 30 via a via h in the first gate dielectric layer 33. The via h serves as a "window" for charge transfer between the floating gate 31 and the substrate 30.

[0073] For example, the projection of the via h on the plane XY can be circular or rectangular. When the via h is circular, the diameter of the via h is in the range of 10 nm to 20 nm. When the via h is rectangular, the length of the via h is in the range of 10 nm to 20 nm, and the width is in the range of 10 nm to 20 nm.

[0074] Continuing with FIG3 , each control gate 32 corresponds to a plurality of floating gates 31, and the control gate 32 is disposed on the corresponding plurality of floating gates 31. The floating gate 31 includes an end portion A away from the lower surface R1 of the substrate 30. In a cross-section of the semi-floating gate transistor T, the end portion A of the floating gate 31 is embedded within the control gate 32. Alternatively, a portion of the control gate 32 is embedded between two adjacent floating gates 31.

[0075] It can be understood that the "cross-section of the half-floating gate transistor T" is both perpendicular to the lower surface R1 of the substrate 30 and parallel to the direction in which the multiple floating gates 31 are spaced apart. From Figure 3, the cross-section of the half-floating gate transistor T is both perpendicular to the plane XY and parallel to the first direction X.

[0076] The source S and the drain D are arranged along the second direction Y, and the floating gate 31 is located between the source S and the drain D. Each floating gate 31 and the corresponding source S, drain D and control gate 32 constitute a half-floating gate transistor T. Since the floating gate 31 and the control gate 32 are stacked along the third direction Z, this structure of the half-floating gate transistor T can be called a "vertical stacked gate structure".

[0077] Furthermore, along the first direction X, in each row of half-floating gate transistors T, multiple half-floating gate transistors T share a source S, a drain D, and a control gate 32 , and every two adjacent half-floating gate transistors T in the second direction Y share a source S.

[0078] Exemplarily, the memory array 3 further includes a second gate dielectric layer 34 . The second gate dielectric layer 34 is located between the floating gate 31 and the control gate 32 and is used for insulating the floating gate 31 from the control gate 32 .

[0079] For example, part of the floating gate 31 may be embedded in the substrate 30, and part may be located on the surface of the substrate 30. By increasing the size of the floating gate 31 along the third direction Z, the area of ​​the floating gate 31 along the plane XY can be reduced while ensuring that the performance of the floating gate 31 in storing charges remains unchanged, which is beneficial to the miniaturization of the device.

[0080] 3 , the half-floating gate transistor T further includes a spacer layer 35 . Along the second direction Y, the spacer layer 35 is located between two adjacent half-floating gate transistors T to separate the floating gate 31 and the control gate 32 of the two adjacent half-floating gate transistors T, thereby achieving insulation between the devices.

[0081] FIG4 is a schematic diagram of a semi-floating gate transistor performing a write operation; FIG5 is a schematic diagram of a semi-floating gate transistor performing an erase operation.

[0082] Referring to Figure 4, a write operation voltage is applied to the control gate 32, source S and drain D of the semi-floating gate transistor T. For example, the operation voltage received by the control gate 32 is -1.5V, the source S is connected to the ground terminal GND, and the operation voltage of the drain D is 3V. Under the action of the electric field, positive charges enter the floating gate 31 from the drain D and the n-well 30b through the hole h. The positive charge in the floating gate 31 increases, causing the threshold voltage of the semi-floating gate transistor T to decrease, thereby realizing data writing (writing data "1").

[0083] Based on this, by applying a fixed read operation voltage to the control gate 32, source S and drain D of the semi-floating gate transistor T, the semi-floating gate transistor T is fully turned on due to the low threshold voltage of the semi-floating gate transistor T, and a large drain-source current I is generated between the drain D and the source S. ds , at this time the data "1" can be read.

[0084] Referring to Figure 5, an operating voltage is applied to the control gate 32, source S and drain D of the semi-floating gate transistor T. For example, the operating voltage received by the control gate 32 is 1.2V, the source S is connected to the ground terminal GND, and the operating voltage of the drain D is 0.6V. Under the action of the electric field, positive charges pass from the floating gate 31 through the hole h into the n-well 30b and the drain D. The positive charge in the floating gate 31 is reduced, which increases the threshold voltage of the semi-floating gate transistor T, thereby achieving data erasure (also known as: writing data "0").

[0085] Based on this, by applying the same read operation voltage to the control gate 32, source S and drain D of the semi-floating gate transistor T, due to the high threshold voltage of the semi-floating gate transistor T, the semi-floating gate transistor T is not fully turned on, and a small drain-source current I is generated between the drain D and the source S. ds , at this time the data "0" can be read.

[0086] During the data writing process of the semi-floating gate transistor T, a large amount of positive charge is stored in the floating gate 31, and a coupling capacitance can be generated between the control gate 32 and the floating gate 31. It can be understood that the data is stored in the coupling capacitance, and the capacitance value of the coupling capacitance directly affects its data retention capability.

[0087] In the present application, the control gate 32 of the semi-floating gate transistor T is stacked on the floating gate 31. In a cross-sectional view of the semi-floating gate transistor T, the end A of the floating gate 31, which is away from the lower surface R1 of the substrate 30, is embedded in the control gate 32. Compared to the prior art in which the control gate and the floating gate only face each other in the third direction Z, in the present application, the control gate 32 and the floating gate 31 face each other not only in the third direction Z but also in the first direction X. This achieves surface facing of the control gate 32 and the floating gate 31 in multiple directions, increases the effective facing area between the control gate 32 and the floating gate 31, and facilitates increasing the coupling capacitance between the control gate 32 and the floating gate 31, thereby improving the data retention capability of the device and reducing the refresh power consumption of the device.

[0088] In addition, the source S and the drain D are arranged along the second direction Y, the floating gate 31 also includes a side wall close to the drain D, and the control gate 32 can also cover the side wall of the floating gate 31 close to the drain D, thereby achieving that the control gate 32 and the floating gate 31 are directly facing each other on the upper surface in the second direction Y, and also increasing the effective facing area between the control gate 32 and the floating gate 31, which is beneficial to increasing the coupling capacitance value between the control gate 32 and the floating gate 31.

[0089] To facilitate the introduction of local structural features of the memory array in FIG3 , FIG6 is shown below as a partial enlarged view of the memory array at position M in FIG3 .

[0090] 6 , the memory array 3 further includes shallow trench isolation (STI) structures 34 disposed on the substrate 30 . A plurality of STI structures 36 are arranged in a spaced relationship along a first direction X. The STI structures 36 and the floating gates 31 are alternately disposed along the first direction X. Each STI structure 36 is located between two adjacent floating gates 31 , and serves to isolate the two adjacent floating gates 31 .

[0091] For the sake of convenience, the lower surface R1 of the substrate 30 is taken as the reference plane R1, the shallow trench isolation structure 36 includes a first surface P1 away from the reference plane R1, and the floating gate 31 includes a second surface P2 away from the reference plane R1. Relative to the reference plane R1, the first surface P1 of the shallow trench isolation structure 36 is lower than the second surface P2 of the floating gate 31. In other words, the top surface of the shallow trench isolation structure 36 is lower than the top surface of the floating gate 31.

[0092] By setting the top surface of the shallow trench isolation structure 36 lower than the top surface of the floating gate 31, the shallow trench isolation structure 36 can form a groove C with the floating gates 31 located on both sides thereof, and at least a portion of the control gate 32 can be embedded in the groove C. Along the first direction X, the portion of the control gate 32 embedded in the groove C is opposite to the surface of the floating gate 31, which is beneficial to increase the effective facing area between the control gate 32 and the floating gate 31, and increase the coupling capacitance value between the control gate 32 and the floating gate 31.

[0093] 6 , the second gate dielectric layer 34 extends into the control gate 32 and can be broken down into a first portion 34a and a second portion 34b. Along a first direction X, the first portion 34a is located between the floating gate 31 and the control gate 32. Along a third direction Z, the second portion 34b is located between the floating gate 31 and the control gate 32. In other words, the second gate dielectric layer 34 covers the top surface and the portion of the sidewall adjacent to the top surface of the floating gate 31, thereby insulating the floating gate 31 from the control gate 32. The second gate dielectric layer 34 serves as the dielectric for the coupling capacitor formed between the floating gate 31 and the control gate 32.

[0094] For example, the second gate dielectric layer 34 serves as the dielectric of the coupling capacitor, and the dielectric constant of the material thereof may range from 4 to 100, for example, the dielectric constant of the material thereof may be 4, 20, 50, 80, or 100. The second gate dielectric layer 34 may be made of a material with a high dielectric constant, for example, at least one of hafnium oxide, zirconium oxide, or hafnium zirconium oxide, which helps increase the coupling capacitance between the control gate 32 and the floating gate 31.

[0095] 6 , the portion of the control gate 32 embedded in the recess C includes a third surface P3 close to the reference plane R1. Relative to the reference plane R1, the third surface P3 of the control gate 32 is lower than the second surface P2 of the floating gate 31. A portion of the second gate dielectric layer 34 is also located between the third surface P3 and the first surface P1.

[0096] Exemplarily, the substrate 30 also includes an upper surface R2 near the control gate 32, and a portion of the shallow trench isolation structure 36 is located within the substrate 30. Moreover, relative to the reference plane R1, the first surface P1 of the shallow trench isolation structure 36 is higher than the upper surface R2 of the substrate 30, which is equivalent to that a portion of the shallow trench isolation structure 36 is embedded in the substrate 30 and a portion thereof extends outside the substrate 30.

[0097] It is understandable that if the first surface P1 of the shallow trench isolation structure 36 is flush with the upper surface R2 of the substrate 30 , the portion of the control gate 32 embedded in the groove C may be in direct contact with the shallow trench isolation structure 36 , and there is a possibility that the control gate 32 is in electrical contact with the substrate 30 .

[0098] By setting a second gate dielectric layer 34 between the third surface P3 of the control gate 32 and the first surface P1 of the shallow trench isolation structure 36, the distance between the control gate 32 and the shallow trench isolation structure 36 along the third direction Z can be increased, and the distance between the control gate 32 and the upper surface R2 of the substrate 30 can be further increased, thereby reducing the risk of short circuit due to electrical contact between the control gate 32 and the substrate 30.

[0099] 6 , a control gate 32 extends along a first direction X. In each row of half-floating-gate transistors T, multiple half-floating-gate transistors T share a common control gate 32. Typically, one of the two opposite ends of the control gate 32 along the first direction X receives a voltage signal, and this end of the control gate 32 can be referred to as the "proximal end." The other end can be referred to as the "distal end." The voltage signal is transmitted from the proximal end to the distal end of the control gate 32.

[0100] Currently, the control gate is mostly made of polysilicon, which has a large resistance. During the transmission of the voltage signal on the control gate, a voltage drop (IR drop) will be generated, causing the actual operating voltage received by the far end of the control gate to be lower than the rated operating voltage, which will affect the read / write operation of the semi-floating gate transistor.

[0101] In the present application, the control gate 32 is made of metal or metal nitride. For example, the material of the control gate 32 includes at least one of tungsten, aluminum, titanium nitride or tantalum nitride, which can reduce the resistance of the control gate 32 and reduce the voltage drop generated by the voltage signal transmitted on the control gate 32. In this way, on the premise that the actual operating voltage received at the far end of the control gate 32 reaches the rated operating voltage, it is beneficial to increase the number of semi-floating gate transistors T corresponding to the same control gate 32, thereby helping to improve the storage density of the memory array 3.

[0102] The above describes the structural features of the memory array provided by the present application and the working principle of the half-floating gate transistor in the memory array in conjunction with Figures 3 to 6. Next, the preparation method of the memory array shown in Figure 3 is further described in conjunction with Figures 7A to 7K.

[0103] The method for preparing the storage array comprises the following steps:

[0104] 7A , a plurality of first trenches 40 are formed on a substrate 30 , and the plurality of first trenches 40 are arranged along a first direction X. The depth of the first trenches 40 is greater than the depth of the n-well 30 b , and the bottom of the first trenches 40 is located in the p-well 30 a .

[0105] For example, a thin film deposition process can be used to sequentially form a first mask layer 41 and a second mask layer 42 on the substrate 30. The material of the first mask layer 41 can include, for example, silicon oxide, and the material of the second mask layer 42 can include, for example, silicon nitride. Then, a photolithography process is used to etch the first mask layer 41 and the second mask layer 42 to form via holes, thereby patterning the first mask layer 41 and the second mask layer 42. Finally, the substrate 30 is etched using the first mask layer 41 and the second mask layer 42 as masks to form a plurality of first trenches 40 on the substrate 30.

[0106] Referring to FIG. 7B , a dielectric material, such as silicon dioxide, is deposited to fill a plurality of first trenches 40, thereby forming shallow trench isolation structures 36 within the first trenches 40. Shallow trench isolation structures 36 include a first surface P1 distal from reference plane R1. The region of substrate 30 between two adjacent shallow trench isolation structures 36 may be defined as an active area AA. The active area AA of substrate 30 may serve as a channel for charge transfer in semi-floating-gate transistor T.

[0107] It can be understood that before removing the first mask layer 41 and the second mask layer 42, the dielectric material is deposited, and the dielectric material will also fill the vias on the first mask layer 41 and the second mask layer 42, so that the first surface P1 of the shallow trench isolation structure 36 is flush with the upper surface of the second mask layer 42. Therefore, the first surface P1 of the shallow trench isolation structure 36 is higher than the upper surface R2 of the substrate 30, so that the shallow trench isolation structure 36 is partially embedded in the substrate 30 and partially extends outside the substrate 30.

[0108] 7B and 7C , the first mask layer 41 and the second mask layer 42 are removed, and then the substrate 30 is etched using a photolithography process to form a second trench 43. The depth of the second trench 43 is greater than the depth of the n-well 30b and less than the depth of the shallow trench isolation structure 36. The bottom of the second trench 43 is located in the p-well 30a.

[0109] 7C and 7D , a first gate dielectric layer 33 is formed on the substrate 30 . A plurality of via holes h are formed in the first gate dielectric layer 33 , and the via holes h expose the substrate 30 .

[0110] For example, a thin film deposition process can be used to form the first gate dielectric layer 33. The first gate dielectric layer 33 covers the upper surface R2 of the substrate 30, the surface of the second trench 43, and the shallow trench isolation structure 36. The thickness of the first gate dielectric layer 33 does not exceed half the width of the second trench 43, so that the first gate dielectric layer 33 does not completely fill the second trench 43. Then, a photolithography process is used to etch the first gate dielectric layer 33 to form a via h exposing the substrate 30.

[0111] The material of the first gate dielectric layer 33 may include at least one of silicon dioxide, silicon nitride, or silicon oxynitride.

[0112] Alternatively, when the material of the substrate 30 includes silicon, a thermal oxidation process can be used to form an oxide layer on the upper surface R2 of the substrate 30 and the surface of the second trench 43. The oxide layer can serve as the first gate dielectric layer 33, that is, the material of the first gate dielectric layer 33 includes silicon dioxide.

[0113] 7D and 7E , a floating gate material layer is formed using a thin film deposition process. The floating gate material may include, for example, polysilicon doped with P-type ions. The floating gate material layer fills the second trench 43 and covers the first gate dielectric layer 33. A chemical mechanical polishing (CMP) process is then used to polish the upper surface of the floating gate material layer to make it flat. Finally, a photolithography process is used to etch the floating gate material layer, breaking the floating gate material layer along the second direction Y to form a floating gate layer 310. The floating gate layer 310 includes a second surface P2.

[0114] The floating gate layer 310 is formed on the first gate dielectric layer 33 and is electrically connected to the substrate 30 via a via h in the first gate dielectric layer 33. A portion of the floating gate layer 310 fills the second trench 43, and a portion is located on the upper surface R2 of the substrate 30. Increasing the size of the floating gate layer 310 along the third direction Z can improve the charge storage performance of the floating gate layer 310, or reduce the area of ​​the floating gate layer 310 along the XY plane, thereby facilitating device miniaturization.

[0115] 7F , when the materials of the first gate dielectric layer 33 and the shallow trench isolation structure 36 are both silicon dioxide and the material of the floating gate layer 310 is polysilicon, silicon dioxide and polysilicon have an etching selectivity ratio. Based on this, the first gate dielectric layer 33 and the shallow trench isolation structure 36 can be selectively etched to expose the portion of the sidewall adjacent to the top surface of the floating gate layer 310, so that the first surface P1 of the shallow trench isolation structure 36 is lower than the second surface P2 of the floating gate layer 310 and higher than the upper surface R2 of the substrate 30. The top of the shallow trench isolation structure 36 can form a groove C with the floating gate layer 310.

[0116] 7G , a second gate dielectric layer 34 is formed by a thin film deposition process. The second gate dielectric layer 34 covers the upper surface and the portion of the sidewall adjacent to the top surface of the floating gate layer 310 , the upper surface R2 of the substrate 30 , and the first surface P1 of the shallow trench isolation structure 36 .

[0117] The material of the second gate dielectric layer 34 may include at least one of silicon dioxide, silicon nitride, or silicon oxynitride.

[0118] Referring to FIG. 7H , a thin film deposition process is used to deposit a control gate material layer. The control gate material may include, for example, at least one of tungsten, aluminum, titanium nitride, or tantalum nitride. The control gate material layer fills the recess C and covers the second gate dielectric layer 34. A chemical mechanical polishing process is then used to polish the upper surface of the control gate material layer to make it flat. Finally, a photolithography process is used to etch the control gate material layer, breaking the control gate material layer along the second direction Y to form a control gate layer 320.

[0119] 7I , the control gate layer 320 , the second gate dielectric layer 34 , the floating gate layer 310 and the first gate dielectric layer 33 are etched to form a third trench 44 along the second direction Y to disconnect two adjacent rows of half-floating gate transistors T.

[0120] 7J , a spacer 35 is formed on the sidewalls of the third trench 44, with the bottom of the spacer 35 exposing the substrate 30. The spacer 35 can separate two adjacent rows of half-floating gate transistors T, thereby achieving insulation between the two adjacent rows of half-floating gate transistors T.

[0121] 7K , using the spacer layer 35 as a mask, an ion implantation process is employed to implant n-type ions into the n-well 30 b of the substrate 30 , and annealing is performed to form a source S and a drain D in the substrate 30 . Two adjacent rows of half-floating-gate transistors T share a common source S.

[0122] In the present application, the n-well 30b of the substrate 30 is disposed on the p-well 30a. By implanting n-type ions into the n-well 30b, a source S and a drain D are formed in the n-well 30b. The resulting semi-floating-gate transistor T is an N-type transistor. In other examples, the p-well of the substrate 30 may also be disposed on the n-well. By implanting p-type ions into the p-well, a source S and a drain D are formed in the p-well. The resulting semi-floating-gate transistor T is a P-type transistor.

[0123] The fabrication method provided herein first forms a plurality of shallow trench isolation structures 36 spaced apart along a first direction X. A floating gate layer 310 is then formed between two adjacent shallow trench isolation structures 36. The shallow trench isolation structures 36 are then etched until the top surfaces of the shallow trench isolation structures 36 are lower than the top surface of the floating gate layer 310, forming a recess C between the shallow trench isolation structures 36 and the floating gate layer 310. Finally, a control gate material is filled into the recess C, embedding the control gate layer 320 within the recess C. Along the first direction X, the portion of the control gate layer 320 embedded within the recess C faces the surface of the floating gate layer 310, thereby increasing the effective facing area between the control gate layer 320 and the floating gate layer 310. After the semi-floating gate transistor T is fabricated, the coupling capacitance between the control gate 32 and the floating gate 31 is increased, thereby improving the device's data retention capability and reducing the device's refresh power consumption.

[0124] Figure 8 is a partial structural diagram of another memory array provided in the present application. The difference from the memory array in Figure 3 is that the portion of the sidewall of the floating gate 31 adjacent to the top surface covers the first gate dielectric layer 33, and the portion of the control gate 32 embedded in the groove C is in direct contact with the shallow trench isolation structure 36.

[0125] 8 , along a first direction X, the first gate dielectric layer 33 is located between the floating gate 31 and the shallow trench isolation structure 36. The first gate dielectric layer 33 extends into the control gate 32 and is also located between the floating gate 31 and the control gate 32. Along a third direction Z, the second gate dielectric layer 34 is located between the floating gate 31 and the control gate 32. The first gate dielectric layer 33 and the second gate dielectric layer 34 provide insulation between the floating gate 31 and the control gate 32. The first gate dielectric layer 33 and the second gate dielectric layer 34 serve as dielectrics for the coupling capacitor formed between the floating gate 31 and the control gate 32.

[0126] Exemplarily, the first gate dielectric layer 33 and the second gate dielectric layer 34 serve as dielectrics for the coupling capacitor. The dielectric constant of the material of the first gate dielectric layer 33 may range from 4 to 100, for example, 4, 20, 50, 80, or 100. The dielectric constant of the material of the second gate dielectric layer 34 may range from 4 to 100, for example, 4, 20, 50, 80, or 100. Both the first gate dielectric layer 33 and the second gate dielectric layer 34 may be made of a high dielectric constant material, for example, at least one of hafnium oxide, zirconium oxide, or hafnium zirconium oxide, which helps increase the coupling capacitance between the control gate 32 and the floating gate 31.

[0127] 8 , the portion of the control gate 32 embedded in the groove C contacts the shallow trench isolation structure 36 , and the third surface P3 of the control gate 32 contacts the first surface P1 of the shallow trench isolation structure 36 .

[0128] Exemplarily, the substrate 30 further includes an upper surface R2 close to the control gate 32 , and the first surface P1 of the shallow trench isolation structure 36 is higher than the upper surface R2 of the substrate 30 , that is, part of the shallow trench isolation structure 36 is embedded in the substrate 30 and part of it extends outside the substrate 30 .

[0129] By setting the first surface P1 of the shallow trench isolation structure 36 higher than the upper surface R2 of the substrate 30 , the distance between the control gate 32 and the upper surface R2 of the substrate 30 can be increased, thereby reducing the risk of electrical contact and short circuit between the control gate 32 and the substrate 30 .

[0130] The present application also provides a method for preparing the memory array in Figure 8. Figures 9A to 9K are diagrams of the steps of preparing the memory array provided in the present application, which are similar to the method for preparing the memory array in Figures 7A to 7K, except for the two steps of Figures 9F and 9G: during the etching of the shallow trench isolation structure 36, only the portion of the first gate dielectric layer 33 covering the top surface of the shallow trench isolation structure 36 is etched, and the portion of the first gate dielectric layer 33 covering the sidewall of the shallow trench isolation structure 36 is retained. The retained portion of the first gate dielectric layer 33 will cover the sidewall of the floating gate layer 310, exposing the top surface of the floating gate layer 310. When the material of the floating gate layer 310 includes polysilicon, a thermal oxidation process can be used to form an oxide layer on the top surface of the floating gate layer 310, and the oxide layer is used as the second gate dielectric layer 34.

[0131] The method for preparing the storage array comprises the following steps:

[0132] 9A , a plurality of first trenches 40 are formed on a substrate 30 , and the plurality of first trenches 40 are arranged along a first direction X. The depth of the first trenches 40 is greater than the depth of the n-well 30 b , and the bottom of the first trenches 40 is located in the p-well 30 a .

[0133] 9B , a dielectric material is deposited. The dielectric material may include silicon dioxide, for example. The dielectric material is filled in the plurality of first trenches 40 to form a shallow trench isolation structure 36 in the first trenches 40. The shallow trench isolation structure 36 includes a first surface P1 away from the reference plane R1. The first surface P1 of the shallow trench isolation structure 36 is higher than the upper surface R2 of the substrate 30, thereby achieving a state where the shallow trench isolation structure 36 is partially embedded in the substrate 30 and partially extends outside the substrate 30.

[0134] 9B and 9C , the first mask layer 41 and the second mask layer 42 are removed, and then the substrate 30 is etched using a photolithography process to form a second trench 43. The depth of the second trench 43 is greater than the depth of the n-well 30b and less than the depth of the shallow trench isolation structure 36. The bottom of the second trench 43 is located in the p-well 30a.

[0135] 9D , a first gate dielectric layer 33 is formed on a substrate 30. A plurality of via holes h are defined in the first gate dielectric layer 33, and the via holes h expose the substrate 30. The first gate dielectric layer 33 includes a third portion 33 a and a fourth portion 33 b. The third portion 33 a covers the first surface P1 of the shallow trench isolation structure 36, and the fourth portion 33 b covers the sidewalls of the shallow trench isolation structure 36.

[0136] 9D and 9E , a thin film deposition process is used to form a floating gate material layer. The floating gate material may include, for example, polysilicon doped with P-type ions. The floating gate material layer fills the second trench 43 and covers the first gate dielectric layer 33. A chemical mechanical polishing (CMP) process is then used to polish the upper surface of the floating gate material layer to make it flat. Finally, a photolithography process is used to etch the floating gate material layer, breaking the floating gate material layer along the second direction Y to form a floating gate layer 310. The floating gate layer 310 includes a second surface P2.

[0137] 9F , a photolithography process is used to etch the third portion 33 a of the first gate dielectric layer 33 and the shallow trench isolation structure 36 , leaving the fourth portion 33 b of the first gate dielectric layer 33 . The fourth portion 33 b covers the sidewalls of the floating gate layer 310 , exposing the second surface P2 of the floating gate layer 310 .

[0138] By etching the shallow trench isolation structure 36 , the first surface P1 of the shallow trench isolation structure 36 is lower than the second surface P2 of the floating gate layer 310 and higher than the upper surface R2 of the substrate 30 . The top of the shallow trench isolation structure 36 can form a groove C with the floating gate layer 310 .

[0139] 9F and 9G , when the material of the floating gate layer 310 includes polysilicon, a thermal oxidation process may be used to form an oxide layer on the second surface P2 of the floating gate layer 310 , which may serve as the second gate dielectric layer 34 , that is, the material of the second gate dielectric layer 34 includes silicon dioxide.

[0140] Referring to FIG. 9H , a thin film deposition process is used to deposit a control gate material layer. The control gate material may include, for example, at least one of tungsten, aluminum, titanium nitride, or tantalum nitride. The control gate material layer fills the recess C and covers the fourth portion 33b of the first gate dielectric layer 33 and the second gate dielectric layer 34. A chemical mechanical polishing process is then used to polish the upper surface of the control gate material layer to make it smooth. Finally, a photolithography process is used to etch the control gate material layer, breaking the control gate material layer along the second direction Y to form a control gate layer 320.

[0141] 9I , the control gate layer 320 , the second gate dielectric layer 34 , the floating gate layer 310 and the first gate dielectric layer 33 are etched to form a third trench 44 along the second direction Y to disconnect two adjacent rows of half-floating gate transistors T.

[0142] 9J , a spacer 35 is formed on the sidewalls of the third trench 44, with the bottom of the spacer 35 exposing the substrate 30. The spacer 35 can separate two adjacent rows of half-floating gate transistors T, thereby achieving insulation between the two adjacent rows of half-floating gate transistors T.

[0143] 9K , using the spacer layer 35 as a mask, an ion implantation process is employed to implant n-type ions into the n-well 30 b of the substrate 30 , and annealing is performed to form a source S and a drain D in the substrate 30 . Two adjacent rows of half-floating-gate transistors T share a common source S.

[0144] The above-mentioned preparation method provided in the present application, during the process of etching the shallow trench isolation structure 36, only the portion of the first gate dielectric layer 33 covering the top surface of the shallow trench isolation structure 36 is etched, and the portion of the first gate dielectric layer 33 covering the side wall of the shallow trench isolation structure 36 is retained. The retained portion of the first gate dielectric layer 33 will cover the side wall of the floating gate layer 310, exposing the top surface of the floating gate layer 310. When the material of the floating gate layer 310 includes polysilicon, a thermal oxidation process can be used to form an oxide layer on the top surface of the floating gate layer 310, and the oxide layer is used as the second gate dielectric layer 34, avoiding the use of a thin film deposition process to form the second gate dielectric layer 34, thereby simplifying the preparation process.

[0145] Figure 10 is a partial structural diagram of another storage array provided in the present application. The difference from the storage array in Figure 3 is that the top surface of the shallow trench isolation structure 36 is flush with the upper surface R2 of the substrate 30, and the first gate dielectric layer 33 also covers the top surface of the shallow trench isolation structure 36 to add a first gate dielectric layer 33 between the control gate 32 and the shallow trench isolation structure 36.

[0146] 10 , a shallow trench isolation structure 36 is located in the substrate 30 , and a first surface P1 of the shallow trench isolation structure 36 is flush with an upper surface R2 of the substrate 30 .

[0147] The third surface P3 of the control gate 32 is lower than the second surface P2 of the floating gate 31 and higher than the first surface P1 of the shallow trench isolation structure 36 . Portions of the first gate dielectric layer 33 and the second gate dielectric layer 34 are also located between the third surface P3 and the first surface P1 .

[0148] It is understandable that the first surface P1 of the shallow trench isolation structure 36 is flush with the upper surface R2 of the substrate 30 . If the portion of the control gate 32 embedded in the groove C is in direct contact with the shallow trench isolation structure 36 , there is a possibility that the control gate 32 is in electrical contact with the substrate 30 .

[0149] Based on this, a first gate dielectric layer 33 and a second gate dielectric layer 34 are set between the third surface P3 of the control gate 32 and the first surface P1 of the shallow trench isolation structure 36, which can increase the distance between the control gate 32 and the shallow trench isolation structure 36 along the third direction Z, and further increase the distance between the control gate 32 and the upper surface R2 of the substrate 30, thereby reducing the risk of short circuit due to electrical contact between the control gate 32 and the substrate 30.

[0150] The present application also provides a method for preparing the memory array in Figure 10. Figures 11A to 11J are diagrams of the steps of preparing the memory array provided in the present application, which are similar to the method for preparing the memory array in Figure 3, except that in steps 11A, 11B and 11E: a shallow trench isolation structure 36 is formed, the top surface of the shallow trench isolation structure 36 is roughly flush with the upper surface R2 of the substrate 30, and then a floating gate layer 310 is formed covering the shallow trench isolation structure 36, the top surface of the floating gate layer 310 is higher than the top surface of the shallow trench isolation structure 36, and the portion of the floating gate layer 310 located on the shallow trench isolation structure 36 is removed by etching to form a groove C on the floating gate layer 310.

[0151] The method for preparing the storage array comprises the following steps:

[0152] 11A , a plurality of first trenches 40 are formed on a substrate 30 , and the plurality of first trenches 40 are arranged along a first direction X. The depth of the first trenches 40 is greater than the depth of the n-well 30 b , and the bottom of the first trenches 40 is located in the p-well 30 a .

[0153] For example, a thin film deposition process can be used to sequentially form a first mask layer 41 and a second mask layer 42 on the substrate 30. The material of the first mask layer 41 can include, for example, silicon oxide, and the material of the second mask layer 42 can include, for example, silicon nitride. Then, a photolithography process is used to etch the first mask layer 41 and the second mask layer 42 to form via holes, thereby patterning the first mask layer 41 and the second mask layer 42. Finally, the substrate 30 is etched using the first mask layer 41 and the second mask layer 42 as masks to form a plurality of first trenches 40 on the substrate 30.

[0154] 11A and 11B , a dielectric material is deposited. The dielectric material may include silicon dioxide, for example. The dielectric material is filled into a plurality of first trenches 40 to form shallow trench isolation structures 36 in the first trenches 40. The shallow trench isolation structure 36 includes a first surface P1 away from the reference plane R1. The first surface P1 of the shallow trench isolation structure 36 is flush with the upper surface R2 of the substrate 30. The entire shallow trench isolation structure 36 is embedded in the substrate 30.

[0155] It is understood that the thickness of the first mask layer 41 and the second mask layer 42 is set to be relatively thin, and the dielectric material is deposited to fill the first trench 40 to form the shallow trench isolation structure 36 in the first trench 40. Then, during the process of etching away the first mask layer 41 and the second mask layer 42, the top of the shallow trench isolation structure 36 is also etched, so that the first surface P1 of the shallow trench isolation structure 36 is substantially flush with the upper surface R2 of the substrate 30, thereby achieving that the shallow trench isolation structure 36 is completely embedded in the substrate 30.

[0156] 11C , the substrate 30 is etched using a photolithography process to form a second trench 43. The depth of the second trench 43 is greater than that of the n-well 30b and less than that of the shallow trench isolation structure 36. The bottom of the second trench 43 is located in the p-well 30a.

[0157] 11C and 11D , a first gate dielectric layer 33 is formed on a substrate 30. A plurality of via holes h are defined in the first gate dielectric layer 33, and the via holes h expose the substrate 30. The first gate dielectric layer 33 covers the upper surface R2 of the substrate 30, the surface of the second trench 43, and the shallow trench isolation structure 36.

[0158] 11D and 11E , a floating gate material layer is formed using a thin film deposition process. The floating gate material may include, for example, polysilicon doped with P-type ions. The floating gate material layer fills the second trench 43 and covers the first gate dielectric layer 33. A chemical mechanical polishing process is then used to polish the upper surface of the floating gate material layer to make it flat. Finally, a photolithography process is used to etch the floating gate material layer, breaking it along the second direction Y and removing the portion of the floating gate material layer located above the shallow trench isolation structure 36 to form a floating gate layer 310. The floating gate layer 310 includes a second surface P2.

[0159] Since the first surface P1 of the shallow trench isolation structure 36 is lower than the second surface P2 of the floating gate layer 310 , a groove C can be formed between the top of the shallow trench isolation structure 36 and the floating gate layer 310 by removing the portion of the floating gate material layer located on the shallow trench isolation structure 36 .

[0160] 11F , a second gate dielectric layer 34 is formed by a thin film deposition process. The second gate dielectric layer 34 covers the upper surface and the portion of the sidewalls adjacent to the top surface of the floating gate layer 310 , and covers the first gate dielectric layer 33 .

[0161] Referring to FIG. 11G , a thin film deposition process is used to deposit a control gate material layer. The control gate material may include, for example, at least one of tungsten, aluminum, titanium nitride, or tantalum nitride. The control gate material layer fills the recess C and covers the second gate dielectric layer 34. A chemical mechanical polishing process is then used to polish the upper surface of the control gate material layer to make it flat. Finally, a photolithography process is used to etch the control gate material layer, breaking the control gate material layer along the second direction Y to form a control gate layer 320.

[0162] 11H , the control gate layer 320 , the second gate dielectric layer 34 , the floating gate layer 310 and the first gate dielectric layer 33 are etched to form a third trench 44 along the second direction Y to disconnect two adjacent rows of half-floating gate transistors T.

[0163] 11I , a spacer 35 is formed on the sidewalls of the third trench 44, with the bottom of the spacer 35 exposing the substrate 30. The spacer 35 can separate two adjacent rows of half-floating gate transistors T, thereby achieving insulation between the two adjacent rows of half-floating gate transistors T.

[0164] 11J , using the spacer layer 35 as a mask, an ion implantation process is employed to implant n-type ions into the n-well 30 b of the substrate 30 , and annealing is performed to form a source S and a drain D in the substrate 30 . Two adjacent rows of half-floating-gate transistors T share a common source S.

[0165] The above-described fabrication method provided herein forms a floating gate layer 310 covering a plurality of shallow trench isolation structures 36. The top surface of the floating gate layer 310 is higher than the top surface of the shallow trench isolation structures 36. The portion of the floating gate layer 310 located above the shallow trench isolation structures 36 is removed by etching to form a recess C in the floating gate layer 310.

[0166] FIG12 is a partial structural diagram of another memory array provided in the present application, which differs from the memory array in FIG10 in that an insulating layer 37 is additionally provided between the control gate 32 and the shallow trench isolation structure 36 .

[0167] 12 , the memory array 3 further includes an insulating layer 37 , portions of the first and second gate dielectric layers 33 and 34 , and the insulating layer 37 is located between the third surface P3 of the control gate 32 and the first surface P1 of the shallow trench isolation structure 36 .

[0168] It is understandable that the first surface P1 of the shallow trench isolation structure 36 is flush with the upper surface R2 of the substrate 30 . If the portion of the control gate 32 embedded in the groove C is in direct contact with the shallow trench isolation structure 36 , there is a possibility that the control gate 32 is in electrical contact with the substrate 30 .

[0169] On the basis of setting the first gate dielectric layer 33 and the second gate dielectric layer 34 between the third surface P3 of the control gate 32 and the first surface P1 of the shallow trench isolation structure 36, an insulating layer 37 is added between the third surface P3 of the control gate 32 and the second gate dielectric layer 34, which can further increase the distance between the control gate 32 and the shallow trench isolation structure 36 along the third direction Z, increase the distance between the control gate 32 and the upper surface R2 of the substrate 30, and reduce the risk of short circuit due to electrical contact between the control gate 32 and the substrate 30.

[0170] The present application also provides a method for fabricating the memory array shown in FIG. 12 . FIG. 13A to FIG. 13L illustrate the steps of fabricating the memory array provided in the present application. The method is similar to the method for fabricating the memory array shown in FIG. 10 , with the difference being in steps FIG. 13G and FIG. 13H : A thin film deposition process is employed to form an insulating material layer 370 covering the recess C. Then, the insulating material layer 370 is etched to form an insulating layer 37 . A surface P4 of the insulating layer 37 , which is away from the reference plane R1 , is lower than the second surface P2 of the floating gate layer 310 , to prevent the insulating layer 37 from filling the recess C.

[0171] The method for preparing the storage array comprises the following steps:

[0172] 13A , a plurality of first trenches 40 are formed on a substrate 30 , and the plurality of first trenches 40 are arranged along a first direction X. The depth of the first trenches 40 is greater than the depth of the n-well 30 b , and the bottom of the first trenches 40 is located in the p-well 30 a .

[0173] Referring to Figure 13B, a dielectric material is deposited. The dielectric material may include silicon dioxide, for example, so that the dielectric material fills the plurality of first trenches 40 to form a shallow trench isolation structure 36 in the first trenches 40. The shallow trench isolation structure 36 includes a first surface P1 away from the reference plane R1. The first surface P1 of the shallow trench isolation structure 36 is flush with the upper surface R2 of the substrate 30, and the entire shallow trench isolation structure 36 is embedded in the substrate 30.

[0174] 13C , the substrate 30 is etched using a photolithography process to form a second trench 43. The depth of the second trench 43 is greater than that of the n-well 30b and less than that of the shallow trench isolation structure 36. The bottom of the second trench 43 is located in the p-well 30a.

[0175] 13C and 13D , a first gate dielectric layer 33 is formed on a substrate 30. A plurality of via holes h are defined in the first gate dielectric layer 33, and the via holes h expose the substrate 30. The first gate dielectric layer 33 covers the upper surface R2 of the substrate 30, the surface of the second trench 43, and the shallow trench isolation structure 36.

[0176] 13D and 13E , a floating gate material layer is formed using a thin film deposition process. The floating gate material may include, for example, polysilicon doped with P-type ions. The floating gate material layer fills the second trench 43 and covers the first gate dielectric layer 33. A chemical mechanical polishing process is then used to polish the upper surface of the floating gate material layer to make it flat. Finally, a photolithography process is used to etch the floating gate material layer, breaking it along the second direction Y and removing the portion of the floating gate material layer located above the shallow trench isolation structure 36 to form a floating gate layer 310. The floating gate layer 310 includes a second surface P2.

[0177] Since the first surface P1 of the shallow trench isolation structure 36 is lower than the second surface P2 of the floating gate layer 310 , a groove C can be formed between the top of the shallow trench isolation structure 36 and the floating gate layer 310 by removing the portion of the floating gate material layer located on the shallow trench isolation structure 36 .

[0178] 13F , a second gate dielectric layer 34 is formed by a thin film deposition process. The second gate dielectric layer 34 covers the upper surface and the portion of the sidewalls adjacent to the top surface of the floating gate layer 310 , and covers the first gate dielectric layer 33 .

[0179] 13G , a thin film deposition process is used to form an insulating material layer 370 covering the groove C. The material of the insulating material layer 370 is different from that of the second gate dielectric layer 34 .

[0180] Referring to Figure 13H, the material of the insulating material layer 370 is different from the material of the second gate dielectric layer 34, and the two have an etching selectivity. Based on this, the insulating material layer 370 can be selectively etched to form an insulating layer 37. The surface P4 of the insulating layer 37 away from the reference plane R1 is lower than the second surface P2 of the floating gate layer 310 to prevent the insulating layer 37 from filling the groove C.

[0181] Referring to FIG. 13I , a thin film deposition process is used to deposit a control gate material layer. The control gate material may include, for example, at least one of tungsten, aluminum, titanium nitride, or tantalum nitride. The control gate material layer fills the recess C and covers the second gate dielectric layer 34. A chemical mechanical polishing process is then used to polish the upper surface of the control gate material layer to make it flat. Finally, a photolithography process is used to etch the control gate material layer, breaking the control gate material layer along the second direction Y to form a control gate layer 320.

[0182] 13J , the control gate layer 320 , the second gate dielectric layer 34 , the floating gate layer 310 and the first gate dielectric layer 33 are etched to form a third trench 44 along the second direction Y to disconnect two adjacent rows of half-floating gate transistors T.

[0183] 13K , a spacer 35 is formed on the sidewalls of the third trench 44, with the bottom of the spacer 35 exposing the substrate 30. The spacer 35 can separate two adjacent rows of half-floating gate transistors T, thereby achieving insulation between the two adjacent rows of half-floating gate transistors T.

[0184] 13L , using the spacer layer 35 as a mask, an ion implantation process is employed to implant n-type ions into the n-well 30 b of the substrate 30 , and annealing is performed to form a source S and a drain D in the substrate 30 . Two adjacent rows of half-floating-gate transistors T share a common source S.

[0185] The above-mentioned fabrication method provided herein utilizes a thin film deposition process to form an insulating material layer 370 covering the recess C. The material of the insulating material layer 370 is different from that of the second gate dielectric layer 34, and the two have an etching selectivity. Based on this, the insulating material layer 370 can be selectively etched to form an insulating layer 37. A surface P4 of the insulating layer 37, which is away from the reference plane R1, is lower than the second surface P2 of the floating gate layer 310 to prevent the insulating layer 37 from filling the recess C. The insulating layer 37 can increase the distance between the control gate 32 and the shallow trench isolation structure 36 along the third direction Z, and increase the distance between the control gate 32 and the upper surface R2 of the substrate 30, thereby reducing the risk of electrical contact between the control gate 32 and the substrate 30 and causing a short circuit.

[0186] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention are intended to be covered by the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope of protection of the claims.

Claims

1. An integrated circuit, characterized in that: The integrated circuit comprises half-floating gate transistors arranged at intervals; the half-floating gate transistors comprise: A substrate, comprising a lower surface and an upper surface opposite to each other along a thickness direction thereof; A first gate dielectric layer is disposed on the upper surface of the substrate, and a via hole is formed in the first gate dielectric layer; A floating gate is disposed on the first gate dielectric layer, and the floating gate is electrically connected to the substrate through the via hole; A control gate, disposed on the floating gate; The floating gate includes an end portion away from the lower surface of the substrate, and on a cross-sectional plane of the semi-floating gate transistor, the end portion of the floating gate is embedded in the control gate.

2. The integrated circuit according to claim 1, characterized in that The integrated circuit further comprises a shallow trench isolation structure, which is arranged on the substrate, and the shallow trench isolation structure is located between the floating gates of two adjacent semi-floating gate transistors; Taking the lower surface of the substrate as a reference plane, the shallow trench isolation structure includes a first surface away from the reference plane, the floating gate includes a second surface away from the reference plane, and relative to the reference plane, the first surface is lower than the second surface; The shallow trench isolation structure and the two floating gates located on both sides form a groove, and a portion of the control gate is embedded in the groove.

3. The integrated circuit according to claim 2, characterized in that The portion of the control gate embedded in the groove includes a third surface close to the reference plane, and the third surface is in contact with the first surface.

4. The integrated circuit according to claim 2, characterized in that The integrated circuit further includes a second gate dielectric layer; The portion of the control gate embedded in the groove includes a third surface close to the reference plane. Relative to the reference plane, the third surface is lower than the second surface. Part of the second gate dielectric layer is located between the third surface and the first surface.

5. The integrated circuit according to claim 4, characterized in that A portion of the first gate dielectric layer is located between the second gate dielectric layer and the first surface.

6. The integrated circuit according to claim 4 or 5, characterized in that: The integrated circuit further includes an insulating layer, and the insulating layer is located between the third surface and the second gate dielectric layer.

7. The integrated circuit according to any one of claims 2 to 6, characterized in that: The first gate dielectric layer is located between the floating gate and the shallow trench isolation structure, and the first gate dielectric layer extends into the control gate; along the arrangement direction of the plurality of floating gates, the first gate dielectric layer is also located between the floating gate and the control gate; The integrated circuit further comprises a second gate dielectric layer, wherein the second gate dielectric layer is located on a side of the floating gate away from the reference plane, and the second gate dielectric layer is also located between the floating gate and the control gate.

8. The integrated circuit according to any one of claims 2 to 6, characterized in that: The integrated circuit further includes a second gate dielectric layer, and the second gate dielectric layer extends into the control gate; The second gate dielectric layer includes a first portion and a second portion, and along the arrangement direction of the plurality of floating gates, the first portion is located between the floating gate and the control gate; The second portion is located on a side of the floating gate away from the reference plane, and the second portion is also located between the floating gate and the control gate.

9. The integrated circuit according to claim 7 or 8, characterized in that: The dielectric constant of the material of the first gate dielectric layer is in the range of 4-100; the dielectric constant of the material of the second gate dielectric layer is in the range of 4-100.

10. The integrated circuit according to any one of claims 1 to 9, characterized in that: The material of the control gate includes at least one of tungsten, aluminum, titanium nitride or tantalum nitride.

11. A method for preparing an integrated circuit, characterized in that: The integrated circuit includes half-floating gate transistors arranged at intervals; The preparation method comprises: A first gate dielectric layer is formed on a substrate, wherein a via is provided on the first gate dielectric layer; the substrate comprises a lower surface and an upper surface opposite to each other along a thickness direction thereof, the first gate dielectric layer is located on the upper surface of the substrate, and the via exposes the upper surface of the substrate; forming a floating gate on the first gate dielectric layer, wherein the floating gate is electrically connected to the substrate through the via hole; forming a control gate on the floating gate; The floating gate includes an end portion away from the lower surface of the substrate, and on a cross-sectional plane of the semi-floating gate transistor, the end portion of the floating gate is embedded in the control gate.

12. The preparation method according to claim 11, characterized in that: Before forming the first gate dielectric layer, the preparation method further includes: A shallow trench isolation structure is formed on the substrate, wherein a portion of the shallow trench isolation structure is located in the substrate; taking the lower surface of the substrate as a reference surface, the shallow trench isolation structure includes a first surface away from the reference surface, and relative to the reference surface, the first surface is higher than the upper surface of the substrate; The floating gate includes a second surface away from the reference plane, and after the floating gates are formed and arranged at intervals, the shallow trench isolation structure is located between two adjacent floating gates, and the preparation method further includes: Etching the shallow trench isolation structure so that the first surface is lower than the second surface and higher than the upper surface of the substrate relative to the reference surface; Forming the control gate includes: The control gate is formed on the first surface of the shallow trench isolation structure and the second surface of the floating gate.

13. The preparation method according to claim 11, characterized in that: Before forming the first gate dielectric layer, the preparation method further includes: A shallow trench isolation structure is formed on the substrate, wherein the shallow trench isolation structure is located in the substrate; taking the lower surface of the substrate as a reference surface, the shallow trench isolation structure includes a first surface away from the reference surface, and the first surface is flush with the upper surface of the substrate; Forming the floating gate includes: forming a floating gate layer, wherein the floating gate layer is located on the substrate and the shallow trench isolation structure; Removing a portion of the floating gate layer located on the shallow trench isolation structure to obtain the floating gates arranged at intervals, wherein the floating gates include a second surface away from the reference plane; the shallow trench isolation structure is located between two adjacent floating gates, and relative to the reference plane, the first surface is lower than the second surface; Forming the control gate includes: The control gate is formed on the first surface of the shallow trench isolation structure and the second surface of the floating gate.

14. A memory, characterized in that: include: An integrated circuit as claimed in any one of claims 1 to 10; A controller, wherein the integrated circuit is electrically connected to the controller.

15. An electronic device, characterized in that: include: The memory as claimed in claim 14; A circuit board, wherein the memory is electrically connected to the circuit board.

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