Hybrid analog-to-digital conversion circuit, analog-to-digital conversion method, and chip

Abstract

The present application provides a hybrid analog-to-digital conversion circuit, an analog-to-digital conversion method, and a chip. The hybrid analog-to-digital conversion circuit comprises: an integration module, used to sample and integrate an analog input signal, to obtain a first output; a first quantization module, used to perform N-bit quantization processing on the first output of the integration module in a first period, to obtain a first quantized output; a second quantization module, used to perform M-bit quantization processing on the first output of the integration module, to obtain a second quantized output; and a filter output module, used to output a target conversion result on the basis of the first quantized output, or used to output a target conversion result on the basis of the first quantized output and the second quantized output. Using the present application, an analog input signal can be quantized in parallel by means of two quantization modules, so that a quantization mode can be flexibly selected on the basis of the actual situation of an analog input, so as to meet various application requirements.

Description

A hybrid analog-to-digital conversion circuit, analog-to-digital conversion method, and chip

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on September 22, 2023, with application number 202311240399.6 and invention name “A hybrid analog-to-digital conversion circuit, analog-to-digital conversion method, and chip”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of electronic technology, and in particular to a hybrid analog-to-digital conversion circuit, an analog-to-digital conversion method, and a chip. Background Art

[0003] In the field of electronics, a Σ-Δ analog-to-digital converter (Σ-Δ ADC) typically consists of an integration module, a quantization module, and a filter output module. The Σ-Δ ADC works as follows: the integration module samples and integrates the analog input signal multiple times to obtain a first output. The quantization module quantizes the first output of the integration module to obtain a quantized signal. Finally, the filter output module filters the quantized signal and outputs the conversion result of the input signal.

[0004] Since the Σ-Δ analog-to-digital conversion circuit is based on quantized signal averaging to obtain the conversion result, in order to obtain a high-precision conversion result, 2 N For some application scenarios that require fast conversion results, this analog-to-digital conversion circuit that requires a long quantization cycle cannot adaptably and quickly output the target conversion result corresponding to the analog input signal. Technical issues

[0005] The embodiments of the present application provide a hybrid analog-to-digital conversion circuit, an analog-to-digital conversion method, a chip, and an electronic device to improve the conversion efficiency of the analog-to-digital conversion circuit while ensuring the accuracy of the analog-to-digital conversion. Technical Solutions

[0006] The technical solution of this application is as follows:

[0007] In a first aspect, the present application provides a hybrid analog-to-digital conversion circuit, comprising:

[0008] an integration module, configured to sample and integrate the analog input signal to obtain a first output;

[0009] a first quantization module, configured to perform N-bit quantization processing on the first output of the integration module in a first cycle to obtain a first quantized output;

[0010] a second quantization module, configured to perform M-bit quantization processing on the first output of the integration module to obtain a second quantized output;

[0011] The filtering output module is used to output a target conversion result according to the first quantization output, or to output a target conversion result according to the first quantization output and the second quantization output.

[0012] In a second aspect, the present application provides an analog-to-digital conversion method, wherein the method is applied to a hybrid analog-to-digital conversion circuit, the hybrid analog-to-digital conversion circuit including an integration module, a first quantization module, a second quantization module, and a filtering output module, the method comprising:

[0013] Using the integration module to sample and integrate the analog input signal to obtain a first output;

[0014] Using the first quantization module, performing N-bit quantization processing on the first output of the integration module in a first cycle to obtain a first quantized output;

[0015] Using the second quantization module, perform M-bit quantization processing on the first output of the integration module to obtain a second quantized output;

[0016] The target conversion result is outputted according to the first quantized output by using the filter output module, or the target conversion result is outputted according to the first quantized output and the second quantized output by using the filter output module.

[0017] In a third aspect, the present application provides a chip, which includes the hybrid analog-to-digital conversion circuit described in the first aspect.

[0018] In a fourth aspect, the present application provides an electronic device, comprising a device body and a chip as described in the third aspect above, which is provided in the device body. Beneficial effects

[0019] The present application provides a hybrid analog-to-digital conversion circuit, an analog-to-digital conversion method, a chip, and an electronic device, wherein two quantization modules are provided in the hybrid analog-to-digital conversion circuit, namely a first quantization module and a second quantization module. The first quantization module performs N-bit quantization processing on the first output of the integration module in a first cycle to obtain a first quantized output, and the second quantization module performs M-bit quantization processing on the first output of the integration module to obtain a second quantized output. Then, a filtering output module outputs a target conversion result based on the first quantized output, or outputs a target conversion result based on the first quantized output and the second quantized output.

[0020] By selecting an embodiment of the present application, two quantization modules are built into the hybrid analog-to-digital conversion circuit to perform quantization processing on the input analog input signal with different bit numbers, that is, the two quantization modules can quantize the analog input signal in parallel, so the quantization mode can be flexibly selected according to the actual situation of the analog input to meet various application requirements.

[0021] These and other aspects of the present application will become more readily apparent from the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0023] FIG1 shows a schematic diagram of a logic structure of a hybrid analog-to-digital conversion circuit provided in an embodiment of the present application;

[0024] FIG2 shows another logical structure diagram of a hybrid analog-to-digital conversion circuit provided in an embodiment of the present application;

[0025] FIG3 shows a digital circuit diagram of a hybrid analog-to-digital conversion circuit provided in an embodiment of the present application;

[0026] FIG4 shows another structural diagram of a hybrid analog-to-digital conversion circuit provided in an embodiment of the present application;

[0027] FIG5 is a schematic diagram showing a working cycle of a first quantization module and a working cycle of a second quantization module provided in an embodiment of the present application;

[0028] FIG6 shows a timing diagram of two M-bit quantization processes in the second cycle provided by an embodiment of the present application;

[0029] FIG7 shows another timing diagram of two M-bit quantization processes in the second cycle provided by an embodiment of the present application;

[0030] FIG8 is a schematic diagram showing the working timing of the first quantization module and the second quantization module in the second cycle provided by an embodiment of the present application;

[0031] FIG9 shows a timing diagram of two operating modes of the hybrid analog-to-digital conversion circuit provided in an embodiment of the present application;

[0032] FIG10 shows a special timing diagram of the second cycle of the hybrid analog-to-digital conversion circuit provided in an embodiment of the present application;

[0033] FIG11 shows a schematic diagram of a working timing of the second quantization module provided in an embodiment of the present application;

[0034] FIG12 shows a schematic diagram of a control signal output by a detection control module according to an embodiment of the present application;

[0035] FIG13 shows a flow chart of an analog-to-digital conversion method provided in an embodiment of the present application.

[0036] Implementation Methods of the Application

[0037] The embodiments of the present application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0038] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0039] In the embodiments of the present application, it should be noted that, in this document, relational terms such as first and second, etc., are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0040] Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0041] In the description of the embodiments of this application, words such as "example" or "for example" are used to indicate an example, illustration, or description. Any embodiment or design described as "for example" or "for example" in the embodiments of this application is not to be construed as being preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to clearly present relative concepts.

[0042] In addition, in the embodiments of the present application, "plurality" refers to two or more. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two, or more. For example, "including at least one" means including one, two, or more, and does not limit which ones are included. For example, "including at least one of A, B, and C" means including A, B, C, A and B, A and C, B and C, or A, B, and C.

[0043] It should be noted that in the embodiments of the present application, "and / or" describes the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects are in an "or" relationship.

[0044] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0045] Conventional incremental Σ-Δ ADCs reset the integrator and filter after each quantization cycle to eliminate the information about the previous quantization state, ensuring that the initial state for each quantization cycle is identical. This allows them to offer the advantages of high gain and high linearity, resulting in precise, high-precision ADCs.

[0046] However, at the end of quantization, an incremental Σ-Δ ADC inevitably generates residual charge within the circuit. This residual charge is part of the analog input signal. Each reset erases this residual charge, resulting in lower quantization accuracy. In the prior art, increasing the quantization cycle of the ADC circuit is often used to improve the quantization accuracy of incremental Σ-Δ ADCs.

[0047] However, for some application scenarios that require fast conversion results, traditional analog-to-digital conversion circuits cannot adaptively output the target conversion results corresponding to the analog input signals quickly and accurately.

[0048] As an example, in one possible use case, it is necessary to perform analog-to-digital conversion on the sudden change portion of the analog input signal to obtain the magnitude of the sudden change. For example, in an analog-to-digital conversion circuit used for battery power monitoring, it is necessary to monitor the sudden voltage change during the charging and discharging process to prevent overvoltage from damaging the battery life. In this scenario, it is necessary to quickly obtain the conversion result of the sudden voltage change and then perform overvoltage protection based on the conversion result.

[0049] However, the existing Σ-Δ analog-to-digital conversion circuit uses a quantizer with fewer bits to convert the first output of the integration module into a digital signal with fewer bits at each sampling clock within a quantization period of N sampling clocks. As an example, a single-bit quantizer is used to convert the first output into a 1-bit digital signal.

[0050] In this case, to ensure conversion accuracy, the value of N is typically set relatively high. Consequently, obtaining the conversion result of the analog input signal requires waiting for N sampling clocks to complete before outputting the corresponding conversion result. This means that the analog-to-digital conversion circuit has a relatively long operating cycle. In scenarios where rapid conversion results are required, conventional Σ-Δ analog-to-digital conversion circuits are unable to quickly obtain the conversion result for the abruptly changing input signal, impacting the practical application of the analog-to-digital conversion circuit.

[0051] In view of this, in a first aspect, the present application provides a hybrid analog-to-digital conversion circuit, as shown in FIG1 . The hybrid analog-to-digital conversion circuit provided by the present application includes the following parts:

[0052] The integration module 10 is configured to sample and integrate the analog input signal to obtain a first output.

[0053] The first quantization module 11 is configured to perform N-bit quantization processing on the first output of the integration module in a first cycle to obtain a first quantized output.

[0054] The second quantization module 12 is configured to perform M-bit quantization processing on the first output of the integration module to obtain a second quantized output.

[0055] The filtering output module 13 is configured to output a target conversion result according to the first quantization output and / or the second quantization output.

[0056] In the embodiment of the present application, the two quantization modules built into the hybrid analog-to-digital conversion circuit perform quantization processing on the input analog input signal with different bit counts. That is, the two quantization modules can quantize the analog input signal in parallel. Therefore, the quantization mode can be flexibly selected based on the actual situation of the analog input to meet various application requirements.

[0057] The following is a detailed description of the above-mentioned integration module, quantization module and filter output module:

[0058] As an implementation method, the integration module modulates the analog input signal into a PDM (Pulse Density Modulation) code, which is essentially a pulse sequence. That is, in this application, after the integration module samples and integrates the analog input signal, the first output obtained is essentially a pulse sequence.

[0059] In the present application, the integration module is connected to the quantization module, and the quantization module performs quantization processing on the discrete digital bit stream of the first output. Wherein, the number of quantization modules connected to the integration module of the present application is not 1. That is, the first quantization module and the second quantization module in the present application are both connected to the output end of the same integration module, but the number of bits (N bits) of the data supported by the first quantization module for quantization processing is different from the number of bits (M bits) of the data supported by the second quantization module for quantization processing. Wherein, as an example, the number of bits of the data supported by the first quantization module for quantization processing may be less than the number of bits of the data supported by the second quantization module for quantization processing.

[0060] In an embodiment of the present application, the quantization module divides the first output signal into a number of discrete quantization intervals, maps the sampling values ​​of the analog input signal into the corresponding quantization intervals, and then converts them into binary code outputs, thereby generating a digital sequence to represent the approximate value of the analog input signal.

[0061] In the present application, the filtering output module may specifically include a digital filter. The filtering output module specifically sends the digital sequence output by the quantization module into the digital filter, and the digital filter filters out the noise and aliasing interference in the signal, retains the effective signal, and obtains the target conversion result, and outputs the target conversion result.

[0062] In some embodiments, as shown in FIG2 , the filter output module 13 may include a first filter output module 131 and a second filter output module 132. As an implementation, as shown in FIG2 , the first filter output module 131 is configured to output a target conversion result based on the first quantized output. The second filter output module 132 is configured to output a target conversion result based on the first quantized output and the second quantized output.

[0063] As an implementation method, the first filtering output module is a digital filtering module in a Σ-Δ analog-to-digital conversion circuit. The filtering processing performed on the received first quantized output can be regarded as directly calculating a weighted average value of the quantized digital signal, and outputting the weighted average value as the target conversion result.

[0064] In some embodiments, the second filter output module may be a digital filter module in a non-Σ-Δ analog-to-digital conversion circuit, such as a digital filter module in a SAR-ADC (a successive approximation register ADC) analog-to-digital conversion circuit.

[0065] The second filter output module, for the first quantized output, continues to use the digital filter module in the Σ-Δ analog-to-digital conversion circuit to calculate a weighted average value to obtain a first sub-conversion result. The second filter output module, for the second quantized output, continues to use the digital filter module in the SAR-ADC analog-to-digital conversion circuit to calculate a weighted average value to obtain a second sub-conversion result. The second filter output module then performs a correlation operation on the first sub-conversion result and the second sub-conversion result to obtain a target conversion result.

[0066] As an example, the second filter output module adds the first sub-conversion result and the second sub-conversion result to obtain the target conversion result. As shown in Figure 3, Vin is an analog input signal, the integration module is used to convert the analog input into a first output V1 based on the sampling frequency Fs, and the first quantization module and the second quantization module respectively quantize the first output V1 to obtain a first quantized output and a second quantized output. The first filter output module converts the first quantized output into the target conversion result Dout1. Depending on the needs of the scenario, part of the first quantized output can be added to the second quantized output, and the second quantized output module outputs the target conversion result Dout2.

[0067] In some embodiments, as shown in FIG4 , the hybrid analog-to-digital conversion circuit provided in the present application further includes: a detection control module 14, wherein the detection control module is configured to control the activation of the second quantization module based on the analog input signal. As an embodiment, the detection control module 14 is specifically configured to detect the analog input signal and then control the activation of the second quantization module based on the detection result. As an example, the detection control module 14 is specifically configured to detect the amplitude of the analog input signal and, if it is detected that the amplitude of the analog input signal is greater than a preset amplitude threshold, control the activation of the second quantization module.

[0068] In some embodiments, the duty cycle of the first quantization module is determined as a first cycle, and the duty cycle of the second quantization module is determined as a second cycle. As an embodiment, the first cycle includes at least one second cycle. As shown in FIG5 , the first cycle includes two second cycles, or may include more second cycles. There is a clock interval between each second cycle in the first cycle.

[0069] In some embodiments, the second quantization module is used to perform at least two M-bit quantization processes on the first output of the integration module within the second cycle to obtain at least two quantized outputs. As an embodiment, as shown in Figure 6, there is a preset clock interval between the first M-bit quantization process and the second M-bit quantization process, that is, the first M-bit quantization process and the second M-bit quantization process are discontinuous. The preset clock interval can be pre-set, and the specific number of interval clocks can be flexibly set based on actual experience or actual product requirements and is not strictly limited here. During this period, the first quantization module also operates in parallel.

[0070] As another implementation, as shown in FIG. 7 , there is no preset clock interval between the first M-bit quantization process and the second M-bit quantization process, that is, the first M-bit quantization process and the second M-bit quantization process are continuous.

[0071] In some embodiments, the first quantization module is configured to perform a first N-bit quantization process on the first output of the integration module for i clocks at the beginning of the second cycle to obtain a third quantized output. The second quantization module is configured to perform a first M-bit quantization process on the first output for j clocks at the beginning of the second cycle to obtain a fourth quantized output, and at the end of the i-th clock, perform a second M-bit quantization process on the first output for j clocks to obtain a fifth quantized output. Where i ≥ j, multiple first M-bit quantization processes and multiple second M-bit quantization processes may occur within the second cycle.

[0072] The second filtering output module is used to output a target conversion result according to the third quantization output, the fourth quantization output, and the fifth quantization output.

[0073] As an implementation, the timing relationship between the quantization processing of the first quantization module and the second quantization module within the second cycle can be shown as a timing diagram in FIG8 . Because the first quantization module itself operates in parallel, the first N-bit quantization processing performed by the first quantization module for i clocks at the beginning of the second cycle (assuming the clock sequence number at the beginning of the second cycle is 1) can be extracted to obtain the third output. Because the length of the second cycle can be flexibly set, in the case of a very long cycle length, the number of N-bit quantization processing times of the first quantization module can be different from 1.

[0074] Similarly, the second quantization module performs the first M-bit quantization process for j clocks at the beginning of the second cycle (assuming the starting clock number is 1) to obtain the fourth quantized output. Then, the second M-bit quantization process is started at the end of the i-th clock to obtain the fifth quantized output.

[0075] Since the second cycle length, M, and N values ​​can be flexibly set, multiple M-bit quantization processes can occur within a second cycle, but the number of M-bit quantization processes must be an even number, that is, multiple fourth quantization outputs and multiple fifth quantization outputs can occur within a second cycle. In this article, the "two j-clock M-bit quantization processes + one i-clock N-bit quantization process" shown in Figures 8 and 9 is collectively referred to as a three-stage quantization processing mode, which can also be called a burst enable mode.

[0076] Similarly, since the second cycle length, M, and N values ​​can be flexibly set, as one embodiment, when outputting the target conversion result, the second filter output module can output a target conversion result based on all third quantized outputs, fourth quantized outputs, and fifth quantized outputs within the second cycle. As another embodiment, after a three-stage quantization mode ends, the second filter output module can output a target conversion result based on one third quantized output, one fourth quantized output, and one fifth quantized output in the three-stage mode.

[0077] In one embodiment, the second cycle includes multiple three-stage quantization processing modes, and the end time of the second M-bit quantization processing in the last three-stage quantization processing mode is later than the end time of the second cycle, then only the third quantization output, the fourth quantization output and the fifth quantization output in the complete three-stage quantization processing under the previous complete three-stage quantization processing mode are used to calculate the target output result, and the quantization output of the last three-stage quantization processing mode is directly discarded and is not included in the calculation process of the target conversion result.

[0078] As an example, as shown in Figure 10: the first cycle includes multiple second cycles. Assuming that the second cycle only includes one three-stage quantization processing mode, when the last M-bit quantization processing in the last second cycle is later than the end time of the second cycle, the third quantization output, fourth quantization output and fifth quantization output of the three-stage quantization processing in which the last M-bit quantization processing is located are all discarded and are not included in the calculation of the final target conversion result.

[0079] In this embodiment of the present application, a hybrid ADC structure is used to combine residual charge quantization with Σ-Δ ADC quantization. By reusing the second quantization module, the residual charge quantizer, the overall ADC accuracy can be improved energy-efficiently, and both normal and burst modes are supported. In normal mode, quantization results can be output with high precision, while in burst mode, multiple quantization results can be output quickly. The two modes operate in parallel, flexibly meeting the needs of different application scenarios.

[0080] In some embodiments, as shown in the timing diagram of FIG11 , the second quantization module is used to perform an M-bit quantization process on the first output at the end of the first cycle to obtain a sixth quantized output. The second filter output module is used to output a target conversion result based on the first quantized output and the sixth quantized output. When using an embodiment of the present application, after the first quantization module normally performs N-bit quantization processing, the second quantization module can perform an M-bit quantization process on the residual charge in the circuit. On the basis of the original quantization processing of the first quantization module, the quantization processing of the residual charge amount can be added, thereby improving the output accuracy of the entire circuit.

[0081] In some embodiments, the start or end of the second cycle is determined by the detection control module 14. Specifically, as an embodiment, the detection control module is configured to start the second cycle upon receiving the first control signal and end the second cycle after a preset number of clock cycles.

[0082] As an example, when the detection control module receives the first control signal, it triggers the enable signal. The rising edge of the enable signal triggers the start of the second cycle. When a preset number of clock cycles arrives, the falling edge of the enable signal triggers the end of the second cycle.

[0083] In another embodiment, the detection control module is configured to start the second cycle upon receipt of the first control signal and to end the second cycle upon receipt of the second control signal. In one embodiment, the first control signal and the second control signal may be user-triggered or automatically triggered based on a preset event. Thus, the detection control module starts the second cycle upon receipt of the first control signal and ends the second cycle upon receipt of the second control signal.

[0084] In some embodiments, both the first control signal and the second control signal are control signals output by the detection and control module based on the analog input signal. In one embodiment, the detection and control module outputs the first control signal based on a change in a first amplitude of the analog input signal. In another embodiment, the detection and control module is further configured to output the second control signal based on a change in a second amplitude of the analog input signal.

[0085] As an example, as shown in FIG12 , if the detection and control module detects that the analog input signal amplitude change is greater than a first preset amplitude change threshold, the detection and control module outputs a first control signal. Alternatively, if the detection and control module detects that the analog input signal amplitude change ratio is greater than a first preset ratio, the detection and control module outputs a first control signal.

[0086] Alternatively, as shown in Figure 12, if the detection control module detects that the amplitude change is a sudden change from a normal amplitude to an abnormally high potential amplitude, it outputs a first control signal; when the detection control module detects that the amplitude change is a sudden change from an abnormally first high potential amplitude to an abnormally second high potential amplitude, it outputs a second control signal.

[0087] In this embodiment of the present application, the detection control module built into the analog-to-digital conversion circuit detects the analog input signal and triggers the start of the second cycle based on the detection result. Therefore, when the target conversion result needs to be output quickly, the burst enable mode is triggered, and the second quantization module cooperates with the first quantization module to quickly and accurately output the target conversion result.

[0088] In some embodiments, the analog-to-digital conversion circuit provided in the present application can be a hybrid structure Σ-Δ ADC analog-to-digital conversion circuit, which can be understood as adding a second quantization module on the basis of the quantization module of the traditional Σ-Δ ADC analog-to-digital conversion circuit, and the second quantization module performs multi-bit quantization processing on the first output of the integration module.

[0089] As an embodiment, at the end of the first cycle, the detection control module can trigger a reset signal to control the reset of the integration module, the first quantization module, the second quantization module, and the filter output module, so that the initial state of the quantization of each first cycle is the same. At the end of the second cycle, because the length of the second cycle is less than the cycle length of the first cycle, that is, the burst enable mode quantization processing efficiency is faster, there is no need to control the reset of the integration module, the first quantization module, the second quantization module, and the filter output module at the end of the second cycle. This can effectively reduce the impact of frequent resets on the stability of the analog-to-digital conversion circuit, thereby improving the conversion efficiency and conversion accuracy of the entire analog-to-digital conversion circuit.

[0090] The following text uses a specific calculation formula, combined with the logic circuit diagram shown in Figure 3, to provide proof that the accuracy of the entire analog-to-digital conversion circuit is improved: In the figure, Fs is the sampling frequency of the integration module, V1 is the first output, D is the first quantized output, Dout1 is the target conversion result obtained by converting the first quantized output, and Dout2 is the second conversion result obtained by converting the first quantized output and the second quantized output.

[0091] The process of the first quantization module performing single-bit quantization processing on the first output in the normal first cycle can be understood as follows:

[0092] Before the start of the first cycle, each module in the analog-to-digital conversion circuit is reset. At this time:

[0093] V1[0]=0

[0094] First conversion cycle:

[0095] V1[1]=(V1[0]+a1*Vin[0]-b1*Vref*D[0])=(a1*Vin[0]-b1*Vref*D[0])···Formula (1)

[0096] Second conversion cycle:

[0097] V1[2]=(V1[1]+a1*Vin[1]-b1*Vref*D[1])=[a1*(Vin[1]+Vin[0])-b1*Vref*(D[1]+D[0])]···Formula (2)

[0098] By converting the formula, we can get the nth conversion cycle:

[0099] Where a1 is the input gain coefficient, b1 is the feedback coefficient, Vref is the reference voltage, D[n] is the first quantized output, Vin is the analog input signal, and V1[n] is the first output.

[0100] By transforming formula (3), we can get:

[0101] At this time, the quantization error is:

[0102] At this point, if the second quantization module is continued to be used to quantize the first output, then:

[0103] V1[n]=D_END+Eq2 ···Formula (6)

[0104] Where D_END is the codeword after quantization of the first output V1[n], Eq2 is the current quantization error of the second quantization module, and the simulated input signal is further:

[0105] The current quantization error Eq2 of the second quantization module is:

[0106] Wherein, M is the number of quantization processing bits of the second quantization module.

[0107] At this time, the overall quantization error of the system is Eq1_new = Eq*Eq2, that is:

[0108] If after controlling the second quantization module to perform quantization processing, each module in the circuit is not reset, the first output V1[0]≠0, then:

[0109] The nth conversion cycle:

[0110] Since V1[n] is the random value of the first output sampled by the integration module, then:

[0111] (V1[n]-V1[0])_max=2V1[n]_max ···Formula (12)

[0112] The corresponding quantization error is:

[0113] Since the second quantization module performs M-bit quantization on the first output at the beginning and end of the second cycle, that is, quantizes V1[0] and V1[n] respectively, the quantization error of the first quantization module is:

[0114] The quantization error of the second quantization module is:

[0115] The quantization error of the entire analog-to-digital conversion circuit is:

[0116] Wherein, D_END is the codeword for quantizing V1[n], Eq2 is the error of the first quantization of the second quantization module; D_INI is the codeword for quantizing V1[0], Eq3 is the error of the second quantization of the second quantization module, and X is the gain error of the second quantization module.

[0117] It can be seen that when the second quantization module does not reset after quantization output, the quantization accuracy of the entire circuit is improved by M bits. Therefore, the second quantization module can be used to flexibly perform efficient and fast quantization processing on the analog input signal.

[0118] In one possible embodiment, the process in which the first quantization module normally performs N-bit quantization processing on the first output and outputs it during the first cycle is referred to as normal mode. The process in which the first quantization module cooperates with the second quantization module to perform N-bit quantization processing on the first output during the second cycle, and cooperates with the second quantization module to perform M-bit quantization processing on the first output, is referred to as burst mode. By selecting an embodiment of the present application, parallel conversion between burst mode and normal mode can be achieved, and the corresponding output results can be achieved by adding different filters, thereby expanding the application scope and application flexibility of the analog-to-digital converter.

[0119] In a second aspect, the present application provides an analog-to-digital conversion method, wherein the analog-to-digital conversion method is applied to the above-mentioned hybrid analog-to-digital conversion circuit, as shown in FIG13 , and the method includes the following steps:

[0120] S11 . Utilize an integration module to sample and integrate the analog input signal to obtain a first output.

[0121] S12. Using a first quantization module, perform N-bit quantization processing on the first output of the integration module within a first period to obtain a first quantized output.

[0122] S13. Use the second quantization module to perform M-bit quantization processing on the first output of the integration module to obtain a second quantized output.

[0123] S14. Utilize the filtering output module to output the target conversion result according to the first quantized output, or utilize the filtering output module to output the target conversion result according to the first quantized output and the second quantized output.

[0124] In some embodiments, the filter output module includes a first filter output module and a second filter output module; the method further includes:

[0125] Outputting a target conversion result using a first filtering output module according to the first quantization output;

[0126] The output module outputs the target conversion result according to the first quantization output and the second quantization output by using the second filtering.

[0127] In some embodiments, the first period includes at least one second period; and the method further comprises:

[0128] In a second cycle, the first output of the integration module is subjected to at least two M-bit quantization processes by using a second quantization module to obtain at least two second outputs;

[0129] The target conversion result is outputted by utilizing the second filtering output module according to the first quantized output of the second period and the at least two second quantized outputs of the second period.

[0130] In some embodiments, the method further comprises:

[0131] At the beginning of the second cycle, the first output is subjected to a first N-bit quantization process for i clocks by the first quantization module to obtain a third quantized output; the first output is subjected to a first M-bit quantization process for j clocks by the second quantization module to obtain a fourth quantized output;

[0132] At the end of i clock cycles, the second quantization module performs a second M-bit quantization process on the first output to obtain a fifth quantized output; wherein i ≥ j, there are multiple first M-bit quantization processes and multiple second M-bit quantization processes in the second cycle;

[0133] The second filtering output module is used to output a target conversion result according to the third quantization output, the fourth quantization output, and the fifth quantization output.

[0134] In some embodiments, the method further comprises:

[0135] At the end of the first cycle, the first output is quantized once with M bits using the second quantization module to obtain a sixth quantized output;

[0136] The target conversion result is outputted by the second filtering output module according to the first quantization output and the sixth quantization output.

[0137] In some embodiments, the circuit further includes a detection control module, and the method further includes:

[0138] The detection control module is used to control the start-up of the second quantization module according to the analog input signal.

[0139] The analog-to-digital conversion method provided in this application is applied to the above-mentioned hybrid analog-to-digital conversion circuit, and therefore has the same principle as the above-mentioned hybrid analog-to-digital conversion circuit, which will not be elaborated here.

[0140] The present application also provides a chip including the aforementioned analog-to-digital conversion circuit. An integrated circuit (IC) is also referred to as a chip, and the chip may be, but is not limited to, a SOC (System on Chip) chip or a SIP (System in Package) chip. The chip, through the analog-to-digital conversion circuit provided by the present application, can solve the technical problems of slow conversion efficiency and poor conversion accuracy in the application of existing analog-to-digital conversion circuits in practical applications.

[0141] The embodiment of the present application also provides an electronic device, which includes a device body and a chip as described above provided in the device body. The electronic device can be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central control panel, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smart phones, laptops, tablet computers, and POS (point of sales terminals). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights. This electronic device can solve the technical problems of low analog-to-digital conversion efficiency and poor analog-to-digital conversion accuracy through an analog-to-digital conversion circuit.

[0142] The above is only a preferred embodiment of the present application and does not constitute any form of limitation to the present application. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A hybrid analog-to-digital conversion circuit, characterized in that: The hybrid analog-to-digital conversion circuit comprises: An integration module, used for sampling and integrating the analog input signal to obtain a first output; A first quantization module, used for performing N-bit quantization processing on the first output of the integration module in a first cycle to obtain a first quantized output; A second quantization module, used for performing M-bit quantization processing on the first output of the integration module to obtain a second quantized output; A filtering output module is used to output a target conversion result according to the first quantization output, or to output a target conversion result according to the first quantization output and the second quantization output.

2. The hybrid analog-to-digital conversion circuit according to claim 1, characterized in that: The filter output module includes a first filter output module and a second filter output module; The first filtering output module is used to output a target conversion result according to the first quantization output; The second filtering output module is used to output a target conversion result according to the first quantization output and the second quantization output.

3. The hybrid analog-to-digital conversion circuit according to claim 2, characterized in that: The first cycle includes at least one second cycle; The second quantization module is used to perform M-bit quantization processing on the first output of the integration module at least twice in the second period to obtain at least two second quantization outputs; The second filtering output module is used to output a target conversion result according to the first quantized output of the second period and at least two second quantized outputs of the second period.

4. The hybrid analog-to-digital conversion circuit according to claim 3, characterized in that: The first quantization module is used to perform a first N-bit quantization process on the first output for i clocks at the beginning of the second cycle to obtain a third quantized output; The second quantization module is used to perform a first M-bit quantization process on the first output for j clocks at the beginning of the second cycle to obtain a fourth quantized output, and to perform a second M-bit quantization process on the first output for j clocks at the end of the i clocks to obtain a fifth quantized output, wherein i ≥j, there are multiple first M-bit quantization processes and multiple second M-bit quantization processes in the second cycle; The second filtering output module is used to output a target conversion result according to the third quantization output, the fourth quantization output and the fifth quantization output.

5. The hybrid analog-to-digital conversion circuit according to claim 2, characterized in that: The second quantization module is used to perform an M-bit quantization process on the first output at the end of the first cycle to obtain a sixth quantized output; The second filtering output module is used to output a target conversion result according to the first quantization output and the sixth quantization output.

6. The hybrid analog-to-digital conversion circuit according to claim 1, characterized in that: The circuit further comprises a detection control module, and the detection module is used to control the start-up of the second quantization module according to the analog input signal.

7. An analog-to-digital conversion method, characterized in that: The method is applied to a hybrid analog-to-digital conversion circuit, which includes an integration module, a first quantization module, a second quantization module, and a filtering output module. The method includes: Using the integration module to sample and integrate the analog input signal to obtain a first output; Using the first quantization module, performing N-bit quantization processing on the first output of the integration module in a first cycle to obtain a first quantized output; Using the second quantization module, performing M-bit quantization processing on the first output of the integration module to obtain a second quantized output; The target conversion result is outputted by the filtering output module according to the first quantized output, or the target conversion result is outputted by the filtering output module according to the first quantized output and the second quantized output.

8. The analog-to-digital conversion method according to claim 7, wherein: The filter output module includes a first filter output module and a second filter output module; the method further includes: Outputting a target conversion result using the first filtering output module according to the first quantization output; Utilize the second filtering output module according to the first quantized output and the second quantized output, The output module outputs the target conversion result.

9. The analog-to-digital conversion method according to claim 8, characterized in that: The first cycle includes at least one second cycle; the method further includes: In the second cycle, using the second quantization module to perform at least two M-bit quantization processes on the first output of the integration module to obtain at least two second outputs; The target conversion result is outputted by utilizing the second filtering output module according to the first quantized output of the second period and the at least two second quantized outputs of the second period.

10. The analog-to-digital conversion method according to claim 9, wherein: The method further comprises: At the beginning of the second cycle, the first output is subjected to a first N-bit quantization process for i clocks by using the first quantization module to obtain a third quantized output; the first output is subjected to a first M-bit quantization process for j clocks by using the second quantization module to obtain a fourth quantized output; At the end of the i clocks, using the second quantization module to perform a second M-bit quantization process on the first output to obtain a fifth quantized output; wherein i≥j, there are multiple first M-bit quantization processes and multiple second M-bit quantization processes in the second cycle; The target conversion result is outputted by utilizing the second filtering output module according to the third quantization output, the fourth quantization output and the fifth quantization output.

11. The analog-to-digital conversion method according to claim 8, wherein: The method further comprises: At the end of the first cycle, using the second quantization module to perform an M-bit quantization process on the first output to obtain a sixth quantized output; The second filtering output module is used to output a target conversion result according to the first quantized output and the sixth quantized output.

12. The analog-to-digital conversion method according to claim 7, wherein: The circuit further includes a detection control module, and the method further includes: The detection control module is used to control the start-up of the second quantization module according to the analog input signal.

13. A chip, characterized in that: The chip includes the hybrid analog-to-digital conversion circuit described in claims 1 to 6 above.

14. An electronic device, characterized in that: The electronic device comprises a device body and a chip as claimed in claim 13 arranged in the device body.

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