Semiconductor device manufacturing method and semiconductor device

Abstract

Provided is a semiconductor device manufacturing method by which it is possible to reduce the width of a termination region and achieve electrical field relaxation in the termination region.　The semiconductor device manufacturing method has, in the periphery of an active region, a termination region in which a plurality of second semiconductor regions with a second conductivity type functioning as RESURF regions are formed on a surface of a first semiconductor region with a first electroconductive type. When defining a distance from a reference window at the outermost periphery as x, the method uses a mask, as for forming the second semiconductor region, in which an interval S(x) between an injection window at the position of a distance x and an injection window thereof on the active region side is substantially equal to the value determined by S(x)=Smax–(Smax–Smin)·(x / XN)β 0.3 ≦β≦ 0.5, to form the second semiconductor region through injection of an impurity of the second conductivity type.

Description

Semiconductor device manufacturing method and semiconductor device

[0001] The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device.

[0002] In recent years, price competition has intensified in the field of power semiconductor devices, and cost reduction is required. To reduce costs, it is necessary to increase the diameter of wafers, lower the process temperature, and miniaturize chips, which in turn requires shallower junctions in the termination region, a narrower width of the termination region, and the mitigation of the electric field in the termination region.

[0003] Conventional techniques relating to the structure of the termination region are disclosed in, for example, Japanese Patent Application Laid-Open No. 2003-122299 and Japanese Patent Application Laid-Open No. 2003-122299.

[0004] Patent Document 1 describes a termination structure (32) provided on the periphery of a semiconductor element, which comprises an N-type drift region (1) formed in a semiconductor substrate (30) and a P-type impurity region (2) formed on the upper surface of the N-type drift region (1), and the P-type impurity region (2) has, when viewed macroscopically, a P-type impurity concentration decreasing from the inner periphery to the outer periphery of the termination structure (32), and the P-type impurity region (2) is, when viewed microscopically, composed of a plurality of P-type high-concentration regions (2b) and low-concentration regions (2a) surrounding them, with the low-concentration regions (2a) having spaced apart portions (abstract, Figure 2).

[0005] Here, Patent Document 1 describes that the impurity concentration of the low concentration region (2a) is set to a value that satisfies the condition (resurf condition) under which the low concentration region (2a) is completely depleted, and that the impurity concentration of the high concentration region (2b) is set to a value that determines whether or not the high concentration region (2b) is depleted depending on variations in the wafer process (paragraph 0020).

[0006] Furthermore, Patent Document 1 describes that the aperture ratio of the implantation mask (20) used in the ion implantation to form such a P-type impurity region (2) is decreased toward the outside of the termination structure (32) (paragraph 0042), and that functions for decreasing the aperture ratio include linear functions, but functions with a high rate of decrease, such as exponential functions, are desirable, and that, for example, using a function that decreases according to an exponential function or polynomial that is convex downward when viewed macroscopically can alleviate local concentration of the electric field (paragraph 0043).

[0007] In Patent Document 2, a P-resurf layer (3) (electric field relaxation layer) having a lower concentration than the P-base layer (2) is formed so as to surround the P-base layer (2), and the P-resurf layer (3) is configured by alternately arranging high-concentration P-resurf layers (7a, 8a, 9a, 10a) and low-concentration P-resurf layers (8b, 9b, 10b, 11b), and the widths of each are expressed as w(7a) = w(8b) + w(8a) = w(9b) + w(9a) = w The document describes a structure in which the widths of the high-concentration P resurf layers (7a, 8a, 9a, 10a) are gradually narrowed outward, and the widths of the low-concentration P resurf layers (8b, 9b, 10b, 11b) are gradually widened outward, while the sum of the widths of each pair of high-concentration P resurf layers and low-concentration P resurf layers is kept equal so that (10b) + w(10a) = w(11b) (paragraphs 0027 to 0039, Figures 3 and 4).

[0008] International Publication No. WO 2014 / 054319 International Publication No. WO 2013 / 136550

[0009] In Patent Document 1, a linear function, a downwardly convex exponential function (a ｘ ), a function that decreases according to a polynomial is described, and Patent Document 2 describes a technique in which the width of the high-concentration P resurf layer gradually narrows toward the outside while the width of the low-concentration P resurf layer gradually widens toward the outside, while keeping the total width of each pair of high-concentration P resurf layer and low-concentration P resurf layer equal, in other words, a technique in which the concentration decreases in a pseudo-linear manner.However, as a result of simulations conducted by the inventors of the present application, it was found that a different shape is preferable for the mask shape to reduce the width of the termination region and to alleviate the electric field in the termination region.

[0010] The problem to be solved by the present invention is to provide a semiconductor device and a method for manufacturing the same that can reduce the width of the termination region and alleviate the electric field in the termination region.

[0011] In order to solve the above-mentioned problems, the present invention provides a method for manufacturing a semiconductor device having a termination region in which, for example, a plurality of second semiconductor regions having a second conductivity type are formed on a surface of a first semiconductor region having a first conductivity type around an active region, the second semiconductor regions having a second conductivity type and a depletion layer that spreads into the first semiconductor region when a voltage is applied and is continuous with the active region, and at least one second semiconductor region including a second semiconductor region formed at a position farthest from the active region among the plurality of second semiconductor regions is completely depleted when a voltage is applied to the second semiconductor region, and functions as a resurf region; When an injection window corresponding to a second semiconductor region formed at a position farthest from the active region in the second semiconductor region where a depletion layer extending into one semiconductor region is continuous with the active region is taken as a reference window, the position of the reference window on the active region side is taken as X0, the distance between the active region side position of the injection window adjacent to the active region and X0 is taken as XN, the interval between the reference window and the injection window on that one active region side is taken as Smax, the interval between the edge of the active region and the injection window adjacent to the active region is taken as Smin, the distance from X0 is taken as x, and the power coefficient is taken as β, the interval S(x) between the injection window at a position of distance x and the injection window on that one active region side is given by: S(x)=Smax-(Smax-Smin)(x / XN) β The second semiconductor region is formed by implanting the second conductivity type impurity using a mask having a value substantially equal to the value defined by 0.3≦β≦0.5.

[0012] Furthermore, the semiconductor device of the present invention is, for example, a semiconductor device having an active region and a termination region formed around the active region, wherein the termination region has a first semiconductor region having a first conductivity type and a plurality of second semiconductor regions having a second conductivity type formed on the surface of the first semiconductor region, the second semiconductor regions having a depletion layer that spreads into the first semiconductor region when a voltage is applied and is continuous with the active region, and when a voltage is applied, at least one second semiconductor region including the second semiconductor region formed at a position farthest from the active region among the plurality of second semiconductor regions becomes completely depleted and functions as a resurf region, and the termination region has the second semiconductor region formed using the above-mentioned semiconductor device manufacturing method.

[0013] According to the present invention, it is possible to realize a semiconductor device and a manufacturing method thereof that can reduce the width of the termination region and alleviate the electric field in the termination region.

[0014] 1 is a cross-sectional view of a semiconductor device according to a first embodiment; a plan view illustrating the shape of a mask according to the first embodiment; a diagram illustrating the distance between an implantation window of a mask and an implantation window on one active region side, and the width of the implantation window in the first embodiment; a diagram illustrating a dose profile according to the first embodiment; a diagram illustrating the effect of reducing the width of the termination region when β is changed; a diagram illustrating the change in breakdown voltage when β is changed; a diagram illustrating the change in the amount of decrease in breakdown voltage when β is changed; a cross-sectional view of a semiconductor device having a non-resurf structure as a comparative example; a diagram illustrating the difference in electric field strength characteristics between a resurf structure and a non-resurf structure; a diagram illustrating a dose profile according to a second embodiment; a diagram illustrating the distance between an implantation window of a mask and an implantation window on one active region side, and the width of the implantation window in the third embodiment; a diagram illustrating the distance between an implantation window of a mask and an implantation window on one active region side, and the width of the implantation window in the fourth embodiment; a cross-sectional view of a semiconductor device according to a fifth embodiment; a cross-sectional view of a semiconductor device according to a sixth embodiment;

[0015] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing and each embodiment, the same or similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0016] FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment.

[0017] The semiconductor device 10 of the first embodiment has a termination region 12 in which a plurality of second semiconductor regions 2 having a second conductivity type (e.g., p-type) are formed on the surface of a first semiconductor region 1 having a first conductivity type (e.g., n-type) around an active region 11. Here, the first conductivity type is described as n-type and the second conductivity type as p-type, but the first conductivity type may also be p-type and the second conductivity type may also be n-type.

[0018] Semiconductor elements such as an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and a diode are formed in the active region 11, but are not shown in the figure. The semiconductor substrate on which the semiconductor device 10 is formed may be made of, but is not limited to, silicon or silicon carbide.

[0019] A first semiconductor region 1 and a second semiconductor region 2 are also formed in the active region 11, and the second semiconductor region 2 in the active region 11 will be referred to herein as a second semiconductor region 2a.

[0020] The semiconductor device 10 also includes a channel stopper 6 formed in the termination region 12 and having a first conductivity type with a higher concentration than the first semiconductor region 1, an oxide film 4 formed to cover the first semiconductor region 1, the second semiconductor region 2, and the channel stopper 6, and an electrode 5 formed in the active region 11. The electrode 5 is, for example, a gate electrode or emitter electrode in the case of an IGBT, a gate electrode or source electrode in the case of a MOSFET, or an anode electrode in the case of a diode. Note that FIG. 1 illustrates only the front side of the semiconductor device 10, and the back side is not illustrated. An electrode (not shown), such as a collector electrode in the case of an IGBT, a drain electrode in the case of a MOSFET, or a cathode electrode in the case of a diode, is provided on the back side of the semiconductor device 10.

[0021] In the semiconductor device 10 of Example 1, in a thermal equilibrium state, the depletion layer 3 extending into the first semiconductor region 1 continues from the active region 11 to each second semiconductor region 2, and each second semiconductor region 2 becomes approximately an intrinsic region 7. One of the characteristics of the semiconductor device 10 is that depletion of each second semiconductor region 2 (shrinkage of the intrinsic region 7) due to the application of a voltage begins in the second semiconductor region 2 on the outer periphery of the termination region 12 (the side farther from the active region 11).

[0022] Furthermore, in the semiconductor device 10 of Example 1, even when a voltage is applied, the depletion layer 3 extending into the first semiconductor region 1 up to the plurality of second semiconductor regions 2 in the termination region 12 is continuous with the active region 11. Another feature of the semiconductor device 10 of Example 1 is that when a voltage is applied, at least one second semiconductor region 2 including the second semiconductor region 2 (2b described below) formed at a position farthest from the active region 11 among the plurality of second semiconductor regions 2 is completely depleted and functions as a resurf region 8.

[0023] The resurf region 8 has a function of alleviating the electric field and increasing the breakdown voltage by means of a reduced surface field (RESURF). In the resurf region 8, the second semiconductor region 2 is completely depleted and does not have the intrinsic region 7. If the impurity concentration of the second semiconductor region 2 is high, the second semiconductor region 2 will not be completely depleted and the intrinsic region 7 will remain. Therefore, the impurity concentration of the second semiconductor region 2 is set to a low value that will cause the second semiconductor region 2 to be completely depleted when a voltage is applied.

[0024] 1 , it is desirable that the second semiconductor region 2 of the termination region 12 be overlapped by a plurality of second semiconductor regions 2 from the side closest to the active region 11 to the side furthest from the active region 11. This allows the width of the termination region 12 to be reduced. However, this is not limiting, and the second semiconductor regions 2 of the termination region 12 may be overlapped by a plurality of second semiconductor regions 2 on the side closer to the active region 11, and may be separated from each other on the side farther from the active region 11. In either case, the second semiconductor region 2 of the termination region 12 is also continuous with the second semiconductor region 2 a of the active region 11 on the side closer to the active region 11.

[0025] In a thermal equilibrium state, the depletion layer 3 extending into the first semiconductor region 1 is continuous with the active region 11, and the second semiconductor region 2 formed at the position farthest from the active region 11 will be referred to as the outermost second semiconductor region 2b where the depletion layer 3 is continuous.

[0026] FIG. 2 is a plan view illustrating the shape of the mask of Example 1. FIG. 3 is a diagram illustrating the distance between the implantation window of the mask of Example 1 and the implantation window on the side of the next active region, and the width of the implantation window. For ease of viewing, the number of implantation windows 22 in FIG. 2 is simplified to be fewer than the number of second semiconductor regions 2 in FIG. 1. The horizontal axis of FIG. 3 represents the position POS, the vertical axis on the left represents the distance S (corresponding to the width of the shielding portion 21) between the implantation window 22 of the mask 20 and the implantation window 22 on the side of the next active region 11, and the vertical axis on the right represents the width W of the implantation window 22.

[0027] 2 is used to inject impurities of the second conductivity type to form the second semiconductor region 2. The mask 20 has a shielding portion 21 that blocks the impurities and an injection window 22 that is an opening that allows the impurities to pass through. Note that due to diffusion of the injected impurities, the size of the second semiconductor region 2 becomes larger than the size of the injection window 22.

[0028] Here, among the injection windows 22, the injection window 22 corresponding to the second semiconductor region 2a of the active region 11 will be referred to as the active region injection window 22a, and the injection window 22 corresponding to the outermost second semiconductor region 2b where the depletion layer 3 is continuous will be referred to as the reference window 22b.

[0029] The shape of the mask 20 in Example 1 is such that, when the position of the reference window 22b on the active region 11 side is X0, the distance between the position of the implantation window 22 adjacent to the active region 11 on the active region 11 side and X0 is XN, the spacing between the reference window 22b and the implantation window 22 one active region 11 away is Smax, the spacing between the edge of the active region 11 and the implantation window 22 adjacent to the active region 11 is Smin, the distance from X0 is x, and the power coefficient is β, the spacing S(x) between the implantation window 22 at the position of distance x and the implantation window 22 one active region 11 away is approximately equal to the value defined by the following equation (1). The range of β is preferably 0.3≦β≦0.5, as will be described later.

[0030] S(x)=Smax-(Smax-Smin)・(x / XN) β ...(1) This makes it possible to reduce the width of the termination region 12 and alleviate the electric field in the termination region 12. The effects will be described in detail later.

[0031] Furthermore, the mask 20 of Example 1 is shaped so that the width W(x) of the implantation window 22 at the position of the distance x decreases with increasing distance from the active region 11 .

[0032] This allows the width of the second semiconductor region 2 to be smaller than when the width W(x) of the implantation window 22 is constant regardless of the position of the distance x, and therefore the width of the termination region 12 can be reduced.

[0033] In the first embodiment, as shown in FIG. 3, the width W(x) of the implantation window at the position of the distance x is made to decrease linearly with increasing distance from the active region 11 .

[0034] 4 is a diagram illustrating the dose profile of Example 1. The horizontal axis of Fig. 4 represents the position POS, and the vertical axis represents the dose DO.

[0035] In order to form the resurf region 8, the impurity concentration of the second semiconductor region 2 must be set to a low value so that the second semiconductor region 2 is completely depleted at least on the side farther from the active region 11 when a voltage is applied. To achieve this, the dose amount in the second semiconductor region 2 of the termination region 12 when implanting the second conductivity type impurity using the mask 20 is set to 4×10 １２ cm －２ That's it, 3 x 10 １３ cm －２ It is desirable that the following:

[0036] Furthermore, in order to fully utilize the effect of alleviating the electric field by the resurf region 8, it is desirable that when a voltage up to the breakdown voltage is applied, the second semiconductor region 2 corresponding to at least the range of 0≦x≦XN / 2 is completely depleted so as to function as the resurf region 8. It is more desirable that the second semiconductor region 2 corresponding to at least the range of 0≦x≦XN×2 / 3 is completely depleted. However, it is not necessary to completely deplete the second semiconductor region 2 up to the range of x=XN.

[0037] In Example 1, when implanting impurities of the second conductivity type using the mask 20, the dose profile is set such that the dose amount in the second semiconductor region 2a of the active region 11 and the dose amount in the second semiconductor region 2a of the termination region 12 are approximately equal.

[0038] This makes it possible to form the second semiconductor region 2 by implanting the second conductivity type impurity using a single mask 20 .

[0039] The dose amount may be smaller than the above-mentioned range, but the dose amount required for the second semiconductor region 2a of the active region 11 may be insufficient because the second semiconductor region 2a of the active region 11 is used as a body region of a semiconductor element formed in the active region 11. Therefore, two masks 20 are required, but if necessary, when implanting the second conductivity type impurity using the masks 20, the dose amount in the second semiconductor region 2a of the termination region 12 may be smaller than the dose amount in the second semiconductor region 2a of the active region 11.

[0040] Next, the effect of realizing a reduction in the width of the termination region 12 and a relaxation of the electric field in the termination region 12 due to the shape of the mask 20 of the first embodiment will be described in detail.

[0041] 5 is a diagram illustrating the effect of reducing the width of the termination region when β is changed, where the horizontal axis represents the position POS and the vertical axis represents the distance S between the implantation window 22 in the mask 20 and the implantation window 22 on the active region 11 side (corresponding to the width of the shielding portion 21).

[0042] It is assumed that the distance S(x) between the implantation window 22 at a position of a distance x from X0 and the implantation window 22 on the side of the active region 11 can be expressed by the following equation (2).

[0043] S(x)=Smax-(Smax-Smin)・(x / Lx(β)) β ... (2) When Lx(β) = XN, the equation is the same as equation (1). Here, when the number of implantation windows 22 is 19 and the distance between the position of the implantation window 22 adjacent to the active region 11 on the active region 11 side and X0 is Lx(β), the spacing S(x) and Lx(0.3), Lx(0.4), Lx(0.5), Lx(1.0), and Lx(2.0) were calculated for β = 0.3, 0.4, 0.5, 1.0, and 2.0, and are shown in Figure 5.

[0044] As a result, it is found that the smaller β is, the smaller Lx(β), that is, the width of the termination region 12 can be reduced.

[0045] Here, β = 1.0 corresponds to a linear increase in the spacing S(x) as it approaches the outer periphery of the termination region 12 (as x approaches 0). While not strictly the same, this roughly corresponds to the case in Patent Document 1 where the aperture ratio of the implantation mask (20) decreases according to a linear function toward the outside of the termination structure (32) or the case in Patent Document 2 where the concentration decreases in a pseudo-linear manner toward the outside. Furthermore, β = 2.0 roughly corresponds to the case in Patent Document 1 where the aperture ratio of the implantation mask (20) decreases according to a polynomial toward the outside of the termination structure (32). However, when β = 1.0 or β = 2.0, Lx(1.0) or Lx(2.0) becomes larger than Lx(0.3) to Lx(0.5), and it was found that this is not suitable for reducing the width of the termination region 12.

[0046] Although not shown in FIG. 5, an example of an exponential function is ｘ (This roughly corresponds to the case in Patent Document 1 where the aperture ratio of the implantation mask (20) decreases exponentially toward the outside of the termination structure (32)), but the results were roughly close to the case where β = 2.0. Therefore, it was found that this case is also not suitable for reducing the width of the termination region 12.

[0047] 6 is a diagram illustrating the change in breakdown voltage when β is changed, in which the horizontal axis represents β and the vertical axis represents breakdown voltage V.

[0048] In FIG. 6, the interface charge density Qss is 0 cm －２ The breakdown voltage V was calculated assuming a diode with a nominal breakdown voltage of 750 V, and when β is smaller than 0.3, the slope of the decrease in the breakdown voltage V becomes steep. When β≦0.3, the breakdown voltage V is 850 V or higher, which is a breakdown voltage that is sufficiently higher than the nominal breakdown voltage of 750 V.

[0049] 7 is a diagram illustrating the change in the amount of breakdown voltage drop when β is changed, in which the horizontal axis represents β and the vertical axis represents the amount of breakdown voltage drop ΔV.

[0050] The breakdown voltage V shown in FIG. 6 is the value when the interface charge density Qss is 0 cm －２Since it is assumed that β is 0.4, this corresponds to the initial breakdown voltage. However, during stress testing or actual use, the interface charge density Qss changes, and as a result, the breakdown voltage V also changes. This change in the breakdown voltage V is the breakdown voltage drop ΔV shown in FIG. 7, with the top of the vertical axis representing 0 V and the bottom representing negative values. At β = 0.4, the absolute value of the breakdown voltage drop ΔV (negative value) is smallest (it peaks in the graph of FIG. 7), indicating the best performance. Furthermore, in the range where β is less than 0.3 or greater than 0.5, the slope of the breakdown voltage drop ΔV becomes steep, indicating that performance is likely to deteriorate. Therefore, it is desirable for β to be 0.3≦β≦0.5.

[0051] FIG. 8 is a cross-sectional view of a semiconductor device having a non-RESURF structure, which is a comparative example.

[0052] In the case of the non-RESURF structure, which is a comparative example, the impurity concentration of second semiconductor region 2 in termination region 12 is set high, and even when a voltage up to the breakdown voltage is applied, second semiconductor region 2 in termination region 12 is not completely depleted, leaving intrinsic region 7. Therefore, the amount of intrinsic region 7 that remains undepleted becomes dead space, and an area that is wasted when reducing the width of termination region 12 exists.

[0053] 9 is a diagram illustrating the difference in electric field strength characteristics between the RESURF structure and the non-RESURF structure, in which the horizontal axis represents the position POS and the vertical axis represents the electric field strength E.

[0054] The dotted line graph labeled "Non RESURF" in Figure 9 shows the characteristics of the electric field strength E of the non-RESURF structure, which is a comparative example, and it can be seen that the electric field strength E changes significantly between the valley portion corresponding to the shielding portion 21 and the mountain portion corresponding to the injection window 22.

[0055] In contrast, the solid line graph labeled "RESURF" in Figure 9 shows the characteristics of the electric field strength E of the RESURF structure of this embodiment, and it can be seen that the change in the electric field strength E is small, so that the electric field concentration is suppressed and the electric field is relaxed. This makes it possible to ensure the breakdown voltage.

[0056] As described above, according to Example 1, a RESURF structure is adopted in the termination region 12, and the mask 20 is shaped so that the spacing S(x) between the injection window 22 at the distance x and the injection window 22 on the side of the active region 11 is approximately equal to the value defined by equation (1) and 0.3≦β≦0.5, thereby making it possible to reduce the width of the termination region 12 and alleviate the electric field in the termination region 12.

[0057] 10 is a diagram illustrating a dose profile in Example 2. FIG. 10 is a diagram corresponding to FIG. 4 in Example 1.

[0058] The dose profile of Example 2 is different from that of Example 1. As shown in FIG. 10 , the dose profile of Example 2 is such that the dose amount of the second semiconductor region 2 in the termination region 12a closer to the active region 11 in the termination region 12 is greater than the dose amount of the second semiconductor region 2 in the termination region 12b farther from the active region 11 in the termination region 12. This has the effect of suppressing a decrease in breakdown voltage due to positive interface charge. However, in Example 2, in order to vary the dose amount depending on the region, it is necessary to implant the second conductivity type impurity using two masks 20, which also differs from Example 1.

[0059] Other than the above, the present embodiment is the same as the first embodiment, and therefore a duplicated description will be omitted.

[0060] 11 is a diagram for explaining the distance between the implantation window of the mask and the implantation window on the next active region side, and the width of the implantation window in Example 3. Fig. 11 is a diagram corresponding to Fig. 3 in Example 1.

[0061] In Example 3, the width W(x) of the implantation window 22 at the distance x is different from that in Example 1. The shape of the mask 20 in Example 3 is such that the width W(x) of the implantation window 22 at the distance x decreases linearly with increasing distance from the active region 11, and the slope of the decrease on the side closer to the active region 11 (x>XN') is greater than the slope of the decrease on the side farther from the active region 11 (x≦XN'). In FIG. 11 , Wmax' is the value of the width W(x) of the implantation window 22 at the distance x of XN'.

[0062] Next, the reason for changing the slope of the decrease in the width W(x) of the implantation window 22 will be explained. Heat treatment after implanting the second conductivity type impurities expands the width of the second semiconductor region 2 and reduces the peak concentration. The decrease in peak concentration is greater the narrower the width W(x) of the implantation window 22, and less the wider the width W(x) of the implantation window 22. In contrast, the width of the implantation window 22 in the second semiconductor region 2a in the active region 11 is orders of magnitude wider than the width W(x) of the implantation window in the termination region 12. Therefore, the decrease in peak concentration in the second semiconductor region 2a in the active region 11 is smaller than that in the second semiconductor region 2 in the termination region 12. Therefore, a difference in peak concentration occurs between the active region 11 and the adjacent second semiconductor region 2. If a large concentration difference exists, electric field concentration may occur at the edge of the active region 11, potentially resulting in a decrease in breakdown voltage. Therefore, a wider width W(x) of the implantation window 22 is preferable near the active region 11. On the other hand, if the width W(x) of the injection window 22 is wide, the overall width of the termination region 12 will be large, so it is better to make it as narrow as possible. Since the vicinity of the active region 11 is sufficient as a countermeasure against the electric field concentration at the edge of the active region 11, by making the slope of the decrease on the side closer to the active region 11 (x>XN') greater than the slope of the decrease on the side farther from the active region 11 (x≦XN'), as shown in Figure 11, it is possible to narrow the overall width of the termination region 12 compared to the case of Figure 3 while still taking measures against the electric field concentration at the edge of the active region 11. This is the reason for changing the slope of the decrease in the width W(x) of the injection window 22.

[0063] This also has the effect of suppressing a decrease in breakdown voltage due to positive interface charge, as in Example 2, even when forming the second semiconductor region 2 by injecting second conductivity type impurities with the same dose profile as in FIG. 4 of Example 1 using a single mask 20.

[0064] Other than the above, the present embodiment is the same as the first embodiment, and therefore a duplicated description will be omitted.

[0065] 12 is a diagram illustrating the distance between the implantation window of the mask and the implantation window on the next active region side, and the width of the implantation window, in Example 4. Fig. 12 is a diagram corresponding to Fig. 3 in Example 1.

[0066] In Example 4, the width W(x) of the injection window 22 at the position of the distance x differs from Examples 1 and 3. The shape of the mask 20 in Example 4 is such that, when the width of the injection window 22 at the position of the distance XN is Wmax and the width of the injection window 22 of the reference window 22b is Wmin, the width W(x) of the injection window 22 at the position of the distance x is approximately equal to the value defined by the following equation (3).

[0067] W(x)=Wmax-(Wmax-Wmin)・(1-x / XN) β In the fourth embodiment, the width W(x) of the injection window 22 can be changed smoothly instead of linearly, and a decrease in breakdown voltage due to positive interface charges can be suppressed.

[0068] Other than the above, the present embodiment is the same as the first and third embodiments, and therefore a duplicated description will be omitted.

[0069] FIG. 13 is a cross-sectional view of a semiconductor device according to a fifth embodiment.

[0070] In the fifth embodiment, the semiconductor device 10 has, in a part of the second semiconductor region 2a in the active region 11, a high concentration second semiconductor region 2c having a higher concentration of second conductivity type impurities than the surrounding area.

[0071] The high-concentration second semiconductor region 2c is provided, for example, in a part of the surface of the second semiconductor region 2a in the active region 11. This makes it possible to further suppress the expansion of the depletion layer 3 toward the surface side in the active region 11. Furthermore, the high-concentration second semiconductor region 2c is provided, for example, in a position in contact with the electrode 5. This makes it possible to further reduce the contact resistance between the electrode 5 and the second semiconductor region 2a in the active region 11, which functions as a body region, for example.

[0072] The impurity concentration of the second conductivity type in the high-concentration second semiconductor region 2c is 1×10 １４ cm －３ It is desirable that the concentration of the second conductivity type impurity in the high concentration second semiconductor region 2c is about 1×10 or higher. In other words, it is desirable that the concentration of the second conductivity type impurity in the high concentration second semiconductor region 2c is higher by one order of magnitude or more than the concentration of the second conductivity type impurity in the second semiconductor region 2a in the active region 11 around the high concentration second semiconductor region 2c and in the second semiconductor region 2 in the termination region 12. In this embodiment, the concentration of the second conductivity type impurity in the high concentration second semiconductor region 2c is set to 2×10 １４ cm －３ It was decided.

[0073] Other than the above, the present embodiment is the same as the first to fourth embodiments, and therefore a duplicated description will be omitted.

[0074] FIG. 14 is a cross-sectional view of a semiconductor device according to a sixth embodiment.

[0075] In the sixth embodiment, a channel stopper electrode 9 is provided.

[0076] The semiconductor device 10 of this embodiment has a channel stopper electrode 9 formed on the oxide film 4 and connected to the channel stopper 6 via an opening provided in the oxide film 4. The end of the channel stopper electrode 9 closer to the active region 11 is located closer to the active region 11 than the end of the channel stopper 6 closer to the active region 11. In other words, the channel stopper electrode 9 has a shape that protrudes further toward the active region 11 than the channel stopper 6.

[0077] To reduce the width of the termination region 12, it is necessary not only to reduce the overall dimensions of the second semiconductor region 2 in the termination region 12 but also to reduce the distance DCSP between the outermost second semiconductor region 2b, where the depletion layer 3 is continuous, and the channel stopper 6. Equipotential lines also extend in the region between the outermost second semiconductor region 2b, where the depletion layer 3 is continuous, and the channel stopper 6. When the distance DCSP is wide, the equipotential lines do not extend to the channel stopper 6. However, when the distance DCSP is narrow, multiple equipotential lines reach the channel stopper 6. Because the channel stopper 6 has a high concentration, the equipotential lines do not extend into the channel stopper 6. As a result, many equipotential lines are concentrated at the end of the channel stopper 6 closer to the active region 11, resulting in extremely high localized electric field strength. Therefore, there is a lower limit to the distance DCSP.

[0078] Therefore, in this embodiment, a channel stopper electrode 9 is provided, and the end of the channel stopper electrode 9 closer to the active region 11 is positioned closer to the active region 11 than the end of the channel stopper 6 closer to the active region 11. This generates a field plate effect of the channel stopper electrode 9. The equipotential lines that were concentrated at the end of the channel stopper 6 closer to the active region 11 are shifted by a certain percentage to the end of the channel stopper electrode 9 closer to the active region 11, thereby reducing the local increase in electric field strength at the end of the channel stopper 6 closer to the active region 11. This reduction effect is determined by the distance LFP between the end of the channel stopper electrode 9 closer to the active region 11 and the end of the channel stopper 6 closer to the active region 11. Increasing the distance LFP provides a significant reduction effect, but at the same time increases the electric field strength in the oxide film 4 below the end of the channel stopper electrode 9 closer to the active region 11. The appropriate value of the distance LFP depends on the breakdown voltage and the concentration of the low-concentration first semiconductor region 1, but it may be set to a few μm to a few tens of μm. In this example, the distance LFP was set to 20 μm. This enabled the distance DCSP to be reduced by 10% or more compared to when the field plate effect of the channel stopper electrode 9 was not used.

[0079] Other than the above, the present embodiment is the same as the first to fourth embodiments, and therefore a duplicated description will be omitted.

[0080] Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible within the scope of the technical concept of the present invention. In addition, some or all of the configurations described in each embodiment may be combined and applied.

[0081] 1...first semiconductor region, 2...second semiconductor region, 2a...second semiconductor region in active region, 2b...second semiconductor region at the outermost periphery where the depletion layer is continuous, 2c...highly doped second semiconductor region, 3...depletion layer, 4...oxide film, 5...electrode, 6...channel stopper, 7...intrinsic region, 8...resurf region, 9...channel stopper electrode, 10...semiconductor device, 11...active region, 12, 12a, 12b...termination region, 20...mask, 21...shielding portion, 22...implantation window, 22a...active region implantation window, 22b...reference window, S...spacing between implantation window and implantation window one position closer to the active region, W...implantation window width, x...distance, β...power coefficient, DO...dose amount, POS...position, V...breakdown voltage, ΔV...amount of decrease in breakdown voltage, Qss...interface charge density, E...electric field strength

Claims

1. A method for manufacturing a semiconductor device having a termination region in which a first semiconductor region having a first conductivity type is surrounded by a surface of the first semiconductor region, the second semiconductor region having a second conductivity type and a depletion layer extending into the first semiconductor region when a voltage is applied thereto is formed so as to be continuous with the active region, and at least one of the second semiconductor regions, including the second semiconductor region formed at a position farthest from the active region among the second semiconductor regions, is completely depleted when a voltage is applied to the second semiconductor region, and functions as a resurf region, A mask for forming the second semiconductor region, wherein an injection window corresponding to a second semiconductor region formed at a position farthest from an active region in the second semiconductor region where a depletion layer spreading into the first semiconductor region in a thermal equilibrium state is continuous with the active region is defined as a reference window, a position of the reference window on the active region side is defined as X0, a distance between a position of the injection window adjacent to the active region on the active region side and X0 is defined as XN, a spacing between the reference window and the injection window on one active region side is defined as Smax, a spacing between an end of the active region and the injection window adjacent to the active region is defined as Smin, a distance from X0 is defined as x, and a power coefficient is defined as β, whereby a spacing S(x) between the injection window at a position of distance x and the injection window on one active region side is expressed as follows: S(x)=Smax-(Smax-Smin)·(x / XN). β 6. A method for manufacturing a semiconductor device, comprising the steps of: implanting an impurity of the second conductivity type using a mask having a value substantially equal to the value defined by 0.3≦β≦0.5 to form the second semiconductor region.

2. A method of manufacturing a semiconductor device according to claim 1, wherein the mask has an implantation window width W(x) at the position of the distance x that decreases with increasing distance from the active region.

3. A method of manufacturing a semiconductor device according to claim 2, wherein the mask has an implantation window width W(x) at the position of the distance x that decreases linearly with increasing distance from the active region.

4. A method for manufacturing a semiconductor device as claimed in claim 2, characterized in that the width W(x) of the implantation window at the position of the distance x in the mask decreases linearly with increasing distance from the active region, and the slope of the decrease on the side closer to the active region is greater than the slope of the decrease on the side farther from the active region.

5. In claim 2, when the width of the injection window at the position of the distance XN is Wmax and the width of the injection window of the reference window is Wmin, the width W(x) of the injection window at the position of the distance x is expressed as follows: W(x) = Wmax - (Wmax - Wmin) (1 - x / XN) β 4. A method for manufacturing a semiconductor device, comprising the steps of:

6. A method for manufacturing a semiconductor device according to claim 1, characterized in that when the mask is used to inject the second conductivity type impurity, the dose amount in the second semiconductor region of the active region and the dose amount in the second semiconductor region of the termination region are approximately equal.

7. A method for manufacturing a semiconductor device according to claim 1, characterized in that when the mask is used to inject the second conductivity type impurity, the dose amount in the second semiconductor region of the termination region is smaller than the dose amount in the second semiconductor region of the active region.

8. A method for manufacturing a semiconductor device as claimed in claim 1, characterized in that when the second conductivity type impurity is implanted using the mask, the dose amount of the second semiconductor region on the side closer to the active region in the termination region is greater than the dose amount of the second semiconductor region on the side farther from the active region.

9. The method according to claim 1, wherein the dose of the second conductive type impurity implanted into the second semiconductor region of the termination region using the mask is 4×10 １２ cm －２ That's it, 3 x 10 １３ cm －２ 1. A method for manufacturing a semiconductor device, comprising:

10. The method for manufacturing a semiconductor device according to claim 1, wherein the second semiconductor region, which corresponds to at least the range of 0≦x≦XN / 2, is completely depleted when a voltage up to the breakdown voltage is applied to the second semiconductor region and functions as the resurf region.

11. A semiconductor device having an active region and a termination region formed around the active region, wherein the termination region comprises a first semiconductor region having a first conductivity type and a plurality of second semiconductor regions having a second conductivity type formed on the surface of the first semiconductor region, the depletion layer of which spreads into the first semiconductor region when a voltage is applied and is continuous with the active region, wherein at least one second semiconductor region including a second semiconductor region formed at a position farthest from the active region among the plurality of second semiconductor regions becomes completely depleted when a voltage is applied and functions as a resurf region, and wherein the second semiconductor region is formed in the termination region using the manufacturing method for a semiconductor device described in any one of claims 1 to 10.

12. A semiconductor device according to claim 11, characterized in that in a state of thermal equilibrium, in the region of the second semiconductor region from the second semiconductor region formed by the injection window adjacent to the active region to the second semiconductor region formed by the reference window, the depletion layer spreading into the first semiconductor region is continuous from the active region, and each second semiconductor region is an approximately intrinsic region, and depletion of each of the second semiconductor regions due to the application of a voltage begins in the second semiconductor region formed by the reference window.

13. A semiconductor device according to claim 11, characterized in that there is an overlap from a second semiconductor region defined by an implantation window adjacent to said active region to a second semiconductor region defined by said reference window.

14. A semiconductor device according to claim 11, characterized in that in the second semiconductor region, in the region from the second semiconductor region formed by the injection window adjacent to the active region to the second semiconductor region formed by the reference window, a plurality of the second semiconductor regions overlap on the side closer to the active region, and the second semiconductor regions are separated from each other on the side farther from the active region.

15. A semiconductor device according to claim 11, further comprising a high concentration second semiconductor region in a portion of said second semiconductor region in said active region, said high concentration second semiconductor region having a higher concentration of said second conductivity type impurities than the surrounding area.

16. A semiconductor device according to claim 11, comprising: a channel stopper formed in the termination region and having a first conductivity type with a higher concentration than the first semiconductor region; an oxide film formed to cover the first semiconductor region, the second semiconductor region and the channel stopper; and a channel stopper electrode formed on the oxide film and connected to the channel stopper through an opening provided in the oxide film, wherein an end of the channel stopper electrode closer to the active region is located closer to the active region than an end of the channel stopper closer to the active region.

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