Semiconductor device

Abstract

[Problem] To effectively suppress the concentration of an electric field caused when a reverse voltage is applied in a semiconductor device that has a structure in which an outer peripheral trench is provided in a drift layer. [Solution] A semiconductor device 1 comprises a semiconductor substrate 20, a drift layer 30 provided on the semiconductor substrate 20, an anode electrode 40 in contact with the drift layer 30, and a cathode electrode 50 in contact with the semiconductor substrate 20. The drift layer 30 has an outer peripheral trench 61 which is provided so as to surround the anode electrode 40 in plan view without overlapping the anode electrode 40 in plan view, an outer peripheral trench 62 which is adjacent to the outer peripheral trench 61 and which is provided outside the outer peripheral trench 61 so as to surround the outer peripheral trench 61 in plan view, and a mesa region 311 which is positioned between the outer peripheral trench 61 and the outer peripheral trench 62. The width Wm1 of the mesa region 311 is less than the width Wt1 of the outer peripheral trench 61.

Description

Semiconductor Devices

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device having a structure in which a peripheral trench is provided in a drift layer.

[0002] Patent Document 1 discloses a semiconductor device having a first electrode layer in contact with the front surface of an n-type gallium oxide semiconductor layer, a second electrode layer in contact with the back surface of the n-type gallium oxide semiconductor layer, and a p-type nickel oxide semiconductor layer embedded in trenches provided in the n-type gallium oxide semiconductor layer. In Patent Document 1, by providing multiple trenches in which the p-type nickel oxide semiconductor layer is embedded, concentration of an electric field that occurs when a reverse voltage is applied is suppressed.

[0003] Japanese Patent Application Laid-Open No. 2023-010539

[0004] However, the structure disclosed in Patent Document 1 does not provide a sufficient effect of suppressing the concentration of an electric field generated when a reverse voltage is applied to a trench portion, such as the trench bottom, in the drift layer.

[0005] This disclosure describes a technique for effectively suppressing electric field concentration that occurs when a reverse voltage is applied to a semiconductor device having a structure in which a peripheral trench is provided in a drift layer.

[0006] A semiconductor device according to one aspect of the present disclosure includes a semiconductor substrate, a drift layer provided on the semiconductor substrate, a first electrode in contact with the drift layer, and a second electrode in contact with the semiconductor substrate, wherein the drift layer has a plurality of peripheral trenches including a first peripheral trench provided so as to surround the first electrode in a planar view without overlapping with the first electrode in a planar view, and a second peripheral trench adjacent to the first peripheral trench and provided outside the first peripheral trench so as to surround the first peripheral trench in a planar view, and a first mesa region located between the first peripheral trench and the second peripheral trench, and the width of the first mesa region is narrower than the width of the first peripheral trench.

[0007] According to the present disclosure, a technique is provided for effectively suppressing electric field concentration that occurs when a reverse voltage is applied in a semiconductor device having a structure in which a peripheral trench is provided in a drift layer.

[0008] FIG. 1A is a schematic plan view showing a configuration of a semiconductor device 1 according to a first embodiment of the technology disclosed herein. FIG. 1B is a schematic cross-sectional view taken along line A-A in FIG. 1A. FIG. 2A is a schematic cross-sectional view illustrating a structure according to a first modified example of the semiconductor device 1. FIG. 2B is a schematic cross-sectional view illustrating a structure according to a second modified example of the semiconductor device 1. FIG. 2C is a schematic cross-sectional view illustrating a structure according to a third modified example of the semiconductor device 1. FIG. 3A is a schematic cross-sectional view illustrating a structure according to a fourth modified example of the semiconductor device 1. FIG. 3B is a schematic cross-sectional view illustrating a structure according to a fifth modified example of the semiconductor device 1. FIG. 3C is a schematic cross-sectional view illustrating a structure according to a sixth modified example of the semiconductor device 1. FIG. 4A is a schematic cross-sectional view illustrating a structure according to a seventh modified example of the semiconductor device 1. FIG. 4B is a schematic cross-sectional view illustrating a structure according to an eighth modified example of the semiconductor device 1. FIG. 5A is a schematic plan view showing the configuration of a semiconductor device 2 according to a second embodiment of the technology disclosed herein. FIG. 5B is a schematic cross-sectional view taken along line A-A in FIG. 5A. FIG. 6 is a schematic cross-sectional view illustrating a structure according to a first modified example of the semiconductor device 2. FIG. 7 is a schematic cross-sectional view illustrating a structure according to a second modified example of the semiconductor device 2. FIG. 8 is a schematic cross-sectional view illustrating a structure according to a third modified example of the semiconductor device 2. FIG. 9 is a schematic cross-sectional view illustrating a structure according to a fourth modified example of the semiconductor device 2. FIG. 10 is a schematic cross-sectional view illustrating a structure according to a fifth modified example of the semiconductor device 2. FIG. 11A is a schematic plan view showing the configuration of a semiconductor device 3 according to a third embodiment of the technology disclosed herein. FIG. 11B is a schematic cross-sectional view taken along line A-A in FIG. 11A. FIG. 12 is a schematic cross-sectional view illustrating a structure according to a modified example of the semiconductor device 3.

[0009] Hereinafter, embodiments of the technology according to the present disclosure will be described in detail with reference to the accompanying drawings.

[0010] 1A is a schematic plan view showing the configuration of a semiconductor device 1 according to a first embodiment of the technology disclosed herein, and FIG. 1B is a schematic cross-sectional view taken along line AA in FIG. 1A.

[0011] The semiconductor device 1 shown in FIG. 1 is a Schottky barrier diode. ２ O ３ The semiconductor substrate 20 and the drift layer 30 are made of silicon (Si) or tin (Sn) as an n-type dopant. The concentration of the dopant is higher in the semiconductor substrate 20 than in the drift layer 30, so that the semiconductor substrate 20 is made of n-type ＋ layer, and the drift layer 30 is n － For example, the dopant concentration of the semiconductor substrate 20 is 1×10 １８ cm －３ and the dopant concentration in the drift layer 30 is 1×10 １６ cm －３ is.

[0012] The semiconductor substrate 20 is cut from a bulk crystal formed by a melt growth method or the like, and has a thickness of about 250 μm. The planar size of the semiconductor substrate 20 is not particularly limited, but is generally selected depending on the amount of current to be passed through the element. If the maximum forward current is about 20 A, the size should be about 2.4 mm × 2.4 mm in plan view.

[0013] The semiconductor substrate 20 has an upper surface 21 that is located on the upper surface side when mounted, and a back surface 22 that is opposite the upper surface 21 and is located on the lower surface side when mounted. A drift layer 30 is formed on the entire upper surface 21. The drift layer 30 is a thin film formed by epitaxially growing gallium oxide on the upper surface 21 of the semiconductor substrate 20 using a method such as reactive sputtering, PLD, MBE, MOCVD, or HVPE. The film thickness of the drift layer 30 is not particularly limited, but is generally selected depending on the reverse withstand voltage of the device. To ensure a withstand voltage of about 600 V, the thickness may be, for example, about 15 μm.

[0014] An anode electrode 40 is formed on the upper surface 31 of the drift layer 30, making Schottky contact with the drift layer 30. The anode electrode 40 functions as a first electrode of the semiconductor device 1. The anode electrode 40 is made of a metal such as platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), molybdenum (Mo), or copper (Cu). The anode electrode 40 may have a multilayer structure in which different metal films are stacked, such as Pt / Au, Pt / Al, Pd / Au, Pd / Al, Pt / Ti / Au, or Pd / Ti / Au. Meanwhile, a cathode electrode 50 is provided on the rear surface 22 of the semiconductor substrate 20, making ohmic contact with the semiconductor substrate 20. The cathode electrode 50 functions as a second electrode of the semiconductor device 1. The cathode electrode 50 is made of a metal such as titanium (Ti). The cathode electrode 50 may have a multilayer structure in which different metal films are stacked, such as Ti / Au or Ti / Al. In this case, Ti is in contact with the semiconductor substrate 20.

[0015] In this embodiment, peripheral trenches 61, 62 are provided in the drift layer 30. The peripheral trench 61 is provided so as to surround the anode electrode 40 in plan view without overlapping with the anode electrode 40 in plan view. In other words, the peripheral trench 61 is provided further outward than the outer edge 41 of the anode electrode 40. The peripheral trench 62 is provided outside the peripheral trench 61 so as to surround the peripheral trench 61 in plan view. The peripheral trenches 61 and 62 are adjacent to each other. P-type semiconductor members 71, 72, which are semiconductor members having the opposite conductivity type to the drift layer 30, are buried inside the peripheral trenches 61, 62, respectively. Each of the p-type semiconductor members 71, 72 and the drift layer 30 form a p-n junction. The p-type semiconductor members 71 and 72 may be Si, GaAs, GaN, SiC, Ge, ZnSe, CdS, InP, SiGe, AlN, BN, AlGaN, NiO, Cu ２ O, Ir ２ O ３ , Ag ２ O and the like can be used.

[0016] As shown in FIG. 1B , the p-type semiconductor member 72 embedded in the peripheral trenches 61 and 62 is not in contact with the anode electrode 40 .

[0017] The region of the upper surface 31 of the drift layer 30 located between the peripheral trenches 61 and 62 constitutes a mesa region 311. The mesa region 311 is not in contact with the anode electrode 40. Here, if the width of the peripheral trench 61 is Wt1, the width of the peripheral trench 62 is Wt2, and the width of the mesa region 311 is Wm1, then in the example shown in FIG. 1B , Wm1 < Wt1 = Wt2 holds. That is, the width of the mesa region 311 is narrower than the width of the peripheral trench 61. Note that the width Wt1 of the peripheral trench 61 and the width Wt2 of the peripheral trench 62 do not need to be the same; for example, the width Wt2 of the peripheral trench 62 may be narrower than the width Wt1 of the peripheral trench 61.

[0018] As a result, when a reverse voltage is applied to semiconductor device 1, the difference in potential between periphery trench 61 and periphery trench 62 becomes small. As a result, the electric field applied to periphery trench 61 is dispersed over a wide area, and the electric field gradient becomes gentle. As a result, the electric field strength applied to the bottom of periphery trench 61, indicated by symbol B in FIG. 1B, decreases, improving the reliability of semiconductor device 1.

[0019] As an example, if the thickness of drift layer 30 is 15 μm, the depth of peripheral trenches 61, 62 is 2 μm, p-type semiconductor members 71, 72 are made of NiO, anode electrode 40 is made of Ni, and cathode electrode 50 is made of a Ti / Au laminated film, the electric field strength applied to the bottom of peripheral trench 61 indicated by symbol B when a reverse voltage of 2000 V is applied is 4.7 MV / cm when designed so that Wt1 = Wt2 = Wm1 = 3 μm, whereas it is reduced to 4.5 MV / cm when designed so that Wt1 = Wt2 = 4 μm and Wm1 = 3 μm.

[0020] Fig. 2(a) is a schematic cross-sectional view illustrating the structure of a first modified example of semiconductor device 1. The first modified example shown in Fig. 2(a) differs from semiconductor device 1 shown in Fig. 1(b) in that peripheral trenches 61, 62 are not completely filled with p-type semiconductor members 71, 72, respectively, and p-type semiconductor members 71, 72 are provided only on the inner walls of peripheral trenches 61, 62, respectively. Even with this structure, it is possible to obtain the same effects as those of semiconductor device 1 described above.

[0021] 2(b) is a schematic cross-sectional view illustrating a structure according to a second modified example of the semiconductor device 1. The second modified example shown in Fig. 2(b) differs from the semiconductor device 1 shown in Fig. 1(b) in that p-type semiconductor members 71, 72 are provided only on the bottoms and corners that form the boundaries between the bottoms and side surfaces of the inner walls of the peripheral trenches 61, 62. Even with this structure, it is possible to obtain the same effects as the semiconductor device 1 described above.

[0022] 2(c) is a schematic cross-sectional view illustrating a structure according to a third modified example of semiconductor device 1. The third modified example shown in Fig. 2(c) differs from the first modified example of semiconductor device 1 shown in Fig. 2(a) in that the inner walls of peripheral trenches 61, 62 and portions of upper surface 31 of drift layer 30 located in the vicinity thereof are covered with p-type semiconductor members 71, 72. Even with this structure, it is possible to obtain the same effects as those of semiconductor device 1 described above.

[0023] Fig. 3(a) is a schematic cross-sectional view for explaining the structure of a fourth modified example of the semiconductor device 1. The fourth modified example shown in Fig. 3(a) differs from the first modified example of the semiconductor device 1 shown in Fig. 2(a) in that the surfaces of the p-type semiconductor members 71, 72 are covered with an insulating film 81. Even with this structure, it is possible to obtain the same effects as the semiconductor device 1 described above.

[0024] Fig. 3(b) is a schematic cross-sectional view illustrating the structure of a fifth modified example of the semiconductor device 1. The fifth modified example shown in Fig. 3(b) differs from the fourth modified example of the semiconductor device 1 shown in Fig. 3(a) in that the peripheral trenches 61, 62 are filled with an insulating film 81 via p-type semiconductor members 71, 72, respectively. Even with this structure, it is possible to obtain the same effects as the semiconductor device 1 described above.

[0025] Fig. 3(c) is a schematic cross-sectional view for explaining the structure of a sixth modified example of the semiconductor device 1. The sixth modified example shown in Fig. 3(c) differs from the fifth modified example of the semiconductor device 1 shown in Fig. 3(b) in that the upper surface 31 of the drift layer 30 exposed from the anode electrode 40 and the outer periphery of the anode electrode 40 are covered with an insulating film 81. Even with this structure, it is possible to obtain the same effects as those of the semiconductor device 1 described above.

[0026] Fig. 4(a) is a schematic cross-sectional view for explaining the structure of a seventh modified example of the semiconductor device 1. The seventh modified example shown in Fig. 4(a) differs from the fifth modified example of the semiconductor device 1 shown in Fig. 3(b) in that the upper surface 31 of the drift layer 30 exposed from the anode electrode 40 and the outer periphery of the anode electrode 40 are covered with an insulating film 82 different from the insulating film 81. Even with this structure, it is possible to obtain the same effects as the semiconductor device 1 described above.

[0027] Fig. 4(b) is a schematic cross-sectional view for explaining the structure of an eighth modified example of the semiconductor device 1. The eighth modified example shown in Fig. 4(b) differs from the fourth modified example of the semiconductor device 1 shown in Fig. 3(a) in that the upper surface 31 of the drift layer 30 exposed from the anode electrode 40, the outer periphery of the anode electrode 40, and the inside of the outer periphery trench 62 are covered with an insulating film 82 different from the insulating film 81. Even with this structure, it is possible to obtain the same effects as those of the semiconductor device 1 described above.

[0028] Second Embodiment Fig. 5A is a schematic plan view showing the configuration of a semiconductor device 2 according to a second embodiment of the technology disclosed herein, and Fig. 5B is a schematic cross-sectional view taken along line AA shown in Fig. 5A.

[0029] The semiconductor device 2 according to the second embodiment differs from the semiconductor device 1 according to the first embodiment in that peripheral trenches 63 to 65 are further provided in the drift layer 30, and p-type semiconductor members 73 to 75 are respectively embedded in the peripheral trenches 63 to 65. Since the other basic configuration is the same as that of the semiconductor device 1 according to the first embodiment, the same elements are denoted by the same reference numerals and redundant explanations will be omitted.

[0030] The peripheral trench 63 is provided outside the peripheral trench 62 so as to surround the peripheral trench 62 in a plan view. The peripheral trench 64 is provided outside the peripheral trench 63 so as to surround the peripheral trench 63 in a plan view. The peripheral trench 65 is provided outside the peripheral trench 64 so as to surround the peripheral trench 64 in a plan view. The peripheral trench 65 constitutes the outermost trench located at the outermost periphery. Furthermore, none of the p-type semiconductor members 71 to 75 embedded in the peripheral trenches 61 to 65, respectively, contacts the anode electrode 40.

[0031] Of the upper surface 31 of the drift layer 30, the region located between the periphery trench 62 and the periphery trench 63 constitutes a mesa region 312. Of the upper surface 31 of the drift layer 30, the region located between the periphery trench 63 and the periphery trench 64 constitutes a mesa region 313. Of the upper surface 31 of the drift layer 30, the region located between the periphery trench 64 and the periphery trench 65 constitutes a mesa region 314. Like the mesa region 311, none of the mesa regions 312 to 314 contact the anode electrode 40.

[0032] Here, assuming that the widths of the peripheral trenches 61-65 are Wt1-Wt5, respectively, and the widths of the mesa regions 311-314 are Wm1-Wm4, respectively, in the example shown in FIG. 5 , Wm1<Wt1=Wt2=Wt3=Wt4=Wt5, and Wm1<Wm2=Wm3=Wm4. That is, the width of the mesa region 311 is narrower than the widths of the peripheral trenches 61-65 and narrower than the width of the mesa region 314. In the example shown in FIG. 5 , of two adjacent mesa regions, the width of the mesa region located on the outer periphery is wider than or equal to the width of the mesa region located on the inner periphery. That is, of two adjacent mesa regions, the width of the mesa region located on the outer periphery is equal to or greater than the width of the mesa region located on the inner periphery.

[0033] In this way, by providing three or more peripheral trenches in drift layer 30, the electric field gradient becomes gentler when a reverse voltage is applied to semiconductor device 2, thereby mitigating the maximum electric field applied to drift layer 30. Furthermore, because the width of mesa region 311 is narrower than the widths of the other mesa regions 312 to 314, the potential difference between peripheral trench 61 and peripheral trench 62 is reduced, mitigating the maximum electric field applied to drift layer 30. This further improves the reliability of semiconductor device 2.

[0034] As an example, in the semiconductor device 1 according to the first embodiment, if the thickness of the drift layer 30 is 15 μm, the depth of the peripheral trenches 61, 62 is 2 μm, the p-type semiconductor members 71, 72 are made of NiO, the anode electrode 40 is made of Ni, and the cathode electrode 50 is made of a Ti / Au laminated film, the maximum electric field strength applied to the drift layer 30 when a reverse voltage of 2000 V is applied is Wt1=Wt2=4 μm, and Wm1=3 μm. On the other hand, in the semiconductor device 2 according to the second embodiment, when the thickness of the drift layer 30 is 15 μm, the depth of the peripheral trenches 61 to 65 is 2 μm, the p-type semiconductor members 71 to 75 are made of NiO, the anode electrode 40 is made of Ni, and the cathode electrode 50 is made of a Ti / Au laminated film, the maximum electric field strength applied to the drift layer 30 when a reverse voltage of 2000 V is applied is relaxed to 6.3 MV / cm when the designs are Wt1=Wt2=Wt3=Wt4=Wt5=4 μm, Wm1=1 μm, and Wm2=Wm3=Wm4=4 μm.

[0035] Fig. 6 is a schematic cross-sectional view illustrating the structure of a first modified example of semiconductor device 2. The first modified example shown in Fig. 6 differs from semiconductor device 2 shown in Fig. 5(b) in that, unlike the first modified example of semiconductor device 1 shown in Fig. 2(a), peripheral trenches 61-65 are not completely filled with p-type semiconductor members 71-75, respectively, and p-type semiconductor members 71-75 are provided only on the inner walls of peripheral trenches 61-65, respectively. Even with this structure, it is possible to obtain the same effects as those of semiconductor device 2 described above.

[0036] Furthermore, in the semiconductor device 2 according to the second embodiment, as in the second modified example of the semiconductor device 1 shown in FIG. 2( b), p-type semiconductor members 71-75 may be provided only on the bottom surface and on the corners that form the boundary between the bottom surface and the side surface of the inner walls of the peripheral trenches 61-65, respectively; or as in the third modified example of the semiconductor device 1 shown in FIG. 2( c), the inner walls of the peripheral trenches 61-65 and a portion of the upper surface 31 of the drift layer 30 located in the vicinity thereof may be covered with the p-type semiconductor members 71-75, respectively.

[0037] Furthermore, in the semiconductor device 2 according to the second embodiment, the surfaces of the p-type semiconductor members 71 to 75 may be covered with an insulating film 81 as in the fourth modified example of the semiconductor device 1 shown in FIG. 3( a), the peripheral trenches 61 to 65 may be filled with the insulating film 81 via the p-type semiconductor members 71 to 75, respectively, as in the fifth modified example of the semiconductor device 1 shown in FIG. 3( b), or the upper surface 31 of the drift layer 30 exposed from the anode electrode 40 and the peripheral portion of the anode electrode 40 may be covered with the insulating film 81 as in the sixth modified example of the semiconductor device 1 shown in FIG.

[0038] Furthermore, in the semiconductor device 2 according to the second embodiment, as in the seventh modified example of the semiconductor device 1 shown in FIG. 4( a), the peripheral trenches 61 to 65 may be filled with an insulating film 81 via the p-type semiconductor members 71 to 75, respectively, and the upper surface 31 of the drift layer 30 exposed from the anode electrode 40 and the outer periphery of the anode electrode 40 may be covered with an insulating film 82 different from the insulating film 81. Alternatively, as in the eighth modified example of the semiconductor device 1 shown in FIG. 4( b), the surfaces of the p-type semiconductor members 71 to 75 may be covered with the insulating film 81, and the upper surface 31 of the drift layer 30 exposed from the anode electrode 40, the outer periphery of the anode electrode 40, and the insides of the peripheral trenches 62 to 65 may be covered with an insulating film 82 different from the insulating film 81.

[0039] 7 is a schematic cross-sectional view illustrating a structure according to a second modified example of the semiconductor device 2. The second modified example shown in FIG. 7 differs from the semiconductor device 2 shown in FIG. 5B in that Wm1<Wm2<Wm3<Wm4 holds. That is, of two adjacent mesa regions, the width of the mesa region located on the outer periphery is wider than the width of the mesa region located on the inner periphery. As a result, the potential difference between two adjacent outer periphery trenches decreases toward the inner periphery, further reducing the maximum electric field applied to the drift layer 30.

[0040] As an example, if the drift layer 30 is 15 μm thick, the peripheral trenches 61-65 are 2 μm deep, the p-type semiconductor members 71-75 are made of NiO, the anode electrode 40 is made of Ni, and the cathode electrode 50 is made of a Ti / Au laminated film, the maximum electric field strength applied to the drift layer 30 when a reverse voltage of 2000 V is applied is reduced to 5.6 MV / cm if the following are designed: Wt1 = Wt2 = Wt3 = Wt4 = Wt5 = 4 μm, Wm1 = 1 μm, Wm2 = 3 μm, Wm3 = 4 μm, and Wm4 = 5 μm. In the above example, the width of the mesa region 314 located at the outermost periphery is greater than the width of the peripheral trenches 61-65. Furthermore, the width of the mesa region 313 located second from the outermost periphery is the same as the width of the peripheral trenches 61-65. In this way, the mesa region 311 located at the innermost periphery may be designed to be narrower than the peripheral trenches 61 to 65, and the mesa region 314 located at the outermost periphery may be designed to be wider than the peripheral trenches 61 to 65.

[0041] FIG. 8 is a schematic cross-sectional view illustrating a structure according to a third modified example of the semiconductor device 2. The third modified example shown in FIG. 8 differs from the second modified example of the semiconductor device 2 shown in FIG. 7 in that Wm1<Wm2<Wm3≦Wm4<Wt4 is satisfied. That is, the width of the mesa region 314 located on the outermost periphery is narrower than the width of the outer peripheral trench 64 adjacent to the outermost peripheral trench 65. This further reduces the maximum electric field applied to the drift layer 30. In addition, in the example shown in FIG. 8, of two adjacent mesa regions, the width of the mesa region located on the outer periphery is equal to or greater than the width of the mesa region located on the inner periphery.

[0042] As an example, if the thickness of drift layer 30 is 15 μm, the depth of peripheral trenches 61 to 65 is 2 μm, p-type semiconductor members 71 to 75 are made of NiO, anode electrode 40 is made of Ni, and cathode electrode 50 is made of a Ti / Au laminated film, the maximum electric field strength applied to drift layer 30 when a reverse voltage of 2000 V is applied is relaxed to 5.3 MV / cm if the following are designed: Wt1 = Wt2 = Wt3 = Wt4 = Wt5 = 4 μm, Wm1 = 1 μm, Wm2 = 2 μm, and Wm3 = Wm4 = 3 μm.

[0043] FIG. 9 is a schematic cross-sectional view illustrating a structure according to a fourth modified example of the semiconductor device 2. The fourth modified example shown in FIG. 9 differs from the semiconductor device 2 shown in FIG. 5B in that Wt1 = Wt2 = Wt3 = Wt4 > Wt5. That is, the width of the outermost peripheral trench 65 is narrower than the width of the first peripheral trench 61. This enables a reduction in chip size while ensuring the same effects as the semiconductor device 2 shown in FIG. 5B. In addition, in the example shown in FIG. 9, of two adjacent peripheral trenches, the width of the peripheral trench located on the outer side is narrower than or equal to the width of the peripheral trench located on the inner side. That is, of two adjacent peripheral trenches, the width of the peripheral trench located on the outer side is equal to or smaller than the width of the peripheral trench located on the inner side.

[0044] As an example, if the thickness of drift layer 30 is 15 μm, the depth of peripheral trenches 61 to 65 is 2 μm, p-type semiconductor members 71 to 75 are made of NiO, anode electrode 40 is made of Ni, and cathode electrode 50 is made of a Ti / Au laminated film, the maximum electric field strength applied to drift layer 30 when a reverse voltage of 2000 V is applied is 5.9 MV / cm when designed as follows: Wt1=Wt2=Wt3=Wt4=4 μm, Wt5=3 μm, Wm1=1 μm, and Wm2=Wm3=Wm4=4 μm, and an effect equivalent to that of semiconductor device 2 shown in FIG. 5B when Wt1=Wt2=Wt3=Wt4=Wt5=4 μm can be obtained.

[0045] 10 is a schematic cross-sectional view illustrating a structure according to a fifth modified example of the semiconductor device 2. The fifth modified example shown in FIG. 10 differs from the semiconductor device 2 shown in FIG. 5B in that the relationship Wt1>Wt2>Wt3>Wt4>Wt5 holds. That is, of two adjacent peripheral trenches, the width of the peripheral trench located on the outer periphery is narrower than the width of the peripheral trench located on the inner periphery. This makes it possible to further reduce the chip size while maintaining the same effects as the semiconductor device 2 shown in FIG. 5B.

[0046] As an example, if the thickness of drift layer 30 is 15 μm, the depth of peripheral trenches 61 to 65 is 2 μm, p-type semiconductor members 71 to 75 are made of NiO, anode electrode 40 is made of Ni, and cathode electrode 50 is made of a Ti / Au laminated film, the maximum electric field strength applied to drift layer 30 when a reverse voltage of 2000 V is applied is 5.9 MV / cm when designed as follows: Wt1 = 4 μm, Wt2 = 3.5 μm, Wt3 = 3 μm, Wt4 = 2.5 μm, Wt5 = 2 μm, Wm1 = 1 μm, and Wm2 = Wm3 = Wm4 = 4 μm. This provides an effect equivalent to that of semiconductor device 2 shown in FIG. 5B when Wt1 = Wt2 = Wt3 = Wt4 = Wt5 = 4 μm.

[0047] 11A is a schematic plan view showing the configuration of a semiconductor device 3 according to a third embodiment of the technology disclosed herein, and FIG. 11B is a schematic cross-sectional view taken along line AA in FIG.

[0048] The semiconductor device 3 according to the third embodiment differs from the semiconductor device 2 according to the second embodiment in that a plurality of central trenches 90 are further provided in the drift layer 30, and an anode electrode 40 is provided in the central trench 90 via an insulating film 83. Since the other basic configurations are the same as those of the semiconductor device 2 according to the second embodiment, the same elements are denoted by the same reference numerals and redundant description will be omitted.

[0049] Unlike the peripheral trenches 61 to 65, the central trenches 90 all overlap the anode electrode 40 in plan view. In contrast, the peripheral trenches 61 to 65 all do not overlap the anode electrode 40 in plan view.

[0050] The anode electrodes 40 provided in the multiple central trenches 90 and the anode electrodes 40 provided on the upper surface 31 of the drift layer 30 may be made of the same material or different materials. The multiple central trenches 90 and the peripheral trenches 61-65 may have the same depth or different depths. For example, the depths of the multiple central trenches 90 and the peripheral trenches 61-65 may all be about 2 μm.

[0051] The region of the upper surface 31 of the drift layer 30 sandwiched between the two central trenches 90 constitutes a mesa region 310. The mesa region 310 becomes a depletion layer when a reverse voltage is applied between the anode electrode 40 and the cathode electrode 50. This pinches off the channel region of the drift layer 30, significantly suppressing leakage current when a reverse voltage is applied.

[0052] As described above, the semiconductor device 3 according to the third embodiment has a plurality of central trenches 90 provided at positions overlapping the anode electrode 40 in a plan view, thereby reducing leakage current. Furthermore, the provision of a plurality of central trenches 90 also reduces the electric field strength applied to the bottom of the peripheral trench 61 indicated by the symbol B in FIG.

[0053] As an example, in the case where the thickness of the drift layer 30 is 15 μm, the depth of the peripheral trenches 61 to 65 and the central trench 90 is 2 μm, the p-type semiconductor members 71 to 75 are made of NiO, the anode electrode 40 is made of Ni, and the cathode electrode 50 is made of a Ti / Au laminated film, the electric field strength applied to the bottom of the peripheral trench 61 indicated by the symbol B when a reverse voltage of 2000 V is applied is designed to be Wt1=Wt2=Wt3=Wt4=Wt5=4 μm, Wm1=1 μm, Wm2=2 μm, and Wm3=Wm4=3 μm. In this case, when the central trench 90 is not present, the electric field strength is 4.1 MV / cm, whereas when multiple central trenches 90 are provided, this is reduced to 3.1 MV / cm.

[0054] 11A and 11B may be provided in the semiconductor device 1 according to the first embodiment or the semiconductor device 2 according to the second embodiment. That is, in the semiconductor device 1 according to the first embodiment or the semiconductor device 2 according to the second embodiment, a plurality of central trenches 90 may be provided in the drift layer 30, and the anode electrode 40 may be provided in the central trench 90 via the insulating film 83.

[0055] FIG. 12 is a schematic cross-sectional view illustrating a structure according to a modified example of the semiconductor device 3. The modified example shown in FIG. 12 differs from the semiconductor device 3 shown in FIG. 11( b) in that p-type semiconductor members 79, which are semiconductor members having the opposite conductivity type to that of the drift layer 30, are embedded in the multiple central trenches 90. The drift layer 30 and the p-type semiconductor members 79 form a pn junction. This results in a so-called junction barrier Schottky diode. Furthermore, similar to the semiconductor device 3, when a reverse voltage is applied between the anode electrode 40 and the cathode electrode 50, the channel region between the mesa regions 310 is pinched off, thereby significantly reducing leakage current when a reverse voltage is applied. Furthermore, by providing the p-type semiconductor members 79 in the multiple central trenches 90, the electric field strength applied to the bottom of the peripheral trench 61, indicated by the symbol B in FIG. 12, is reduced.

[0056] As an example, in the case where the thickness of the drift layer 30 is 15 μm, the depth of the peripheral trenches 61 to 65 and the central trench 90 is 2 μm, the p-type semiconductor members 71 to 75, 79 are made of NiO, the anode electrode 40 is made of Ni, and the cathode electrode 50 is made of a Ti / Au laminated film, the electric field strength applied to the bottom of the peripheral trench 61 indicated by the symbol B when a reverse voltage of 2000 V is applied is designed to be Wt1 = Wt2 = Wt3 = Wt4 = Wt5 = 4 μm, Wm1 = 1 μm, Wm2 = 2 μm, and Wm3 = Wm4 = 3 μm. In this case, when the central trench 90 is not present, the electric field strength is 4.1 MV / cm, whereas when a plurality of central trenches 90 each provided with a p-type semiconductor member 79 is provided, this is reduced to 3.3 MV / cm.

[0057] 12 may be provided in the semiconductor device 1 according to the first embodiment or the semiconductor device 2 according to the second embodiment. That is, in the semiconductor device 1 according to the first embodiment or the semiconductor device 2 according to the second embodiment, a plurality of central trenches 90 may be provided in the drift layer 30, and a p-type semiconductor member 79 having a conductivity type opposite to that of the drift layer 30 may be provided in each central trench 90.

[0058] The above describes embodiments of the technology according to the present disclosure, but the technology according to the present disclosure is not limited to the above embodiments, and various modifications are possible within the scope of the gist of the technology, and it goes without saying that these modifications are also included within the scope of the technology according to the present disclosure.

[0059] For example, in each of the above embodiments, gallium oxide is used as the material of the semiconductor substrate 20 and the drift layer 30, but the material of the semiconductor substrate 20 and the drift layer 30 is not limited to gallium oxide, and materials such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), diamond (C), silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), etc. Even when these materials are used as the material of the semiconductor substrate 20 and the drift layer 30, it is possible to obtain the same effect based on the same principle as when gallium oxide is used.

[0060] The technology according to the present disclosure includes, but is not limited to, the following configuration examples.

[0061] A semiconductor device according to one aspect of the present disclosure includes a semiconductor substrate, a drift layer provided on the semiconductor substrate, a first electrode in contact with the drift layer, and a second electrode in contact with the semiconductor substrate, the drift layer having a plurality of peripheral trenches including a first peripheral trench provided so as to surround the first electrode in plan view without overlapping with the first electrode in plan view, and a second peripheral trench adjacent to the first peripheral trench and provided outside the first peripheral trench so as to surround the first peripheral trench in plan view, and a first mesa region located between the first and second peripheral trenches, the width of the first mesa region being narrower than the width of the first peripheral trench, thereby mitigating the electric field strength applied to the bottom of the first peripheral trench.

[0062] In the semiconductor device described above, the plurality of peripheral trenches may further include an outermost peripheral trench located on the outermost periphery, the drift layer may further include a second mesa region located between the outermost peripheral trench and the outermost peripheral trench adjacent to the outermost peripheral trench, and the width of the first mesa region may be narrower than the width of the second mesa region. This makes the electric field gradient gentler, thereby mitigating the maximum electric field applied to the drift layer.

[0063] In the semiconductor device described above, the drift layer has a plurality of mesa regions including first and second mesa regions, and of two adjacent mesa regions, the width of the mesa region located on the outer periphery may be equal to or greater than the width of the mesa region located on the inner periphery. In this way, the potential difference between two adjacent outer periphery trenches decreases toward the inner periphery, thereby further mitigating the maximum electric field applied to the drift layer.

[0064] In the semiconductor device described above, the width of the second mesa region may be narrower than the width of the outermost trench adjacent to the outermost trench, thereby further reducing the maximum electric field applied to the drift layer.

[0065] In the semiconductor device described above, the width of the outermost peripheral trench among the plurality of peripheral trenches may be narrower than the width of the first peripheral trench, which allows for a reduction in chip size.

[0066] In the semiconductor device described above, the plurality of outer periphery trenches may include at least three outer periphery trenches, and the width of the outer periphery trench of two adjacent outer periphery trenches may be equal to or less than the width of the outer periphery trench of the inner periphery trench, thereby enabling a further reduction in chip size.

[0067] In the semiconductor device described above, the drift layer may further include a plurality of central trenches provided at positions overlapping the first electrode in plan view, and the first electrode may be provided in the plurality of central trenches via an insulating film, thereby reducing leakage current and alleviating the electric field strength applied to the bottom of the first outer peripheral trench.

[0068] In the semiconductor device described above, the drift layer may further include a plurality of central trenches provided at positions overlapping the first electrode in plan view, and the plurality of central trenches may be provided with a semiconductor material having an opposite conductivity type to that of the drift layer, thereby reducing leakage current and alleviating the electric field strength applied to the bottom of the first outer peripheral trench.

[0069] In the semiconductor device described above, the first electrode may be an anode electrode and the second electrode may be a cathode electrode, thereby forming a diode.

[0070] In the semiconductor device described above, the first electrode may be in Schottky contact with the drift layer, and the second electrode may be in ohmic contact with the semiconductor substrate, thereby forming a Schottky barrier diode.

[0071] In the above-described semiconductor device, the plurality of peripheral trenches are provided with semiconductor members of an opposite conductivity type to that of the drift layer, and the semiconductor members provided in the plurality of peripheral trenches do not necessarily have to be in contact with the first electrode.

[0072] This application claims the benefit of Japanese Patent Application No. 2023-156321, filed on September 21, 2023, the entire disclosure of which is incorporated herein by reference.

[0073] 1 to 3 semiconductor device 20 semiconductor substrate 21 upper surface of semiconductor substrate 22 back surface of semiconductor substrate 30 drift layer 31 upper surface of drift layer 40 anode electrode 41 outer edge of anode electrode 50 cathode electrode 61 to 65 peripheral trench 71 to 75, 79 p-type semiconductor member 81 to 83 insulating film 90 central trench 310 to 314 mesa region

Claims

1. A semiconductor device comprising: a semiconductor substrate; a drift layer provided on the semiconductor substrate; a first electrode in contact with the drift layer; and a second electrode in contact with the semiconductor substrate, wherein the drift layer has a plurality of peripheral trenches including a first peripheral trench provided so as to surround the first electrode in a planar view without overlapping with the first electrode in a planar view, and a second peripheral trench adjacent to the first peripheral trench and provided outside the first peripheral trench so as to surround the first peripheral trench in a planar view; and a first mesa region located between the first and second peripheral trenches, wherein a width of the first mesa region is narrower than a width of the first peripheral trench.

2. The semiconductor device according to claim 1, wherein the plurality of peripheral trenches further include an outermost trench located on the outermost periphery, the drift layer further has a second mesa region located between the outermost trench and an outermost trench adjacent to the outermost trench, and a width of the first mesa region is narrower than a width of the second mesa region.

3. The semiconductor device according to claim 2, wherein the drift layer has a plurality of mesa regions including the first and second mesa regions, and of two adjacent mesa regions, the width of the mesa region located on the outer periphery is equal to or greater than the width of the mesa region located on the inner periphery.

4. The semiconductor device according to claim 2, wherein a width of said second mesa region is narrower than a width of a peripheral trench adjacent to said outermost peripheral trench.

5. The semiconductor device according to claim 1, wherein the width of the outermost peripheral trench among the plurality of outer peripheral trenches is narrower than the width of the first outer peripheral trench.

6. The semiconductor device according to claim 5, wherein the plurality of outer periphery trenches include at least three outer periphery trenches, and of two adjacent outer periphery trenches, the width of the outer periphery trench located on the outer periphery side is equal to or smaller than the width of the outer periphery trench located on the inner periphery side.

7. The semiconductor device according to claim 1, wherein the drift layer further has a plurality of central trenches provided at positions overlapping the first electrode in a planar view, and the first electrode is provided in the plurality of central trenches via an insulating film.

8. The semiconductor device according to claim 1, wherein the drift layer further has a plurality of central trenches provided at positions overlapping the first electrode in a planar view, and the plurality of central trenches are provided with semiconductor material having an opposite conductivity type to that of the drift layer.

9. The semiconductor device according to any one of claims 1 to 8, wherein the first electrode is an anode electrode, and the second electrode is a cathode electrode.

10. The semiconductor device according to claim 9, wherein the first electrode is in Schottky contact with the drift layer, and the second electrode is in ohmic contact with the semiconductor substrate.

11. The semiconductor device according to claim 1, wherein the plurality of peripheral trenches are provided with a semiconductor material having an opposite conductivity type to that of the drift layer, and the semiconductor material provided in the plurality of peripheral trenches is not in contact with the first electrode.

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