Power semiconductor transistor and manufacturing method thereof

Abstract

This power semiconductor transistor comprises: a buffer layer, a channel layer, and a barrier layer which are stacked in sequence on a substrate; a source electrode which is formed in a predetermined area on the barrier layer; a gate electrode which is formed on the barrier layer to be spaced a predetermined distance apart from the source electrode in the widthwise direction; a p-GaN drain which is formed on the barrier layer to be spaced a predetermined distance apart from the gate electrode in the widthwise direction; and a drain electrode which is formed to cover the p-GaN drain on the barrier layer.

Description

Power semiconductor transistor and its manufacturing method

[0001] The present invention relates to a power semiconductor transistor, and more particularly, to a power semiconductor transistor including a p-GaN insert electrode and a method for manufacturing the same.

[0002] In order to implement normally-off operating characteristics in which no channel exists and no drain current flows when no gate voltage is applied in GaN (Gallium Nitride) power semiconductor devices, a GIT (Gate Injection Transistor) structure that forms p-GaN under the gate is mainly utilized.

[0003] It is known that a method of improving the on-characteristics or improving the off-characteristics by inserting p-GaN into the drain electrode in a GIT device is possible, and this structure is called a HD-GIT (Hybrid-Drain-embedded Gate Injection Transistor) structure.

[0004] Inserting a p-GaN drain structure connected to the drain electrode between the gate and the drain can prevent the current collapse phenomenon on the drain side due to holes injected from the p-type drain (pdrain).

[0005] For GITs with a drain structure similar to that of a typical GaN HEMT, a steep potential drop occurs near the drain edge region due to the carrier trapping effect, which not only lowers the breakdown voltage but also causes an increase in the dynamic on-resistance (Ron) during switching due to trapped charges.

[0006] The introduction of the HD-GIT structure can compensate for negative charge charging due to carrier trapping by hole injection at the p-drain and suppress the phenomenon of increased dynamic Ron during switching.

[0007] In addition, when the HD-GIT structure is introduced, the reverse voltage blocking performance of the drain is improved, so that even when the gate is turned on, the reverse voltage blocking characteristics are similar to those in the gate turn-off state.

[0008] However, the HD-GIT structure has a problem in that a drain turn-on voltage of approximately 1 to 2 V occurs due to the depletion region caused by the pn junction in the p-type drain, which causes an increase in on-resistance.

[0009] An object of the present invention is to provide a power semiconductor transistor including a p-GaN inserted drain electrode and a method for manufacturing the same.

[0010] According to a preferred embodiment of the present invention for achieving the above-described purpose, a power semiconductor transistor includes a buffer layer, a channel layer, and a barrier layer sequentially stacked on a substrate, a source electrode formed in a predetermined region on the barrier layer, a gate electrode formed on the barrier layer at a predetermined interval in the width direction from the source electrode, a p-GaN drain formed on the barrier layer at a predetermined interval in the width direction from the gate electrode, and a drain electrode formed to cover the p-GaN drain on the barrier layer.

[0011] The above p-GaN drain is characterized by being arranged in a longitudinal bar shape.

[0012] The above p-GaN drain is characterized by including a plurality of p-GaN drain islands formed at a predetermined interval in the longitudinal direction.

[0013] The above p-GaN drain island is characterized in that it is formed with a length in the y-axis direction of 0.2 um or more and a width in the x-axis direction of 0.2 um or more.

[0014] The above p-GaN drain is characterized by including a main axis portion in the shape of a rod extending in the longitudinal direction, and a plurality of protrusions formed by extending from the main axis portion in the direction of the gate electrode while being spaced apart from each other by a predetermined interval in the longitudinal direction.

[0015] The width between the boundary of the p-GaN drain closest to the gate electrode and the boundary of the drain electrode closest to the gate electrode is characterized by being 0.2 um to 1.0 um.

[0016] According to a preferred embodiment of the present invention for achieving the above-described purpose, a power semiconductor transistor includes a buffer layer, a channel layer, and a barrier layer sequentially laminated on a substrate, a source electrode formed in a predetermined region on the barrier layer, a source electrode and a gate electrode formed on the barrier layer at a predetermined interval in the width direction from the source electrode, a p-GaN drain formed on the barrier layer at a predetermined interval in the width direction from the gate electrode, and a drain electrode formed to cover a portion of the p-GaN drain on the barrier layer.

[0017] The above p-GaN drain includes a plurality of p-GaN drain islands formed at a predetermined interval in the length direction, and the drain electrode is characterized in that a part of the gate side of the plurality of p-GaN drain islands is exposed and the remainder is covered.

[0018] The above p-GaN drain island is characterized in that it is formed with a length in the y-axis direction of 0.2 um or more and a width in the x-axis direction of 0.2 um or more.

[0019] A method for manufacturing a power semiconductor transistor according to a preferred embodiment of the present invention for achieving the above-described object includes the steps of sequentially forming a buffer layer, a channel layer, and a barrier layer on a substrate, the step of depositing a gallium nitride film on the barrier layer, the step of patterning the gallium nitride film to form a p-GaN gate and a p-GaN drain, the step of forming a source electrode and a drain electrode on the barrier layer, the step of forming the drain electrode so as to cover the p-GaN drain, and the step of forming a gate electrode on the p-GaN gate.

[0020] The step of forming the above p-GaN drain is characterized by arranging the p-GaN drain in a longitudinal rod shape.

[0021] The step of forming the above p-GaN drain is characterized by forming a p-GaN drain including a plurality of p-GaN drain islands spaced apart at a predetermined interval in the length direction.

[0022] The above p-GaN drain island is characterized in that it is formed with a length in the y-axis direction of 0.2 um or more and a width in the x-axis direction of 0.2 um or more.

[0023] The step of forming the above p-GaN drain is characterized by forming a p-GaN drain including a main axis portion having a rod shape extending in the longitudinal direction and a plurality of protrusions formed by extending from the main axis portion in the direction of the gate electrode while being spaced apart from each other by a predetermined interval in the longitudinal direction.

[0024] The width between the boundary of the p-GaN drain closest to the gate electrode and the boundary of the drain electrode closest to the gate electrode is characterized by being 0.2 um to 1.0 um.

[0025] A method for manufacturing a power semiconductor transistor according to a preferred embodiment of the present invention for achieving the above-described object includes the steps of sequentially forming a buffer layer, a channel layer, and a barrier layer on a substrate, the step of depositing a gallium nitride film on the barrier layer, the step of patterning the gallium nitride film to form a p-GaN gate and a p-GaN drain, the step of forming a source electrode and a drain electrode on the barrier layer, the step of forming the drain electrode so as to cover a portion of the p-GaN drain, and the step of forming a gate electrode on the p-GaN gate.

[0026] The step of forming the p-GaN drain is characterized in that the step of forming the p-GaN drain includes forming a p-GaN drain including a plurality of p-GaN drain islands spaced apart at a predetermined interval in the length direction, and the step of forming the drain electrode is characterized in that a part of the gate side of the plurality of p-GaN drain islands is exposed and the remainder is covered.

[0027] The above p-GaN drain island is characterized in that it is formed with a length in the y-axis direction of 0.2 um or more and a width in the x-axis direction of 0.2 um or more.

[0028] According to the present invention, the present invention can provide a GaN-based power semiconductor transistor having improved on- and off-characteristics without increasing drain turn-on voltage and on-resistance while maintaining the advantage of improved switching characteristics by hole injection by inserting a p-GaN drain into a drain electrode.

[0029] FIG. 1 is a cross-sectional view in the width direction for explaining the structure of a power semiconductor transistor including an ohmic electrode according to an embodiment of the present invention.

[0030] Figure 2 is an enlarged cross-sectional view of part A in Figure 1.

[0031] FIGS. 3a to 3c are diagrams showing simulation results of hole injection by the p-GaN drain of the present invention compared with the prior art.

[0032] FIGS. 4A to 4C are diagrams showing simulation results of the characteristics of drain turn-on voltage and on-resistance of the present invention compared with those of the prior art.

[0033] Figure 5 is a graph for observing the characteristics of drain turn-on voltage and on-resistance of the present invention in comparison with the prior art.

[0034] Figure 6 is a transfer curve for comparing the flow of current within the device of the present invention with that of the prior art.

[0035] Figure 7 is a plan view for explaining the shape of the gate and drain electrodes of a conventional HEMT (High Electron Mobility Transistor).

[0036] Figure 8 is a plan view for explaining the shape of the gate and drain electrodes of a conventional HD-GIT (Hybrid-Drain-embedded Gate Injection Transistor).

[0037] FIG. 9 is a plan view for explaining the shapes of gate and drain electrodes of a semiconductor device according to the first embodiment of the present invention.

[0038] FIG. 10 is a plan view for explaining the shape of the gate and drain electrodes of a semiconductor device according to the second embodiment of the present invention.

[0039] FIG. 11 is a plan view for explaining the shape of the gate and drain electrodes of a semiconductor device according to the third embodiment of the present invention.

[0040] FIG. 12 is a plan view for explaining the shape of the gate and drain electrodes of a semiconductor device according to the fourth embodiment of the present invention.

[0041] FIG. 13 is a flowchart illustrating a method for manufacturing a power semiconductor transistor including an ohmic electrode according to an embodiment of the present invention.

[0042] Before going into a detailed description of the present invention, it should be understood that the embodiments described in this specification and the configurations illustrated in the drawings are merely the most preferred embodiments of the present invention and do not represent all of the technical ideas of the present invention, and therefore, there may be various equivalents and modified examples that can replace them at the time of filing this application.

[0043] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. It should be noted that, where possible, identical components are represented by identical reference numerals throughout the drawings. Furthermore, detailed descriptions of well-known functions and structures that may obscure the gist of the present invention will be omitted. For the same reason, some components in the attached drawings are exaggerated, omitted, or schematically depicted, and the dimensions of each component do not fully reflect their actual size.

[0044] In addition, the terms and words used in the present specification and claims described below should not be interpreted as limited to their usual or dictionary meanings, but should be interpreted as meanings and concepts that conform to the technical idea of ​​the present invention based on the principle that the inventor can appropriately define the concept of the term to explain his or her own invention in the best way.

[0045] First, the structure of a power semiconductor transistor including an ohmic electrode according to an embodiment of the present invention will be described. Fig. 1 is a cross-sectional view in the width direction for explaining the structure of a power semiconductor transistor including an ohmic electrode according to an embodiment of the present invention. Fig. 2 is an enlarged cross-sectional view of portion A in Fig. 1.

[0046] Referring to FIG. 1, a power semiconductor transistor according to an embodiment of the present invention includes a buffer layer (10), a channel layer (20), a barrier layer (30), a p-GaN gate (40a), a p-GaN drain (40b), a source electrode (50a), a drain electrode (50b), and a gate electrode (60).

[0047] Here, a buffer layer (10), a channel layer (20), and a barrier layer (30) are sequentially laminated on a substrate (1). In addition, a p-GaN gate (40a) and a gate electrode (60) are formed by being laminated in a predetermined region on the barrier layer (30). Here, the buffer layer (10) and the channel layer (20) are formed of GaN (Gallium Nitride), and the barrier layer (30) is formed of AlGaN (Aluminium gallium nitride).

[0048] As shown, a source electrode (50a) is formed at a predetermined interval to the left of the width direction of the gate electrode (60), and a p-GaN drain (40b) and a drain electrode (50b) are formed at a predetermined interval to the right of the width direction of the gate electrode (60). In particular, the drain electrode (50b) is formed to cover the p-GaN drain (40b).

[0049] Referring to FIG. 2, it is preferable that the width (LD-ext) between the boundary of the p-GaN drain (40b) closest to the gate electrode (60) and the boundary of the drain electrode (50b) closest to the gate electrode (60) be formed to be 0.2 um to 1.0 um.

[0050] Next, the effects of the drain structure (40b, 50b) of the present invention described above will be explained in comparison with the prior art. FIGS. 3A to 3C are diagrams showing simulation results of hole injection by the p-GaN drain of the present invention in comparison with the prior art. FIGS. 4A to 4C are diagrams showing simulation results of the characteristics of drain turn-on voltage and on-resistance of the present invention in comparison with the prior art. FIG. 5 is a graph for observing the characteristics of drain turn-on voltage and on-resistance of the present invention in comparison with the prior art. FIG. 6 is a transfer curve for comparing the flow of current in the device of the present invention with the prior art.

[0051] FIG. 3a shows a simulation result of hole injection by a p-GaN drain of a conventional HEMT (High Electron Mobility Transistor), FIG. 3b shows a simulation result of hole injection by a p-GaN drain of a conventional HD-GIT (Hybrid-Drain-embedded Gate Injection Transistor), and FIG. 3c shows a simulation result of hole injection by a p-GaN drain of a semiconductor device according to the present invention.

[0052] According to the prior art, there is a disadvantage of increased drain turn-on voltage and on-resistance (Ron) due to the depletion region of the p-GaN drain. However, in the drain structure (40b, 50b) of the present invention, drain current starts to flow before the p-GaN drain region (40b) is turned on due to the influence of the width (LD-ext) between the boundary of the p-GaN drain (40b) and the boundary of the drain electrode (50b). Accordingly, the present invention can maintain the advantage of improved switching characteristics by hole injection from the p-GaN drain (40b) without increasing the drain turn-on voltage and on-resistance (Ron).

[0053] Fig. 4a shows the simulation results of a conventional HEMT (High Electron Mobility Transistor), Fig. 4b shows the simulation results of a conventional HD-GIT (Hybrid-Drain-embedded Gate Injection Transistor), and Fig. 4c shows the simulation results of a semiconductor device according to the present invention. The simulation results of Figs. 4a to 4c were achieved through TCAD-based device simulation.

[0054] Referring to FIGS. 4a and 4b, it can be seen that the device with the conventional HD-GIT structure illustrated in FIG. 4b has a drain turn-on voltage of about 1 V and thus a larger on-resistance compared to the HEMT device with the conventional general ohmic drain structure illustrated in FIG. 4a.

[0055] Referring to FIGS. 4b and 4c, device simulations were performed on the conventional HD-GIT structure illustrated in FIG. 4b and the HD-GIT structure having the improved ohmic electrode structure (40b, 50b) of the present invention illustrated in FIG. 4c, and the results confirming the elimination of drain turn-on voltage and improvement of on-resistance (Ron) characteristics in the HD-GIT structure of the present invention.

[0056] Referring to FIG. 5, the simulation results show that the HD-GIT device of the present invention exhibits significantly improved operating characteristics and lower on-resistance when operating at low VDS compared to the conventional HD-GIT device, and has characteristics similar to the on-resistance of the conventional HEMT, so that the introduction of the p-GaN drain structure (40b, 50b) does not cause a decrease in on-resistance characteristics.

[0057] In Fig. 6, a transfer curve is shown, which observes the flow of current within the device while fixing the drain current and changing the gate voltage. Referring to this, as in Fig. 6 (b), when VDS = 10 V is sufficiently large, there is not a large difference in the forward transfer characteristics of the conventional HEMT structure, the conventional HD-GIT structure, and the proposed HD-GIT structure due to the forward turn-on of the p-GaN drain (40b). However, as in Fig. 6 (a), in the low VDS region (e.g., when VDS = 2 V) when the power device is generally turned on, a large current difference occurs, which shows that the drain structures (40b, 50b) of the present invention have a remarkable effect.

[0058] Next, various embodiments of the drain structure (40b, 50b) according to an embodiment of the present invention will be described. FIGS. 7 to 12 are plan views for comparing and explaining the conventional technology with the present invention. In particular, FIGS. 7 to 12 are plan views illustrating an area corresponding to the width of part B of FIG. 1, i.e., an area including gate and drain electrodes. FIG. 7 is a plan view for explaining the shape of the gate and drain electrodes of a conventional HEMT (High Electron Mobility Transistor). FIG. 8 is a plan view for explaining the shape of the gate and drain electrodes of a conventional HD-GIT (Hybrid-Drain-embedded Gate Injection Transistor). FIG. 9 is a plan view for explaining the shape of the gate and drain electrodes of a semiconductor device according to a first embodiment of the present invention. FIG. 10 is a plan view for explaining the shape of the gate and drain electrodes of a semiconductor device according to a second embodiment of the present invention. Fig. 11 is a plan view for explaining the shapes of the gate and drain electrodes of a semiconductor device according to a third embodiment of the present invention. Fig. 12 is a plan view for explaining the shapes of the gate and drain electrodes of a semiconductor device according to a fourth embodiment of the present invention.

[0059] As illustrated in Fig. 7, in the case of a conventional HEMT (High Electron Mobility Transistor) device, a gate electrode (6) and a drain electrode (5b) are formed on a barrier layer (3) with a predetermined interval between them. In addition, as illustrated in Fig. 8, in the case of a conventional HD-GIT (Hybrid-Drain-embedded Gate Injection Transistor) device, a p-GaN drain (4b) is formed in a drain structure (4b, 5b) on the barrier layer (3) so that the drain structure is exposed.

[0060] Referring to FIG. 9, the drain structure (40b, 50b) of the semiconductor device according to the first embodiment of the present invention is formed such that the drain electrode (50b) covers the p-GaN drain (40b). In other words, the p-GaN drain (40b) has a form in which it is embedded within the drain electrode (50b). At this time, the p-GaN drain (40b) is arranged in a longitudinal bar shape.

[0061] Referring to FIG. 10, in the drain structure (40b, 50b) of the semiconductor device according to the second embodiment of the present invention, the p-GaN drain (40b) includes a plurality of p-GaN drain islands formed at a predetermined interval in the length direction. The p-GaN drain (40b) of the island structure can be a form in which the drain structure of the HEMT and the proposed HD-GIT structure are combined. In the drain structure (40b, 50b) including the p-GaN drain (40b) of the island structure according to the second embodiment, the cross-section taken along line a is the same as the drain structure (40b, 50b) of the first embodiment, and the cross-section taken along line b is the same as the drain (5b) structure of the HEMT of FIG. 7. Accordingly, the drain structure (40b, 50b) including the p-GaN drain (40b) of the island structure according to the second embodiment maintains the improvement in dynamic characteristics for hole injection, and the DC characteristics of the device in the turn-on state have an intermediate value between the characteristics of the drain structure (40b, 50b) of the first embodiment and the characteristics of the drain (5b) of the HEMT of FIG. 7. Therefore, the dynamic characteristics can be improved without deteriorating the DC characteristics in the turn-on state.

[0062] Referring to FIG. 11, in the drain structure (40b, 50b) of the semiconductor device according to the third embodiment of the present invention, the p-GaN drain (40b) includes a plurality of p-GaN drain islands formed at a predetermined interval in the length direction. In addition, the drain electrode (50b) may be formed so that a part of the gate electrode (60) side of the plurality of p-GaN drain islands is exposed and the remainder is covered. In the drain structure (40b, 50b) of the semiconductor device according to the third embodiment of FIG. 11, a cross-section taken along the c line is similar to the drain structure (4b, 5b) of the HD-GIT of FIG. 8, and a cross-section taken along the c line is similar to the drain (5b) structure of the HEMT of FIG. 7. In this way, when the p-GaN drain (40b) protrudes out of the ohmic drain region (50b) and toward the gate, the DC characteristics at a low VDS can be improved compared to C_HD-GIT, but since the drain turn-on voltage generated at the protruding portion of the p-GaN drain (40b) causes a loss in the on-resistance, at least a part of the p-GaN drain (40b) must be inserted into the ohmic drain electrode (50b).

[0063] Meanwhile, it is preferable that the length (Y) in the y-direction of the p-GaN drain island of the second and third embodiments be formed to be 0.2 μm or more. The maximum value of the length (Y) in the y-direction may be limited depending on the number of p-GaN drain islands and the length of the semiconductor device. In addition, it is preferable that the width (X) in the x-direction of the p-GaN drain island of the second and third embodiments be set to 0.2 μm or more. The maximum value of the width (X) in the x-direction may be limited depending on the width of the drain electrode (50b) and the width (LD-ext) between the boundary of the p-GaN drain (40b) and the boundary of the drain electrode (50b).

[0064] Referring to FIG. 12, in the drain structure (40b, 50b) of the semiconductor device according to the fourth embodiment of the present invention, the p-GaN drain (40b) includes a main axis portion (40b-a) in the shape of a rod extending in the longitudinal direction and a plurality of protrusions (40b-b) formed by extending from the main axis portion in the direction of the gate electrode while being spaced apart from each other by a predetermined distance in the longitudinal direction.

[0065] Next, a method for manufacturing a power semiconductor transistor including an ohmic electrode according to an embodiment of the present invention will be described. Fig. 13 is a flowchart for explaining a method for manufacturing a power semiconductor transistor including an ohmic electrode according to an embodiment of the present invention.

[0066] Referring to FIGS. 1 and 13, in step S110, a buffer layer (10), a channel layer (20), and a barrier layer (30) are sequentially formed on a substrate (1). Then, in step S120, a gallium nitride (GaN) film is deposited on the barrier layer (30). Subsequently, in step S130, the gallium nitride film is patterned to form a p-GaN gate (40a) and a p-GaN drain (40b).

[0067] Next, in step S140, a source electrode (50a) and a drain electrode (50b) are formed on the barrier layer (30), and the drain electrode (50b) is formed to cover the p-GaN drain (40b).

[0068] According to the first embodiment, the p-GaN drain (40b) can be arranged in a longitudinal bar shape at step S130, and the drain electrode (50b) can be formed to cover the entire p-GaN drain (40b) at step S140.

[0069] According to the second embodiment, a p-GaN drain (40b) including a plurality of p-GaN drain islands spaced apart at a predetermined interval in the length direction can be formed in step S130, and a drain electrode (50b) can be formed to cover the entire p-GaN drain (40b) in step S140.

[0070] According to the third embodiment, a p-GaN drain (40b) including a plurality of p-GaN drain islands spaced apart at a predetermined interval in the length direction can be formed in step S130, and a drain electrode (50b) can be formed so that a part of the gate side of the plurality of p-GaN drain islands is exposed and the remainder is covered in step S140.

[0071] In particular, it is preferable that the length (Y) in the y-direction of the p-GaN drain island of the second and third embodiments be formed to be 0.2 μm or more. The maximum value of the length (Y) in the y-direction may be limited depending on the number of p-GaN drain islands and the length of the semiconductor device. In addition, it is preferable that the width (X) in the x-direction of the p-GaN drain island of the second and third embodiments be set to be 0.2 μm or more. The maximum value of the width (X) in the x-direction may be limited depending on the width of the drain electrode (50b) and the width (LD-ext) between the boundary of the p-GaN drain (40b) and the boundary of the drain electrode (50b).

[0072] According to the fourth embodiment, a p-GaN drain (40b) is formed in step S130, which includes a main axis portion (40b-a) having a rod shape extending in the longitudinal direction, and a plurality of protrusions (40b-b) formed by extending from the main axis portion (40b-a) toward the gate electrode (60) while being spaced apart from each other by a predetermined interval in the longitudinal direction. Then, a drain electrode (50b) can be formed to cover the entire p-GaN drain (40b) in step S140.

[0073] Meanwhile, it is preferable that the width between the boundary of the p-GaN drain (40b) closest to the gate electrode (60) and the boundary of the drain electrode (50b) closest to the gate electrode (60) be formed to be 0.2 um to 1.0 um.

[0074] Next, a gate electrode (60) is formed on the p-GaN gate (40a) at step S150.

[0075] As described above, the power semiconductor transistor according to the embodiment of the present invention can maintain the advantage of improved switching characteristics by hole injection from the p-GaN drain (40b) without increasing the drain turn-on voltage and on-resistance.

[0076] While the present invention has been described using several preferred embodiments, these embodiments are illustrative and not limiting. As such, those skilled in the art will appreciate that various changes and modifications can be made in accordance with the doctrine of equivalents without departing from the spirit of the invention and the scope of the claims.

Claims

1. In power semiconductor transistors, A buffer layer, a channel layer, and a barrier layer sequentially laminated on a substrate; A source electrode formed in a predetermined area on the above barrier layer; A gate electrode formed on the barrier layer at a predetermined distance from the source electrode in the width direction; A p-GaN drain formed on the barrier layer at a predetermined interval in the width direction from the gate electrode; and A drain electrode formed to cover the p-GaN drain on the barrier layer; characterized by including Power semiconductor transistor.

2. In paragraph 1, The above p-GaN drain is Characterized by being arranged in a longitudinal bar shape Power semiconductor transistor.

3. In paragraph 1, The above p-GaN drain is characterized by including a plurality of p-GaN drain islands formed at a predetermined interval in the longitudinal direction. Power semiconductor transistor.

4. In paragraph 3, The above p-GaN drain island is The length in the y-axis direction is formed to be 0.2 um or more, It is characterized by being formed with a width of 0.2 um or more in the x-axis direction. Power semiconductor transistor.

5. In paragraph 1, The above p-GaN drain is A main shaft in the shape of a rod extending in the longitudinal direction, It is characterized by including a plurality of protrusions formed by extending from the main shaft portion toward the gate electrode while being spaced apart at a predetermined interval in the longitudinal direction. Power semiconductor transistor.

6. In paragraph 1, The width between the boundary of the p-GaN drain closest to the gate electrode and the boundary of the drain electrode closest to the gate electrode is Characterized by a size of 0.2um to 1.0um Power semiconductor transistor.

7. In power semiconductor transistors, A buffer layer, a channel layer, and a barrier layer sequentially laminated on a substrate; A source electrode formed in a predetermined area on the above barrier layer; A source electrode and a gate electrode formed on the barrier layer at a predetermined interval in the width direction from the source electrode; A p-GaN drain formed on the barrier layer at a predetermined interval in the width direction from the gate electrode; and A drain electrode formed to cover a portion of the p-GaN drain on the barrier layer; characterized by including Power semiconductor transistor.

8. In paragraph 7, The above p-GaN drain is It comprises a plurality of p-GaN drain islands formed at a predetermined interval in the longitudinal direction, The above drain electrode is characterized in that a portion of the gate side of a plurality of p-GaN drain islands is exposed and the remainder is formed to be covered. Power semiconductor transistor.

9. In paragraph 8, The above p-GaN drain island is The length in the y-axis direction is formed to be 0.2 um or more, It is characterized by being formed with a width of 0.2 um or more in the x-axis direction. Power semiconductor transistor.

10. In a method for manufacturing a power semiconductor transistor, A step of sequentially forming a buffer layer, a channel layer, and a barrier layer on a substrate; A step of depositing a gallium nitride film on the above barrier layer; A step of patterning the gallium nitride film to form a p-GaN gate and a p-GaN drain; A step of forming a source electrode and a drain electrode on the barrier layer, wherein the drain electrode is formed to cover the p-GaN drain; and A step of forming a gate electrode on the p-GaN gate; characterized by including Method for manufacturing power semiconductor transistors.

11. In paragraph 10, The step of forming the above p-GaN drain is characterized in that the p-GaN drain is arranged in a longitudinal bar shape. Method for manufacturing power semiconductor transistors.

12. In paragraph 10, The step of forming the above p-GaN drain is Characterized in that it forms a p-GaN drain including a plurality of p-GaN drain islands spaced apart at a predetermined interval in the longitudinal direction. Method for manufacturing power semiconductor transistors.

13. In paragraph 12, The above p-GaN drain island is The length in the y-axis direction is formed to be 0.2 um or more, It is characterized by being formed with a width of 0.2 um or more in the x-axis direction. Method for manufacturing power semiconductor transistors.

14. In paragraph 10, The step of forming the above p-GaN drain is A p-GaN drain is formed by including a main shaft portion in the shape of a rod extending in the longitudinal direction and a plurality of protrusions formed by extending from the main shaft portion in the direction of the gate electrode while being spaced apart from each other at a predetermined interval in the longitudinal direction. Method for manufacturing power semiconductor transistors.

15. In paragraph 10, The boundary of the p-GaN drain closest to the gate electrode and The width between the boundaries of the drain electrode closest to the gate electrode is Characterized by a size of 0.2um to 1.0um Method for manufacturing power semiconductor transistors.

16. In a method for manufacturing a power semiconductor transistor, A step of sequentially forming a buffer layer, a channel layer, and a barrier layer on a substrate; A step of depositing a gallium nitride film on the above barrier layer; A step of patterning the gallium nitride film to form a p-GaN gate and a p-GaN drain; A step of forming a source electrode and a drain electrode on the barrier layer, wherein the drain electrode is formed to cover a portion of the p-GaN drain; and A step of forming a gate electrode on the p-GaN gate; characterized by including Method for manufacturing power semiconductor transistors.

17. In paragraph 16, The step of forming the above p-GaN drain is Forming a p-GaN drain including a plurality of p-GaN drain islands spaced apart at predetermined intervals in the longitudinal direction, The step of forming the above drain electrode is Characterized in that a part of the gate side of the plurality of p-GaN drain islands is exposed and the rest is formed to be covered. Method for manufacturing power semiconductor transistors.

18. In paragraph 17, The above p-GaN drain island is The length in the y-axis direction is formed to be 0.2 um or more, It is characterized by being formed with a width of 0.2 um or more in the x-axis direction. Method for manufacturing power semiconductor transistors.

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