Array substrate and display apparatus

Abstract

An array substrate and a display apparatus provided by the present disclosure comprise a base substrate. The base substrate comprises a display area, and a binding area located at one side of the display area and used for binding a driving chip; multiple gate lines arranged along a row direction in the display region, an extension direction of the multiple gate lines being perpendicular to an extension direction of the binding region; multiple data lines arranged in the display area along a column direction, an extension direction of the multiple data lines being parallel to the extension direction of the binding area.

Description

Array substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] With technological advancements and the continuous improvement of people's living standards, the market's performance requirements for display screens are increasing, especially for high-performance products such as high resolution and high refresh rate. Resolution refers to the number of pixels a display screen can display, reflecting the precision of the screen image. The higher the resolution, the finer the display image and the better the viewing experience.

[0003] Summary of the Invention

[0004] The present disclosure provides an array substrate and a display device, the specific solutions of which are as follows:

[0005] In one aspect, an embodiment of the present disclosure provides an array substrate, comprising:

[0006] A base substrate, the base substrate comprising a display area and a binding area located on one side of the display area and used for binding a driver chip;

[0007] a plurality of gate lines, the plurality of gate lines being located in the display area, the plurality of gate lines being arranged along a row direction, and an extension direction of the plurality of gate lines being perpendicular to an extension direction of the binding area;

[0008] A plurality of data lines are located in the display area, the plurality of data lines are arranged along a column direction, and an extension direction of the plurality of data lines is parallel to an extension direction of the binding area.

[0009] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a transistor, a gate of the transistor is connected to the gate line, and the gate of the transistor extends along the row direction.

[0010] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, the base substrate further includes a first border region, a second border region, and a third border region sequentially connected around the display region, wherein the first border region is opposite to the third border region, the second border region includes the binding region, and the binding region includes a plurality of gate pads and a plurality of source and drain pads for binding a driver chip, and the plurality of source and drain pads are located on a side of the plurality of gate pads away from the first border region;

[0011] The array substrate also includes: a plurality of first routing lines and a plurality of second routing lines, wherein the plurality of first routing lines are located in the second border area, and the plurality of first routing lines are connected between the plurality of gate lines and the plurality of gate pads; the plurality of second routing lines extend from at least one of the first border area and the third border area to the second border area, and the plurality of second routing lines are connected between the plurality of data lines and the plurality of source and drain pads.

[0012] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the orthographic projection of at least part of the second trace on the base substrate overlaps with the orthographic projection of at least part of the first trace on the base substrate.

[0013] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the multiple second routings include multiple first sub-routings, the multiple first sub-routings extend from the first border area to the second border area, and the orthographic projections of the multiple first sub-routings on the base substrate overlap with the orthographic projections of the multiple first routings on the base substrate.

[0014] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the first sub-routing includes a first routing portion located in the second border area and connected to the source and drain pads, the first routing includes a second routing portion connected to the gate pad, and the orthographic projection of the first routing portion on the base substrate vertically overlaps with the orthographic projection of the second routing portion on the base substrate.

[0015] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the first routing portion is provided in the same layer as the gate line, and the second routing portion is provided in the same layer as the data line.

[0016] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the first sub-routing also includes a third routing portion extending from the first border area to the second border area, the third routing portion is connected between the data line and the first routing portion, and the first routing portion or the third routing portion is a broken line at a position adjacent to the connection between the two.

[0017] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, one of the two adjacent third routing portions is provided in the same layer as the gate line, and the other is provided in the same layer as the data line.

[0018] In some embodiments, the above-mentioned array substrate provided in the embodiments of the present disclosure further includes a gate insulation layer located between the layer where the gate line is located and the layer where the data line is located, the gate insulation layer includes multiple first vias, the third routing portion located at the layer where the data line is located is connected to the first routing portion through the first vias, and the third routing portion located at the layer where the gate line is located is integrated with the first routing portion.

[0019] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the first routing portion further includes a fourth routing portion connected to the data line, and a fifth routing portion connected between the fourth routing portion and the second routing portion, wherein the fourth routing portion extends obliquely from the gate line and then extends along the column direction to the fifth routing portion, and the fifth routing portion is arranged obliquely relative to the column direction.

[0020] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the fourth routing portion is integrally provided with the gate line, and the fifth routing portion is integrally provided with the second routing portion.

[0021] In some embodiments, the above-mentioned array substrate provided in the embodiments of the present disclosure further includes a gate insulation layer located between the layer where the gate line is located and the layer where the data line is located, the gate insulation layer includes at least one row of second vias in the row direction, and the fourth routing portion and the fifth routing portion are connected through the first vias.

[0022] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the multiple second routings further include multiple second sub-routes, and the multiple second sub-routes extend from the third border area to the second border area, and the orthographic projections of the multiple second sub-routes on the base substrate do not overlap with the orthographic projections of the multiple first routings on the base substrate.

[0023] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the second sub-routing includes a sixth routing portion located in the second border area, the sixth routing portion extends along the row direction and then connects to the source and drain pads along the column direction, and the sixth routing portion is arranged on the same layer as the gate line.

[0024] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the second sub-routing also includes a seventh routing portion in the second border area, the seventh routing portion extends along the column direction and is connected to the sixth routing portion, and the seventh routing portion is arranged on the same layer as the data line.

[0025] In some embodiments, the above-mentioned array substrate provided in the embodiments of the present disclosure further includes a gate insulation layer located between the layer where the gate line is located and the layer where the data line is located, the gate insulation layer includes at least one row of third vias in the first direction, the sixth routing portion and the seventh routing portion are connected through the third vias, and the first direction is respectively arranged to cross the row direction and the column direction.

[0026] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the second sub-routing also includes an eighth routing portion extending from the third border area to the second border area, and the eighth routing portion is connected between the data line and the seventh routing portion, wherein one of the two adjacent eighth routing portions is arranged on the same layer as the gate line, and the other is arranged on the same layer as the data line.

[0027] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a first transfer structure provided on the same layer as the gate line, and the seventh routing portion is connected to the eighth routing portion through the first transfer structure.

[0028] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a second transfer structure provided on the same layer as the data line, and the eighth routing portion located on the layer where the gate line is located is connected to the first transfer structure through the second transfer structure.

[0029] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a gate insulating layer located between the layer where the gate lines are located and the layer where the data lines are located, the gate insulating layer including at least one row of fourth via holes in the row direction and at least one row of fifth via holes in the row direction;

[0030] The seventh routing portion is connected to the first adapter structure through the fourth via, and the eighth routing portion is connected to the second adapter structure through the fifth via.

[0031] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the eighth routing portion located at the layer where the data line is located and the seventh routing portion connected thereto are integrally provided.

[0032] On the other hand, an embodiment of the present disclosure provides a display device, including the above-mentioned array substrate provided by an embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] FIG1 is a schematic structural diagram of an array substrate provided in an embodiment of the present disclosure;

[0034] FIG2 is a schematic structural diagram of a sub-pixel in FIG1 ;

[0035] FIG3 is a schematic structural diagram of an array substrate in the related art;

[0036] FIG4 is a schematic structural diagram of a sub-pixel in FIG3 ;

[0037] FIG5 is an enlarged view of area B in FIG3 ;

[0038] FIG6 is an enlarged view of area A in FIG1 ;

[0039] FIG7 is an enlarged view of area C in FIG6 ;

[0040] FIG8 is an enlarged view of area D in FIG7 ;

[0041] FIG9 is a picture of the first routing portion and the second routing portion;

[0042] FIG10 is an enlarged view of area E in FIG6 ;

[0043] FIG11 is a cross-sectional view along line aa' in FIG10;

[0044] FIG12 is an enlarged view of the F area in FIG6 ;

[0045] FIG13 is an enlarged view of the H region in FIG6 ;

[0046] FIG14 is an enlarged view of area I in FIG13 ;

[0047] FIG15 is another enlarged view of area I in FIG13 ;

[0048] FIG16 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure;

[0049] Icons: 101-substrate; AA-display area; BB1-first frame area; BB2-second frame area; BB3-third frame area; 102-gate line; 103-first routing line; 301-second routing line; 302-fourth routing line; 303-fifth routing line; 104-data line; 105-second routing line; 1051-first sub-routing line; 511-first routing line; 512-third routing line; 1052-second sub-routing line; 521-sixth routing line; 522-seventh routing line; 523-eighth routing line; 10 6-gate insulation layer; h1-first via; h2-second via; h3-third via; h4-fourth via; h5-fifth via; 107-first transfer structure; 108-second transfer structure; 109-transistor; g-gate; s-first electrode; d-second electrode; 110-passivation layer; G-gate pad; G'-gate channel; SD-source-drain pad; SD'-source-drain channel; IC-driver chip. DETAILED DESCRIPTION

[0050] To further clarify the objectives, technical solutions, and advantages of the embodiments of the present disclosure, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below in conjunction with the accompanying drawings of the embodiments of the present disclosure. It should be noted that in the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In this disclosure, exemplary embodiments are described with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes shown in the drawings are to be expected, for example, as a result of manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shapes of the regions shown in this disclosure, but rather include deviations in shape resulting from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features; a sharp angle illustrated may be rounded, etc. Therefore, the regions shown in the drawings are schematic in nature, and their sizes and shapes are not intended to illustrate the precise shapes of the regions or reflect true scale, but are intended solely to illustrate the present disclosure. Throughout, identical or similar reference numerals denote identical or similar elements or elements having identical or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0051] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar terms used in the present disclosure and the claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0052] In the following description, when an element or layer is referred to as being “on” or “connected to” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as being “disposed on one side of” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as being “directly on” or “directly connected to” another element or layer, there are no intermediate elements or intermediate layers. The term “and / or” includes any and all combinations of one or more of the associated listed items.

[0053] Related display products include multiple pixels arranged in an array. Each pixel can have three sub-pixels. Each column of sub-pixels is connected to a data line, and each row of sub-pixels is connected to a gate line. That is, in related display products, multiple gate lines extend along the row direction and are arranged along the column direction, and multiple data lines extend along the column direction and are arranged along the row direction. For a display product with a resolution of M*N, it has 3M data lines and N gate lines. One data line is connected to a source-drain channel of a driver IC, and one gate line is connected to a gate channel of the driver IC. Therefore, due to the high resolution in both the row and column directions, the gate and source-drain channels provided by the driver IC may not meet the requirements of high-resolution products. In some cases, it is necessary to redevelop a suitable driver IC to meet the requirements of high-resolution products, which significantly increases costs. In addition, pixels are charged row by row, and the charging time for each row per frame is 1 / the total number of gate lines / the refresh rate. When the refresh rate is high, the charging time per frame is shortened, which may lead to insufficient charging time and poor display.

[0054] In order to solve the above technical problems existing in the related art, an embodiment of the present disclosure provides an array substrate, as shown in FIG1 and FIG2 , comprising:

[0055] The base substrate 101, optionally, the base substrate 101 is a substrate that allows visible light to pass through, for example, glass, quartz, plastic and the like; in some embodiments, the base substrate 101 includes a display area AA, and a first frame area BB1, a second frame area BB2 and a third frame area BB3 connected in sequence around the display area AA, wherein the first frame area BB1 and the third frame area BB3 are opposite to each other, the second frame area BB2 includes a binding area BD, the binding area BD includes a plurality of gate pads G and a plurality of source and drain pads SD for binding the driver chip IC, and the plurality of source and drain pads SD are located on a side of the plurality of gate pads G away from the first frame area BB1; optionally, the gate pads G and the source and drain pads SD are arranged on the same layer as the pixel electrode or the common electrode, and the layer where the pixel electrode or the common electrode is located is the conductive layer in the array substrate that is farthest away from the base substrate 101, and the material of the pixel electrode or the common electrode includes transparent conductive materials such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0056] Multiple gate lines 102 are located in the display area AA, and the extension direction of the multiple gate lines 102 is perpendicular to the extension direction of the binding area BD. For example, the multiple gate lines 102 extend along the column direction Y and are arranged along the row direction X. Optionally, the material of the gate lines 102 includes a metal material, which can be a single-layer or multi-layer structure formed of molybdenum, aluminum, titanium, copper, alloy, etc. Exemplarily, the gate lines 102 are a single-layer structure composed of a molybdenum metal layer.

[0057] Multiple first traces 103 are located in the second border area BB1, and multiple first traces 103 are connected between multiple gate lines 102 and multiple gate pads G; optionally, the material of the first traces 103 includes metal material, which can be a single-layer or multi-layer structure formed by molybdenum, aluminum, titanium, copper, alloy, etc.

[0058] Multiple data lines 104 are located in the display area AA, and the extension direction of the multiple data lines 104 is parallel to the extension direction of the binding area BD. For example, the multiple data lines 104 extend along the row direction X and are arranged along the column direction Y. Optionally, the material of the data lines 104 includes a metal material, having a single-layer or multi-layer structure formed of molybdenum, aluminum, titanium, copper, alloy, etc. Exemplarily, the data lines 104 are a stacked structure consisting of a titanium metal layer / an aluminum metal layer / aluminum metal layer.

[0059] Multiple second traces 105 extend from at least one of the first border area BB1 and the third border area BB3 to the second border area BB2, and the multiple second traces 105 are connected between the multiple data lines 102 and the multiple source and drain pads SD; optionally, the material of the first trace 103 includes a metal material, which can be a single-layer or multi-layer structure formed of molybdenum, aluminum, titanium, copper, alloy, etc.

[0060] Multiple sub-pixels px are located in an area defined by multiple gate lines 102 and multiple data lines 103. The sub-pixels px include an opening area O and a non-opening area UO, and the opening area O, the gate line 102, and the data line 103 are jointly arranged around the non-opening area UO. The size l of the non-opening area UO in the row direction X is greater than the size w of the non-opening area UO in the column direction Y.

[0061] As shown in FIG3 , a display product with an M*N resolution in the related art has N gate lines 102 extending in the row direction X and arranged in the column direction Y, 3M data lines 104 extending in the column direction Y and arranged in the row direction X, the N gate lines 102 connected to N gate pads G, and the 3M data lines 104 connected to 3M source and drain pads SD, with the N gate pads G located to the left and right of the 3M source and drain pads. The driver chip IC requires 3M source and drain channels SD' connected to the 3M source and drain pads SD, and N gate channels G' connected to the N gate pads G, with the N gate channels G' located to the left and right of the 3M source and drain channels SD'. FIG4 is a schematic structural diagram of a subpixel px in FIG3 . As can be seen from FIG4 , the dimension w' of the non-opening area UO of the subpixel px in the row direction X is smaller than the dimension l' of the non-opening area UO in the column direction Y. By comparison, it can be seen that the sub-pixel px shown in FIG4 is equivalent to the sub-pixel px shown in FIG2 provided by the present disclosure being flipped.

[0062] In the above-mentioned array substrate provided by the present disclosure, as shown in FIG1 , if the resolution is also M*N, then there are 3M gate lines 102 extending along the column direction Y and arranged along the row direction X, and there are N data lines 104 extending along the row direction X and arranged along the column direction Y. The N data lines 104 are connected to N source and drain pads SD through N second traces 105, and the 3M gate lines 102 are connected to 3M gate pads G through 3M first traces 103. The 3M gate pads G are located on a single side of the source and drain pads SD (i.e., compared to the related art, the gate pads G on the other side of the source and drain pads SD are idle). Accordingly, the gate channels G' required for the driver chip IC are 3M and the source and drain channels SD' are N, which is equivalent to flipping the number of channels of the driver chip IC required for the same resolution display product. In this way, high-resolution display products can be adapted to driver chip ICs with low channel counts, reducing costs.

[0063] For example, a display product with a resolution of 400*800 requires 1200 source-drain channels SD' and 800 gate channels G', but the relevant driver chip IC can only provide 900 source-drain channels SD' and 1200 gate channels G', so the display product cannot use this driver chip IC. However, in the present disclosure, the gate lines 102 in the row direction X and the data lines 104 in the column direction Y are flipped, so that the gate lines 102 extend along the column direction Y and the data lines 104 extend along the row direction X. At this time, the number of source-drain channels SD' required becomes 800, and the number of gate channels G' becomes 400*3=1200. In this way, the driver chip IC that was previously unable to match can now match, eliminating the need to develop a new driver chip IC, thereby reducing costs.

[0064] On the other hand, pixels are charged row by row, and the charging time for each row in each frame is 1 / total number of gate lines / refresh rate. When the refresh rate is high, the charging time for each frame will be shortened, which may lead to insufficient charging time and poor display. The present disclosure increases the charging time and improves poor display by arranging the gate lines 102 extending along the column direction Y and arranged along the row direction X, and the data lines 104 extending along the row direction X and arranged along the column direction Y.

[0065] For example, for a display product with a resolution of 300*1600, the charging time of each row in the related solution is 1 / 1600 / 60=10.4 (μs); in the present disclosure, the gate line 102 extends along the column direction Y and the data line 104 extends along the row direction X, so the charging is changed from turning on the gate line 102 for each row to turning on the gate line 102 for each column, and the charging time of each row is 1 / 300*3 / 60=18.5 (μs). Compared with the related art, the charging time of the present disclosure is increased by about 78%, thereby ensuring the charging effect and improving the display quality.

[0066] From the above, it can be seen that in the related art shown in Figures 3 and 4, the gate line 102 extends along the row direction X and is arranged along the column direction Y, the data line 104 extends along the column direction Y and is arranged along the row direction X, the size w' of the non-opening area UO of the sub-pixel px in the row direction X is smaller than the size l' of the non-opening area UO in the column direction Y, and when charging the sub-pixel, a voltage is applied to the gate line 102 row by row, and then the data line 104 applies a voltage to charge the sub-pixel px. In the technical solution of the present disclosure shown in Figures 1 and 2, the gate line 102 extends along the column direction Y and is arranged along the row direction X, the data line 104 extends along the row direction X and is arranged along the column direction Y, the size l of the non-opening area UO of the sub-pixel px in the row direction X is larger than the size w of the non-opening area UO in the column direction Y, and when charging the sub-pixel px, a voltage is applied to the gate line 102 column by column, and then the data line 104 applies a voltage to charge the sub-pixel px. The present disclosure flips the gate line 102 , the data line 104 , and the sub-pixel px in the above manner, which has the advantages of reducing the required channels of the driver chip IC and increasing the charging time.

[0067] Fig. 5 shows the wiring schematic diagram that gate line 102 and data line 104 are connected to driver chip IC after extending from display area AA to frame area respectively in the relevant art.As shown in Figures 3 and 5, because the source-drain electrode channel SD' of driver chip IC is generally arranged in the middle thereof, gate channel G' is generally arranged on both sides of driver chip IC, so the data line 104 extending along column direction Y in the relevant display product can be connected to the middle of driver chip IC, and gate line 102 is connected to both sides of driver chip IC, and is without crossing line.But in the present disclosure, as shown in Figures 1 and 6, the gate line 102 extending along column direction Y needs to be connected to the gate channel G' on the left side of driver chip IC by first routing line 103, and the data line 104 extending along row direction X needs to be connected to the source-drain electrode channel SD' in the middle of driver chip IC by second routing line 105, so that first routing line 103 and second routing line 105 just need crossing line to be connected to the corresponding channel of driver chip IC. Based on this, in the array substrate provided in the embodiment of the present disclosure, as shown in FIG6 , the orthographic projection of at least part of the second trace 105 on the base substrate 101 overlaps with the orthographic projection of at least part of the first trace 103 on the base substrate 101 .

[0068] It should be noted that similar channels (e.g., gate channel G' or source-drain channel SD') of a driver chip IC are generally numbered sequentially from left to right. In actual use, the gate line 102 is sequentially connected to the subsequent gate channels G' starting from the gate line channel numbered 1. If the total number of gate lines 102 is less than the total number of gate line channels, the subsequent gate channels G' not connected to the gate lines 102 can be black-inserted. Therefore, the gate line 102 in the present disclosure is only connected to the left gate channel G' of the gate chip IC, and the right gate channel G' can be black-inserted.

[0069] In some embodiments, in order to reduce single-sided wiring and achieve a narrow frame effect, as shown in Figures 1 and 6, the present disclosure disperses multiple second traces 105 in the first frame area BB1 and the third frame area BB3, so that the data line 104 is connected to the source-drain channel SD' in the middle of the driver chip IC through the first frame area BB1 and the third frame area BB3 on the left and right sides. In this way, there will be a cross-line between the second trace 105 led out from the first frame area BB1 on the left and the first trace 103 used to connect the gate line 102 and the driver chip IC, and there will be no cross-line between the second trace 105 led out from the third frame area BB3 on the right and the first trace 103 used to connect the gate line 102 and the driver chip IC.

[0070] Therefore, in the above-mentioned array substrate provided in the embodiment of the present disclosure, as shown in Figure 6, the multiple second routing lines 105 may include multiple first sub-routes 1051, the multiple first sub-routes 1051 extend from the first border area BB1 to the second border area BB2, and the orthographic projections of the multiple first sub-routes 1051 on the base substrate 101 overlap with the orthographic projections of the multiple first routing lines 103 on the base substrate 101, that is, there are cross-lines between the first sub-routes 1051 and the first routing lines 103; optionally, the multiple second routing lines 105 also include multiple second sub-routes 1052, the multiple second sub-routes 1052 extend from the third border area BB3 on the right to the second border area BB2 on the lower side, and the orthographic projections of the multiple second sub-routes 1052 on the base substrate 101 do not overlap with the orthographic projections of the multiple first routing lines 103 on the base substrate 101.

[0071] However, there will be a problem with cross-line, that is, when different lines overlap, there will be overlapping capacitance, and the existence of overlapping capacitance will cause mutual interference between different signals. The principle is as follows: when two lines overlap, an overlapping capacitance will be generated, and charge will be stored between the capacitors. The formula is Q=CU. When the voltage at one end of the capacitor changes, because the charge is unchanged at that moment, the voltage on the other side will be disturbed as the voltage on one side changes. Therefore, in order to ensure that the disturbance between each line is similar, the present disclosure needs to perform special processing on the overlapping lines. Optionally, the present disclosure designs the overlapping lines to overlap vertically.

[0072] Specifically, as shown in Figures 7 to 9, the first sub-trace 1051 includes a first trace portion 511 located in the second border area BB2 and connected to the driver chip IC. The first trace 103 includes a second trace portion 301 connected to the driver chip IC. The orthographic projection of the first trace portion 511 on the substrate 101 and the orthographic projection of the second trace portion 301 on the substrate 101 vertically overlap. This design can avoid the appearance of diagonal traces at the overlap, as the appearance of diagonal traces will cause the overlap area to change, resulting in different disturbances caused by signal changes, and thus causing sudden changes in capacitance.

[0073] It should be noted that in the embodiments provided in the present disclosure, due to the limitations of process conditions or the influence of other factors such as measurement, the above-mentioned "vertical" may be exactly vertical, or there may be some deviations (for example, ±5°). Therefore, as long as the "vertical" relationship between the above-mentioned features meets the error allowance, it falls within the scope of protection of the present disclosure.

[0074] In some embodiments, in the above-mentioned array substrate provided in the embodiment of the present disclosure, the first routing portion 511 can be arranged in the same layer as the gate line 102, and the second routing portion 301 can be arranged in the same layer as the data line 104. In the present disclosure, "the same layer" refers to a layer structure formed by a single patterning process using the same film-forming process to form a film layer for making a specific pattern, and then using the same mask. That is, a single patterning process corresponds to a mask (also called a photomask). Depending on the specific pattern, a single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may be at the same height or have the same thickness, or may be at different heights or have different thicknesses. Therefore, the present disclosure can avoid adding an additional film layer by arranging the first routing portion 511 and the gate line 102 in the same layer, and the second routing portion 301 and the data line 104 in the same layer, which is conducive to a lightweight design.

[0075] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, as shown in Figures 6 and 10, the first sub-routing 501 also includes a third routing portion 512 extending from the first border area BB1 to the second border area BB2, and the third routing portion 512 is connected between the data line 104 and the first routing portion 511. The first routing portion 511 or the third routing portion 512 is a broken line at a connection position adjacent to the two, so that within the second border BB2, the first routing portion 511 can avoid the binding area for binding the driver chip IC.

[0076] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, one of the two adjacent third routing portions 512 is disposed on the same layer as the gate line 102, and the other is disposed on the same layer as the data line 104. In other words, the third routing portion 512 is alternately routed on the layer where the gate line 102 and the layer where the data line 104 reside. Compared to a technical solution in which the third routing portion 512 is routed only on the layer where the gate line 102 or the data line 104 reside, by arranging the third routing portion 512 in a manner that alternates routing on the layer where the gate line 102 and the layer where the data line 104 reside, the number of single-layer routings on the layer where the gate line 102 and the layer where the data line 104 reside is relatively small, and accordingly, the required routing space is small, which is conducive to a narrow bezel design. Furthermore, arranging the third routing portion 512 on the same layer as the gate line 102 and the data line 104 can also avoid the need for additional film layers, which is conducive to a lightweight and thin design.

[0077] In some embodiments, the array substrate provided in the embodiments of the present disclosure, as shown in Figures 10 and 11, may further include a gate insulating layer 106 located between the layer where the gate line 102 is located and the layer where the data line 104 is located. The gate insulating layer 106 includes a plurality of first via holes h1. The third routing portion 512 located in the layer where the data line 104 is located is connected to the first routing portion 511 through the first via holes h1. The third routing portion 512 located in the layer where the gate line 102 is located is integrally provided with the first routing portion 511. Optionally, the material of the gate insulating layer 106 may be at least one of inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0078] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in Figures 6 and 12 , the first routing line 103 may further include a fourth routing portion 302 connected to the gate line 102, and a fifth routing portion 303 connected between the fourth routing portion 302 and the second routing portion 301. The fourth routing portion 302 extends obliquely from the gate line 102 and then extends along the column direction Y to the fifth routing portion 303. The fifth routing portion 303 is arranged obliquely relative to the column direction Y to facilitate connecting the gate line 102 to the driver chip IC via the fourth routing portion 302, the fifth routing portion 303, and the second routing portion 301 in sequence. Furthermore, this routing method of the first routing lines 103 can ensure that adjacent first routing lines 103 are compact and prevent short circuits.

[0079] In some embodiments, the fourth routing portion 302 can be integrally provided with the gate line 102, the fifth routing portion 303 can be integrally provided with the second routing portion 301, and the fourth routing portion 302 and the fifth routing portion 303 can be connected via a second via h2 penetrating the gate insulating layer 106. Optionally, the plurality of second via holes h2 form at least one row in the row direction X.

[0080] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, as shown in Figures 6, 13 and 14, the second sub-route 1052 may include a sixth routing portion 521 located in the second border area BB2, and the sixth routing portion 521 extends along the row direction X and then connects to the gate pad G (equivalent to the driver chip IC) along the column direction Y, making the wiring simpler. Optionally, the sixth routing portion 521 is on the same layer as the gate line 102. In this way, the second sub-route 1052 drawn from the right side of the data line 105 can be connected to the gate pad G through the sixth routing portion 521 of the layer where the gate line 102 is located; and in the present disclosure, the first sub-route 1051 drawn from the left side of the data line 105 is connected to the gate pad G through the first routing portion 511 of the layer where the gate line 102 is located, thereby facilitating the use of the same connection method to achieve the connection between the first routing portion 511 and the gate pad G, and the connection between the sixth routing portion 521 and the gate pad G.

[0081] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, as shown in Figures 6, 13 and 14, the second sub-routing 1052 may also include a seventh routing portion 522 in the second border area BB2. In order to ensure that the wiring is neat and not messy, the seventh routing portion 522 may be provided to extend along the column direction Y and be connected to the sixth routing portion 521. Optionally, the seventh routing portion 522 is provided in the same layer as the data line 104. The second sub-routing 1052 extends from the third border area BB3 to the second border area BB2 and is connected to the driver chip IC. If the second sub-routing 1052 is single-layered, the wiring of the second sub-routing 1052 will be longer, and static electricity will easily accumulate. Excessive static electricity may cause adjacent second sub-routing 1052 to short-circuit. The present disclosure provides a second sub-routing 1052 including a sixth routing portion 521 on the same layer as the gate line 102 and a seventh routing portion 522 on the same layer as the data line 104, so that the length of the second sub-routing 1052 in a single-layer continuous wiring can be shortened, which is beneficial to reducing static electricity accumulation and avoiding short circuiting of adjacent second sub-routings 1052.

[0082] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, as shown in Figure 14, the sixth routing portion 521 of the layer where the gate line 102 is located and the seventh routing portion 522 of the layer where the data line 104 is located can be connected through a third via h3 that penetrates the gate insulation layer 106. Optionally, in order to facilitate the layer-changing connection between the sixth routing portion 521 and the seventh routing portion 522, the third via h3 can be set to form at least one row along the first direction Z, and the first direction Z is respectively cross-arranged with the row direction X and the column direction Y.

[0083] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIG6 , FIG13 , and FIG14 , the second sub-routing 1052 may further include an eighth routing portion 523 extending from the third border area BB3 to the second border area BB2, the eighth routing portion 523 being connected between the data line 104 and the seventh routing portion 522, wherein one of two adjacent eighth routing portions 523 is disposed on the same layer as the gate line 102, and the other is disposed on the same layer as the data line 104. Compared to a technical solution in which the eighth routing portion 523 is only wired on the layer where the gate line 102 or the data line 104 is located, by arranging the eighth routing portion 523 in a manner of alternating wiring on the layer where the gate line 102 is located and the layer where the data line 104 is located, the number of single-layer wiring on the layer where the gate line 102 and the layer where the data line 104 are located is ensured to be relatively small, and accordingly, the required wiring space is small, which is conducive to a narrow border design. Furthermore, placing the eighth routing portion 523 on the same layer as the gate line 102 and the data line 104 can avoid the need for an additional film layer, thereby facilitating a lightweight and thin design. Furthermore, since the seventh routing portion 522 connected to the eighth routing portion 523 can be located on the same layer as the data line 104, if one of two adjacent eighth routing portions 523 is placed on the same layer as the gate line 102 and the other is placed on the same layer as the data line 104, at least one of the adjacent second sub-routes 1052 can be prevented from being routed continuously and excessively long within a single layer, thereby mitigating the effects of static electricity.

[0084] In some embodiments, in the above-mentioned array substrate provided by the embodiment of the present disclosure, as shown in FIG14 , a first adapter structure 107 may also be included that is provided on the same layer as the gate line 102, and the seventh routing portion 522 is connected to the eighth routing portion 523 through the first adapter structure 107. In this way, regardless of whether the eighth routing portion 523 is located on the layer where the gate line 102 is located or on the layer where the data line 103 is located, due to the presence of the first adapter structure 107 on the same layer as the gate line 102, it will not be provided as a whole with the seventh routing portion 522 located on the layer where the data line 103 is located, thereby ensuring that the length of the second sub-routing 1052 continuously wired in a single layer is short, which is beneficial to reducing static electricity accumulation and avoiding short circuits between adjacent second sub-routing 1052. Of course, in some embodiments, as shown in FIG15 , the eighth routing portion 523 located on the layer where the data line 104 is located may also be provided as a whole with the seventh routing portion 522 connected thereto, which is not limited here.

[0085] In some embodiments, the array substrate provided in the embodiments of the present disclosure, as shown in FIG14 , may further include a second transfer structure 108 disposed on the same layer as the data line 104. The eighth routing portion 523 located on the layer where the gate line 102 resides is connected to the first transfer structure 107 via the second transfer structure 108. This prevents the eighth routing portion 523 and the first transfer structure 107 from being disposed consecutively on the layer where the gate line 102 resides, thereby reducing static electricity accumulation and the probability of shorting adjacent second sub-routes 1052. Further referring to FIG14 , it can be seen that in some embodiments, the seventh routing portion 522 may be connected to the first transfer structure 107 via a fourth via h4 penetrating the gate insulating layer 106, and the eighth routing portion 523 may be connected to the second transfer structure 108 via a fifth via h5 penetrating the gate insulating layer 106. Optionally, the fourth via holes h4 form at least one row in the row direction X, and the fifth via holes h5 form at least one row in the row direction X. The row of the fourth via holes h4 and the row of the fifth via holes h5 can be arranged side by side in the second direction Y.

[0086] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIG2 , a sub-pixel px may include a transistor 109 and a pixel electrode 110, wherein a gate electrode g of the transistor 109 is connected to the gate line 102, a first electrode s of the transistor 109 is connected to the data line 104, and a second electrode d of the transistor 109 is connected to the pixel electrode 110. Unlike the related art shown in FIG4 , in which the gate electrode g of the transistor 109 extends in the column direction Y and the first electrode s and the second electrode d of the transistor 109 are arranged side by side in the row direction X, in the present disclosure, the transistor 109 is also flipped to accommodate the gate line 102 and the data line 104 after the extension direction is flipped. As shown in FIG2 , in the present disclosure, the gate electrode g of the transistor 109 extends in the row direction X, and the first electrode s and the second electrode d of the transistor 109 are arranged side by side in the column direction Y.

[0087] In some embodiments, transistor 109 may be a dual-gate transistor to reduce leakage current. Of course, in other embodiments, transistor 109 may also be a single-gate transistor, such as a bottom-gate transistor or a top-gate transistor. Optionally, transistor 109 may be a P-type transistor or an N-type transistor. The first electrode s of transistor 109 may be a source electrode, and the second electrode d may be a drain electrode, or the first electrode s of transistor 109 may be a drain electrode, and the second electrode d may be a source electrode, which is not limited here. The material of the active layer of transistor 109 may be amorphous silicon (a-Si), polycrystalline silicon (poly), oxide (Oxide, such as indium gallium zinc oxide IGZO), etc.

[0088] In some embodiments, as shown in FIG11 , the layer where the gate line 102 is located may be located on a side of the layer where the data line 103 is located away from the base substrate 101, and the array substrate provided in the embodiment of the present disclosure may further include a passivation layer 111 covering the layer where the data line 103 is located. Other essential components of the array substrate are well understood by those skilled in the art and are not described in detail here, nor should they be construed as limiting the present disclosure.

[0089] Based on the same inventive concept, an embodiment of the present disclosure provides a display device, as shown in FIG16 , comprising the array substrate 001 provided in the embodiment of the present disclosure. Because the principles for solving the problems solved by the display device are similar to those solved by the array substrate, the implementation of the display device can refer to the embodiments of the array substrate, and any repetitions will not be repeated.

[0090] Optionally, as shown in FIG16 , the display device provided in the embodiment of the present disclosure may further include an opposing substrate 002 disposed opposite the array substrate 001, and a liquid crystal layer 003 located between the array substrate 001 and the opposing substrate 002. A black matrix BM and a plurality of red color resists R, green color resists G, and blue color resists B separated by the black matrix BM may be provided on the side of the opposing substrate 002 facing the liquid crystal layer 003. A first polarizer may be provided on the side of the opposing substrate 002 facing away from the liquid crystal layer 003, and a second polarizer may be provided on the side of the array substrate 001 facing away from the liquid crystal layer 003. The polarization directions of the first polarizer and the second polarizer are perpendicular to each other.

[0091] In some embodiments, in the above-mentioned display device provided by the embodiment of the present disclosure, as shown in FIG16 , it may further include a backlight module 004 located on the light incident side of the array substrate 001, and the backlight module 004 may be a direct-type backlight module or an edge-entry backlight module. Optionally, the edge-entry backlight module may include a light bar, a reflective sheet arranged in a stacked manner, a light guide plate, a diffuser, a prism group, etc., and the light bar is located on one side of the thickness direction of the light guide plate. The direct-type backlight module may include a matrix light source, a reflective sheet, a diffuser, and a brightening film stacked on the light emitting side of the matrix light source, etc., and the reflective sheet includes an opening arranged directly opposite to the position of each lamp bead in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source may be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED, etc.).

[0092] Submillimeter or even micron-scale micro-LEDs are self-luminous devices, just like organic light-emitting diodes (OLEDs). Like organic light-emitting diodes, they have a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. And because inorganic light-emitting diodes emit light based on metal semiconductors with more stable properties and lower resistance, they have the advantages of lower power consumption, greater resistance to high and low temperatures, and longer service life compared to organic light-emitting diodes that emit light based on organic matter. And when micro-LEDs are used as backlight sources, more precise dynamic backlight effects can be achieved. While effectively improving screen brightness and contrast, they can also solve the glare phenomenon caused by traditional dynamic backlighting between bright and dark areas of the screen, thereby optimizing the visual experience.

[0093] In some embodiments, the above-mentioned display device provided in the embodiments of the present disclosure may be: a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or any other product or component with a display function. Optionally, the display device provided in the present disclosure includes, but is not limited to, components such as a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip. Optionally, the control chip is a central processing unit, a digital signal processor, a system-on-chip (SoC), etc. For example, the control chip may further include a memory, a power module, etc., and realize power supply and signal input and output functions through additionally provided wires, signal lines, etc. For example, the control chip may further include hardware circuits and computer executable code, etc. The hardware circuit may include conventional very large scale integration (VLSI) circuits or gate arrays and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field programmable gate arrays, programmable array logic, programmable logic devices, etc. In addition, those skilled in the art will understand that the above structure does not constitute a limitation on the above display device provided in the embodiment of the present disclosure. In other words, the above display device provided in the embodiment of the present disclosure may include more or fewer of the above components, or a combination of certain components, or different component arrangements.

[0094] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0095] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. An array substrate, wherein, comprising: a substrate, the substrate including a display area and a bonding area located on one side of the display area for bonding a driving chip; a plurality of gate lines, the plurality of gate lines being located in the display area, the plurality of gate lines being arranged in a row direction, and an extending direction of the plurality of gate lines being perpendicular to an extending direction of the bonding area; a plurality of data lines, the plurality of data lines being located in the display area, the plurality of data lines being arranged in a column direction, and an extending direction of the plurality of data lines being parallel to an extending direction of the bonding area.

2. The array substrate according to claim 1, wherein, further comprising a transistor, a gate of the transistor being connected to the gate line, and the gate of the transistor extending in a row direction.

3. The array substrate according to claim 1 or 2, wherein, the substrate further includes a first border area, a second border area, and a third border area that are sequentially connected around the display area, wherein the first border area and the third border area are opposite to each other, the second border area includes the bonding area, the bonding area includes a plurality of gate pads and a plurality of source / drain pads for bonding a driving chip, and the plurality of source / drain pads are located on a side of the plurality of gate pads away from the first border area; the array substrate further includes: a plurality of first traces and a plurality of second traces, wherein the plurality of first traces are located in the second border area, and the plurality of first traces are connected between the plurality of gate lines and the plurality of gate pads; the plurality of second traces extend from at least one of the first border area and the third border area to the second border area, and the plurality of second traces are connected between the plurality of data lines and the plurality of source / drain pads.

4. The array substrate according to claim 3, wherein, a positive projection of at least a part of the second trace on the substrate overlaps with a positive projection of at least a part of the first trace on the substrate.

5. The array substrate according to claim 4, wherein, the plurality of second traces include a plurality of first sub-traces, the plurality of first sub-traces extend from the first border area to the second border area, and a positive projection of the plurality of first sub-traces on the substrate overlaps with a positive projection of the plurality of first traces on the substrate.

6. The array substrate according to claim 5, wherein, the first sub-trace includes a first trace portion located in the second border area and connected to the source / drain pad, the first trace includes a second trace portion connected to the gate pad, and a positive projection of the first trace portion on the substrate perpendicularly overlaps with a positive projection of the second trace portion on the substrate.

7. The array substrate according to claim 6, wherein, the first trace portion and the gate line are disposed on the same layer, and the second trace portion and the data line are disposed on the same layer.

8. The array substrate according to claim 6 or 7, wherein, The first sub-wire further includes a third wire portion extending from the first border area to the second border area, the third wire portion being connected between the data line and the first wire portion, and the first wire portion or the third wire portion being a broken line at a position adjacent to their connection position.

9. The array substrate according to claim 8, wherein, one of two adjacent third wire portions is disposed on the same layer as the gate line, and the other is disposed on the same layer as the data line.

10. The array substrate according to claim 9, wherein, it further includes a gate insulating layer located between the layer where the gate line is located and the layer where the data line is located, the gate insulating layer including a plurality of first vias; the third wire portion located on the layer where the data line is located is connected to the first wire portion through the first via, and the third wire portion located on the layer where the gate line is located is integrally provided with the first wire portion.

11. The array substrate according to any one of claims 6 to 10, wherein, the first wire further includes a fourth wire portion connected to the gate line, and a fifth wire portion connected between the fourth wire portion and the second wire portion, wherein the fourth wire portion extends obliquely from the gate line and then extends in the column direction to the fifth wire portion, and the fifth wire portion is disposed obliquely with respect to the column direction.

12. The array substrate according to claim 11, wherein, the fourth wire portion is integrally provided with the gate line, and the fifth wire portion is integrally provided with the second wire portion.

13. The array substrate according to claim 12, wherein, it further includes a gate insulating layer located between the layer where the gate line is located and the layer where the data line is located, the gate insulating layer including at least one row of second vias in the row direction, and the fourth wire portion is connected to the fifth wire portion through the second vias.

14. The array substrate according to any one of claims 1 to 13, wherein, the plurality of second wires further includes a plurality of second sub-wires, the plurality of second sub-wires extending from the third border area to the second border area, and the orthographic projections of the plurality of second sub-wires on the substrate do not overlap with the orthographic projections of the plurality of first wires on the substrate.

15. The array substrate according to claim 14, wherein, the second sub-wire includes a sixth wire portion located in the second border area, the sixth wire portion extending in the row direction and then connecting to the source-drain pad in the column direction, and the sixth wire portion is disposed on the same layer as the gate line.

16. The array substrate according to claim 15, wherein, the second sub-wire further includes a seventh wire portion in the second border area, the seventh wire portion extending in the column direction and connecting to the sixth wire portion, and the seventh wire portion is disposed on the same layer as the data line.

17. The array substrate according to claim 16, wherein, it further includes a gate insulating layer located between the layer where the gate line is located and the layer where the data line is located, the gate insulating layer including at least one row of third vias in a first direction, the sixth wire portion being connected to the seventh wire portion through the third vias, and the first direction intersecting with the row direction and the column direction respectively.

18. The array substrate according to claim 17, in, The second sub-routing also includes an eighth routing portion extending from the third border area to the second border area, the eighth routing portion is connected between the data line and the seventh routing portion, wherein one of the two adjacent eighth routing portions is arranged on the same layer as the gate line, and the other is arranged on the same layer as the data line.

19. The array substrate according to claim 18, in, It also includes a first transfer structure disposed on the same layer as the gate line, and the seventh routing portion is connected to the eighth routing portion through the first transfer structure.

20. The array substrate according to claim 19, in, It also includes a second switching structure arranged at the same layer as the data line, and the eighth routing portion located at the layer where the gate line is located is connected to the first switching structure through the second switching structure.

21. The array substrate according to claim 20, in, Also comprising a gate insulating layer located between the layer where the gate line is located and the layer where the data line is located, the gate insulating layer comprising at least one row of fourth via holes in the row direction and at least one row of fifth via holes in the row direction; The seventh routing portion is connected to the first adapter structure through the fourth via hole, and the eighth routing portion is connected to the second adapter structure through the fifth via hole.

22. The array substrate according to claim 21, in, The eighth routing portion located at the layer where the data line is located is integrally arranged with the seventh routing portion connected thereto.

23. A display device, in, It comprises the array substrate as claimed in any one of claims 1 to 22.

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