Semiconductor device and manufacturing method therefor

Abstract

A semiconductor device and a manufacturing method therefor. The semiconductor device (100) comprises a transistor array (1000). The transistor array (1000) comprises, extending in a first direction and alternately arranged at intervals in a second direction, a plurality of first gate structures (10) and second gate structures (20). Each first gate structure (10) comprises a first isolation structure (13), and each second gate structure (20) comprises a second isolation structure (23), each two adjacent first isolation structure (13) and second isolation structure (23) being arranged opposite to each other in the second direction, and the first isolation structures (13) and the second isolation structures (23) all being located at the same side in the first direction. Yield and reliability are improved.

Description

Semiconductor device and manufacturing method thereof Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] As the feature size of memory cells approaches the process lower limit, planar processes and manufacturing technologies become challenging and costly, which causes the storage density of 2D structured memories to approach an upper limit.

[0003] To overcome the limitations of 2D structured memories, the industry has developed memories with three-dimensional structures to increase storage density.

[0004] However, as the integration requirements for memories increase, how to properly arrange the layout of various gates to reduce mutual interference between gates remains a problem to be overcome.

[0005] Summary of the Invention

[0006] The present application provides a semiconductor device and a method for manufacturing the same, which can improve the yield and reliability of the semiconductor device.

[0007] In a first aspect, the present application provides a method for manufacturing a semiconductor device, comprising:

[0008] providing a substrate;

[0009] forming a plurality of first gate trenches and second gate trenches extending along a first direction in the substrate, wherein the plurality of first gate trenches and the plurality of second gate trenches are alternately arranged along a second direction, wherein the second direction intersects the first direction;

[0010] forming a first gate structure in the first gate trench, and including a first gate line, a second gate line, and a first isolation structure between the first gate line and the second gate line;

[0011] forming a second gate structure in the second gate trench, and making the second gate structure include a third gate line and a fourth gate line, and a second isolation structure located between the third gate line and the fourth gate line;

[0012] Wherein, two adjacent first isolation structures and second isolation structures are arranged opposite to each other along the second direction, and the first isolation structure and the second isolation structure are both located on the same side in the first direction.

[0013] In a second aspect, the present application further provides a semiconductor device, comprising:

[0014] A transistor array comprising a plurality of first gate structures and second gate structures extending along a first direction and alternately arranged along a second direction; the second direction intersecting the first direction;

[0015] The first gate structure includes a first gate line and a second gate line, and a first isolation structure located between the first gate line and the second gate line;

[0016] The second gate structure includes a third gate line and a fourth gate line, and a second isolation structure located between the third gate line and the fourth gate line;

[0017] Wherein, two adjacent first isolation structures and second isolation structures are arranged opposite to each other along the second direction, and the first isolation structure and the second isolation structure are both located on the same side in the first direction.

[0018] In a third aspect, the present application further provides a semiconductor device, including:

[0019] A transistor array comprising a plurality of first gate structures and second gate structures extending along a first direction and alternately arranged along a second direction; the second direction intersecting the first direction;

[0020] The first gate structure includes a first gate line and a second gate line, and a first isolation structure located between the first gate line and the second gate line;

[0021] The second gate structure includes a third gate line and a fourth gate line, and a second isolation structure located between the third gate line and the fourth gate line;

[0022] a first gate line lead-out structure connected to the first gate line at a first end of the first gate structure along the first direction, and a second gate line lead-out structure connected to the second gate line at a second end of the first gate structure along the first direction;

[0023] a third gate line lead-out structure connected to the third gate line at a first end of the second gate structure along the first direction, and a fourth gate line lead-out structure connected to the fourth gate line at a second end of the second gate structure along the first direction;

[0024] Wherein, two adjacent first isolation structures and second isolation structures are arranged opposite to each other along the second direction, and the first isolation structure and the second isolation structure are both located on the same side in the first direction.

[0025] In a fourth aspect, the present application further provides a storage system, comprising the semiconductor device as described in the second aspect or the third aspect; and a memory controller coupled to the semiconductor device and controlling the semiconductor device.

[0026] The present application reserves a larger space for the gate line lead-out structure to perform the lead-out operation by arranging each adjacent first isolation structure and second isolation structure along the second direction, such as on the same side of the first direction. This not only simplifies the manufacturing process and reduces the manufacturing cost, but also avoids crosstalk and short circuits during lead-out based on the reserved space, reduces the device size, improves space utilization, and reduces the size of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0028] FIG1 is a circuit diagram of a memory cell of a semiconductor device provided in an embodiment of the present application;

[0029] FIG2 is a cross-sectional structural diagram of a vertical transistor in a semiconductor device provided in an embodiment of the present application;

[0030] FIG3 is a top view of a substrate provided in an embodiment of the present application;

[0031] FIG4 is a cross-sectional structural diagram of a substrate provided in an embodiment of the present application;

[0032] FIG5 is a top view of forming an isolation trench according to an embodiment of the present application;

[0033] FIG6 is a cross-sectional structural diagram of an isolation trench formed along the AA′ cutting line in FIG5 according to an embodiment of the present application;

[0034] FIG7 is a top view of a dielectric material deposited in an isolation trench according to an embodiment of the present application;

[0035] FIG8 is a cross-sectional structural diagram of the BB' cutting line in FIG7 provided in an embodiment of the present application;

[0036] 9 is a top view of forming a first gate trench, a second gate trench, and a shield trench according to an embodiment of the present application;

[0037] FIG10 is a cross-sectional structural diagram of the CC' cutting line in FIG9 provided in an embodiment of the present application;

[0038] FIG11 is a top view of a first gate structure, a second gate structure, and a shielding structure provided in an embodiment of the present application;

[0039] FIG12 is a cross-sectional structural diagram of the DD′ cutting line in FIG9 provided in an embodiment of the present application;

[0040] FIG13 is a top view of the first to fourth grooves provided in an embodiment of the present application;

[0041] FIG14 is a top view of another first to fourth grooves provided in an embodiment of the present application;

[0042] FIG15 is a cross-sectional structural diagram of the EE' cutting line in FIG13 or FIG14 provided in an embodiment of the present application;

[0043] FIG16 is a cross-sectional structural diagram taken along the II′ cutting line in FIG13 or FIG14 provided by an embodiment of the present application;

[0044] FIG17 is a top view of first to fourth isolation structures provided in an embodiment of the present application;

[0045] FIG18 is a top view of another first to fourth isolation structures provided in an embodiment of the present application;

[0046] FIG19 is a cross-sectional structural diagram of the FF' cutting line in FIG17 or FIG18 provided in an embodiment of the present application;

[0047] FIG20 is a top view of the first to fourth lead-out structures and the shielding lead-out structure provided in an embodiment of the present application;

[0048] FIG21 is a top view of another first to fourth lead-out structures and a shielding lead-out structure provided in an embodiment of the present application;

[0049] FIG22 is a cross-sectional structural diagram of a JJ' cutting line in FIG20 or FIG21 provided in an embodiment of the present application;

[0050] FIG23 is another cross-sectional structural diagram of the JJ′ cutting line in FIG20 or FIG21 provided in an embodiment of the present application;

[0051] FIG24 is a top view of a shielding lead structure and a capacitor array provided in an embodiment of the present application;

[0052] FIG25 is an enlarged top view of the first to fourth isolation structures in FIG17 and FIG18 provided in an embodiment of the present application;

[0053] FIG26 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0054] Figure 27 is a structural diagram of the storage system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0056] Transistors are used in dynamic random access memory (DRAM) to control the capacitance within each memory cell. The basic memory cell structure of DRAM consists of a transistor and a capacitor. Its main function is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0057] With the development of dynamic random access memory technology, the size of storage cells is getting smaller and smaller, and its array architecture is composed of 8F 2 Go to 6F 2 Then go to 4F 2 In addition, based on the requirements for ions and leakage current in dynamic random access memory, the memory architecture has evolved from planar array transistor to recessed gate array transistor, from recessed gate array transistor to buried saddle fin array transistor, and then from buried saddle fin array transistor to vertical gate transistor.

[0058] In practical applications, whether using planar transistors, recessed gate array transistors, buried transistors, or vertical gate transistors, dynamic random access memory (DRAM) is composed of multiple memory cell structures. Each memory cell structure primarily consists of a transistor and a capacitor structure controlled by the transistor. In other words, a DRAM consists of one transistor (T) and one capacitor (C), a 1T1C architecture. Its primary working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0059] Figure 1 is a circuit diagram of a 1T1C architecture provided in an embodiment of the present application. As shown in Figure 1, the drain of the transistor T is electrically connected to the bit line (BL), the source of the transistor T is electrically connected to one of the electrode plates of the capacitor C, the other electrode plate of the capacitor C is grounded via the ground terminal (GND), and the gate of the transistor T is connected to the word line (WL). A voltage is applied through the word line WL to control whether the transistor T is turned on or off. The bit line BL is used to perform a read or write operation on the capacitor C when the transistor T is turned on.

[0060] FIG2 is a cross-sectional schematic diagram of a semiconductor device 200 provided in an embodiment of the present application. As shown in FIG2 , the semiconductor device 200 includes: a first transistor 210 and a second transistor 220 arranged side by side along the Y-axis direction and separated by a shielding member 206, wherein the shielding member 206 includes an air gap 205. The first transistor 210 includes: a gate 201 extending along the Z-axis direction, a channel region 204 extending along the Z-axis direction, an oxide layer (Gate oxide layer) 202 located between the gate 201 and the channel region 204 and extending along the Z-axis direction, a bonding layer 207 located between the gate 201 and the oxide layer 202 and extending along the Z-axis direction, and a source (not shown in the figure) and a drain (not shown in the figure) located at opposite ends of the channel region 204 along the Z-direction. The gate 201 is located on one side of the channel region 204. The gate 201 of the first transistor 210 is located on the side of the channel region 204 that is away from the shield 206, and the gate of the second transistor 220 is also located on the side of the channel region that is away from the shield 206. Similarly, the second transistor 220 has the same structure as the first transistor 210. When using a vertical gate transistor structure as shown in FIG. 2 , the shield 206 can be used to improve the coupling effect between the adjacent first and second transistors 210, 220 in the semiconductor device 200. However, this semiconductor device 200 requires high process control.

[0061] In specific examples of the present application, the first direction and the second direction have an angle therebetween, and the third direction has an angle therebetween with the plane containing the first and second directions, wherein the angle range is less than or equal to 90 degrees. For example, in some embodiments of the present application, the first direction is the X direction, the second direction is the Y direction, and the third direction is the Z direction.

[0062] 3 to 27 , some embodiments of the present application provide a semiconductor device 100 and a method for manufacturing the same, as well as a storage system 300. In the present application, the first isolation structure 13 and the second isolation structure 23 are disposed opposite each other along the second direction Y on the same side in the first direction X. This allows for reserved space for lead extraction, improving space utilization while reducing process control requirements. The reserved space also facilitates subsequent lead extraction.

[0063] Figures 3 to 25 are schematic diagrams of the fabrication process of a semiconductor device 100 according to some embodiments of the present application. First, referring to Figures 17 to 19, Figure 17 is a top view of one structure of the semiconductor device 100 according to an embodiment of the present application, Figure 18 is a top view of another structure of the semiconductor device 100 according to an embodiment of the present application, and Figure 19 is a cross-sectional structural diagram of the semiconductor device 100 according to an embodiment of the present application taken along the FF' cut line in Figures 17 or 18. As shown in Figures 17, 18, and 19, the semiconductor device 100 includes:

[0064] A transistor array 1000 includes a plurality of first gate structures 10 and second gate structures 20 extending along a first direction X and alternately arranged along a second direction Y; the second direction Y intersects the first direction X;

[0065] The first gate structure 10 includes a first gate line 11 and a second gate line 12, and a first isolation structure 13 located between the first gate line 11 and the second gate line 12;

[0066] The second gate structure 20 includes a third gate line 21 and a fourth gate line 22, and a second isolation structure 23 located between the third gate line 21 and the fourth gate line 22;

[0067] Two adjacent first isolation structures 13 and second isolation structures 23 are arranged opposite to each other along the second direction Y, and the first isolation structure 13 and the second isolation structure 23 are both located on the same side in the first direction X.

[0068] In the embodiments of the present application, as shown in Figures 17 to 19, each adjacent first isolation structure 13 and second isolation structure 23 along the second direction Y are arranged relative to each other in the second direction Y, and each adjacent first isolation structure 13 and second isolation structure 23 along the second direction Y are located on the first side in the first direction X, that is, each adjacent first isolation structure 13 and second isolation structure 23 along the second direction Y are arranged relative to each other on the same side of the first direction X along the second direction Y as shown in Figures 17 to 19. In this way, a larger space can be reserved for the gate line lead-out structure in the corresponding embodiments of Figures 20 to 25 below for lead-out configuration.

[0069] In some embodiments, as shown in Figures 17 to 19, the first gate structure 10 further includes a third isolation structure 14 located between the first gate line 11 and the second gate line 12 and located on the other side in the first direction X; the second gate structure 20 further includes a fourth isolation structure 24 located between the third gate line 21 and the fourth gate line 22 and located on the other side in the first direction X; wherein, two adjacent third isolation structures 14 and the fourth isolation structures 24 are arranged opposite to each other along the second direction Y.

[0070] As shown in Figures 17 to 19, the first gate structure 10 includes a first gate line 11 and a second gate line 12, a first isolation structure 13 located between the first gate line 11 and the second gate line 12 and on a first side in the first direction X, and a third isolation structure 14 located between the first gate line 11 and the second gate line 12 and on a second side in the first direction X. In other words, the first isolation structure 13 and the third isolation structure 14 separate the first gate structure 10 to form the first gate line 11 and the second gate line 12. The dimensions of the first isolation structure 13 and the third isolation structure 14 in the first gate structure 10 along the first direction X may be the same or different. Assuming that the dimensions of the first isolation structure 13 and the third isolation structure 14 along the first direction X are equal, in the example shown in Figure 17, the dimension of the first gate line 11 along the first direction X is greater than the dimension of the second gate line 12 along the first direction X. In the example shown in Figure 18, the dimension of the first gate line 11 along the first direction X is equal to the dimension of the second gate line 12 along the first direction X.

[0071] As shown in Figures 17 to 19, the second gate structure 20 includes a third gate line 21 and a fourth gate line 22, a second isolation structure 23 located between the third gate line 21 and the fourth gate line 22 and on a first side in the first direction X, and a fourth isolation structure 24 located between the third gate line 21 and the fourth gate line 22 and on a second side in the first direction X. In other words, the second isolation structure 23 and the fourth isolation structure 24 separate the second gate structure 20 to form the third gate line 21 and the fourth gate line 22. The dimensions of the second isolation structure 23 and the fourth isolation structure 24 in the second gate structure 20 along the first direction X may be the same or different. Assuming that the dimensions of the second isolation structure 23 and the fourth isolation structure 24 along the first direction X are equal, in the example shown in Figure 17, the dimension of the third gate line 21 along the first direction X is greater than the dimension of the fourth gate line 22 along the first direction X. In the example shown in Figure 18, the dimension of the third gate line 21 along the first direction X is equal to the dimension of the fourth gate line 22 along the first direction X.

[0072] As shown in Figures 17 to 19, each adjacent first isolation structure 13 and second isolation structure 23 along the second direction Y are arranged relative to each other in the second direction Y, and each adjacent first isolation structure 13 and second isolation structure 23 along the second direction Y are located on the first side in the first direction X, that is, the first isolation structure 13 and the second isolation structure 23 are arranged relative to each other on the first side in the first direction X as shown in Figures 17 to 19. In addition, each adjacent third isolation structure 14 and fourth isolation structure 24 along the second direction Y are arranged relative to each other in the second direction Y, and each adjacent third isolation structure 14 and fourth isolation structure 24 along the second direction Y are located on the second side in the first direction X, that is, the third isolation structure 14 and the fourth isolation structure 24 are arranged relative to each other on the second side in the first direction X as shown in Figures 17 to 18. Such an arrangement can reserve more space for the gate line lead-out structure to be described in the embodiments below for lead-out configuration, and the two ends of multiple gate lines along the first direction X are led out in an odd-even interval manner, which can simplify the manufacturing process flow and reduce manufacturing costs.

[0073] It should be noted that, as shown in Figures 18, 21 and 24, the first isolation structure 13 is located on the first side of the first gate structure 10 along the first direction X, and the third isolation structure 14 is located on the second side of the first gate structure 10 along the first direction X, the second isolation structure 23 is located on the first side of the second gate structure 20 along the first direction X, and the fourth isolation structure 24 is located on the second side of the second gate structure 20 along the first direction X, and the first isolation structure 13 and the third isolation structure 14 in the first gate structure 10 are respectively located on opposite sides of the capacitor array 93 shown in Figure 24 in the first direction, and the second isolation structure 23 and the fourth isolation structure 24 in the second gate structure 20 are respectively located on opposite sides of the capacitor array 93 shown in Figure 24 in the first direction.

[0074] In some embodiments, the first isolation structure 13 and the third isolation structure 14 of the same first gate structure 10 are located on different sides along the second direction Y, and the second isolation structure 23 and the fourth isolation structure 24 of the same second gate structure 20 are located on different sides along the second direction Y.

[0075] In an embodiment of the present application, as shown in Figures 18 and 19, each adjacent first isolation structure 13 and second isolation structure 23 along the second direction Y are arranged relative to each other in the second direction Y, and each adjacent first isolation structure 13 and second isolation structure 23 along the second direction Y are located on the first side in the first direction X, and the first isolation structure 13 and the third isolation structure 14 of the same first gate structure 10 are located on different sides along the second direction Y, that is, the first isolation structure 13 and the second isolation structure 23 are arranged face to face and relative to each other along the second direction Y on the first side in the first direction X as shown in Figures 18 and 19. Every adjacent third isolation structure 14 and fourth isolation structure 24 along the second direction Y are arranged relative to each other in the second direction Y, and every adjacent third isolation structure 14 and fourth isolation structure 24 along the second direction Y are located on the second side in the first direction X, and the second isolation structure 23 and the fourth isolation structure 24 of the same second gate structure 20 are located on different sides along the second direction Y, that is, the third isolation structure 14 and the fourth isolation structure 24 are arranged back to back relative to each other along the second direction Y as shown in Figures 18 and 19 on the second side in the first direction X. While reserving a larger space for the gate line lead-out structure in the following embodiments for lead-out operation, multiple gate lines along the first direction X are staggered and led out at both ends of the gate lines in the second direction Y in an odd-even interval manner according to the row arrangement order. In this way, the manufacturing process is simplified and the manufacturing cost is reduced.

[0076] In some embodiments, the first gate structure 10 further includes: a first spacer structure 15 located between the first gate line 11 and the second gate line 12 and extending along the first direction X; and a first oxide layer 16 located outside each of the first gate line 11 and the second gate line 12 and away from each other.

[0077] The second gate structure 20 further includes: a second oxide layer 26 located between the third gate line 21 and the fourth gate line 22 and extending along the first direction X; and a second oxide layer 26 located outside each of the third gate line 21 and the fourth gate line 22 and away from each other.

[0078] In the embodiment of the present application, the first gate structure 10 and the second gate structure 20 both include a spacer structure and an oxide layer. The first gate structure 10 is separated by a first isolation structure 13 and a third isolation structure 14 to form a first gate line 11 and a second gate line 12, and the second gate structure 20 is separated by a second isolation structure 23 and a fourth isolation structure 24 to form a third gate line 21 and a fourth gate line 22. In particular, a first oxide layer 16 extending along the first direction X and the third direction Z is provided between the semiconductor pillar 31 and the first gate line 11 of the first gate structure 10 along the second direction Y. In addition, a first spacer structure 15 extending along the first direction X and the third direction Z is provided between the first gate line 11 of the first gate structure 10 and the first oxide layer 16 along the second direction Y. The first oxide layer 16 of the present application is located at the outermost side of the first gate structure 10, and the first spacer structure 15 is located between the first oxide layer 16 and the first gate line 11 or the second gate line 12. As shown in Figures 11 to 19 and 25, a semiconductor pillar 31, the first oxide layer 16 in the first gate structure 10, the first gate line 11, the first spacer structure 15, the second gate line 12, the first oxide layer 16, and another semiconductor pillar 31 are arranged in sequence along the second direction Y. Similarly, the second gate structure 20 also includes a second oxide layer 26 and a second spacer structure 25, and has the same structural arrangement as the first gate structure 10, which will not be described in detail here.

[0079] In some specific examples, the first oxide layer 16 and the second oxide layer 26 may be formed of materials including silicon oxide, silicon oxynitride, and the like.

[0080] In some specific examples, the constituent materials of the first spacing structure 15 and the second spacing structure 25 may include any one or a combination of multiple insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, polysiloxane or polysilazane.

[0081] In some embodiments, the semiconductor device 100 further includes:

[0082] A plurality of shielding structures 40 extend along a first direction X, and along a second direction Y, the shielding structures 40 are located between adjacent first gate structures 10 and second gate structures 20 .

[0083] In the embodiment of the present application, as shown in Figures 11 to 25, the semiconductor device 100 further includes a plurality of shielding structures 40 extending along the first direction X and the third direction. Along the second direction Y, the first gate structures 10 and the second gate structures 20 are alternately arranged, and a shielding structure 40 is provided between every two adjacent first gate structures 10 and second gate structures 20 in the second direction Y.

[0084] In some specific examples, the shielding structure 40 may be made of a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof.

[0085] In some embodiments, a dimension of the shielding structure 40 along the first direction X is greater than a dimension of the first gate structure 10 or the second gate structure 20 along the first direction X.

[0086] In the embodiments of the present application, as the density of semiconductor memory devices continues to increase, the physical size of memory cells decreases, the word lines in the memory cells become physically closer, and the capacitive coupling between adjacent word lines increases. When the number of accesses to a row of memory cells exceeds a threshold, data anomalies on nearby rows may occur. This phenomenon is commonly referred to as the row hammer effect. The row hammer effect refers to the phenomenon that when a word line is repeatedly accessed over a certain period of time, another adjacent word line that shares a bit line 92 with the word line will be opened, resulting in the loss of information in the capacitor. The projection size of the first gate structure 10 in the second direction Y is equal to the projection size of the second gate structure 20 in the second direction Y, and the projection size of the shielding structure 40 in the second direction is greater than the projection size of the first gate structure 10 in the second direction Y. That is to say, the projection size of the shielding structure 40 in the second direction includes the projection size of the first gate structure 10 or the second gate structure 20 in the second direction Y, that is, the size of the shielding structure 40 along the first direction X is greater than the size of the gate structure (including the first gate structure 10 and the second gate structure 20) along the first direction X. In this way, the shielding structure 40 can be led out through the end area extending along the gate structure in the first direction X, which not only facilitates the lead-out but also eliminates the hammer effect. The manufacturing cost of the semiconductor device 100 of the present application is low, and the problem of yield loss caused by the hammer effect is improved, the requirements for process consistency are reduced, the manufacturing process is reduced and the manufacturing cost is reduced.

[0087] In some embodiments, a dimension of the shielding structure 40 along the first direction X is smaller than a dimension of the first gate structure 10 or the second gate structure 20 along the first direction X.

[0088] In the embodiment of the present application, the projection size of the first gate structure 10 in the second direction Y is equal to the projection size of the second gate structure 20 in the second direction Y, and the projection size of the shield structure 40 in the second direction is smaller than the projection size of the first gate structure 10 in the second direction Y. In other words, the projection size of the first gate structure 10 or the second gate structure 20 in the second direction Y includes the projection size of the shield structure 40 in the second direction Y. That is, the size of the shield structure 40 along the first direction X can be smaller than the size of the gate structures (including the first gate structure 10 and the second gate structure 20) along the first direction X. This allows the shield structure 40 to be led out in the first direction X through the area reserved by the first isolation structure 13 and the second isolation structure 23 arranged opposite each other in the second direction Y. This not only facilitates the lead-out but also eliminates the hammer effect. The semiconductor device 100 of the present application has a low manufacturing cost and improves the yield loss caused by the hammer effect. It also reduces the material consumption used to deposit and form the shield structure 40, further reducing manufacturing costs. Since the amount of conductive material used to deposit and form the shield structure 40 is reduced, not only the manufacturing time of the semiconductor device 100 is shortened, but also the production efficiency of the semiconductor device 100 is improved.

[0089] Please refer to Figures 3 to 25, which are schematic diagrams of a manufacturing process of a semiconductor device 100 provided in some embodiments of the present application. First, the semiconductor device 100 will be described. Figure 20 is a top view of a structure of a semiconductor device 100 provided in an embodiment of the present application, and Figure 21 is a top view of another structure of a semiconductor device 100 provided in an embodiment of the present application. Figures 22 and 25 are two cross-sectional structural diagrams of the semiconductor device 100 provided in an embodiment of the present application along the JJ' cutting line in Figures 20 and 21, respectively. As shown in Figures 20 to 25, the semiconductor device 100 includes:

[0090] A transistor array 1000 includes a plurality of first gate structures 10 and second gate structures 20 extending along a first direction X and alternately arranged along a second direction Y; the second direction Y intersects the first direction X;

[0091] The first gate structure 10 includes a first gate line 11 and a second gate line 12, and a first isolation structure 13 located between the first gate line 11 and the second gate line 12;

[0092] The second gate structure 20 includes a third gate line 21 and a fourth gate line 22, and a second isolation structure 23 located between the third gate line 21 and the fourth gate line 22;

[0093] a first gate line lead-out structure 50 connected to the first gate line 11 at a first side of the first gate structure 10 along the first direction X, and a second gate line lead-out structure 60 connected to the second gate line 12 at a second side of the first gate structure 10 along the first direction X;

[0094] a third gate line lead-out structure 70 connected to the third gate line 21 at a first side of the second gate structure 20 along the first direction X, and a fourth gate line lead-out structure 80 connected to the fourth gate line 22 at a second side of the second gate structure 20 along the first direction X;

[0095] Two adjacent first isolation structures 13 and second isolation structures 23 are arranged opposite to each other along the second direction Y, and the first isolation structure 13 and the second isolation structure 23 are both located on the same side in the first direction X.

[0096] In the embodiment of the present application, the same contents as those of the semiconductor device 100 manufactured by the manufacturing process shown in Figures 2 to 19 refer to the contents of the embodiment corresponding to Figures 2 to 19 above. The difference between the semiconductor device 100 of this embodiment and the semiconductor device 100 corresponding to Figures 17 to 19 is that, in this embodiment, gate line lead-out structures are provided at the ends of the first gate structure 10 and the second gate structure 20. Specifically, as shown in Figures 20, 21 and 22, the semiconductor device 100 includes a plurality of first gate structures 10 and second gate structures 20 extending along the first direction X and alternately arranged along the second direction Y. As shown in Figures 20 to 22, each adjacent first isolation structure 13 and second isolation structure 23 in the second direction Y is arranged relative to each other on the first side in the first direction X along the second direction Y, and a first gate line lead-out structure 50 is provided at the first end of the first gate structure 10 along the first direction X, and the first gate line lead-out structure 50 is connected to the first gate line 11 to lead the first gate line 11 out. A second gate line lead-out structure 60 is provided at a second end of the first gate structure 10 along the first direction X. The second gate line lead-out structure 60 is connected to the second gate line 12 to lead the second gate line 12 out. Similarly, a third gate line lead-out structure 70 is provided at a first end of the second gate structure 20 along the first direction X. The third gate line lead-out structure 70 is connected to the third gate line 21 to lead the third gate line 21 out. A fourth gate line lead-out structure 80 is provided at a second end of the second gate structure 20 along the first direction X. The fourth gate line lead-out structure 80 is connected to the fourth gate line 22 to lead the fourth gate line 22 out.

[0097] In some embodiments, the first gate structure 10 further includes a third isolation structure 14 located between the first gate line 11 and the second gate line 12 and located on the other side in the first direction X;

[0098] The second gate structure 20 further includes a fourth isolation structure 24 located between the third gate line 21 and the fourth gate line 22 and located on the other side in the first direction X;

[0099] In which, along the second direction Y, two adjacent third isolation structures 14 and four isolation structures 24 are arranged opposite to each other.

[0100] Specifically, the first gate structure 10 includes a first isolation structure 13 and a third isolation structure 14 located between the first gate line 11 and the second gate line 12, and the second gate structure 20 includes a second isolation structure 23 and a fourth isolation structure 24 located between the third gate line 21 and the fourth gate line 22. Furthermore, the first isolation structure 13 and the second isolation structure 23 are respectively located at the first ends of the first gate structure 10 and the second gate structure 20 in the first direction X, and are arranged opposite each other along the second direction Y. The third isolation structure 14 and the fourth isolation structure 24 are respectively located at the second ends of the first gate structure 10 and the second gate structure 20 in the first direction X, and are arranged opposite each other along the second direction Y. Thus, the first isolation structure 13 and the third isolation structure 14 are respectively located on the first side and the second side of the first gate structure 10 in the first direction X, thereby isolating the first gate structure 10 to form the first gate line 11 and the second gate line 12. The second isolation structure 23 and the fourth isolation structure 24 are respectively located on the first side and the second side of the second gate structure 20 in the first direction X, thereby isolating the second gate structure 20 to form the third gate line 21 and the fourth gate line 22.

[0101] In some embodiments, the first isolation structure 13 and the third isolation structure 14 of the same first gate structure 10 are located on different sides along the second direction Y, and the second isolation structure 23 and the fourth isolation structure 24 of the same second gate structure 20 are located on different sides along the second direction Y.

[0102] In an embodiment of the present application, as shown in Figures 18 and 19, each adjacent first isolation structure 13 and second isolation structure 23 along the second direction Y are arranged relative to each other in the second direction Y, and each adjacent first isolation structure 13 and second isolation structure 23 along the second direction Y are located on the first side in the first direction X, and the first isolation structure 13 and the third isolation structure 14 of the same first gate structure 10 are located on different sides along the second direction Y, that is, the first isolation structure 13 and the second isolation structure 23 are arranged face to face and relative to each other along the second direction Y on the first side in the first direction X as shown in Figures 18 and 19. Every adjacent third isolation structure 14 and fourth isolation structure 24 along the second direction Y are arranged relative to each other in the second direction Y, and every adjacent third isolation structure 14 and fourth isolation structure 24 along the second direction Y are located on the second side in the first direction X, and the second isolation structure 23 and the fourth isolation structure 24 of the same second gate structure 20 are located on different sides along the second direction Y, that is, the third isolation structure 14 and the fourth isolation structure 24 are arranged back to back relative to each other along the second direction Y as shown in Figures 18 and 19 on the second side in the first direction X. In this way, a larger space can be reserved for the gate line lead-out structure in the following embodiments to perform the lead-out operation. At the same time, multiple gate lines along the first direction X are staggered and led out at both ends of the gate lines in the second direction Y in an odd-even interval manner according to the row arrangement order. In this way, the manufacturing process is simplified and the manufacturing cost is reduced.

[0103] In some embodiments, the semiconductor device 100 further includes:

[0104] A plurality of shielding structures 40 extend along a first direction X, and the shielding structures 40 are located between adjacent first gate structures 10 and second gate structures 20 along a second direction Y. As shown in FIG11 to FIG25 , the shielding structures 40 in this embodiment can be referred to the relevant descriptions of the embodiments corresponding to FIG11 to FIG25 above, and will not be repeated here.

[0105] In some embodiments, the semiconductor device 100 further includes a shielding lead-out structure 90 connected to one end of the shielding structure 40 along the first direction X.

[0106] In an embodiment of the present application, the semiconductor device 100 further includes a shielding lead-out structure 90, as shown in Figures 20 and 21. The shielding lead-out structure 90 is disposed at one end of the shielding structure 40 along the first direction X. As shown in Figures 20 and 21, a plurality of shielding lead-out structures 90 can be disposed at the first end of the shielding structure 40 along the first direction X. Of course, the plurality of shielding lead-out structures 90 can also be disposed at the second end of the shielding structure 40 along the first direction X. Alternatively, the plurality of shielding lead-out structures 90 can also be disposed at the first end and the second end of the shielding structure 40 along the first direction X, and the shielding lead-out structures 90 disposed at the plurality of first ends and the plurality of second ends are staggered along the second direction Y at the first end and the second end of the shielding structure 40 in a row arrangement order with an odd-even interval.

[0107] In some embodiments, the plurality of shielding structures 40 include odd-row shielding structures 41 and even-row shielding structures 42 that are staggered and arranged along the second direction Y, and the plurality of shielding lead-out structures 90 are respectively connected to the first ends of the odd-row shielding structures 41 and the second ends of the even-row shielding structures 42, and the first ends and the second ends are the opposite ends of each shielding structure 40 along the first direction X.

[0108] In an embodiment of the present application, as shown in Figures 20 and 21, the multiple shielding structures 40 include odd-row shielding structures 41 and even-row shielding structures 42 that are staggered and arranged along the second direction Y. As shown in Figures 20 to 25, a shielding lead-out structure 90 extending along the third direction Z is connected to the first end of each odd-row shielding structure 41, and a shielding lead-out structure 90 extending along the third direction Z is connected to the second end of each even-row shielding structure 42. In this way, the multiple shielding lead-out structures 90 can be arranged in the order of row numbers along the second direction Y, and alternately led out at the first ends of the multiple odd-row shielding structures 41 that are staggered and arranged along the second direction Y and at the second ends of the even-row shielding structures 42.

[0109] In some embodiments, the shielding lead-out structure 90 is located between the adjacent first isolation structure 13 and the second isolation structure 23 , or between the adjacent third isolation structure 14 and the fourth isolation structure 24 .

[0110] In an embodiment of the present application, as shown in Figures 20 to 25, multiple shielding lead-out structures 90 include a first shielding lead-out structure 90a and a second shielding lead-out structure 90b. A first shielding lead-out structure 90a connected to the first end of the odd-row shielding structure 41 is arranged between the first isolation structure 13 and the second isolation structure 23 adjacent to each other in the second direction Y, and a second shielding lead-out structure 90b connected to the second end of the even-row shielding structure 42 is arranged between the third isolation structure 14 and the fourth isolation structure 24 adjacent to each other in the second direction Y. The first shielding lead-out structure 90a and the second shielding lead-out structure 90b are arranged relative to each other in the first direction X, and the first shielding lead-out structure 90a and the second shielding lead-out structure 90b are arranged relative to each other in the second direction Y. Due to the existence of the isolation structure, the shielding lead-out structure has a larger landing window. Therefore, as shown in Figures 20 to 25, the first shielding lead-out structure 90a and the second shielding lead-out structure 90b are alternately staggered in the first direction X and the second direction Y to correspond to the distribution positions of the corresponding isolation structures, that is, the position of the first shielding lead-out structure 90a corresponds to the positions of the first isolation structure 13 and the second isolation structure 23 adjacent thereto, and the position of the second shielding lead-out structure 90b corresponds to the positions of the third isolation structure 14 and the fourth isolation structure 24 adjacent thereto, so that the spacing between the lead-out channels of the shielding structure 40 is increased, and at the same time the device size can be reduced and the space utilization rate can be improved.

[0111] In some embodiments, further comprising:

[0112] a semiconductor pillar array 30; the semiconductor pillar array 30 includes a plurality of semiconductor pillars 31 arranged in an array along the first direction X and the second direction Y and extending along a third direction Z, wherein the third direction Z intersects the first direction X and the second direction Y, and the semiconductor pillars 31 are located between the adjacent shielding structure 40 and the first gate structure 10 or the second gate structure 20;

[0113] a capacitor structure 91 located on one side of the semiconductor pillar 31 along the third direction Z, the capacitor structure 91 being connected to the semiconductor pillar 31 and a common terminal, and extending along the third direction Z;

[0114] The bit line 92 is located on the other side of the semiconductor pillar 31 along the third direction Z. The bit line 92 extends along the first direction X and is connected to the semiconductor pillar 31 .

[0115] In an embodiment of the present application, a semiconductor device 100 includes a semiconductor pillar array 30 and a transistor array 1000. The semiconductor pillar array 30 includes a plurality of semiconductor pillars 31 arranged in an array along a first direction X and a second direction Y and extending in a third direction Z. The first direction X, the second direction Y, and the third direction Z intersect with each other. The semiconductor pillars 31 are used to transfer charge or stop the transfer of charge under the action of an external electric field, thereby turning the transistor on or off. The extension direction of each semiconductor pillar 31 is the direction of current when the transistor is turned on. For example, as shown in Figures 9 and 10, the extension direction of the semiconductor pillars 31 is the third direction Z, and the plurality of semiconductor pillars 31 are arranged in an array along the first direction X and the second direction Y to form the semiconductor pillar array 30.

[0116] As shown in Figures 9, 20, and 21, the plurality of semiconductor pillars 31 include a first row of semiconductor pillars 31a, a second row of semiconductor pillars 31b, a third row of semiconductor pillars 31c, and a fourth row of semiconductor pillars 31d arranged along the first direction X and adjacent to each other in the second direction Y. The first gate structure 10 is located between the first row of semiconductor pillars 31a and the second row of semiconductor pillars 31b in the second direction Y. The odd-numbered row shielding structures 41 are located between the second row of semiconductor pillars 31b and the third row of semiconductor pillars 31c in the second direction Y. The second gate structure 20 is located between the third row of semiconductor pillars 31c and the fourth row of semiconductor pillars 31d in the second direction Y. The even-numbered row shielding structures 42 are located between the fourth row of semiconductor pillars 31d and another first row of semiconductor pillars 31a (adjacent to the fourth row of semiconductor pillars 31d in the second direction Y).

[0117] The semiconductor device 100 in the embodiment of the present application further includes a capacitor array 93 located at one end of the semiconductor pillar array 30 in the third direction Z. The capacitor array 93 includes a plurality of capacitor structures 91 arranged in an array along the first direction X and the second direction Y and extending in the third direction Z. The capacitor structure 91 includes a first electrode layer (not shown in the figure) connected to one side of the semiconductor pillar 31 in the third direction Z, and a capacitor dielectric layer (not shown in the figure) and a second electrode layer (not shown in the figure) located within the first electrode layer. The second electrode layer of the capacitor structure 91 is connected to a common terminal. The semiconductor device 100 further includes a bit line 92 connected to the other side of the semiconductor pillar 31 in the third direction Z and to the drain of the semiconductor pillar 31. The bit line 92 extends along the first direction X.

[0118] A gate line is formed on the sidewalls of each semiconductor pillar 31 of the semiconductor array. The gate lines of each semiconductor pillar 31 in the same column (i.e., each semiconductor pillar 31 arranged at intervals along the second direction Y) are connected to form a word line. One end of each semiconductor pillar 31 in the transistor array 1000 along the third direction Z forms a source (not shown in the figure), which is connected to the first electrode layer of the capacitor structure 91. The other end of each semiconductor pillar 31 in the transistor array 1000 along the third direction Z forms a drain (not shown in the figure). The drains of each semiconductor pillar 31 in the same row (i.e., each semiconductor pillar 31 arranged at intervals along the first direction X) are connected to form a bit line 92 (not shown in the figure). In the above-mentioned semiconductor device 100, the semiconductor pillars 31 extend along the third direction Z, and the source and drain are respectively formed at opposite ends of the semiconductor pillar 31 along the third direction Z. The capacitor structure 91 and the bit line 92 are respectively located on opposite sides of the semiconductor pillar 31 along the third direction Z. In this way, they can be manufactured separately on both sides of the substrate 1, improving process manufacturing efficiency.

[0119] It can be understood that the source and drain of the semiconductor pillar 31 are relative concepts, and the source and drain can be any surface of the semiconductor pillar 31 along the third direction Z.

[0120] In some specific examples, the common terminal may include a low voltage terminal and a ground terminal, wherein the low voltage may include -0.5V, -1V, etc. In some embodiments, the shielding structure 40 is connected to the common terminal via a shielding lead-out structure 90. In actual application, the shielding structure 40 can be set to be powered separately without being connected to the common terminal as required. In some embodiments of the present application, a low voltage is applied to the shielding structure 40 or the shielding structure 40 is grounded via the shielding lead-out structure 90 so that the shielding structure 40 can shield interference between adjacent semiconductor pillars 31.

[0121] In some embodiments, the first gate line lead-out structure 50 and the second gate line lead-out structure 60 are located at one end of the first gate structure 10 along the third direction Z away from the capacitor structure 91, the third gate line lead-out structure 70 and the fourth gate line lead-out structure 80 are located at one end of the second gate structure 20 along the third direction Z away from the capacitor structure 91, and the shielding lead-out structure 90 is located at one end of the shielding structure 40 along the third direction Z away from the capacitor structure 91.

[0122] In an embodiment of the present application, as shown in Figures 20, 21, and 22, the shielding lead-out structure 90 is connected to the shielding structure 40, and the shielding lead-out structure 90 is located on a side away from the capacitor structure 91 along the third direction Z. The first gate line 11 in the first gate structure 10 is connected to the first gate line lead-out structure 50, and the first gate line lead-out structure 50 is located on a side of the first gate line 11 away from the capacitor structure 91 along the third direction Z. The second gate line 12 in the first gate structure 10 is connected to the second gate line lead-out structure 60, and the second gate line lead-out structure 60 is located on a side of the second gate line 12 away from the capacitor structure 91 along the third direction Z. Similarly, the third gate line 21 in the second gate structure 20 is connected to the third gate line 21 connecting structure, and the third gate line lead-out structure 70 is located on a side of the third gate line 21 away from the capacitor structure 91 along the third direction Z. The fourth gate line 22 in the second gate structure 20 is connected to the fourth gate line 22 connecting structure, and the fourth gate line lead-out structure 80 is located on a side of the fourth gate line 22 away from the capacitor structure 91 along the third direction Z. In other words, the first gate line lead-out structure 50 to the fourth gate line lead-out structure 80 and the shield lead-out structure 90 are all located at an end away from the capacitor structure 91 (or the capacitor array 93) along the third direction Z. Assuming that the side of the semiconductor device 100 where the capacitor structure 91 (or the capacitor array 93) is located along the third direction Z is the front side, then the first gate line lead-out structure 50 to the fourth gate line lead-out structure 80 and the shield lead-out structure 90 are back-side lead-out along the third direction Z in a direction away from the capacitor structure 91.

[0123] In some embodiments, the first gate line lead-out structure 50 and the second gate line lead-out structure 60 are located at an end of the first gate structure 10 along the third direction Z away from the capacitor structure 91, the third gate line lead-out structure 70 and the fourth gate line lead-out structure 80 are located at an end of the second gate structure 20 along the third direction Z away from the capacitor structure 91, and the shielding lead-out structure 90 is located at an end of the shielding structure 40 along the third direction Z close to the capacitor structure 91.

[0124] In the embodiment of the present application, similar to the above embodiment, the first gate line lead-out structure 50 to the fourth gate line lead-out structure 80 are all located at an end away from the capacitor structure 91 (or capacitor array 93) along the third direction Z, but as shown in Figures 20, 21, and 22, the shield lead-out structure 90 is located at an end close to the capacitor structure 91 (or capacitor array 93) along the third direction Z. Assuming that the side of the semiconductor device 100 where the capacitor structure 91 (or capacitor array 93) is located along the third direction Z is the front side, then the first gate line lead-out structure 50 to the fourth gate line lead-out structure 80 are back-leaded along the third direction Z toward the direction close to the capacitor structure 91, and the shield lead-out structure 90 is front-leaded along the third direction Z toward the direction close to the capacitor structure 91.

[0125] In some specific examples, the constituent materials of the first to fourth gate line lead-out structures 50 to 80 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The materials of the first to fourth gate line lead-out structures 50 to 80 may be the same or different. The present application utilizes the first to fourth gate line lead-out structures 50 to 80 to lead out the connection of the gate lines, which facilitates the process flow and can improve reliability.

[0126] In some specific examples, the shielding lead structure 90 may be formed of a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The shielding lead structure 90 may be formed of the same material as or different from the shielding structure 40. The shielding lead structure 90 of the present application is electrically interconnected with the shielding structure 40, and a fixed voltage is applied to the shielding structure 40 via the shielding lead structure 90, i.e., the shielding lead structure 90 may be connected to a common terminal to enable the shielding structure 40 to function as a shield.

[0127] The present invention also provides a method for manufacturing a semiconductor device 100. The semiconductor device 100 in the above embodiment can be manufactured by the following method for manufacturing a semiconductor device 100. FIG26 is a flow chart of the method for manufacturing a semiconductor device 100 in the embodiment of the present invention, as shown in FIG26, including:

[0128] S100 , providing a substrate 1 .

[0129] In some specific examples, substrate 1 is a material used to manufacture semiconductor device 100. The material of substrate 1 may include silicon (e.g., single crystal silicon, polycrystalline silicon), silicon germanium (SiGe), silicon carbide (SiC), gallium nitride (GaN), indium phosphide (InP), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any suitable combination thereof. Substrate 1 may include a wafer formed by grinding, polishing, and slicing cylindrical single crystal silicon.

[0130] S200, as shown in FIG9 and FIG10, forming a plurality of first gate trenches K2 and second gate trenches K3 extending along a first direction X in the substrate 1, wherein the plurality of first gate trenches K2 and the plurality of second gate trenches K3 are alternately arranged along a second direction Y; the second direction Y intersects the first direction X;

[0131] In some embodiments of the present application, a semiconductor pillar array 30 is first formed before forming the first gate trench K2 and the second gate trench K3. For the specific process of forming the semiconductor pillar array 30, please refer to the embodiments corresponding to Figures 2 to 9 below. After the semiconductor pillar array 30 is formed, the first gate trench K2 and the second gate trench K3 extending along the first direction X are formed in the substrate 1. As shown in Figures 9 and 10, a plurality of the first gate trenches K2 and a plurality of the second gate trenches K3 are staggered and distributed along the second direction Y, and the semiconductor pillars 31 are located between adjacent first gate trenches K2 and second gate trenches K3. In the embodiments of the present application, the first gate trenches K2 extending along the first direction X and the second gate trenches K3 extending along the first direction X can be formed simultaneously, thereby simplifying the manufacturing process and improving efficiency.

[0132] S300 , as shown in FIG. 11 and FIG. 12 , forming a first gate structure 10 in the first gate trench K2 , and making the first gate structure 10 include a first gate line 11 , a second gate line 12 , and a first isolation structure 13 located between the first gate line 11 and the second gate line 12 .

[0133] In some embodiments, the step of forming the first gate structure 10 further includes:

[0134] S310 , forming a first oxide layer 16 on the inner wall of the first gate trench K2 .

[0135] S320 , forming a first conductive layer 18 on the inner wall of the first oxide layer 16 .

[0136] S330 , forming a first spacing structure 15 in the first conductive layer 18 .

[0137] S340, forming the first isolation structure 13 on the first side of the first end portion of the first conductive layer 18, and forming the third isolation structure 14 on the second side of the second end portion of the first conductive layer 18, so as to separate the first gate line 11 and the second gate line 12 formed in the first conductive layer 18, the first end portion and the second end portion being the opposite ends of the first conductive layer 18 in the first direction X, and the first side and the second side being the opposite sides of the first conductive layer 18 in the second direction Y.

[0138] In some embodiments, as shown in FIG9 and FIG10 , after forming the first gate trench K2 and the second gate trench K3, a sacrificial material may be deposited in the first gate trench K2, a mask may be used to remove a portion of the sacrificial material in the second gate trench K3, and then a metal material may be deposited to form a shielding structure 40. After depositing the sacrificial material in the second gate trench K3, a mask may be used to remove a portion of the sacrificial material in the first gate trench K2, and then a first oxide layer 16 may be formed along the inner wall of the first gate trench K2, and a metal material may be deposited on the sidewalls of the first oxide layer 16 to form a first conductive layer 18.

[0139] After forming the first gate trench K2, a first oxide layer 16 can be formed on the sidewalls of the gate trench K2, as shown in Figures 11 and 12. The first oxide layer 16 can be a silicon oxide layer formed using a rapid thermal oxidation (RTO) method or an in-situ steam generation (ISSG) method. As shown in Figures 11 and 12, the exposed sidewalls of the semiconductor pillar 31 are oxidized through the gate trench K2 to form the first oxide layer 16 on the sidewalls of the semiconductor pillar 31, i.e., the sidewalls of the gate trench K2. Processes for oxidizing the sidewalls of the semiconductor pillar 31 exposed in the gate trench K2 include, but are not limited to, direct oxidation, alkaline oxidation, or acidic oxidation.

[0140] In some embodiments of the present application, direct oxidation is performed by heating, causing the silicon on the sidewalls of the semiconductor pillars 31 to chemically react with a gas containing an oxidizing substance at high temperature, thereby producing a dense silicon dioxide film on the silicon surface, forming a first oxide layer 16 located on the sidewalls of the semiconductor pillars 31. The first oxide layer 16 includes an insulating material such as silicon oxide or silicon oxynitride.

[0141] After forming the first oxide layer 16, a first conductive layer 18 is formed within the sidewalls of the first oxide layer 16. In some specific examples, the first conductive layer 18 is deposited and formed within the sidewalls of the first oxide layer 16, and a first spacer structure 15 is formed within the first conductive layer 18 to obtain the first gate structure 10 shown in Figures 11 and 12. After forming the first gate structure 10, a portion of the first oxide layer 16 and a portion of the first spacer structure 15 on the first side of the first gate structure 10 in the first direction X are removed along the third direction Z, as shown in Figures 13 and 15, or as shown in Figures 14 and 15, or as shown in Figures 14 and 16. A first trench K5 is formed on the first side of the first gate structure 10 along the first direction X, and then a first isolation structure 13 is formed in the first trench K5.

[0142] The material of the first conductive layer 18 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The material of the first spacer structure 15 includes, but is not limited to, any one or a combination of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, polysiloxane, or polysilazane.

[0143] In some embodiments, the conductive material may be deposited by methods including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), and atomic layer deposition (ALD).

[0144] S400. Form a second gate structure 20 in the second gate trench K3, and make the second gate structure 20 include a third gate line 21 and a fourth gate line 22, and a second isolation structure 23 located between the third gate line 21 and the fourth gate line 22; wherein, two adjacent first isolation structures 13 and second isolation structures 23 are arranged opposite to each other along the second direction Y, and the first isolation structure 13 and the second isolation structure 23 are both located on the same side in the first direction.

[0145] In some embodiments, the step of forming the second gate structure 20 further includes:

[0146] S410 , forming a second oxide layer 26 on the inner wall of the second gate trench K3 .

[0147] S420 , forming a second conductive layer 28 on the inner wall of the second oxide layer 26 .

[0148] S430 , forming a second spacing structure 25 in the second conductive layer 28 .

[0149] S440, forming the second isolation structure 23 on the first side of the first end portion of the second conductive layer 28, and forming the fourth isolation structure 24 on the second side of the second end portion of the second conductive layer 28, so as to form the third gate line 21 and the fourth gate line 22 separated from the second conductive layer 28, the first end portion and the second end portion being opposite ends of the second conductive layer 28 in the first direction X, and the first side and the second side being opposite sides of the second conductive layer 28 in the second direction Y.

[0150] Specifically, the process of forming the second gate structure 20 in the embodiment of the present application can refer to the process of forming the second gate structure 20 as shown in Figures 9 to 12. After the second gate structure 20 is formed, part of the second oxide layer 26 and part of the second spacer structure 25 on the first side of the second gate structure 20 in the first direction X are removed along the third direction Z, as shown in Figures 13 and 15, or as shown in Figures 14 and 15, or as shown in Figures 14 and 16, a second trench K6 is formed on the first side of the second gate structure 20 along the first direction X, and then a second isolation structure 23 is formed in the second trench K6.

[0151] In some embodiments, further comprising:

[0152] The first gate structure 10 further includes a third isolation structure 14 located between the first gate line 11 and the second gate line 12 and located on the other side in the first direction X;

[0153] The second gate structure 20 further includes a fourth isolation structure 24 located between the third gate line 21 and the fourth gate line 22 and located on the other side in the first direction X;

[0154] In which, along the second direction Y, two adjacent third isolation structures 14 and four isolation structures 24 are arranged opposite to each other.

[0155] In an embodiment of the present application, after the first gate structure 10 is formed, a portion of the first oxide layer 16 and a portion of the first spacer structure 15 on the second side of the first gate structure 10 in the first direction X are removed along the third direction Z, as shown in Figures 13 and 15, or as shown in Figures 14 and 15, or as shown in Figures 14 and 16, a third trench K7 is formed on the second side of the first gate structure 10 along the first direction X, and then a third isolation structure 14 is formed in the third trench K7. The first gate structure 10 is separated by the first isolation structure 13 and the third isolation structure 14 to form a first gate line 11 and a second gate line 12. Similarly, after forming the second gate structure 20, a portion of the second oxide layer 26 and a portion of the second spacer structure 25 on the second side of the second gate structure 20 in the first direction X are removed along the third direction Z, as shown in Figures 13 and 15, or as shown in Figures 14 and 15, or as shown in Figures 14 and 16, and a fourth trench K8 is formed on the second side of the second gate structure 20 along the first direction X. Then, a fourth isolation structure 24 is formed in the fourth trench K8, and the second gate structure 20 is separated by the second isolation structure 23 and the fourth isolation structure 24 to form a third gate line 21 and a fourth gate line 22.

[0156] 13 and 15 , the first trench K5 and the third trench K7 are respectively located on the first side and the second side of the first gate structure 10 along the first direction X, and the first trench K5 and the third trench K7 are respectively located on the same side of the first gate structure 10 along the second direction Y. Similarly, the second trench K6 and the fourth trench K8 are respectively located on the first side and the second side of the second gate structure 20 along the first direction X, and the second trench K6 and the fourth trench K8 are respectively located on the same side of the second gate structure 20 along the second direction Y.

[0157] In some embodiments, dry etching can be used to form corresponding first grooves, second grooves, third grooves, and fourth grooves according to the positions corresponding to the openings of the mask plate, and then a wet etching process is used to expand the size of the first groove to form a first groove K5. Similarly, a wet etching process is used to expand the size of the second groove to form a second groove K6, a wet etching process is used to expand the size of the first groove to form a third groove K7, and a wet etching process is used to expand the size of the first groove to form a fourth groove K8.

[0158] In some embodiments, further comprising:

[0159] The first isolation structure 13 and the third isolation structure 14 of the same first gate structure 10 are located on different sides along the second direction Y;

[0160] The second isolation structure 23 and the fourth isolation structure 24 of the same second gate structure 20 are located on different sides along the second direction Y.

[0161] In the embodiment of the present application, after forming the first gate structure 10, first to fourth trenches K5 to K8 are formed with reference to the above-described embodiments. As shown in FIG14 , FIG15 , and FIG16 , the first trench K5 and the third trench K7 are located on the first side and the second side of the first gate structure 10 along the first direction X, respectively, and the first trench K5 and the third trench K7 are located on different sides of the first gate structure 10 along the second direction Y. Similarly, the second trench K6 and the fourth trench K8 are located on the first side and the second side of the second gate structure 20 along the first direction X, respectively, and the second trench K6 and the fourth trench K8 are located on the same side of the second gate structure 20 along the second direction Y. Then, a first isolation structure 13 is formed in the first trench K5, a second isolation structure 23 is formed in the second trench K6, a third isolation structure 14 is formed in the third trench K7, and a fourth isolation structure 24 is formed in the fourth trench K8.

[0162] In some embodiments, the manufacturing method further comprises the steps of:

[0163] A plurality of shielding trenches K4 extending along a first direction X are formed in the substrate 1 , wherein the shielding trenches K4 are located between adjacent first gate trenches K2 and second gate trenches K3 along a second direction Y; and

[0164] A shielding structure 40 is formed in the shielding trench K4 .

[0165] In the embodiment of the present application, after forming the semiconductor pillar array 30, shielding trenches K4 extending along the first direction X are further formed in the substrate 1. Multiple shielding trenches K4 are spaced apart along the second direction Y, and are located between adjacent first gate structures 10 and second gate structures 20 along the second direction Y. That is, along the second direction Y, the first gate structures 10 and the second gate structures 20 are alternately spaced apart, and a shielding trench K4 is provided between every two adjacent first gate structures 10 and second gate structures 20 in the second direction Y. Then, a conductive material is filled into the shielding trenches K4 to form a shielding structure 40. The materials included in the conductive material can be referred to in the above embodiment and will not be described in detail here.

[0166] In some embodiments, the step of forming the shielding trench K4 includes: making the size of the shielding trench K4 along the first direction X smaller than the size of the first gate trench K2 along the first direction X.

[0167] In the embodiment of the present application, the dimension of the shielding trench K4 along the first direction X can be smaller than the dimension of the first gate trench K2 (or the second gate trench K3) along the first direction X. In this way, the material consumption for depositing the shielding structure 40 can be reduced, further reducing the manufacturing cost. Since the time for manufacturing the semiconductor device 100 of the embodiment of the present application is reduced compared to that for depositing the shielding structure 40 using less conductive material, the production efficiency of the semiconductor device 100 can also be improved.

[0168] In some embodiments, etching the substrate 1 can be performed, for example, using a dry etching process or a wet etching process. If the substrate 1 is etched using a dry etching process, the extension dimensions of the first gate trench K2, the second gate trench K3, and the shielding trench K4 along the third direction Z can be controlled by controlling the dry etching time. As shown in FIG8 , the first etching depth H1 of the first gate trench K2 (i.e., the extension dimension along the third direction Z) can be equal to the second etching depth H2 of the second gate trench K3 (i.e., the extension dimension along the third direction Z). The third etching depth H3 of the shielding trench K4 (i.e., the extension dimension along the third direction Z) is less than the first etching depth H1 of the first gate trench K2 (or the second etching depth H2 of the second gate trench K3).

[0169] In some embodiments, the etching depth can be controlled by etching process parameters (e.g., etching time, gas flow rate, ratio, pressure, temperature, etc.). For example, under a constant etching rate, the longer the etching time, the deeper the trench formed in the third direction Z. In one embodiment of the present application, the etching process parameters can be adjusted so that the first etching depth H1 of the first gate trench K2 is greater than the third etching depth H3 of the shield trench K4. The etching method can be dry etching, which can be, for example, plasma etching.

[0170] In some embodiments, the etching widths (i.e., the extension dimensions along the second direction Y) of the first gate trench K2, the second gate trench K3, and the shielding trench K4 can be set by a mask plate (MASK). For example, the mask plate includes a first opening corresponding to the first gate trench K2, a second opening corresponding to the second gate trench K3, and a third opening corresponding to the shielding trench K4. The dimensions of the first opening and the second opening along the second direction Y can be the same, and the dimension of the first opening along the second direction Y can be larger than the dimension of the second opening along the second direction Y.

[0171] In some embodiments, the spacing between the shielding structure 40 and the adjacent first gate structures 10 and second gate structures 20 may be the same or approximately the same.

[0172] In some embodiments, further comprising:

[0173] forming a first gate line lead-out structure 50 and a second gate line lead-out structure 60, and connecting the first gate line 11 at a first end of the first gate structure 10 along the first direction X to the first gate line 11, and connecting the second gate line 12 at a second end of the first gate structure 10 along the first direction X to the second gate line 12;

[0174] forming a third gate line lead-out structure 70 and a fourth gate line lead-out structure 80, and connecting the third gate line lead-out structure 70 to the third gate line 21 at a first end of the second gate structure 20 along the first direction X, and connecting the fourth gate line lead-out structure 80 to the fourth gate line 22 at a second end of the second gate structure 20 along the first direction X;

[0175] A shielding lead-out structure 90 is formed, and the shielding lead-out structure 90 is connected to one end of the shielding structure 40 along the first direction X.

[0176] In the embodiment of the present application, after forming the first isolation structure 13 to the fourth isolation structure 24 and the shielding structure 40 of Figures 18 and 19, as shown in Figures 20 to 24, a portion of the shielding structure 40 is removed to form a shielding lead-out structure 90 connected to one end of the shielding structure 40 along the first direction X, a portion of the spacing structure near the first gate line 11 on the side of the first gate structure 10 is removed to form a first gate line lead-out structure 50 connected to the first end of the first gate line 11 along the first direction X, and a portion of the spacing structure near the second gate line 12 on the side of the first gate structure 10 is removed. A second gate line lead-out structure 60 is formed, which is connected to the second end of the second gate line 12 along the first direction X. Part of the spacing structure of the second gate structure 20 near the third gate line 21 is removed to form a third gate line lead-out structure 70 connected to the first end of the third gate line 21 along the first direction X. Part of the spacing structure of the second gate structure 20 near the fourth gate line 22 is removed to form a fourth gate line lead-out structure 80 connected to the second end of the fourth gate line 22 along the first direction X. The materials of the gate lead-out contact 32 can be referred to the above embodiments and will not be repeated here.

[0177] In some embodiments, the plurality of shielding structures 40 include odd-numbered rows of shielding structures 41 and even-numbered rows of shielding structures 42 arranged alternately along the second direction Y, and the step of forming the shielding lead-out structure 90 further includes:

[0178] The plurality of shielding lead-out structures 90 are respectively connected to the first ends of the odd-numbered shielding structures 41 and the second ends of the even-numbered shielding structures 42 . The first ends and the second ends are opposite ends of each shielding structure 40 along the first direction X.

[0179] In some embodiments, the step of forming the shielding lead-out structure 90 further includes:

[0180] The shielding lead-out structure 90 is formed between the adjacent first isolation structure 13 and the second isolation structure 23 , or the shielding lead-out structure 90 is formed between the adjacent third isolation structure 14 and the fourth isolation structure 24 .

[0181] In some embodiments, the manufacturing method further comprises:

[0182] A separation structure 211 extending along the second direction Y and arranged at intervals along the first direction X is formed on the substrate 1, so that a semiconductor pillar array 30 is formed on the substrate 1 after the first gate trench K2 and the second gate trench K3 are formed; the semiconductor pillar array 30 includes semiconductor pillars 31 extending along a third direction Z, and the third direction Z intersects the first direction X and the second direction Y.

[0183] forming a capacitor structure 91 located on one side of the semiconductor pillar 31 along the third direction Z, and connecting the capacitor structure 91 to the semiconductor pillar 31 and a common terminal, wherein the capacitor structure 91 extends along the third direction Z;

[0184] A bit line 92 is formed on the other side of the semiconductor pillar 31 along the third direction Z. The bit line 92 extends along the first direction X and is connected to the semiconductor pillar 31 .

[0185] Specifically, as shown in Figures 2 to 9, the steps of forming the semiconductor pillar array 30 include forming an isolation groove K1, then forming a separation structure 211, and forming a first gate trench K2 and a second gate trench K3 on the substrate 1, followed by forming a plurality of semiconductor pillars 31 arrayed and shielded along the first direction X and the second direction Y. As shown in Figures 3 and 4, a first dielectric layer 55 is first deposited along the third direction Z to cover the substrate 1 to protect the surface of the substrate 1, forming a structure in which the substrate 1 and the first dielectric layer 55 are stacked in sequence along the third direction Z as shown in Figures 3 and 4. The constituent material of the first dielectric layer 55 may include any one or more of silicon oxide, silicon nitride, aluminum oxide, or silicon oxynitride. As shown in Figures 5 and 6, a plurality of isolation trenches K1 extending along the third direction Z and spaced apart along the first direction X are formed in the substrate 1, and as shown in Figures 7 and 8, the inner walls of the isolation trenches K1 are filled with a dielectric material 66.

[0186] In some specific examples, multiple isolation trenches K1 may be formed in the substrate 1, or multiple isolation trenches K1 may be formed in the structure shown in Figures 3 and 4 as shown in Figures 5 and 6. As shown in Figures 5 and 6, the multiple isolation trenches K1 extend along the second direction Y and are arranged at intervals along the first direction X, and the isolation trenches K1 extend along the third direction Z but do not penetrate the substrate 1.

[0187] The step of forming the isolation trenches K1 includes etching the surface of the first dielectric layer 55 as shown in FIG4 to form isolation trenches K1 extending along the third direction Z and spaced apart along the first direction X. The isolation trenches K1 may extend along the third direction Z to the substrate 1 but do not penetrate the substrate 1. As shown in FIG5 and FIG6 , during the etching process, a mask (not shown) may be used to cover portions of the surface of the substrate 1 or the first dielectric layer 55, i.e., the areas where the isolation trenches K1 are to be formed. The surface of the substrate 1 is then etched along the thickness direction of the substrate 1 (i.e., the third direction Z). Outside the areas covered by the mask, portions of the substrate 1 and the first dielectric layer 55 are etched away, forming grooves of a certain depth, i.e., the isolation trenches K1 described above. It should be noted that the etching depth for forming the isolation trenches K1 is less than the initial thickness of the substrate 1, i.e., the etching process does not penetrate the substrate 1.

[0188] In some specific examples, etching can be performed using processes such as photolithography (PH) or dry etching (ET), for example, electron beam lithography, plasma etching, or reactive ion etching, which is not limited in some embodiments of the present application.

[0189] In some embodiments of the present application, by etching the entire surface of the substrate 1 to synchronously form a plurality of isolation trenches K1 having the same depth, the manufacturing process can be simplified and the efficiency can be improved.

[0190] In some specific examples, FIG7 is a top view of a dielectric material 66 deposited in an isolation trench K1 according to some embodiments of the present application, and FIG8 is a cross-sectional structural view of a dielectric material 66 deposited in an isolation trench K1 according to some embodiments of the present application. After forming the isolation trench K1 as shown in FIG5 and FIG6 , as shown in FIG7 and FIG8 , a dielectric material 66 is deposited in the isolation trench K1 using a deposition process.

[0191] In some embodiments, dielectric material 66 includes but is not limited to any one of silicon nitride, silicon oxide, or silicon oxynitride, or any combination thereof. Silicon oxide herein refers to a silicon oxide compound, such as SixOy, and silicon nitride refers to a silicon nitrogen compound, such as SixNy.

[0192] Since isolation trenches K1 are formed as shown in Figures 5 and 6, and multiple isolation trenches K1 are arranged at intervals along the first direction X, a separation structure 211 for separating two adjacent isolation trenches K1 will be present between the isolation trenches K1 formed by removing a portion of semiconductor material in the substrate 1. Figure 9 is a top view of the etching process for forming the first gate trench K2, the second gate trench K3, and the shield trench K4, as provided in some embodiments of the present application. Figure 10 is a cross-sectional structural view of the etching process for forming the first gate trench K2, the second gate trench K3, and the shield trench K4, as provided in some embodiments of the present application. As shown in Figures 9 and 10, part of the dielectric material 66 filled between the separation structures 211 in the substrate 1 is removed to form a first gate trench K2, a second gate trench K3 and a shielding trench K4. A plurality of first gate trenches K2, second gate trenches K3 and shielding trenches K4 arranged at intervals along the second direction Y expose adjacent separation structures 211, thereby forming semiconductor pillars 31 distributed in an array between the first gate trench K2 and the shielding trench K4, and between the second gate trench K3 and the shielding trench K4, as shown in Figure 9, along the second direction Y.

[0193] It should be noted that during the actual deposition of the dielectric material 66, the dielectric material 66 will cover the surface of the partition structure 211. As shown in FIG7 , each partition structure 211 is surrounded by the dielectric material 66. In addition, after the deposition is completed, a chemical mechanical polishing (CMP) process can be used to polish away excess dielectric material 66 to achieve planarization.

[0194] In some embodiments of the present application, the deposition method of the dielectric material 66 and the first dielectric layer 55 may be, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), and atomic layer deposition (ALD).

[0195] The step of forming the capacitor structure 91 includes: as shown in Figures 22 and 23, forming a capacitor array 93 at one end of the semiconductor pillar array 30 in the third direction Z, and making the capacitor array 93 include a plurality of capacitor structures 91 arranged in an array along the first direction X and the second direction Y and extending in the third direction Z. The capacitor structure 91 includes a first electrode layer (not shown in the figure) connected to one side of the semiconductor pillar 31 in the third direction Z, and a capacitor dielectric layer (not shown in the figure) and a second electrode layer (not shown in the figure) located within the first electrode layer. The second electrode layer of the capacitor structure 91 is connected to a common terminal. The drains of the semiconductor pillars 31 in the same row (i.e., the semiconductor pillars 31 arranged at intervals along the first direction X) are connected to form a bit line 92 (BL).

[0196] In some embodiments, further comprising:

[0197] The first gate line lead-out structure 50 and the second gate line lead-out structure 60 are respectively formed at one end of the first gate structure 10 away from the capacitor structure 91 along the third direction Z, the third gate line lead-out structure 70 and the fourth gate line lead-out structure 80 are respectively formed at one end of the second gate structure 20 away from the capacitor structure 91 along the third direction Z, and the shield lead-out structure 90 is formed at one end of the shield structure 40 away from the capacitor structure 91 along the third direction Z. The specific contents of the embodiments of the present application can be referred to the above embodiments and will not be repeated here.

[0198] In some embodiments, the steps of forming the first gate line lead-out structure 50 , forming the third gate line lead-out structure 70 , and forming the shield lead-out structure 90 further include:

[0199] The first gate line lead-out structure 50 and the second gate line lead-out structure 60 are respectively formed at one end of the first gate structure 10 away from the capacitor structure 91 along the third direction Z, the third gate line lead-out structure 70 and the fourth gate line lead-out structure 80 are respectively formed at one end of the second gate structure 20 away from the capacitor structure 91 along the third direction Z, and the shield lead-out structure 90 is formed at one end of the shield structure 40 close to the capacitor structure 91 along the third direction Z. The specific contents of the embodiments of the present application can be referred to the above embodiments and will not be repeated here.

[0200] Based on the above-mentioned semiconductor device 100 and its manufacturing method, with reference to FIG27 , an embodiment of the present application further provides a memory 320 , wherein the memory 320 includes:

[0201] The array storage structure 321 includes the semiconductor device 100 of the embodiment shown in Figures 3 to 26; and a peripheral circuit 322, which is connected to the array storage structure 321 to control the bias voltage of the array storage structure 321.

[0202] Based on the above-mentioned semiconductor device 100 and its manufacturing method, referring to Figure 27, an embodiment of the present application also provides a storage system 300, which includes a memory 320 as shown in Figure 27, and a controller coupled to the memory 320, and the controller is used to control the memory to perform data writing and reading operations.

[0203] Specifically, as shown in FIG27 , the storage system 300 includes a controller 310 and one or more memories 320, wherein the memory 320 (3D NAND Flash) includes an array storage structure 321 (array) and a peripheral circuit 322 (periphery circuit), wherein the array storage structure 321 includes any of the semiconductor devices 100 described above. The storage system 300 can communicate with the host 400 through the controller 310, wherein the controller 310 can be connected to the one or more memories 320 via channels in the one or more memories 320. Each memory 320 can be managed by the controller 310 via the channels in the memory 320.

[0204] Specifically, the array storage structure 321 is used to store information, and the peripheral circuit 322 can be located above or below the array storage structure 321, or can be located around the array storage structure 321. The peripheral circuit 322 is used to control the corresponding array storage structure 321. In addition, the semiconductor device 100 can also be applied to other microelectronic devices, such as non-volatile flash memory (Nor Flash), etc., without specific limitation. In addition, the semiconductor device 100 of the embodiment of the present application can be a memory 320, or can be part of a peripheral memory, without special limitation.

[0205] The above is a detailed introduction to a semiconductor device 100 and its manufacturing method, and a storage system 300 provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for manufacturing a semiconductor device, wherein: include: providing a substrate; A plurality of first gate trenches and second gate trenches extending along a first direction are formed in the substrate, wherein the plurality of first gate trenches and the plurality of second gate trenches are alternately arranged along a second direction; the second direction intersects the first direction; forming a first gate structure in the first gate trench, and making the first gate structure include a first gate line and a second gate line, and a first isolation structure located between the first gate line and the second gate line; forming a second gate structure in the second gate trench, and making the second gate structure include a third gate line and a fourth gate line, and a second isolation structure located between the third gate line and the fourth gate line; Wherein, two adjacent first isolation structures and second isolation structures are arranged opposite to each other along the second direction, and the first isolation structure and the second isolation structure are both located on the same side in the first direction.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: Also includes: The first gate structure further includes a third isolation structure located between the first gate line and the second gate line and located on the other side in the first direction; The second gate structure further includes a fourth isolation structure located between the third gate line and the fourth gate line and located on the other side in the first direction; Wherein, two adjacent third isolation structures and the fourth isolation structures are arranged opposite to each other along the second direction.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: Also includes: The first isolation structure and the third isolation structure of the same first gate structure are located on different sides along the second direction; The second isolation structure and the fourth isolation structure of the same second gate structure are located along the Different sides in the second direction.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The step of forming the first gate structure further comprises: forming a first oxide layer on the inner wall of the first gate trench; forming a first conductive layer on an inner wall of the first oxide layer; forming a first spacing structure in the first conductive layer; The first isolation structure is formed on the first side of the first end of the first conductive layer, and the third isolation structure is formed on the second side of the second end of the first conductive layer, so as to separate the first gate line and the second gate line formed by the first conductive layer, wherein the first end and the second end are opposite ends of the first conductive layer in the first direction, and the first side and the second side are opposite sides of the first conductive layer in the second direction.

5. The method for manufacturing a semiconductor device according to claim 2, wherein: The production method further comprises the steps of: A plurality of shielding trenches extending along a first direction are formed in the substrate, wherein the shielding trenches are located between adjacent first gate trenches and second gate trenches along a second direction; as well as, A shielding structure is formed in the shielding trench.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: Also includes: forming a first gate line lead-out structure and a second gate line lead-out structure, and connecting the first gate line lead-out structure to the first gate line at a first end of the first gate structure along the first direction, and connecting the second gate line lead-out structure to the second gate line at a second end of the first gate structure along the first direction; forming a third gate line lead-out structure and a fourth gate line lead-out structure, and connecting the third gate line lead-out structure to the third gate line at a first end of the second gate structure along the first direction, and connecting the fourth gate line lead-out structure to the fourth gate line at a second end of the second gate structure along the first direction; Form a shielding lead-out structure, and connect the shielding lead-out structure to the shielding structure along the first One end of the direction.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The plurality of shielding structures include shielding structures in odd rows and shielding structures in even rows that are alternately arranged along the second direction, and the step of forming a shielding lead-out structure further includes: The plurality of shielding lead-out structures are respectively connected to the first ends of the shielding structures in odd rows and the second ends of the shielding structures in even rows, wherein the first end and the second end are two opposite ends of each shielding structure along the first direction.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The step of forming the shielding lead-out structure further comprises: The shielding lead-out structure is formed between the adjacent first isolation structure and the second isolation structure, or the shielding lead-out structure is formed between the adjacent third isolation structure and the fourth isolation structure.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: Also includes: forming a separation structure extending along the second direction and arranged at intervals along the first direction on the substrate, so that the substrate forms a semiconductor column array after the first gate trench and the second gate trench are formed; the semiconductor column array includes semiconductor columns extending along a third direction, and the third direction intersects the first direction and the second direction; forming a capacitor structure located on one side of the semiconductor column along the third direction, and connecting the capacitor structure to the semiconductor column and a common end, wherein the capacitor structure extends along the third direction; A bit line is formed on the other side of the semiconductor pillar along the third direction, the bit line extending along the first direction and connected to the semiconductor pillar.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: Also includes: The first gate line lead-out structure and the second gate line lead-out structure are respectively formed at one end of the first gate structure away from the capacitor structure along the third direction, and the third gate line lead-out structure and the fourth gate line lead-out structure are respectively formed at one end of the second gate structure away from the capacitor structure along the third direction; The shielding lead-out structure is formed at one end of the shielding structure away from the capacitor structure along the third direction; or the shielding lead-out structure is formed at one end of the shielding structure close to the capacitor structure along the third direction.

11. A semiconductor device, wherein: include: A transistor array, the transistor array comprising a plurality of first gate structures and second gate structures extending along a first direction and arranged alternately and spaced apart along a second direction; the second direction intersects the first direction; The first gate structure includes a first gate line and a second gate line, and a first isolation structure located between the first gate line and the second gate line; The second gate structure includes a third gate line and a fourth gate line, and a second isolation structure located between the third gate line and the fourth gate line; Wherein, two adjacent first isolation structures and second isolation structures are arranged opposite to each other along the second direction, and the first isolation structure and the second isolation structure are both located on the same side in the first direction.

12. The semiconductor device according to claim 11, wherein The first gate structure further includes a third isolation structure located between the first gate line and the second gate line and located on the other side in the first direction; The second gate structure further includes a fourth isolation structure located between the third gate line and the fourth gate line and located on the other side in the first direction; Wherein, two adjacent third isolation structures and the fourth isolation structures are arranged opposite to each other along the second direction.

13. The semiconductor device according to claim 12, wherein: The first isolation structure and the third isolation structure of the same first gate structure are located at different sides along the second direction, and the second isolation structure and the fourth isolation structure of the same second gate structure are located at different sides along the second direction.

14. The semiconductor device according to claim 13, wherein: The first gate structure further includes: a first spacing structure located between the first gate line and the second gate line and extending along the first direction; and a first oxide layer located outside each of the first gate line and the second gate line away from each other; The second gate structure further includes: a second spacing structure located between the third gate line and the fourth gate line and extending along the first direction; and a second oxide layer located outside the third gate line and the fourth gate line and away from each other.

15. The semiconductor device according to claim 11, wherein The semiconductor device further comprises: A plurality of shielding structures are provided extending along a first direction, and the shielding structures are located between adjacent first gate structures and second gate structures along a second direction.

16. A semiconductor device, wherein: The semiconductor device according to any one of claims 11 to 15, comprising: A transistor array, the transistor array comprising a plurality of first gate structures and second gate structures extending along a first direction and arranged alternately and spaced apart along a second direction; the second direction intersects the first direction; The first gate structure includes a first gate line and a second gate line, and a first isolation structure located between the first gate line and the second gate line; The second gate structure includes a third gate line and a fourth gate line, and a second isolation structure located between the third gate line and the fourth gate line; and, A first gate line lead-out structure connected to the first gate line at a first end of the first gate structure along the first direction, and a second gate line lead-out structure connected to the second gate line at a second end of the first gate structure along the first direction; a third gate line lead-out structure connected to the third gate line at a first end of the second gate structure along the first direction, and a fourth gate line lead-out structure connected to the fourth gate line at a second end of the second gate structure along the first direction; Wherein, two adjacent first isolation structures and second isolation structures are arranged opposite to each other along the second direction, and the first isolation structure and the second isolation structure are both located on the same side in the first direction.

17. The semiconductor device according to claim 16, wherein: The semiconductor device further comprises: A plurality of shielding structures extending along a first direction, wherein the shielding structures are located between adjacent first gate structures and second gate structures along a second direction; A shielding lead-out structure is connected to one end of the shielding structure along the first direction.

18. The semiconductor device according to claim 17, wherein: The multiple shielding structures include odd-numbered row shielding structures and even-numbered row shielding structures arranged in an alternating manner along the second direction, and the multiple shielding lead-out structures are respectively connected to the first ends of the odd-numbered row shielding structures and the second ends of the even-numbered row shielding structures, and the first end and the second end are the opposite ends of each shielding structure along the first direction.

19. The semiconductor device according to claim 18, wherein: The shielding lead-out structure is located between the adjacent first isolation structure and the second isolation structure, or between the adjacent third isolation structure and the fourth isolation structure.

20. The semiconductor device according to claim 17, wherein Also includes: A semiconductor column array; the semiconductor column array comprises a plurality of semiconductor columns arranged in an array along the first direction and the second direction and extending along a third direction, the third direction intersecting the first direction and the second direction, and the semiconductor columns are located between the adjacent shielding structure and the first gate structure or the second gate structure; a capacitor structure located on one side of the semiconductor column along the third direction, the capacitor structure being connected to the semiconductor column and a common end, and extending along the third direction; a bit line located at the other side of the semiconductor column along the third direction, the bit line extending along the first direction and connected to the semiconductor column; The first gate line lead-out structure and the second gate line lead-out structure are located at one end of the first gate structure along the third direction away from the capacitor structure, the third gate line lead-out structure and the fourth gate line lead-out structure are located at one end of the second gate structure along the third direction away from the capacitor structure, and the shielding lead-out structure is located at one end of the shielding structure along the third direction away from the capacitor structure; or, the shielding lead-out structure is located at one end of the shielding structure along the third direction close to the capacitor structure.

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