Radio-frequency switch circuit, integrated circuit chip, radio-frequency front-end module, and communication device

Abstract

The embodiments of the present application relate to the technical field of electronics and are used for improving the voltage-withstand capability of a radio-frequency switch circuit. Provided are a radio-frequency switch circuit, an integrated circuit chip, a radio-frequency front-end module, and a communication device. The radio-frequency switch circuit comprises a bias voltage output circuit, a level conversion circuit and a switch circuit, wherein the bias voltage output circuit comprises a plurality of body-terminal bias voltage output ends, which are used for outputting body-terminal bias voltages; the level conversion circuit is used for receiving a signal output by the bias voltage output circuit, and outputting a plurality of body-terminal bias voltages, the values of which are not completely identical or are completely different; and the switch circuit comprises a plurality of body terminals and a plurality of device groups, switch devices in the same device group receive the body-terminal bias voltages by means of the same body terminal, and switch devices in different device groups receive different body-terminal bias voltages, such that source-body parasitic capacitance and drain-body parasitic capacitance of switch devices at each stage tend to be equal, and swings in source-drain voltages of switch devices a first stage are equalized, thereby improving the voltage-withstand capability of the radio-frequency switch circuit.

Description

RF switching circuits, integrated circuit chips, RF front-end modules, communication equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on September 27, 2023, with application number 202311270658.X and application name “RF switching circuit, integrated circuit chip, RF front-end module, communication equipment”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of electronic technology, and in particular to a radio frequency switching circuit, an integrated circuit chip, a radio frequency front-end module, and a communication device. Background Art

[0003] With the rapid development of information communication, wireless communication technology has been widely used and has become an indispensable part of information communication. In wireless communication technology, radio frequency switching circuit is one of the components.

[0004] The switching circuit in an RF switch circuit typically includes multiple switching devices connected in series to withstand the RF high voltage and improve the RF switch circuit's voltage withstand capability. However, due to parasitic effects in the switching devices, the source-drain voltage swings experienced by each switching device in each stage are uneven, resulting in different voltage withstand capabilities of the switching devices in different stages (for example, the previous stage switching device is prone to breakdown, which can cause the entire RF switch circuit to burn out and fail), thus affecting the RF switch circuit's voltage withstand capability.

[0005] Summary of the Invention

[0006] Embodiments of the present application provide a radio frequency switching circuit, an integrated circuit chip, a radio frequency front-end module, and a communication device for improving the voltage resistance of the radio frequency switching circuit.

[0007] To achieve the above objectives, this application adopts the following technical solutions:

[0008] According to a first aspect of an embodiment of the present application, a radio frequency switching circuit is provided. The radio frequency switching circuit can be a single-pole single-throw switching circuit or a single-pole multiple-throw switching circuit. The radio frequency switching circuit includes a bias voltage output circuit, a first level conversion circuit, and a first switching circuit. The bias voltage output circuit includes a plurality of body-end bias voltage output terminals for outputting body-end bias voltages. The first level conversion circuit includes a first control terminal, a plurality of first input terminals, a reference ground voltage terminal, and a plurality of first output terminals; the plurality of first input terminals are coupled to the plurality of body-end bias voltage output terminals in a one-to-one correspondence; the first control terminal is used to receive a first control signal, and the first level conversion circuit is used to output a reference ground voltage or a first body-end bias voltage from the first output terminal under the control of the first control signal; at least two of the plurality of first body-end bias voltages outputted from the plurality of first output terminals have different values. The first switching circuit includes multiple first body terminals and multiple first device groups; the multiple first body terminals are coupled to the multiple first output terminals in a one-to-one manner; the first switching circuit includes multiple stages of first switching devices coupled in series, each first device group includes at least one stage of first switching devices, and the first switching devices in the same first device group are coupled to the same first body terminal.

[0009] In the RF switch circuit provided in an embodiment of the present application, multiple stages of first switching devices are divided into multiple first device groups. The first switching devices in the multiple first device groups are coupled to different first body terminals, and the first body terminal bias voltages received by the multiple first body terminals are not completely the same or completely different. As a result, the source voltage and drain voltage of each stage of the first switching device are not fixed, and the body voltage of each stage of the first switching device is also not fixed. In combination with the source voltage and drain voltage of each stage of the first switching device, the body voltage of each stage of the first switching device is matched and adjusted to change the source-body voltage and drain-body voltage of each stage of the first switching device, so that the source-body parasitic capacitance and the drain-body parasitic capacitance of each stage of the first switching device are close to equal, thereby balancing the source-drain voltage swing of each stage of the first switching device and improving the voltage withstand capability of the RF switch circuit. In addition, the first body-end bias voltage required by the first switching circuit is output by analog circuits such as the bias voltage output circuit and the first level conversion circuit. The design stability and processing consistency of the analog circuit are high, the compensation consistency of the body-source parasitic capacitance and the body-drain parasitic capacitance is good, and the source-drain voltage balance consistency of the first switching circuit is good, which also avoids the problem of poor source-drain voltage balance effect caused by fluctuations in process parameters.

[0010] In a possible implementation, along the direction of the cascade connection of the first switching devices, the first body terminal bias voltage received by the plurality of first body terminals gradually decreases.

[0011] The source voltage and drain voltage of each stage of the first switching device in the first switching circuit decrease step by step. After the first body-end bias voltage received by the body of the first switching devices in multiple first device groups is set to gradually decrease, the source-body parasitic capacitance and the drain-body parasitic capacitance of each stage or every few stages of the first switching devices can be made close to equal, further balancing the swing of the source-drain voltage of each stage of the first switching devices and improving the voltage resistance of the first switching circuit.

[0012] In one possible implementation, the difference between the first-body-terminal bias voltages received by two adjacent first-body terminals is a fixed value. When the first-body-terminal bias voltage decreases according to a fixed pattern, the design difficulty of the first switching circuit can be reduced, which helps further optimize the source-drain voltage swing experienced by the multi-stage first switching devices.

[0013] In one possible implementation, the bias voltage output circuit also includes a gate bias voltage output terminal, and the first switching circuit also includes a first gate terminal; the first gate terminal is coupled to the gate bias voltage output terminal, and the gates of the multi-stage first switching devices are respectively coupled to the first gate terminal.

[0014] By coupling the gates of the multi-stage first switching devices to the same first gate terminal, the multi-stage first switching devices receive the same first gate terminal bias voltage, which can avoid the problem that when the multi-stage first switching devices receive different first gate terminal bias voltages, the first few first device groups receive larger first gate terminal bias voltages, and the static point of the switch is close to the threshold voltage, which leads to a significant deterioration in the switching harmonic performance.

[0015] In a possible implementation, multiple stages of first switching devices in the same first device group are sequentially coupled in series.

[0016] For the first switching circuit, the source and drain voltages experienced by multiple stages of first switching devices connected in series decrease with each stage. The first body-side bias voltage received by the first switching circuit also gradually decreases. Therefore, after the first switching devices are grouped in stages, the first body-side bias voltage received by the subsequent first switching devices will not be higher than the first body-side bias voltage received by the previous first switching devices. This ensures that the body-source parasitic capacitance and body-drain parasitic capacitance generated by each stage of first switching devices are approximately equal, thereby making the voltage drop across each stage of first switching devices approximately equal, thereby balancing the source-drain voltage swing experienced by each stage of first switching devices.

[0017] In one possible implementation, the multiple body-side bias voltage output terminals are configured to output multiple body-side bias voltages, with at least two of the multiple body-side bias voltages having different values. The body-side bias voltage terminals directly output the different body-side bias voltages, and the first level shifter circuit only performs a selection function, thereby simplifying the structure of the first level shifter circuit.

[0018] In one possible implementation, the bias voltage output circuit includes a negative voltage circuit; the negative voltage circuit includes multiple body-side bias voltage output terminals and multiple charge pumps coupled in series, with the multiple body-side bias voltage output terminals being coupled to the output terminals of the multiple charge pumps in a one-to-one correspondence. This is a simple implementation.

[0019] In one possible implementation, the bias voltage output circuit further includes an oscillation signal generating circuit and a voltage multiplier circuit. The oscillation signal generating circuit receives a reference voltage and generates an oscillation signal. The voltage multiplier circuit receives the reference voltage and the oscillation signal and outputs a gate bias voltage from a gate bias voltage output terminal. The negative voltage circuit receives the oscillation signal and outputs a bulk bias voltage from a bulk gate bias voltage output terminal. This is a simple implementation.

[0020] In one possible implementation, the reference voltage ranges from 0.5V to 2.5V. If the reference voltage is too high, the body bias voltages of adjacent device groups will differ significantly, resulting in poor source-drain voltage balancing and the need to increase the power supply voltage, which results in high power consumption. If the reference voltage is too low, the number of voltage multiplication stages required increases, leading to a significant increase in the number of negative charge pumps.

[0021] In one possible implementation, the difference between the first-body bias voltages received by two adjacent first-body terminals is an integer multiple of a reference voltage. By limiting the difference between the first-body bias voltages received by different first device groups to the same value as the reference voltage, or to a multiple of the reference voltage, the source-drain voltages of the first switching devices can be effectively balanced.

[0022] In one possible implementation, the first switching circuit further includes multiple voltage-dividing structures, each of which has two ends coupled to the first source and the first drain of the same first switching device. By providing a voltage-dividing structure corresponding to each stage of switching devices in the switching circuit and adjusting the equivalent resistance of the voltage-dividing structure, the voltage drop across each stage of switching devices can be made equal or have a clear regular pattern.

[0023] In one possible implementation, the theoretical breakdown voltage of the first switching circuit is MV, the actual breakdown voltage of the first switching circuit is NV, and the value of M / N is 1-2. In the embodiment of the present application, after the multiple stages of first switching devices are grouped and receive different first body-terminal bias voltages, the source-drain voltage swing of each stage of the first switching device is relatively balanced. Therefore, when subjected to the same RF voltage, the number of stages of first switching devices included in the first switching circuit provided by the embodiment of the present application can be reduced, and the value of M / N can be reduced, thereby optimizing insertion loss and area.

[0024] In one possible implementation, the radio frequency voltage received by the first-stage first switching device is 40V, and the number of stages of the first switching devices in the first switching circuit is less than or equal to 11. This is a common application scenario.

[0025] In one possible implementation, the radio frequency voltage received by the first switching device in the first stage is 35V, and the number of stages of the first switching devices in the first switching circuit is less than or equal to 11. This is a common application scenario.

[0026] In one possible implementation, the radio frequency voltage received by the first-stage first switching device is 30V, and the number of stages of the first switching devices in the first switching circuit is less than or equal to 10. This is a common application scenario.

[0027] In one possible implementation, the RF switching circuit also includes a second level conversion circuit and a second switching circuit; the second level conversion circuit includes a second control terminal, multiple second input terminals, a reference ground voltage terminal and multiple second output terminals; the multiple second input terminals are coupled one-to-one with the multiple body-terminal bias voltage output terminals; the second control terminal is used to receive a second control signal, and the second level conversion circuit is used to output a reference ground voltage or a second body-terminal bias voltage from the second output terminal under the control of the second control signal; at least two of the multiple second body-terminal bias voltages output by the multiple second output terminals have different values; the second switching circuit includes multiple second body terminals and multiple second device groups; the multiple second body terminals are coupled one-to-one with the multiple second output terminals; the second switching circuit includes multiple stages of second switching devices coupled in series, each second device group includes at least one stage of second switching device, and the second switching devices located in the same second device group are coupled to the same second body terminal.

[0028] In the case where the radio frequency switching circuit includes multiple groups of switching circuits, the multiple groups of switching circuits can share the same bias voltage output circuit, which can save device area.

[0029] According to a second aspect of an embodiment of the present application, an integrated circuit chip is provided, comprising a radio frequency switching circuit and a packaging layer, wherein the packaging layer covers the radio frequency switching circuit; the radio frequency switching circuit comprises the radio frequency switching circuit of any one of the first aspects.

[0030] According to a third aspect of an embodiment of the present application, a radio frequency front-end module is provided, comprising a radio frequency switching circuit and a filter, wherein the radio frequency switching circuit is coupled to the filter; the radio frequency switching circuit comprises the radio frequency switching circuit of any one of the first aspects.

[0031] According to a fourth aspect of an embodiment of the present application, a communication device is provided, comprising an antenna and a radio frequency switching circuit, wherein the antenna and the radio frequency switching circuit are coupled; the radio frequency switching circuit comprises the radio frequency switching circuit of any one of the first aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] FIG1 is a schematic structural diagram of a communication device provided in an embodiment of the present application;

[0033] FIG2A is a schematic structural diagram of an RF front-end module provided in an embodiment of the present application;

[0034] FIG2B is a schematic diagram of an application of a radio frequency switch circuit in an RF front-end module according to an embodiment of the present application;

[0035] FIG3 is an application diagram of a wireless communication system front end provided in an embodiment of the present application;

[0036] FIG4A is a schematic diagram of a topological structure of a switching circuit according to an embodiment of the present application;

[0037] FIG4B is a diagram of an equivalent capacitance model of the switch device in FIG4A when it is turned off;

[0038] FIG4C is a diagram of an equivalent capacitance model of the switch circuit in FIG4A when the switch circuit is turned off;

[0039] 5A and 5B are schematic diagrams of a topological structure of a switching circuit according to an embodiment of the present application;

[0040] FIG5C is a simulation yield curve diagram of the switch circuit shown in FIG5A and FIG5B ;

[0041] FIG6 is a schematic diagram of a topological structure of another switching circuit according to an embodiment of the present application;

[0042] FIG7 is a schematic diagram of a topological structure of another switching circuit according to an embodiment of the present application;

[0043] 8A and 8B are schematic diagrams of a topological structure of a switching circuit provided in an embodiment of the present application;

[0044] FIG9 is a schematic diagram of a radio frequency switch circuit according to an embodiment of the present application;

[0045] FIG10 is a schematic diagram of a radio frequency switch circuit according to an embodiment of the present application;

[0046] FIG11 is a schematic diagram of a topological circuit of a negative voltage circuit provided in an embodiment of the present application;

[0047] FIG12 is a schematic diagram of a topology circuit of a first level conversion circuit provided in an embodiment of the present application.

[0048] FIG13 is an architecture diagram of a radio frequency switch circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0050] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature qualified as "second," "first," etc., may explicitly or implicitly include one or more of such features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0051] In the embodiments of the present application, directional terms such as "up", "down", "left" and "right" may be defined including but not limited to the orientation relative to the components schematically placed in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly according to changes in the orientation of the components in the drawings.

[0052] In the embodiments of this application, unless otherwise specified or limited, the term "connection" should be understood in a broad sense. For example, "connection" can mean fixed connection, detachable connection, or integration; it can mean direct connection or indirect connection through an intermediate medium. In addition, the term "coupling" can mean direct electrical connection or indirect electrical connection through an intermediate medium. The term "contact" can mean direct contact or indirect contact through an intermediate medium.

[0053] In the embodiments of the present application, "and / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, and B exists alone. A and B can be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0054] The technical solution of the present application can be applied to various communication devices including radio frequency switches. The communication device can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted. It can also be deployed on the water (such as a ship). It can also be deployed in the air (such as on an airplane, balloon, or satellite). For example, the channel device can be a terminal or a base station. For example, the terminal includes but is not limited to: mobile phones, tablet computers, laptops, PDAs, mobile internet devices (MIDs), wearable devices (such as smart watches, smart bracelets, pedometers, etc.), vehicle-mounted equipment (such as cars, bicycles, electric vehicles, airplanes, ships, trains, high-speed railways, etc.), virtual reality (VR) equipment, augmented reality (AR) equipment, wireless terminals in industrial control, smart home devices (such as refrigerators, televisions, air conditioners, electricity meters, etc.), intelligent robots, workshop equipment, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, or wireless terminals in smart homes, flight equipment (such as intelligent robots, hot air balloons, drones, airplanes), RF front-end modules, low-noise amplifiers, etc.

[0055] Figure 1 is a schematic diagram of the structure of a communication device provided in an embodiment of the present application, using a mobile phone as an example. The communication device includes a radio frequency (RF) front-end module 101, a memory 102, a processor 103, a sensor component 104, a multimedia component 105, a power supply component 106, an input / output interface 107, and an antenna radiator 108.

[0056] The following is a detailed introduction to the various components of the mobile phone in conjunction with Figure 1:

[0057] The RF front-end module 101 can be used to send and receive information or receive and transmit signals during a call. For example, it receives downlink data from the communication device via the antenna radiator 108 and sends it to the processor 103 for processing. It also sends uplink data to the antenna radiator 108 and transmits it out of the communication device via the antenna radiator 108.

[0058] The memory 102 may be used to store data, software programs, and modules. The mobile phone may include high-speed random access memory and non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0059] The processor 103 is the control center of the mobile phone. It uses various interfaces and lines to connect various parts of the entire device. By running or executing software programs and / or modules stored in the memory 102 and calling data stored in the memory 102, it performs various functions of the mobile phone and processes data, thereby monitoring the mobile phone as a whole.

[0060] Sensor assembly 104 includes one or more sensors for assessing various aspects of the phone's status. Sensor assembly 104 may include an accelerometer, a gyroscope, a magnetic sensor, a pressure sensor, or a temperature sensor. Sensor assembly 104 can detect the phone's acceleration / deceleration, orientation, open / closed state, relative positioning of components, or temperature changes. Sensor assembly 104 may also include a light sensor for use in imaging applications.

[0061] The multimedia component 105 provides a screen as an output interface between the mobile phone and the user. The screen may be a touch panel, and when the screen is a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. In addition, the multimedia component 105 also includes at least one camera, for example, the multimedia component 105 includes a front camera and / or a rear camera.

[0062] The power supply component 106 is used to provide power to various components of the mobile phone. The power supply component 106 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the mobile phone.

[0063] The input / output interface 107 provides an interface between the processor 103 and a peripheral interface module, for example, the peripheral interface module may be a keyboard, a mouse, etc.

[0064] Although not shown, the mobile phone may further include an audio component and a communication module, for example, the audio component includes a microphone and a speaker, and the communication module may include one or more of a wireless fidelity (WiFi) module, a Bluetooth module, a near field communication (NFC) module, a global navigation satellite system (GNSS) module, or a frequency modulation (FM) module, which will not be described in detail in the embodiments of the present application. Those skilled in the art will understand that the mobile phone structure shown in FIG1 does not constitute a limitation on the mobile phone, and may include more or fewer components than shown, or combine certain components, or arrange the components differently.

[0065] With the rapid development of information and communications, wireless communication technology has been widely used and has become an indispensable part of information and communications. In wireless communication technology, radio frequency switching circuits are one of the components. The following is a schematic illustration of the locations where radio frequency switching circuits may be used in the communication devices provided in the embodiments of the present application.

[0066] In some embodiments, the RF front-end module 101 generally includes a transmitting channel and a receiving channel, and switching between the transmitting channel and the receiving channel can be achieved by the radio frequency switching circuit 2.

[0067] FIG2A is a schematic structural diagram of an RF front-end module provided in an embodiment of the present application.

[0068] Typically, the RF front-end module 101 includes, but is not limited to, a radio frequency switch circuit 2, a filter, a power amplifier circuit (PA), a low noise amplifier (LNA), etc. For example, as shown in FIG2A , the RF front-end module 101 may include: a radio frequency switch circuit 2, a filter, a PA, and an LNA.

[0069] The RF front-end module 101 may include a transmitting channel (transmitter, TX) and a receiving channel (receiver, RX). The transmitting channel TX includes a PA and a transmitting channel filter. The RF output end of the PA is coupled to the input end of the transmitting channel filter. The receiving channel RX includes an LNA and a receiving channel filter. The output end of the receiving channel filter is coupled to the RF input end of the LNA.

[0070] RF switch circuit 2 is responsible for switching between the receive channel RX and the transmit channel TX. The baseband signal is transmitted to the transmit channel TX via the transceiver. The transmit channel TX amplifies the received RF signal and outputs it to the antenna radiator 108, where it is then transmitted. The PA amplifies the RF signal on the transmit channel TX, while the transmit channel filter filters the RF signal on the transmit channel TX.

[0071] The receive channel RX receives the RF signal from the antenna radiator 108. The RF signal is amplified by the receive channel RX and then transmitted to the baseband through the transceiver. The LNA is responsible for amplifying the RF signal of the receive channel RX, and the receive channel filter is responsible for filtering the RF signal of the receive channel RX.

[0072] FIG2B is a schematic diagram of an application of a radio frequency switching circuit in an RF front-end module provided in an embodiment of the present application.

[0073] In some embodiments, as shown in FIG2B , the transmit channel TX includes a series RF switch circuit 2 coupled in the transmit channel TX and a parallel RF switch circuit 2 coupled between the transmit channel TX and a reference ground voltage terminal (GND). The receive channel RX includes a series RF switch circuit 2 coupled in the receive channel RX and a parallel RF switch circuit 2 coupled between the receive channel RX and a reference ground voltage terminal GND.

[0074] During the operation of the RF front-end module 101, when the transmit channel TX is operating, the parallel RF switch circuit 2 connected to ground in the transmit channel TX is turned off, and the series RF switch circuit 2 in the receive channel RX is turned off. When the receive channel RX is operating, the parallel RF switch circuit 2 connected to ground in the receive channel RX is turned off, and the series RF switch circuit 2 in the transmit channel TX is turned off. RF switch circuit 2 is responsible for switching between the receive channel RX and the transmit channel TX.

[0075] When the RF switch circuit 2 is turned off, both ends of the RF switch circuit 2 will be subjected to a relatively high power (tens of volts) RF voltage. The voltage resistance of the RF switch circuit 2 has a direct impact on the performance of the RF front-end module 101 .

[0076] With the development of wireless communication technology, communication standards have evolved from 3G, 4G, 5G, to 6G. Early single-standard systems covering a few frequency bands have evolved to today's multi-standard systems covering dozens or even dozens of frequency bands. Switching between different frequency bands and standards is possible through RF switching circuits.

[0077] In other embodiments, the front end of the wireless communication system changes the electrical length of the antenna radiator 108 and tunes the impedance and aperture of the antenna radiator 108 through the RF switch circuit 2 .

[0078] FIG3 is an application diagram of a front end of a wireless communication system provided in an embodiment of the present application.

[0079] As shown in FIG3 , the front end of the wireless communication system includes an antenna radiator 108 , an antenna feed line 109 , and a tuned load 110 .

[0080] One end of the antenna radiator 108 is coupled to the reference ground voltage terminal GND. A feed point is located in the middle of the antenna radiator 108, and an antenna feed line 109 is coupled to the feed point. One or more RF switching circuits 2 are coupled in parallel to the antenna feed line 109, and a tuned load 110 is coupled between the RF switching circuits 2 and the reference ground voltage terminal GND. One or more RF switching circuits 2 are coupled in parallel to the arms of the antenna radiator 108, and a tuned load 110 is coupled between the RF switching circuits 2 and the reference ground voltage terminal GND. Tuned load 110 may include passive components such as capacitors and inductors.

[0081] During use of the communication device, the electrical length of the antenna radiator 108 can be changed by switching on and off a plurality of radio frequency switch circuits 2 to achieve adjustable resonant frequency of the antenna radiator 108 .

[0082] The RF voltage swing at the location of the tuned load 110 is large (up to 80V), and the RF voltage of tens of volts will be directly applied to both ends of the RF switch circuit 2 in the off state. The voltage resistance of the RF switch circuit 2 has a direct impact on the performance of the front end of the wireless communication system.

[0083] Based on this, improving the voltage resistance of the RF switch circuit 2 is a technical problem that needs to be solved by those skilled in the art, and the voltage resistance of the switching circuit in the RF switch circuit 2 directly affects the voltage resistance of the RF switch circuit 2.

[0084] Figure 4A is a schematic diagram of the topological structure of a switching circuit illustrated in an embodiment of the present application, Figure 4B is an equivalent capacitance model of the switching device in Figure 4A when it is turned off, and Figure 4C is an equivalent capacitance model of the switching circuit in Figure 4A when it is turned off.

[0085] An embodiment of the present application provides a switch circuit 20. As shown in FIG4A , the switch circuit 20 includes a multi-stage switch device T coupled in series, a gate bias circuit 21, a body bias circuit 22, and a voltage divider circuit 23.

[0086] The switching device T includes a gate g, a source s, a drain d, and a body (b). The gate g is coupled to a gate bias circuit 21, and the body b is coupled to a body bias circuit 22. The drain d (or source s) of the current-stage switching device T is coupled to the source s (or drain d) of the next-stage switching device T to achieve a series connection of multiple switching devices T. The source s (or drain d) of the first-stage switching device T and the drain d (or source s) of the last-stage switching device T serve as the two terminals of the switching circuit 20, enabling the switching circuit 20 to be coupled in series or in parallel with other circuits.

[0087] The gate bias circuit 21 includes multiple gate resistors Rg. A gate resistor Rg is connected in series between the gate g of each switching device T and the first node A1 , and a common gate resistor Rg is connected in series between the first node A1 and the gate terminal G of the switching circuit 20 .

[0088] The body bias circuit 22 includes multiple body resistors Rb. A body resistor Rb is connected in series between the body terminal b of each stage of the switching device T and the second node A2, and a common body resistor Rb is connected in series between the second node A2 and the body terminal B of the switching circuit 20.

[0089] The voltage divider circuit 23 includes a plurality of resistors R. A resistor R is connected in series between the source s and the drain d of each stage of the switching device T, so that the voltage drop of each stage of the switching device T is equal.

[0090] As shown in FIG4B , when the switch device T is in the off state, the parasitic capacitance in the switch device T includes gate-source parasitic capacitance Cgs, gate-body parasitic capacitance Cgb, gate-drain parasitic capacitance Cgd, source-drain parasitic capacitance Cds, body-source parasitic capacitance Cbs, body-drain parasitic capacitance Cbd, source-substrate parasitic capacitance Csx, body-substrate parasitic capacitance Cbx, and drain-substrate parasitic capacitance Cdx. When multiple switch devices T are connected in series, the equivalent capacitance model of the switch circuit 20 when turned off is shown in FIG4C . When multiple switch devices T are connected in series, parasitic capacitance is also generated between the switch device T and the reference ground. The parasitic capacitance in the switch device T includes gate-source parasitic capacitance Cgs, gate-drain parasitic capacitance Cgd, body-source parasitic capacitance Cbs, body-drain parasitic capacitance Cbd, gate-ground parasitic capacitance Cgp, and body-ground parasitic capacitance Cbp.

[0091] When the voltage swing to which the switching circuit 20 is subjected increases, the source-drain voltage to which each switching device T is subjected increases accordingly, causing the switching device T to easily break down. Within a certain range, the RF voltage to which a single switching device T is subjected can be reduced by increasing the number of cascaded switching devices T. However, increasing the number of stages of switching devices T will lead to a deterioration in area and insertion loss. Moreover, when the switching device T is in the off state, the parasitic capacitance of the switching device T will cause the source-drain voltage swing to which each stage of the switching device T is subjected to to be unequal, and usually the source-drain voltage swing to which the preceding stage switching device T is subjected is large, while the source-drain voltage swing to which the succeeding stage switching device T is subjected is small. This causes the preceding stage switching device T to easily break down, and then the entire switching circuit 20 burns out and fails.

[0092] 5A and 5B are schematic diagrams of a topological structure of a switching circuit according to an embodiment of the present application, and FIG5C is a simulation yield curve of the switching circuit shown in FIG5A and 5B .

[0093] The embodiment of the present application further provides a switching circuit 20, as shown in FIG5A and FIG5B , the switching circuit 20 includes a multi-stage switching device T coupled in series, a gate bias circuit 21, a body bias circuit 22, and a body feedforward capacitor Cfwd.

[0094] The gate bias circuit 21 includes a plurality of gate resistors Rg. A gate resistor Rg is connected in series between the gate g of each stage of the switching device T and the gate terminal G of the switching circuit 20 .

[0095] In some embodiments, as shown in FIG5A , the body bias circuit 22 includes a plurality of body resistors Rb and body capacitors Cb. A body resistor Rb is connected in series between the body b of each stage of the switching device T and the body terminal B of the switching circuit 20 , and a body capacitor Cb is connected in series between the body b of two adjacent stages of the switching devices T.

[0096] The bulk feedforward capacitor Cfwd is connected in series between the source s (or drain d) and the bulk b of the first-stage switching device T.

[0097] A bulk capacitor Cb is connected in series between the bulk electrodes b of two adjacent first-stage switching devices T, and a bulk feedforward capacitor Cfwd is connected in series between the source electrode s (or drain electrode d) and the bulk electrode b of the first-stage switching device T. The bulk feedforward capacitor Cfwd compensates for the bulk-drain parasitic capacitance Cbd of the first-stage switching device T, thereby compensating for the source-drain parasitic capacitance Cds of the first-stage switching device T. The bulk capacitor Cb can effectively compensate for the source-drain parasitic capacitance Cds of each subsequent stage of switching devices T, thereby balancing the parasitic capacitance of each stage and equalizing the source-drain voltage experienced by each stage of switching devices T.

[0098] In other embodiments, as shown in FIG5B , the body bias circuit 22 includes multiple body resistors Rb. A body resistor Rb is connected in series between the body terminal B of each switching device T and the body terminal B of the switching circuit 20. A body resistor Rb is also connected in series between the body terminals b of two adjacent switching devices T. A body resistor Rb is also connected in series between the source s (or drain d) and the body terminal b of the first-stage switching device T. A body feedforward capacitor Cfwd is connected in series between the source s (or drain d) and the body terminal b of the first-stage switching device T.

[0099] A bulk resistor Rb is connected in series between the bulk electrodes b of two adjacent first-stage switching devices T, and a bulk feedforward capacitor Cfwd is connected in series between the source electrode s (or drain electrode d) and the bulk electrode b of the first-stage switching device T. The bulk feedforward capacitor Cfwd compensates for the bulk-drain parasitic capacitance Cbd of the first-stage switching device T, thereby compensating for the source-drain parasitic capacitance Cds of the first-stage switching device T. Connecting bulk resistor Rb between the bulk electrodes b of adjacent switching devices T balances the source-drain voltage experienced by each switching device T.

[0100] In FIG5C , the horizontal axis represents the number of stages of the switching device T, and the vertical axis represents the source-drain voltage. As shown in FIG5C , in the switching circuit 20 shown in FIG4A , the source-drain voltage swing experienced by the switching device T shows a decreasing trend. However, in the switching circuits 20 shown in FIG5A and FIG5B , the source-drain voltage swing experienced by each stage of the switching device T is substantially the same.

[0101] To improve the uniformity of the source-drain voltage across each switching device T, the actual values ​​of the bulk feedforward capacitor Cfwd, bulk resistor Rb, and bulk capacitance Cb require simulation calculations to determine their specific values. Typically, bulk feedforward capacitor Cfwd and bulk capacitance Cb are in the femtofarad range. However, during the manufacturing process, fluctuations in processing parameters can lead to significant fluctuations in the actual capacitance and resistance values. This leads to poor consistency in actual capacitance and resistance compensation, impacting the source-drain voltage balancing effect.

[0102] FIG6 is a schematic diagram of a topological structure of another switching circuit according to an embodiment of the present application.

[0103] The embodiment of the present application further provides a switching circuit 20. As shown in FIG6 , the switching circuit 20 includes a multi-stage switching device T coupled in series, a gate bias circuit 21, a body bias circuit 22, and an impedance compensation network 24.

[0104] The gate bias circuit 21 includes a plurality of gate resistors Rg, and a gate resistor Rg is connected in series between the gates g of the switching devices T of two adjacent stages.

[0105] The body bias circuit 22 includes a plurality of body resistors Rb, and a body resistor Rb is connected in series between the body electrodes b of two adjacent switching devices T.

[0106] The impedance compensation network 24 includes a variable capacitor C′ and a resistor R coupled in series. An impedance compensation network 24 is connected in series between the gate g of the first-stage switching device T and the source s (or drain d) of the first-stage switching device T, and an impedance compensation network 24 is connected in series between the body b of the first-stage switching device T and the source s (or drain d) of the first-stage switching device T. An impedance compensation network 24 is connected in series between the gate g of the last-stage switching device T and the drain d (or source s) of the last-stage switching device T, and an impedance compensation network 24 is connected in series between the body b of the last-stage switching device T and the drain d (or source s) of the last-stage switching device T.

[0107] By setting up multiple impedance compensation networks 24, symmetrical RF impedance is provided at both ends of each stage of the switching device T. The symmetrical RF impedance makes the voltages of the source gate sg, drain gate dg, source s, and drain d of each stage of the switching device T equal, so that the swing amplitude of the source-drain voltage borne by each stage of the switching device T is equal.

[0108] However, the impedance compensation network 24 is composed of a resistor R and a variable capacitor C′. During the processing, fluctuations in processing parameters will cause large fluctuations in actual capacitance and resistance, and the consistency of actual capacitance and resistance compensation will be poor, affecting the source-drain voltage balancing effect.

[0109] FIG7 is a schematic diagram of a topological structure of another switching circuit according to an embodiment of the present application.

[0110] The embodiment of the present application further provides a switching circuit 20. As shown in FIG6 , the switching circuit 20 includes a multi-stage switching device T coupled in series, a gate bias circuit 21, a body bias circuit 22, and a voltage divider circuit 23.

[0111] The switching circuit 20 includes two gate terminals G and two body terminals B. The two gate terminals G receive the same signal, and the two body terminals B receive the same signal. The gate bias circuit 21 includes two first nodes A1, and the body bias circuit 22 includes two second nodes A2. The multi-stage switching devices T are divided into two equal groups, each group corresponding to a first node A1, a second node A2, a gate terminal G, and a body terminal B.

[0112] The gate bias circuit 21 includes multiple gate resistors Rg. The gates g of the switching devices T in the same group are coupled to the same first node A1. A gate resistor Rg is connected in series between the gate g of each switching device T and the first node A1. A common gate resistor Rg is connected in series between each first node A1 and a gate terminal G.

[0113] The body bias circuit 22 includes multiple body resistors Rb. The body terminals b of the switching devices T in the same group are coupled to the same second node A2. A body resistor Rb is connected in series between the body terminal b of each switching device T and the second node A2. A common body resistor Rb is connected in series between each second node A2 and a body terminal B.

[0114] The voltage divider circuit 23 includes a plurality of resistors R. A resistor R is connected in series between the source s and the drain d of each stage of the switching device T, so that the voltage drop of each stage of the switching device T is equal.

[0115] By dividing the multi-stage switching devices T into two groups, the gate terminal G and the body terminal B of each group receive the same signal, and there is no need to increase capacitance and resistance. The impact of process fluctuations on the source-drain voltage balancing effect can be ignored. Simulations have shown that grouping the switching circuit 20 can slightly improve the source-drain voltage balancing effect and reduce the source-drain voltage swing, but the effect is not significant. For example, the switching circuit 20 includes 12 stages of switching devices T. When the switching devices T are not grouped, the RF voltage is 40V, the gate terminal G and the body terminal B voltage are -3V, and the maximum source-drain voltage swing is 4.465V. When the switching devices T are grouped under the same process, the RF voltage is 40V, the gate terminal G and the body terminal B voltage are -3V, and the maximum source-drain voltage swing is 4.464V, and the source-drain voltage balancing effect is not significant.

[0116] Based on this, an embodiment of the present application provides a new switch circuit 20 to improve the source-drain voltage balancing effect, thereby improving the voltage withstand capability of the switch circuit 20.

[0117] 8A and 8B are schematic diagrams of a topological structure of a switching circuit provided in an embodiment of the present application.

[0118] As shown in FIG8A , the switch circuit 20 includes a plurality of switching devices T coupled in series, and the plurality of switching devices T are divided into a plurality of device groups Q. Accordingly, the switch circuit 20 includes a plurality of body terminals B and a plurality of device groups Q. Each device group Q includes one or more switching devices T. The switching devices T in the same device group Q are coupled to the same body terminal B. The body terminal B is configured to receive a body bias voltage, and at least two of the body bias voltages received by the plurality of body terminals B have different values.

[0119] For example, each device group Q in the switch circuit 20 includes only one level of switch devices T. Alternatively, each device group Q in the switch circuit 20 includes multiple levels of switch devices T. Alternatively, some device groups Q in the switch circuit 20 include one level of switch devices T, while some device groups Q include multiple levels of switch devices T.

[0120] In the embodiment of the present application, there is no limit on the number of stages of switching devices T included in the switching circuit 20, nor on the number of device groups Q. For example, the switching circuit 20 may include two or more device groups Q. Each device group Q may include one or more stages of switching devices T, but there is no limit on the number of stages of switching devices T included in each device group Q. The number of stages of switching devices T included in multiple device groups Q may be completely different, completely the same, or partially the same.

[0121] In addition, when the RF switching circuit 2 includes multiple switching circuits 20, there are no restrictive requirements for the number of levels of switching devices T included in the multiple switching circuits 20, the number of divided device groups Q, and the number of levels of switching devices T included in each device group Q. They can be reasonably set in combination with specific application scenarios.

[0122] The switching devices T in the same device group Q are coupled to the same body terminal B and are used to receive the same body terminal bias voltage. The body terminal bias voltages received by the switching devices T in different device groups Q are not completely the same or are completely different.

[0123] In some embodiments, as shown in FIG8A , the switch circuit 20 further includes a gate terminal G. The gates g of the multi-stage switch devices T are all coupled to the same gate terminal G. The gate terminal G is used to receive a gate bias voltage.

[0124] By coupling the gates g of the multi-stage switching devices T to the same gate terminal G, the multi-stage switching devices T receive the same gate bias voltage, which can avoid the problem that when the multi-stage switching devices T receive different gate bias voltages, the gate bias voltages received by the first few device groups Q are large, and the static point of the switch is close to the threshold voltage, resulting in a significant deterioration in the switching harmonic performance.

[0125] In other embodiments, as shown in FIG8B , the switch circuit 20 further includes multiple gate terminals G, and the switch devices T in the same device group Q are coupled to the same gate terminal G. The gate terminal G is used to receive a gate bias voltage, and the gate bias voltages received by the switch devices T in different device groups Q may be the same, completely different, or not completely the same.

[0126] In some embodiments, the switch circuit 20 further includes a gate bias circuit 21 , a body bias circuit 22 , and a voltage divider circuit 23 .

[0127] As shown in FIG8A , the gate bias circuit 21 includes a first node A1. The multi-stage switching devices T are divided into multiple device groups Q, each of which corresponds to the same first node A1 and gate terminal G. The gate bias circuit 21 includes multiple gate resistors Rg. The gates g of the multi-stage switching devices T in the switching circuit 20 are coupled to the first node A1. A gate resistor Rg is connected in series between the gate g of each switching device T and the first node A1. A common gate resistor Rg is connected in series between the first node A1 and a gate terminal G.

[0128] Alternatively, as shown in FIG8B , the gate bias circuit 21 includes multiple first nodes A1, and the multi-stage switching devices T are divided into multiple device groups Q, each device group Q corresponding to a first node A1 and a gate terminal G. The gate bias circuit 21 includes multiple gate resistors Rg. The gates g of the switching devices T in the same group are coupled to the same first node A1, and a gate resistor Rg is connected in series between the gate g of each switching device T and the first node A1. A common gate resistor Rg is connected in series between each first node A1 and a gate terminal G.

[0129] As shown in FIG8A , the body bias circuit 22 includes multiple second nodes A2, one second node A2 and one body terminal B corresponding to each device group Q. The body bias circuit 22 includes multiple body resistors Rb. The body electrodes b of the switching devices T in the same group are coupled to the same second node A2. A body resistor Rb is connected in series between the body electrode b of each switching device T and the second node A2. A common body resistor Rb is connected in series between each second node A2 and a body terminal B.

[0130] The voltage divider circuit 23 includes multiple voltage divider structures. A voltage divider structure is connected in series between the source s and drain d of each switching device T. That is, the two ends of the voltage divider structure are coupled to the source s and drain d of the same switching device T respectively.

[0131] For example, the voltage divider structure includes one or more passive components such as a resistor R, a capacitor, and an inductor. The resistance, capacitance, or inductance of the voltage divider structure coupled to different switch devices T may be different.

[0132] By providing a voltage divider structure corresponding to each stage of switching devices T in the switching circuit 20 and adjusting the equivalent resistance of the voltage divider structure, the voltage drop across each stage of switching devices T can be made equal or have a clear regularity. Using passive components such as resistors R, capacitors, and inductors as the voltage divider structure simplifies the circuit structure and is easy to implement.

[0133] The source-body parasitic capacitance Csb of the switching device T is The leakage parasitic capacitance Cdb is Among them, Csbo is the parasitic capacitance when the source body has zero voltage difference, Vsb is the source body voltage, is the voltage influencing factor, Cdbo is the parasitic capacitance when the drain voltage is zero, and Vdb is the drain voltage. From the formulas of the source parasitic capacitance Csb and the drain parasitic capacitance Cdb, it can be seen that the values ​​of the source parasitic capacitance Csb and the drain parasitic capacitance Cdb of the switching device T are inversely proportional to the source voltage Vsb and the drain voltage Vdb. However, since the source voltage and the drain voltage of each stage of the switching device T are not fixed, in order to ensure that the voltage drop of each stage of the switching device T is equal, the source parasitic capacitance Csb and the drain parasitic capacitance Cdb of each stage of the switching device T need to be equal, which requires that the body bias voltage received by the body electrode b of each stage of the switching device T is different. In the embodiment of the present application, the multi-stage switching device T is divided into multiple device groups Q, and the switching devices T in the multiple device groups Q are coupled to different body terminals B, and the body terminal bias voltages received by the multiple body terminals B are not completely the same or completely different. In this way, the source and drain voltages of each stage of the switching device T are not fixed, and the body voltage of each stage of the switching device T is also not fixed. By matching and adjusting the source and drain voltages of each stage of the switching device T, the body voltage of each stage of the switching device T is adjusted to change the source-body voltage Vsb and drain-body voltage Vdb of each stage of the switching device T, so that the source-body parasitic capacitance Csb and the drain-body parasitic capacitance Cdb of each stage of the switching device T approach equality. This balances the source-drain voltage swing of each stage of the switching device T, thereby improving the withstand voltage capability of the switching circuit 20. Furthermore, in the embodiment of the present application, after the multiple stages of the switching devices T are grouped and receive different body-terminal bias voltages, the source-drain voltage swing of each stage of the switching device T is more balanced. Therefore, when subjected to the same RF voltage, the number of stages of the switching devices T included in the switching circuit 20 provided by the embodiment of the present application can be reduced, thereby optimizing insertion loss and area. Furthermore, the switching circuit 20 of the embodiment of the present application does not innovate the switching circuit 20 itself, but innovates the body-end feeding network, so that the body end B receives different body-end bias voltages to balance the source-drain voltage, avoiding the problem of poor voltage balancing effect caused by fluctuations in process parameters when changing the switching circuit 20.

[0134] Based on the switching circuit 20 with group bias at the body end B provided in the embodiment of the present application, simulations have shown that, under the conditions of the same process, the same RF high voltage, and the same number of stages of the switching devices T, the maximum swing based on the switching circuit architecture shown in FIG4A is the smallest, the harmonic inflection point is the largest, and both the maximum swing and the harmonic inflection point are significantly improved.

[0135] In some embodiments, along the direction of the cascade connection of the switching devices T (that is, the direction in which the signal is transmitted in the switching circuit 20 ), the body-terminal bias voltages received by the plurality of body-terminals B gradually decrease.

[0136] It should be understood that when the switch device T is in the on state, the body terminals B of the multiple switch devices T all receive a reference ground voltage (0V). When the switch device T is in the off state, the body terminals B of the multiple switch devices T receive completely unequal or incompletely equal body bias voltages, and the body bias voltages are negative. Therefore, when the body bias voltage decreases, the absolute value of the body bias voltage increases. The body bias voltages received by the multiple body terminals B may decrease regularly, for example, the body bias voltage received by device group 1 is -1V, the body bias voltage received by device group 2 is -2V, and the body bias voltage received by device group 3 is -3V. The multiple body bias voltages may also decrease irregularly. For example, the body bias voltage received by device group 1 is -1V, the body bias voltage received by device group 2 is -1.5V, and the body bias voltage received by device group 3 is -2.5V. In addition, the body terminal bias voltages received by multiple body terminals B can be reduced in sequence (for example, reduced step by step). For example, the body terminal voltage received by device group one is -1V, the body terminal bias voltage received by device group two is -2V, and the body terminal bias voltage received by device group three is -3V, etc.

[0137] The body-terminal bias voltages received by multiple body terminals B may also decrease in a step-by-step manner (for example, they show a decreasing trend as a whole, but do not decrease step by step. For example, they have a decreasing-decreasing-equal-decreasing trend). For example, the body-terminal voltage received by device group one is -1V, the body-terminal bias voltage received by device group two is -2V, the body-terminal bias voltage received by device group three is -2V, the body-terminal bias voltage received by device group four is -3V, and so on.

[0138] If the source and drain voltages of each stage of switching devices T in the switching circuit 20 decrease step by step, by setting the body-side bias voltage received by the body electrodes b of the switching devices T in multiple device groups Q to gradually decrease, the source-body parasitic capacitance Csb and the drain-body parasitic capacitance Cdb of each stage or every few stages of switching devices T can be made nearly equal, further balancing the source-drain voltage swings of each stage of switching devices T and improving the withstand voltage capability of the switching circuit 20. The fewer switching devices T included in each device group Q, the more obvious the trend of gradually decreasing the body-side bias voltage of the switching devices T, and the better the balancing effect of the source-drain voltage swings of the switching devices T.

[0139] In some embodiments, the difference between the body terminal bias voltages received by two adjacent body terminals B is a fixed value.

[0140] It should be understood that the embodiments of the present application are not limited to the difference between the body-end bias voltages received by two adjacent body terminals B being equal to the value "W". Due to the existence of process errors, the values ​​within the range of W±0.1 are all "fixed values" referred to in the embodiments of the present application.

[0141] For example, the body terminal voltage received by device group one is -1V, the body terminal bias voltage received by device group two is -2V, the body terminal bias voltage received by device group three is -3V, and so on. The difference between the body terminal bias voltages received by two adjacent body terminals B is equal to 1.

[0142] When the body-end bias voltage decreases in a fixed pattern, the design difficulty of the switch circuit 20 can be reduced, which helps to further optimize the swing of the source-drain voltage borne by the multi-stage switch device T.

[0143] In some other embodiments, the difference between the body terminal bias voltages received by two adjacent body terminals B is not a fixed value.

[0144] For example, the body terminal voltage received by device group one is -1V, the body terminal bias voltage received by device group two is -2V, the body terminal bias voltage received by device group three is -4V, the body terminal bias voltage received by device group four is -5V, and so on. The differences between the body terminal bias voltages received by two adjacent body terminals B are not equal.

[0145] In some embodiments, as shown in FIG8A , when a device group Q includes multiple stages of switching devices T, the multiple stages of switching devices T in the same device group Q are sequentially coupled in series. Alternatively, the switching devices T are sequentially grouped along the cascade direction of the multiple stages of switching devices T. For example, the 1st to 3rd stage switching devices T are grouped into device group 1, the 4th to 5th stage switching devices T are grouped into device group 2, the 6th to 9th stage switching devices T are grouped into device group 3, the 10th stage switching devices T are grouped into device group 4, and so on.

[0146] For the switch circuit 20, the source and drain voltages experienced by multiple stages of switching devices T connected in series decrease with each stage. The body bias voltage received by the switch circuit 20 also decreases. Therefore, after the switching devices T are grouped in stages, the body bias voltage received by the subsequent switching devices T will not be higher than the body bias voltage received by the previous switching devices T. This ensures that the body-source parasitic capacitance Cbs and body-drain parasitic capacitance Cbd generated by each stage of switching devices T are approximately equal, thereby ensuring that the voltage drop across each stage of switching devices T is approximately equal, thereby balancing the source-drain voltage swing experienced by each stage of switching devices T.

[0147] For example, based on the switching circuit 20 shown in Figure 4A, the source body parasitic capacitance Csb1 of the first-level switching device T is less than the source body parasitic capacitance Csb2 of the second-level switching device T, and the source body parasitic capacitance Csb3 of the third-level switching device T is less than…and the source body parasitic capacitance CsbW of the last-level (Wth pole) switching device T is less than.

[0148] Based on the switching circuit 20 shown in Figure 8A, by adjusting the source body voltage Vsb of the switching device T at each level or every few levels, the source body parasitic capacitance Csb1 of the first-level switching device T can be made ≈ the source body parasitic capacitance Csb2 of the second-level switching device T ≈ the source body parasitic capacitance Csb3 of the third-level switching device T ≈…≈ the source body parasitic capacitance CsbW of the last-level (Wth pole) switching device T.

[0149] Similarly, based on the switching circuit 20 shown in Figure 4A, the leakage parasitic capacitance Cdb1 of the first-level switching device T is less than the leakage parasitic capacitance Cdb2 of the second-level switching device T, and the leakage parasitic capacitance Cdb3 of the third-level switching device T is less than…and the leakage parasitic capacitance CdbW of the last-level (Wth-pole) switching device T is less than.

[0150] Based on the switching circuit 20 shown in Figure 8A, by adjusting the leakage voltage Vdb of the switching device T at each level or every few levels, the leakage parasitic capacitance Cdb1 of the first-level switching device T can be made ≈ the leakage parasitic capacitance Cdb2 of the second-level switching device T ≈ the leakage parasitic capacitance Cdb3 of the third-level switching device T ≈…≈ the leakage parasitic capacitance CdbW of the last-level (Wth pole) switching device T.

[0151] In the embodiment of the present application, after the multi-stage switching devices T are grouped and receive different body-end bias voltages, the swing of the source-drain voltage of each stage of the switching devices T is more balanced. Therefore, when subjected to the same RF voltage, the number of stages of the switching devices T included in the switching circuit 20 provided in the embodiment of the present application can be reduced.

[0152] In some embodiments, the theoretical breakdown voltage of the switch circuit 20 is MV, the actual breakdown voltage of the switch circuit 20 is NV, and the value of M / N is 1-2.

[0153] For example, the value of M / N can be 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, or 1.9.

[0154] The theoretical breakdown voltage of the switching circuit 20 can be obtained by multiplying the theoretical withstand voltage of each stage of the switching device T by the number of stages of the switching device T. Since the swing of the source-drain voltage of each stage of the switching device T is relatively balanced, the number of stages of the switching device T in the switching circuit 20 can be reduced, so the value of M / N can be 1-2.

[0155] For example, the RF voltage received by the first-stage switching device T is 40V, and the number of stages of the switching devices T in the switching circuit 20 is less than or equal to 11.

[0156] For example, if the RF voltage (actual breakdown voltage) received by the first-stage switching devices T is N = 40V and the breakdown voltage of each switching device T is 5.5V, the switching circuit 20 shown in FIG4A requires 19 switching devices T, with a theoretical breakdown voltage of M = 104.5V and M / N = 2.6. However, the switching circuit 20 shown in FIG8A requires 10 switching devices T, with a theoretical breakdown voltage of M = 55V and M / N = 1.9.

[0157] Alternatively, for example, the RF voltage received by the first-stage switching device T is 35V, and the number of stages of the switching devices T in the switching circuit 20 is less than or equal to 11.

[0158] For example, if the RF voltage (actual breakdown voltage) received by the first-stage switching devices T is N = 35V and the breakdown voltage of each switching device T is 5V, the switching circuit 20 shown in FIG4A requires 14 switching devices T, with a theoretical breakdown voltage of M = 70V and M / N = 2. However, the switching circuit 20 shown in FIG8A requires 10 switching devices T, with a theoretical breakdown voltage of M = 50V and M / N = 1.4.

[0159] Alternatively, for example, the RF voltage received by the first-stage switching device T is 30V, and the number of stages of the switching devices T in the switching circuit 20 is less than or equal to 10.

[0160] For example, if the RF voltage (actual breakdown voltage) received by the first-stage switching devices T is N = 30 V and the breakdown voltage of each switching device T is 4.25 V, the switching circuit 20 shown in FIG4A requires 12 switching devices T, with a theoretical breakdown voltage of M = 51 V and M / N = 1.7. However, the switching circuit 20 shown in FIG8A requires 8 switching devices T, with a theoretical breakdown voltage of M = 34 V and M / N = 1.5.

[0161] The switch circuit 20 with body-end B group biasing provided in the embodiment of the present application not only improves the voltage withstand characteristics of the switch circuit 20, but also optimizes insertion loss and area. Simulations have shown that, under the same process and RF high voltage, the switch circuit architecture shown in FIG4A requires 13 levels of switch devices T to meet the voltage withstand requirements, while the switch circuit architecture shown in FIG8A requires only 10 levels of switch devices T to meet the voltage withstand requirements. The switch circuit 20 can reduce the number of switch devices T by three, reduce the maximum voltage swing by approximately 0.347V, reduce the insertion loss by approximately 0.38dB, and reduce the area by approximately 23%.

[0162] FIG9 is a structural diagram of a radio frequency switch circuit provided in an embodiment of the present application.

[0163] In some embodiments, as shown in FIG. 9 , the RF switch circuit 2 includes a first switch circuit 20 ′, a bias voltage output circuit 30 and a first level conversion circuit 41 .

[0164] The structure of the first switch circuit 20 ′ is the same as that of the switch circuit 20 illustrated above. In the embodiment of the present application, the multiple switch circuits are distinguished in naming only to distinguish the multiple switch circuits included in the RF switch circuit 2 , but the structure remains unchanged.

[0165] For example, the first switch circuit 20′ includes a plurality of first body terminals B1 and a plurality of stages of first switching devices, wherein the plurality of stages of first switching devices are divided into a plurality of first device groups. The first body terminal B1 of the first switch circuit 20′ is the body terminal B in the switch circuit 20, the first switching device in the first switch circuit 20′ is the switch device T in the switch circuit 20, and the first device group in the first switch circuit 20′ is the device group Q in the switch circuit 20.

[0166] The bias voltage output circuit 30 includes multiple body-end bias voltage output terminals Vb. For example, the multiple body-end bias voltage output terminals Vb are respectively used to output body-end bias voltages vb. The multiple body-end bias voltages vb output by the multiple body-end bias voltage output terminals Vb may be the same or different.

[0167] In some embodiments, the multiple body-side bias voltages vb output by the bias voltage output circuit 30 have the same characteristics as the body-side bias voltage received by the body terminal B of the switching circuit 20. For example, at least two of the multiple body-side bias voltages vb output by the bias voltage output circuit 30 have different values. Alternatively, the values ​​of the multiple body-side bias voltages vb output by the bias voltage output circuit 30 may not be completely identical or may be completely different.

[0168] For example, the plurality of body-end bias voltages vb outputted by the bias voltage output circuit 30 gradually decrease. For example, the difference between any two adjacent body-end bias voltages vb is a fixed value.

[0169] The first level shifter circuit 41 includes a first control terminal P1, multiple first input terminals I1, a reference ground voltage terminal GND, and multiple first output terminals O1. The multiple first input terminals I1 are coupled to the multiple body-side bias voltage output terminals Vb in a one-to-one correspondence. The multiple first input terminals I1 are configured to receive the body-side bias voltages output by the multiple body-side bias voltage output terminals Vb. The reference ground voltage terminal GND is configured to receive a reference ground voltage gnd. Both the body-side bias voltage and the reference ground voltage gnd serve as input signals for the first level shifter circuit 41.

[0170] The first control terminal P1 is configured to receive a first control signal. Multiple first level shifting circuits 41 can be coupled to the same first control terminal P1 to receive the same first control signal. The first level shifting circuit 41 is configured to output a reference ground voltage gnd or a first bulk bias voltage vb1 from the first output terminal O1 under the control of the first control signal. For example, when the first switch circuit 20′ is on, the first level shifting circuit 41 is configured to output the reference ground voltage gnd from the first output terminal O1 under the control of the first control signal, and the bulk electrode b of the first switch device in the first switch circuit 20′ receives the reference ground voltage gnd. When the first switch circuit 20′ is off, the first level shifting circuit 41 is configured to output the first bulk bias voltage vb1 from the first output terminal O1 under the control of the first control signal, and the bulk electrode b of the first switch device in the first switch circuit 20′ receives the first bulk bias voltage vb1.

[0171] As can be seen from the above description of the switch circuit 20, at least two of the multiple first body-side bias voltages vb1 outputted by the multiple first output terminals O1 are different. In some embodiments, the multiple first body-side bias voltages vb1 outputted by the first output terminal O1 are identical to the multiple body-side bias voltages vb outputted by the bias voltage output circuit 30. The first level shifter 41 merely selects to output the reference ground voltage gnd or to output the body-side bias voltage vb as the first body-side bias voltage vb1 based on the on / off status of the first switch circuit 20′.

[0172] In the RF switch circuit 2 provided in the embodiment of the present application, the first switch circuit 20′ receives completely different or non-identical first body-side bias voltages vb1, which can balance the body-source parasitic capacitance Cbs and body-drain parasitic capacitance Cbd of each first switching device in the first switch circuit 20′, thereby balancing the source-drain voltage swing of each first switching device, thereby improving the withstand voltage characteristics of the first switch circuit 20′. The first body-side bias voltage vb1 required by the first switch circuit 20′ is output by analog circuits such as the bias voltage output circuit 30 and the first level conversion circuit 41. The analog circuits have high design stability and processing consistency, and the compensation of the body-source parasitic capacitance Cbs and the body-drain parasitic capacitance Cbd is consistent. This ensures consistent source-drain voltage balancing in the first switch circuit 20′, and avoids the problem of poor source-drain voltage balancing due to process parameter fluctuations.

[0173] FIG10 is an architecture diagram of a radio frequency switch circuit provided in an embodiment of the present application.

[0174] In some embodiments, as shown in FIG10 , the RF switch circuit 2 further includes a bandgap reference (BG) and a low dropout regulator (LDO).

[0175] The bandgap reference source BG and the low-dropout linear regulator LDO are used to generate a stable reference voltage Vbase. The reference voltage Vbase can generate multiple negative voltage signals in different voltage domains as the body bias voltage vb through the bias voltage output circuit 30, which are supplied to different first device groups of the first switching circuit 20′.

[0176] It should be understood that when the first switch circuit 20' is in the off state, the first switch circuit 20' receives the body-side bias voltage vb, which can be understood as the off-body-side bias voltage. When the first switch circuit 20' is in the on state, the first switch circuit 20' receives the reference ground voltage (0V), which can be understood as the on-body-side bias voltage.

[0177] For example, a bandgap reference source BG is coupled to a power supply for generating a bandgap voltage, and a low-dropout linear regulator LDO is coupled to the power supply and the bandgap reference source BG for receiving the bandgap voltage and generating a reference voltage Vbase.

[0178] The embodiments of the present application do not limit the structures of the bandgap reference source BG and the low-dropout linear regulator LDO. The bandgap reference source BG and the low-dropout linear regulator LDO in the related art are all applicable to the embodiments of the present application.

[0179] In some embodiments, as shown in FIG10 , the bias voltage output circuit 30 includes a negative voltage circuit 31 , which includes a plurality of body-end bias voltage output terminals Vb for outputting a body-end bias voltage vb from the body-end bias voltage output terminals Vb.

[0180] In some embodiments, the bias voltage output circuit 30 further includes an oscillation signal generating circuit 32 and a voltage doubling circuit 33 .

[0181] The oscillation signal generating circuit 32 is configured to receive a reference voltage Vbase and generate an oscillation signal. For example, the oscillation signal generating circuit 32 is coupled to a low-dropout linear regulator LDO and is configured to receive the reference voltage Vbase output by the low-dropout linear regulator LDO.

[0182] The voltage multiplier circuit 33 is configured to receive the reference voltage Vbase and the oscillation signal, output a gate bias voltage from the gate bias voltage output terminal Vg, and transmit the gate bias voltage to the first gate terminal G1 of the first switch circuit 20 ′.

[0183] For example, one end of the voltage doubler circuit 33 is coupled to the oscillation signal generating circuit 32 and the low dropout linear regulator LDO respectively, and the gate bias voltage output terminal Vg of the voltage doubler circuit 33 is coupled to the first gate terminal G1 of the first switch circuit 20 ′.

[0184] The negative voltage circuit 31 is configured to receive an oscillation signal and output a bulk-end bias voltage vb from a bulk-end gate-end bias voltage output terminal Vb. For example, the negative voltage circuit 31 is coupled to an oscillation signal generating circuit 32 .

[0185] FIG11 is a schematic diagram of a topological circuit of a negative voltage circuit provided in an embodiment of the present application.

[0186] In some embodiments, the negative voltage circuit 31 includes a plurality of charge pumps coupled in series, and a plurality of body-side bias voltage output terminals Vb are coupled to output terminals of the plurality of charge pumps in a one-to-one correspondence.

[0187] For example, the charge pump includes capacitors C1, C2, two capacitors Cpb, two capacitors Cpt, a capacitor CL, transistors NM1, NM2, PM1, and PM2, connected as shown in the figure. A first oscillation signal terminal CLK1 receives an oscillation signal, a second oscillation signal terminal CLK2 receives an anti-oscillation signal, and an output terminal Vo is coupled to the body-side bias voltage output terminal Vb. The first oscillation signal terminal CLK1 of the next charge pump is coupled to the output terminal Vo of the previous charge pump.

[0188] In some embodiments, the difference vb between the body-terminal bias voltages received by two adjacent body terminals B is an integer multiple of the reference voltage Vbase.

[0189] For example, the output terminal of each charge pump in the negative voltage circuit 31 may be coupled to the body-side bias voltage output terminal Vb, and the difference between the body-side bias voltages vb of two adjacent body-side bias voltage output terminals Vb is 1 times the reference voltage Vbase. Alternatively, the output terminals of some charge pumps in the negative voltage circuit 31 may be coupled to the body-side bias voltage output terminal Vb, and the difference between the body-side bias voltages vb of two adjacent body-side bias voltage output terminals Vb is 2 times or more the reference voltage Vbase.

[0190] It should be understood that the embodiments of the present application do not limit the value of the integer multiple of the reference voltage Vbase to "n*Vbase". Due to the existence of process errors, the values ​​within the range of n*Vbase±0.1 all belong to the "integer multiple of the reference voltage Vbase" referred to in the embodiments of the present application.

[0191] In some embodiments, the body-side bias voltage vb outputted by the body-side bias voltage output terminal Vb is a negative multiple of the reference voltage Vbase. For example, the difference between the first body-side bias voltages vb1 received by two adjacent first body terminals B1 is the reference voltage Vbase.

[0192] In some embodiments, the reference voltage Vbase is 0.5 V to 2.5 V. For example, the reference voltage Vbase can be 0.5 V, 0.7 V, 1.0 V, 1.3 V, 1.5 V, 1.7 V, 2.0 V, 2.3 V, or 2.5 V.

[0193] For example, the difference between the first body-end bias voltages vb1 received by two adjacent first body-ends B1 is an integer multiple of any value between 0.5 V and 2.5 V. For example, the difference between the first body-end bias voltages vb1 received by two adjacent first body-ends B1 can be an integer multiple of any value between 0.5 V, 0.7 V, 1.0 V, 1.3 V, 1.5 V, 1.7 V, 2.0 V, 2.3 V, and 2.5 V.

[0194] If the reference voltage Vbase is set too high, the body bias voltages vb of adjacent device groups Q will differ significantly, resulting in poor source-drain voltage balancing and the need to increase the power supply voltage, which in turn increases power consumption. If the reference voltage Vbase is set too low, the number of voltage multiplication stages required will increase, leading to a sharp increase in the number of negative charge pumps.

[0195] Of course, the implementation of the negative voltage circuit 31 is only an illustration and is not intended to be limiting. The structures in the related art are all applicable to the embodiments of the present application.

[0196] FIG12 is a schematic diagram of a topology circuit of a first level conversion circuit provided in an embodiment of the present application.

[0197] In some embodiments, as shown in FIG12 , the first level shifter circuit 41 includes a NOT gate N1, a NOT gate N2, a NOT gate N3, a transistor NM1, and a transistor NM2, connected as shown. A first control terminal P1 is configured to receive a first control signal, a first output terminal O1 is configured to output a first bulk bias voltage vb1, and a first input terminal I1 is coupled to a bulk bias voltage terminal Vb of the negative voltage circuit 31.

[0198] Of course, the implementation of the first level conversion circuit 41 is only an illustration and is not limited in any way. The structures in the related art are all applicable to the embodiments of the present application.

[0199] FIG13 is an architecture diagram of a radio frequency switch circuit provided in an embodiment of the present application.

[0200] In some embodiments, as shown in FIG13 , the RF switch circuit 20 further includes a second level conversion circuit 42 and a second switch circuit 20″. The second level conversion circuit 42 includes a second control terminal P2, multiple second input terminals I2, a reference ground voltage terminal GND, and multiple second output terminals O2. The multiple second input terminals I2 are coupled to the multiple body-side bias voltage output terminals Vb in a one-to-one correspondence, and are configured to receive the same body-side bias voltage as the first level conversion circuit 41.

[0201] The second control terminal P2 is used to receive a second control signal, and the second level conversion circuit 42 is used to output the reference ground voltage gnd or the second body-end bias voltage vb2 from the second output terminal O2 under the control of the second control signal. For example, when the second switch circuit 20″ is turned on, the second level conversion circuit 42 is used to output the reference ground voltage gnd from the second output terminal O2 under the control of the second control signal, and the body electrode b of the second switch device in the second switch circuit 20″ receives the reference ground voltage gnd. When the second switch circuit 20″ is turned off, the second level conversion circuit 42 is used to output the second body-end bias voltage vb2 from the second output terminal O2 under the control of the second control signal, and the voltage received by the body electrode b of the second switch device in the second switch circuit 20″ is the second body-end bias voltage vb2.

[0202] As can be seen from the above description of the switch circuit 20, at least two of the multiple second-body bias voltages vb2 outputted by the multiple second output terminals O2 are different. In some embodiments, the multiple second-body bias voltages vb2 outputted by the second output terminal O2 are identical to the multiple body bias voltages vb outputted by the bias voltage output circuit 30. The second level shifter 42 merely selects to output the reference ground voltage gnd or to output the body bias voltage vb as the second-body bias voltage vb2 based on the on / off status of the second switch circuit 20″.

[0203] The structure of the second switch circuit 20 ″ is the same as that of the switch circuit 20 illustrated above. In the embodiment of the present application, the multiple switch circuits are distinguished in naming only to distinguish the multiple switch circuits included in the radio frequency switch circuit 2, but the structure remains unchanged.

[0204] For example, the second switching circuit 20″ includes multiple second body terminals B2 and multiple stages of second switching devices, and the multiple stages of second switching devices are divided into multiple second device groups. The second body terminal B2 of the second switching circuit 20″ is the body terminal B in the switching circuit 20, the second switching device in the second switching circuit 20″ is the switching device T in the switching circuit 20, and the second device group in the second switching circuit 20″ is the device group Q in the switching circuit 20. The second switching devices located in the same second device group are coupled to the same second body terminal B2.

[0205] When the RF switch circuit 2 includes multiple switch circuits, the multiple switch circuits can share the same bias voltage output circuit 30, which can save device area. Of course, the multiple switch circuits can also share different bias voltage output circuits 30, so that the multiple switch circuits can receive different body-side bias voltages vb.

[0206] When the RF switch circuit 2 provided in the embodiment of the present application is applied to the RF front-end module provided in the embodiment of the present application, the RF switch circuit 2 can evenly distribute the transmit RF voltage of several tens of volts on the switch devices T of all stages in the parallel RF switch circuit 2 of the transmit channel TX and the series RF switch circuit 2 of the receive channel RX, thereby improving the power capacity of the RF switch circuit 2 in the transmit channel TX and the receive channel RX, and also achieving the benefit of reducing the number of stages under the same transmit RF power. Similarly, the RF switch circuit 2 can evenly distribute the receive RF voltage of several tens of volts on the switch devices T of all stages in the series RF switch circuit 2 of the transmit channel TX and the parallel RF switch circuit 2 of the receive channel RX, thereby improving the power capacity of the RF switch circuit 2 in the transmit channel TX and the receive channel RX, and also achieving the benefit of reducing the number of stages under the same transmit RF power.

[0207] When the RF switch circuit 2 provided in the embodiment of the present application is applied to the front end of the wireless communication system shown in Figure 3, the RF switch circuit 2 can reduce the number of levels of the switching device T and reduce the occupied area of ​​the RF switch circuit 2 while ensuring the same withstand voltage.

[0208] Of course, the radio frequency switch circuit 2 provided in the embodiment of the present application can also be directly applied to the communication device provided in the embodiment of the present application without being integrated with other devices.

[0209] The present application also provides an integrated circuit chip, including the RF switch circuit 2 and an encapsulation layer provided in the present application. The encapsulation layer covers the RF switch circuit 2 and encapsulates the RF switch circuit 2. The integrated circuit chip can only integrate the RF switch circuit 2 as an RF switch circuit chip. The integrated circuit chip can also integrate other functional devices. For example, the integrated circuit chip can be a low-noise amplifier. Of course, the present application is not limited to this embodiment, and the above is only an example.

[0210] The above is only a specific embodiment of the present application, but the scope of protection of this application is not limited to this. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A radio frequency switching circuit, characterized in that: include: A bias voltage output circuit, comprising a plurality of body-end bias voltage output terminals; A first level conversion circuit includes a first control terminal, a plurality of first input terminals, a reference ground voltage terminal, and a plurality of first output terminals; The multiple first input terminals are coupled to the multiple body-end bias voltage output terminals in a one-to-one correspondence; the first control terminal is used to receive a first control signal, and the first level conversion circuit is used to output a reference ground voltage or a first body-end bias voltage from the first output terminal under the control of the first control signal; at least two of the multiple first body-end bias voltages outputted from the multiple first output terminals have different values; The first switching circuit includes multiple first body terminals and multiple first device groups; the multiple first body terminals are coupled to the multiple first output terminals in a one-to-one correspondence; the first switching circuit includes multiple stages of first switching devices coupled in series, each of the first device groups includes at least one stage of the first switching device, and the first switching devices in the same first device group are coupled to the same first body terminal.

2. The radio frequency switch circuit according to claim 1, characterized in that: Along the direction of the first switch device cascade, the first body terminal bias voltage received by the plurality of first body terminals gradually decreases.

3. The radio frequency switch circuit according to claim 2, characterized in that: The difference between the first body terminal bias voltages received by two adjacent first body terminals is a fixed value.

4. The radio frequency switch circuit according to any one of claims 1 to 3, characterized in that: The bias voltage output circuit also includes a gate bias voltage output terminal, and the first switch circuit also includes a first gate terminal; the first gate terminal is coupled to the gate bias voltage output terminal, and the gates of the multi-stage first switch devices are respectively coupled to the first gate terminal.

5. The radio frequency switch circuit according to any one of claims 1 to 4, characterized in that: The multiple stages of the first switch devices in the same first device group are coupled in series in sequence.

6. The radio frequency switch circuit according to any one of claims 1 to 5, characterized in that: The multiple body-end bias voltage output terminals are used to output multiple body-end bias voltages, and at least two of the multiple body-end bias voltages have different values.

7. The radio frequency switch circuit according to any one of claims 1 to 6, characterized in that: The bias voltage output circuit includes a negative voltage circuit; the negative voltage circuit includes the multiple body-end bias voltage output terminals and multiple charge pumps coupled in series, and the multiple body-end bias voltage output terminals are coupled to the output terminals of the multiple charge pumps in a one-to-one correspondence.

8. The radio frequency switch circuit according to claim 7, characterized in that: The bias voltage output circuit also includes an oscillation signal generating circuit and a voltage doubling circuit; The oscillation signal generating circuit is used to receive a reference voltage and generate an oscillation signal; The voltage doubler circuit is used to receive the reference voltage and the oscillation signal, and output a gate bias voltage from a gate bias voltage output terminal; The negative voltage circuit is used to receive the oscillation signal and output a body-end bias voltage from the body-end gate-end bias voltage output terminal.

9. The radio frequency switch circuit according to claim 8, characterized in that: The reference voltage has a value of 0.5V-2.5V.

10. The radio frequency switch circuit according to claim 8 or 9, characterized in that: A difference between the first body terminal bias voltages received by two adjacent first body terminals is an integer multiple of the reference voltage.

11. The radio frequency switch circuit according to any one of claims 1 to 10, characterized in that: The first switch circuit further includes a plurality of voltage-dividing structures, and two ends of the voltage-dividing structures are respectively coupled to a first source and a first drain of the same first switch device.

12. The radio frequency switch circuit according to any one of claims 1 to 11, characterized in that: The theoretical breakdown voltage of the first switch circuit is MV, the actual breakdown voltage of the first switch circuit is NV, and the value of M / N is 1-2.

13. The radio frequency switch circuit according to claim 12, characterized in that: The first switching device of the first stage is used to receive a radio frequency voltage of 40V, and the number of stages of the first switching devices in the first switching circuit is less than or equal to 11; or, The first switching device of the first stage is used to receive a radio frequency voltage of 35V, and the number of stages of the first switching devices in the first switching circuit is less than or equal to 11; or, The radio frequency voltage received by the first switching device in the first stage is 30V, and the number of stages of the first switching devices in the first switching circuit is less than or equal to 10.

14. The radio frequency switch circuit according to any one of claims 1 to 13, characterized in that: The radio frequency switch circuit also includes a second level conversion circuit and a second switch circuit; The second level conversion circuit comprises a second control terminal, a plurality of second input terminals, a reference ground voltage terminal and a plurality of second output terminals; the plurality of second input terminals are coupled to the plurality of body-end bias voltage output terminals in a one-to-one correspondence; the second control terminal is used to receive a second control signal, and the second level conversion circuit is used to output the reference ground voltage or the second body-end bias voltage from the second output terminal under the control of the second control signal; At least two of the plurality of second body terminal bias voltages outputted by the plurality of second output terminals have different values; A second switch circuit includes a plurality of second body terminals and a plurality of second device groups; The multiple second body terminals are coupled to the multiple second output terminals in a one-to-one correspondence; the second switching circuit includes a plurality of stages of second switching devices coupled in series, each second device group includes at least one stage of second switching device, and the second switching devices located in the same second device group are coupled to the same second body terminal.

15. An integrated circuit chip, characterized in that: It comprises a radio frequency switch circuit and a packaging layer, wherein the packaging layer covers the radio frequency switch circuit; the radio frequency switch circuit comprises the radio frequency switch circuit according to any one of claims 1 to 14.

16. A radio frequency front-end module, characterized in that: It comprises a radio frequency switching circuit and a filter, wherein the radio frequency switching circuit is coupled to the filter; the radio frequency switching circuit comprises the radio frequency switching circuit according to any one of claims 1 to 14.

17. A communication device, characterized in that: It comprises an antenna and a radio frequency switching circuit, wherein the antenna and the radio frequency switching circuit are coupled; the radio frequency switching circuit comprises the radio frequency switching circuit according to any one of claims 1 to 14.

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