Capacitor and manufacturing method therefor, and chip and electronic device

Abstract

The present application relates to the technical field of capacitors. Provided are a capacitor and a manufacturing method therefor, and a chip and an electronic device, which can solve the problem in the related art of the capacitance density of a capacitor being relatively low. The capacitor comprises a plurality of sub-capacitors, which are stacked, wherein each of the plurality of sub-capacitors comprises a carrier layer and a capacitor unit embedded in the carrier layer, the capacitor unit having an electrode; and at least one of two adjacent sub-capacitors among the plurality of sub-capacitors is provided with a conductive hole, and the conductive hole electrically connects the electrodes of the two adjacent sub-capacitors, such that the capacitor units of the two adjacent sub-capacitors are connected in parallel. The present application can be applied to electronic devices, such as a mobile phone or a notebook computer.

Description

Capacitor and manufacturing method thereof, chip, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on September 25, 2023, with application number 202311246457.6 and application name “Capacitors and their manufacturing methods, chips, and electronic devices”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the technical field of capacitors, and in particular to a capacitor and a manufacturing method thereof, a chip, and an electronic device. Background Art

[0003] Capacitors are important electronic components that store charge, smooth voltage changes, block DC while passing AC, and bypass high-frequency noise. As modern electronic devices continue to evolve toward multifunctionality, high integration, low power consumption, and miniaturization, the demand for capacitor capacitance density is increasing. Improving capacitor capacitance density has become a key issue in the industry.

[0004] A related art capacitor includes a substrate layer, a trench disposed on the substrate layer, and a capacitor unit partially located within the trench. Compared to chip-type multilayer ceramic capacitors, this capacitor has lower parasitic inductance and a thinner thickness, but a lower capacitance density. Consequently, for the same capacitance value, this capacitor occupies a larger area, hindering the optimal layout of other devices surrounding the capacitor.

[0005] Summary of the Invention

[0006] Embodiments of the present application provide a capacitor and a manufacturing method thereof, a chip, and an electronic device, which are used to solve the problem of low capacitance density of capacitors in related technologies.

[0007] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0008] In the first aspect, an embodiment of the present application provides a capacitor comprising a plurality of sub-capacitors arranged in a stacked manner; each of the plurality of sub-capacitors comprises a carrier layer and a capacitor unit embedded in the carrier layer, the capacitor unit having an electrode; among the plurality of sub-capacitors, at least one of two adjacent sub-capacitors is provided with a conductive hole, the conductive hole electrically connecting the electrodes of the two adjacent sub-capacitors so that the capacitor units of the two adjacent sub-capacitors are connected in parallel.

[0009] The capacitor in the embodiment of the present application has a conductive hole on at least one of the two adjacent sub-capacitors, which electrically connects the electrodes of the two adjacent sub-capacitors so that the capacitance units of the two adjacent sub-capacitors are connected in parallel. In this way, the equivalent capacitance of the capacitor is equal to the sum of the capacitance values ​​of the capacitance units in the multiple sub-capacitors, thereby increasing the capacitance value of the capacitor. In addition, since the multiple sub-capacitors of the capacitor are stacked, the capacitor increases the capacitance value while reducing the occupied area of ​​the capacitor, thereby increasing the capacitance density of the capacitor. The increase in capacitance density means that when achieving the same capacitance value, the capacitor occupies a smaller area, which is conducive to the optimized layout of other devices around the capacitor.

[0010] In some embodiments, in two adjacent sub-capacitors, for any one of the conductive vias, the conductive via penetrates the carrier layer of one of the sub-capacitors, and a first end of the conductive via is electrically connected to the electrode of one of the sub-capacitors, while a second end of the conductive via is electrically connected to the electrode of the other sub-capacitor via an interconnect structure. With this arrangement, the interconnect structure can electrically connect conductive vias at different locations to the electrode of the other sub-capacitor, thereby facilitating the placement of the conductive vias.

[0011] In some embodiments, the interconnect structure includes a bump, a first pad, and a second pad. The first pad is disposed on one of the sub-capacitors and electrically connected to the second end of the conductive via. The second pad is disposed on the other sub-capacitor and electrically connected to the electrode of the other sub-capacitor. The bump is disposed between the first and second pads. This configuration reduces the difficulty in designing and manufacturing the interconnect structure, thereby helping to reduce the design and manufacturing costs of the capacitors.

[0012] In some embodiments, the interconnect structure is a hybrid bonding structure and includes multiple third pads and multiple fourth pads. Each third pad is disposed on one of the sub-capacitors and electrically connected to the second end of the conductive via. Each fourth pad is disposed on another sub-capacitor and electrically connected to the electrode of the other sub-capacitor. Each third pad is in contact with a corresponding fourth pad. This configuration can achieve a shorter interconnect distance and a higher interconnect density.

[0013] In some embodiments, one of the sub-capacitors further includes a first redistribution layer, the first redistribution layer covering the second end of the conductive via; the first redistribution layer includes a first insulating layer, a first conductive layer embedded in the first insulating layer, and a first via, the first via connected between the first conductive layer and the second end of the conductive via; a portion of the interconnect structure is disposed on the first insulating layer and electrically connected to the first conductive layer. This configuration facilitates the configuration of the interconnect structure.

[0014] In some embodiments, the first redistribution layer further includes a fifth pad embedded in the first insulating layer, the fifth pad being positioned at the second end of the conductive via, and the first via being connected between the fifth pad and the first conductive layer. This arrangement facilitates electrical connection between the second end of the conductive via and the first via.

[0015] In some embodiments, the other sub-capacitor further includes a second redistribution layer, the second redistribution layer covering the electrode of the other sub-capacitor; the second redistribution layer includes a second insulating layer, and a second conductive layer and a second via embedded in the second insulating layer, the second via being connected between the second conductive layer and the electrode of the other sub-capacitor, and a portion of the interconnect structure is disposed on the second insulating layer and electrically connected to the second conductive layer. Such a configuration can facilitate the configuration of the interconnect structure.

[0016] In some embodiments, the carrier layer includes a front side and a back side disposed opposite each other, the electrodes include a first electrode and a second electrode, and the first electrode and the second electrode are both disposed on the front side of the carrier layer; the two adjacent sub-capacitors are respectively a first sub-capacitor and a second sub-capacitor, and the back side of the first sub-capacitor is disposed adjacent to the front side of the second sub-capacitor; the conductive vias connected between the first electrodes of the two adjacent sub-capacitors and the conductive vias connected between the second electrodes of the two adjacent sub-capacitors are both disposed on the first sub-capacitor and penetrate the carrier layer of the first sub-capacitor. This configuration simplifies the connection process between the electrodes of the first sub-capacitor and the second sub-capacitor, thereby helping to reduce the manufacturing cost of the capacitor.

[0017] In some embodiments, the first sub-capacitor further includes a second redistribution layer, the second redistribution layer covering the front surface of the carrier layer; the second redistribution layer includes a second insulating layer, and a second conductive layer and a second via embedded in the second insulating layer; the second conductive layer includes a first sublayer and a second sublayer; the first sublayer is electrically connected to the first electrode and a portion of the conductive vias through the second vias, and the second sublayer is electrically connected to the second electrode and another portion of the conductive vias through the second vias. With this arrangement, the second redistribution layer can electrically connect conductive vias at different locations to the first electrode and the second electrode, thereby facilitating the arrangement of the conductive vias.

[0018] In some embodiments, the second redistribution layer further includes a sixth pad embedded in the second insulating layer, the sixth pad being positioned at the first end of the conductive via and electrically connected to the corresponding second via. This arrangement facilitates electrical connection between the first end of the conductive via and the second via.

[0019] In some embodiments, in the first sub-capacitor, a capacitor array is provided on the carrier layer, the capacitor array including a plurality of capacitor units, and a first conductive via and a second conductive via are provided between two adjacent capacitor units in the capacitor array; wherein the first conductive via is electrically connected to the first electrode, and the second conductive via is electrically connected to the second electrode. This arrangement can reduce mutual inductive coupling between adjacent first and second conductive vias.

[0020] In some embodiments, in the capacitor array, a plurality of capacitor units are arranged along a first direction, and the first electrodes of the capacitor units form a first electrode array, and the second electrodes of the capacitor units form a second electrode array, wherein the second electrode array and the first electrode array are arranged spaced apart along a second direction, and the second direction is perpendicular to the first direction; along the first direction, the first conductive via is disposed between two adjacent first electrodes, and the second conductive via is disposed between two adjacent second electrodes. This arrangement facilitates electrical connection between the first conductive via and the adjacent first electrode, and facilitates electrical connection between the second conductive via and the adjacent second electrode.

[0021] In some embodiments, the first sublayer is strip-shaped and extends along the first direction, with the projection of the first sublayer on the carrier layer overlapping each of the first electrodes and each of the first conductive vias. This configuration not only facilitates electrical connection between the first sublayer and the first conductive vias and each of the first electrodes, but also reduces the area occupied by the first sublayer on the second redistribution layer.

[0022] In some embodiments, the second sub-layer is strip-shaped and extends along the first direction, and the projection of the second sub-layer on the carrier layer overlaps with each of the second electrodes and each of the second conductive vias. This configuration not only facilitates electrical connection between the second sub-layer and the second conductive vias and each of the second electrodes, but also reduces the area occupied by the second sub-layer on the second redistribution layer.

[0023] In some embodiments, in the capacitor array, multiple capacitor units are arranged along a first direction, and the first electrodes of the capacitor units form a first electrode array, and the second electrodes of the capacitor units form a second electrode array. The second electrode array and the first electrode array are arranged in a second direction, which is perpendicular to the first direction. The first conductive holes and the second conductive holes are alternately arranged along the first direction to form a conductive hole array. The conductive hole array is located between the first electrode array and the second electrode array, and adjacent first conductive holes and second conductive holes in the conductive hole array are respectively located on both sides of the corresponding capacitor unit. This arrangement can further reduce the mutual inductive coupling between adjacent first conductive holes and second conductive holes in the conductive hole array.

[0024] In some embodiments, the first sublayer includes a first trace and a second trace connected to one side of the first trace. The first trace extends along the first direction, and its projection on the carrier layer overlaps with each of the first electrodes. The first trace is electrically connected to each of the first electrodes via a second via. The second trace's projection on the carrier layer overlaps with the first conductive via, and the second trace is electrically connected to the first conductive via via the second via. This configuration not only facilitates electrical connection between the first sublayer and the first conductive vias and each of the first electrodes, but also reduces the area occupied by the first sublayer on the second redistribution layer.

[0025] In some embodiments, the second sublayer includes a third trace and a fourth trace connected to one side of the third trace. The third trace extends along the first direction, and its projection on the carrier layer overlaps with each of the second electrodes. The third trace is electrically connected to each of the second electrodes through the second vias. The fourth trace's projection on the carrier layer overlaps with the second conductive vias, and the fourth trace is electrically connected to the second conductive vias through the second vias. This configuration not only facilitates electrical connection between the second sublayer and each of the second electrodes in the second conductive vias, but also reduces the area occupied by the second sublayer on the second redistribution layer.

[0026] In a second aspect, an embodiment of the present application provides a chip, comprising a carrier substrate, a bare chip disposed on the carrier substrate, and the capacitor described in the first aspect, wherein the capacitor is disposed on the carrier substrate.

[0027] The beneficial effects of the chip in the embodiment of the present application are the same as the beneficial effects of the capacitor in the first aspect, and will not be repeated here.

[0028] In some embodiments, the capacitor is disposed on a surface of the carrier substrate away from the bare chip, with the projection of the capacitor on the carrier substrate at least partially overlapping with the projection of the bare chip core on the carrier substrate. This arrangement can enhance the decoupling effect of the capacitor, thereby optimizing the mid-frequency resonant noise of the electronic device's power supply chain.

[0029] In a third aspect, an embodiment of the present application provides an electronic device, comprising a circuit board and the chip described in the second aspect, wherein the chip is arranged on the circuit board.

[0030] The beneficial effects of the electronic device in the embodiment of the present application are the same as the beneficial effects of the chip in the second aspect, and will not be repeated here.

[0031] In some embodiments, a first capacitor is disposed on a surface of the circuit board facing away from the bare chip, with the projection of the first capacitor on the carrier substrate at least partially overlapping with the projection of the bare chip core on the carrier substrate. This configuration enhances the decoupling effect of the first capacitor, thereby reducing low-frequency transient noise in the power supply link of the electronic device.

[0032] In some embodiments, the first capacitor is a chip-type multilayer ceramic capacitor.

[0033] In a fourth aspect, an embodiment of the present application provides a method for manufacturing a capacitor, wherein the capacitor includes a plurality of sub-capacitors, each of the plurality of sub-capacitors includes a carrier layer and a capacitor unit embedded in the carrier layer, and the capacitor unit has an electrode; the method for manufacturing the capacitor includes: stacking the plurality of sub-capacitors; wherein, at least one of two adjacent sub-capacitors is provided with a conductive hole, and the conductive hole electrically connects the electrodes of the two adjacent sub-capacitors so that the capacitor units of the two adjacent sub-capacitors are connected in parallel.

[0034] The beneficial effects of the method for manufacturing the capacitor in the embodiment of the present application are the same as the beneficial effects of the capacitor in the first aspect, and will not be repeated here.

[0035] In some embodiments, before stacking the two adjacent sub-capacitors, the method further includes providing the conductive vias on at least one of the two adjacent sub-capacitors. This arrangement can reduce damage to the conductive vias during sub-capacitor fabrication and transportation, and can also improve the versatility of the sub-capacitors.

[0036] In some embodiments, for a sub-capacitor in which the conductive via is to be provided, providing the conductive via on the sub-capacitor includes: providing a blind hole on the front surface of the carrier layer; placing a conductor in the blind hole; and thinning the carrier layer from the back side thereof so that the conductor is exposed from the back side of the carrier layer to form the conductive via. This arrangement minimizes damage to other structures of the sub-capacitor during fabrication. Furthermore, before thinning the back side of the carrier layer, the bottom of the blind hole can support the conductor, eliminating the need for additional structures to support the conductor, thereby simplifying the conductive via fabrication process.

[0037] In some embodiments, the electrodes of the capacitor unit are both disposed on the front surface of the carrier layer; the two adjacent sub-capacitors are respectively a first sub-capacitor and a second sub-capacitor; the conductive vias connected between the electrodes of the two adjacent sub-capacitors are both disposed on the first sub-capacitor and penetrate the carrier layer of the first sub-capacitor; and stacking the two adjacent sub-capacitors includes: electrically connecting the electrodes of the second sub-capacitor to the conductive vias on the first sub-capacitor via an interconnect structure, so that the first sub-capacitor and the second sub-capacitor are stacked. This arrangement facilitates the arrangement of the interconnect structure.

[0038] In some embodiments, electrically connecting the electrode of the second sub-capacitor to the conductive via on the first sub-capacitor via an interconnect structure includes: providing a first redistribution layer on the back surface of the carrier layer of the first sub-capacitor to electrically connect to the conductive via; providing a second redistribution layer on the front surface of the carrier layer of the second sub-capacitor to electrically connect to the electrode of the second sub-capacitor; and electrically connecting the second redistribution layer to the first redistribution layer via the interconnect structure. With this arrangement, the second redistribution layer can electrically connect conductive vias at different locations to the electrodes of the first sub-capacitor, thereby facilitating the placement of the conductive vias.

[0039] In some embodiments, before electrically connecting the second sub-capacitor to the conductive via on the first sub-capacitor via the interconnect structure, the method further includes: providing a second redistribution layer on the front surface of the carrier layer of the first sub-capacitor to electrically connect the electrode of the first sub-capacitor to the conductive via. This configuration can reduce the number of flips of the first sub-capacitor, thereby simplifying the capacitor manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] FIG1 is a schematic structural diagram of a capacitor in the related art;

[0041] FIG2 is a front view of an electronic device (mobile phone) in some embodiments of the present application;

[0042] FIG3 is a cross-sectional view taken along line AA of the electronic device in FIG2 ;

[0043] FIG4 is a schematic structural diagram of a module formed by the chip and circuit board in FIG3 ;

[0044] FIG5 is a simplified structural diagram of a capacitor in the first embodiment of the present application;

[0045] FIG6 is an equivalent circuit diagram of the capacitor in FIG5 ;

[0046] FIG7 is a schematic structural diagram of the sub-capacitor in FIG5 ;

[0047] FIG8 is a top view of the capacitor in the first embodiment of the present application;

[0048] FIG9 is a BB cross-sectional view of the capacitor in FIG8 ;

[0049] FIG10 is a CC cross-sectional view of the capacitor in FIG8 ;

[0050] FIG11 is a first structural embodiment of an interconnection structure according to an embodiment of the present application;

[0051] FIG12 is a second structural embodiment of the interconnection structure according to the embodiment of the present application;

[0052] FIG13 is a perspective view of a capacitor in a second embodiment of the present application;

[0053] FIG14a is a schematic diagram illustrating the arrangement of electrodes and conductive vias of a sub-capacitor in a second embodiment of the present application;

[0054] FIG14 b is a schematic diagram illustrating the arrangement of electrodes, conductive vias, and a second conductive layer of a sub-capacitor in the second embodiment of the present application;

[0055] FIG15 is a DD cross-sectional view of the capacitor in FIG14 b;

[0056] FIG16 is a cross-sectional view taken along line EE of the capacitor in FIG14 b;

[0057] FIG17 is a simplified structural diagram of a capacitor in a third embodiment of the present application;

[0058] FIG18 is a longitudinal cross-sectional view of a capacitor in a third embodiment of the present application;

[0059] FIG19 is a simplified structural diagram of a capacitor in a fourth embodiment of the present application;

[0060] FIG20 is a top view of a capacitor in a fourth embodiment of the present application;

[0061] FIG21 is a FF cross-sectional view of the capacitor in FIG20 ;

[0062] FIG22 is a schematic structural diagram of a sub-capacitor in a fourth embodiment of the present application;

[0063] FIG23 is a simplified structural diagram of a capacitor in a fifth embodiment of the present application;

[0064] FIG24 a is a first schematic diagram of the manufacturing process of the capacitor in the first embodiment of the present application;

[0065] FIG24 b is a second schematic diagram of the manufacturing process of the capacitor in the first embodiment of the present application;

[0066] FIG24 c is a third schematic diagram of the manufacturing process of the capacitor in the first embodiment of the present application;

[0067] FIG24 d is a fourth schematic diagram of the manufacturing process of the capacitor in the first embodiment of the present application;

[0068] FIG24e is a fifth schematic diagram of the manufacturing process of the capacitor in the first embodiment of the present application;

[0069] FIG24f is a sixth schematic diagram of the manufacturing process of the capacitor in the first embodiment of the present application;

[0070] FIG24g is a seventh schematic diagram of the manufacturing process of the capacitor in the first embodiment of the present application;

[0071] FIG25 a is a flow chart of a capacitor manufacturing process in some embodiments of the present application;

[0072] FIG25 b is a flow chart of a process for manufacturing a conductive via of a capacitor in some embodiments of the present application. DETAILED DESCRIPTION

[0073] The technical solutions in some embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0074] As shown in Figure 1, Figure 1 is a schematic structural diagram of a capacitor in the related art. The capacitor is an IPD (Integrated Passive Device) capacitor, which is generally manufactured using a deep trench process. The capacitor includes a substrate layer 01, a trench 011 disposed on the substrate layer 01, and a capacitor unit 02 partially located in the trench 011. The capacitor unit 02 includes a first polysilicon layer 021, a second polysilicon layer 022, and a dielectric layer 023. The dielectric layer 023 is located between the first polysilicon layer 021 and the second polysilicon layer 022. The capacitor unit 02 has a first electrode 031 and a second electrode 032. The first electrode 031 is disposed on the first polysilicon layer 021, and the second electrode 032 is disposed on the second polysilicon layer 022.

[0075] As shown in Table 1, Table 1 shows a parameter comparison between this capacitor in the related art and chip multilayer ceramic capacitors (Multi-layer Ceramic Capacitors; MLCC). It can be seen from Table 1 that this capacitor in the related art has lower parasitic inductance (Equivalent series inductance; ESL) and thinner thickness, but lower capacitance density (the ratio of the capacitance value of the capacitor to the area occupied). In this way, when achieving the same capacitance value, the capacitor in the related art occupies a larger area, which is not conducive to the optimized layout of other devices around the capacitor.

[0076] Table 1

[0077] To this end, an embodiment of the present application provides a capacitor and its manufacturing method, chip, and electronic device. The capacitor includes multiple sub-capacitors. The multiple sub-capacitors are stacked and the capacitance units of two adjacent sub-capacitors are connected in parallel through conductive holes provided on the sub-capacitors, thereby improving the capacitance density of the capacitor.

[0078] The electronic device in the embodiments of the present application can be a mobile phone, a tablet computer, a wearable device (such as a smart watch, a smart bracelet, smart glasses, smart jewelry, etc.), a vehicle-mounted device, an augmented reality (AR) device, a virtual reality (VR) device, a laptop computer, an ultra-mobile personal computer (UMPC), a netbook, a personal digital assistant (PDA), and other electronic devices with capacitors.

[0079] The following uses a mobile phone as an example to introduce the structure of the capacitor of the electronic device in the embodiment of the present application. Other types of electronic devices can be specifically configured with reference to the structure of the capacitor in the mobile phone embodiment, and will not be described in detail here.

[0080] As shown in Figures 2 and 3, Figure 2 is a front view of an electronic device (mobile phone) in some embodiments of the present application, and Figure 3 is an AA cross-sectional view of the electronic device in Figure 2. The electronic device includes a housing 200, a display screen 300, a circuit board 400, and a chip 100.

[0081] In some embodiments, as shown in Figures 2 and 3, the housing 200 includes a middle frame 210 (also referred to as a front shell or front frame) and a back cover 220 (also referred to as a battery cover). The display screen 300 and the back cover 220 are mounted on opposite sides of the middle frame 210, respectively. The display screen 300 and the middle frame 210 form a first storage space 230, and the back cover 220 and the middle frame 210 form a second storage space 240.

[0082] The middle frame 210 and the back cover 220 may be detachably connected or may be an integral structure, which is not specifically limited here.

[0083] In some embodiments, as shown in FIG3 , the display screen 300 is a liquid crystal display screen, and a backlight source 500 is disposed in the first receiving space 230. However, the present invention is not limited thereto, and the display screen 300 may also be an OLED (Organic Light-Emitting Diode) display screen.

[0084] A circuit board 400 is disposed in the second receiving space 240 , and a chip 100 is disposed on the circuit board 400 . The chip 100 may be a SOC (System on Chip) chip.

[0085] As shown in Figure 4, Figure 4 is a schematic structural diagram of the module formed by the chip 100 and circuit board 400 in Figure 3. Chip 100 includes a carrier substrate 110, a capacitor 120, and a bare die (DIE) 130 disposed on the carrier substrate 110. Capacitor 120 is an IPD capacitor and is disposed on the carrier substrate 110. However, this is not limiting and capacitor 120 may also be other types of silicon capacitors.

[0086] In some embodiments, as shown in Figure 4, the capacitor 120 is arranged on a side surface of the carrier substrate 110 away from the bare chip 130 (such as the lower surface of the carrier substrate 110 shown in Figure 4), and the projection of the capacitor 120 on the carrier substrate 110 at least partially overlaps with the projection of the core 135 of the bare chip 130 on the carrier substrate 110.

[0087] Among them, the core 135 can be at least one of a CPU (Central Processing Unit; Central Processing Unit) core, a GPU (Graphics Processing Unit; Graphics Processing Unit) core, and an NPU (Neural Processing Unit, Neural Network Processor) core. The core 135 can be embedded in the inside of the bare chip 130, or it can be located on the surface of the bare chip 130, which is not specifically limited here. The projection of the capacitor 120 on the carrier substrate 110 and the projection of the core 135 on the carrier substrate 110 can partially overlap or completely overlap, which is not specifically limited here. The number of capacitors 120 can be one or more, which can be determined according to actual conditions.

[0088] Since the core 135 is the main load of the chip 100, the projection of the capacitor 120 on the carrier substrate 110 is at least partially overlapped with the projection of the core 135 on the carrier substrate 110. This allows the capacitor 120 to be close to the load of the chip 100, thereby improving the decoupling effect of the capacitor 120, thereby optimizing the intermediate frequency (frequency range of tens to hundreds of MHz) resonant noise of the power link of the electronic device, and thereby improving the PI (Power Integrity) performance of the power link.

[0089] The power supply link includes a power supply and a circuit connected between the power supply and the load. The power supply can be a battery, a power supply port, etc.

[0090] In some embodiments, as shown in FIG4 , connection bumps 140 are provided between the carrier substrate 110 and the circuit board 400 to form a gap 150 between the carrier substrate 110 and the circuit board 400, and the capacitor 120 is disposed in the gap 150. The connection bumps 140 electrically connect the carrier substrate 110 and the circuit board 400, thereby achieving electrical connection between the chip 100 and the circuit board 400.

[0091] In some embodiments, as shown in FIG. 4 , the chip 100 further includes a packaging layer 160 . The packaging layer 160 is disposed on the carrier substrate 110 and covers the bare chip 130 to protect the bare chip 130 .

[0092] In some embodiments, as shown in FIG4 , a first capacitor 170 is provided on a surface of the circuit board 400 away from the chip 100 (e.g., the lower surface of the circuit board 400 shown in FIG4 ). The projection of the first capacitor 170 on the carrier substrate 110 at least partially overlaps with the projection of the core 135 on the carrier substrate 110. This arrangement allows the first capacitor 170 to be close to the core 135 (i.e., the load of the chip 100), thereby improving the decoupling effect of the first capacitor 170 and reducing low-frequency transient noise in the power supply link of the electronic device.

[0093] The projection of the first capacitor 170 on the carrier substrate 110 may partially overlap or completely overlap with the projection of the core 135 on the carrier substrate 110, which is not specifically limited here. The number of first capacitors 170 may be one or more, depending on the actual situation.

[0094] In some embodiments, as shown in FIG. 4 , the first capacitor 170 is a chip-type multilayer ceramic capacitor, but is not limited thereto. The first capacitor 170 may also be another type of capacitor, such as a silicon capacitor.

[0095] As shown in Figure 5, Figure 5 is a simplified structural diagram of a capacitor 120 in the first embodiment of the present application. Capacitor 120 includes a plurality of stacked sub-capacitors 1. Each of the plurality of sub-capacitors 1 includes a carrier layer 11 and a capacitor unit 12 embedded in the carrier layer 11. The capacitor unit 12 has an electrode 13. Among the plurality of sub-capacitors 1, at least one of two adjacent sub-capacitors 1 is provided with a conductive hole 2. The conductive hole 2 electrically connects the electrodes 13 of the two adjacent sub-capacitors 1, so that the capacitor units 12 of the two adjacent sub-capacitors 1 are connected in parallel.

[0096] As shown in FIG5 , the conductive via 2 may be a through silicon via (TSV), but is not limited thereto. The conductive via 2 may also be other types of holes with conductive capabilities, such as holes with metal layers covering the hole walls.

[0097] The number of capacitor units 12 of each sub-capacitor 1 can be one or more, which is not specifically limited here; when each sub-capacitor 1 has multiple capacitor units 12, the capacitor units 12 at corresponding positions on the multiple sub-capacitors 1 are connected in parallel through the conductive holes 2; for example, as shown in Figure 5, in two adjacent sub-capacitors 1, the capacitor unit 12a is located on the carrier layer 11 of one of the sub-capacitors 1, and the capacitor unit 12b is located on the carrier layer 11 of the other sub-capacitor 1. The positions of the capacitor units 12a and 12b correspond to each other, and the electrodes 13 of the capacitor units 12a and 12b are electrically connected through the conductive holes 2, so that the capacitor units 12a and 12b are connected in parallel.

[0098] The capacitor 120 in the embodiment of the present application has a conductive hole 2 provided on at least one of the two adjacent sub-capacitors 1. The conductive hole 2 electrically connects the electrodes 13 of the two adjacent sub-capacitors 1, so that the capacitance units 12 of the two adjacent sub-capacitors 1 are connected in parallel. In this way, the equivalent capacitance of the capacitor 120 is equal to the sum of the capacitance values ​​of the capacitance units 12 in the multiple sub-capacitors 1, thereby increasing the capacitance value of the capacitor 120. In addition, since the multiple sub-capacitors 1 of the capacitor 120 are stacked, the capacitor 120 increases the capacitance value while reducing the occupied area of ​​the capacitor, thereby improving the capacitance density of the capacitor 120. The increase in capacitance density means that the capacitor 120 occupies a smaller area while achieving the same capacitance value, which is conducive to the optimized layout of other devices around the capacitor 120.

[0099] In some embodiments, as shown in Figure 5, the supporting layer 11 includes a front surface 117a and a back surface 117b arranged opposite to each other. Specifically, along the thickness direction of the supporting layer 11, the front surface 117a is one side surface of the supporting layer 11, and the back surface 117b is the other side surface of the supporting layer 11.

[0100] The electrode 13 includes a first electrode 131 (e.g., the "+" electrode shown in FIG5 ) and a second electrode 132 (e.g., the "-" electrode shown in FIG5 ). The first electrode 131 and the second electrode 132 are both disposed on the front surface 117a of the carrier layer 11. The two adjacent sub-capacitors 1 are a first sub-capacitor 1a and a second sub-capacitor 1b , respectively. The back surface 117b of the first sub-capacitor 1a is disposed adjacent to the front surface 117a of the second sub-capacitor 1b .

[0101] The conductive via 2 (i.e., the first conductive via 21 in the figure) connected between the first electrodes 131 of the first sub-capacitor 1a and the second sub-capacitor 1b, and the conductive via 2 (i.e., the second conductive via 22 in the figure) connected between the second electrodes 132 of the first sub-capacitor 1a and the second sub-capacitor 1b are both arranged on the first sub-capacitor 1a and pass through the carrier layer 11 of the first sub-capacitor 1a.

[0102] By arranging the conductive vias 2 connecting the first electrode 131 and the second electrode 132 on the first sub-capacitor 1a, it is convenient to electrically connect the second end of the conductive via 2 to the electrode 13 of the second sub-capacitor 1b, simplifying the connection process between the electrode 13 of the first sub-capacitor 1a and the electrode 13 of the second sub-capacitor 1b, which is conducive to reducing the manufacturing cost of the capacitor 120.

[0103] As shown in FIG. 6, FIG. 6 is an equivalent circuit diagram of the capacitor 120 in FIG. 5. Among them, the first sub-capacitor 1a and the second sub-capacitor 1b are IPD capacitors, the conductive via 2 is a through-silicon via, and the equivalent circuit of the first sub-capacitor 1a is a series connection of CIPD1, ESLIPD1, and ESRIPD1; the equivalent circuit of the second sub-capacitor 1b is a series connection of CIPD2, ESLIPD2, and ESRIPD2; the equivalent circuit of the conductive via 2 is a series connection of ESLTSV and ESRTSV. The capacitance value C12 after the first sub-capacitor 1a and the first sub-capacitor 1a are stacked is C12≈C1 + C2; the parasitic inductance ESL12 < ESL1; the parasitic resistance ESR12 < ESR1. It can be seen that the capacitor 120 formed by stacking multiple sub-capacitors 1 not only achieves lower parasitic inductance and parasitic resistance but also increases the capacitance value per unit area of the capacitor 120.

[0104] In some embodiments, as shown in FIG. 7, FIG. 7 is a structural schematic diagram of the sub-capacitor 1 in FIG. 5. The carrier layer 11 of the sub-capacitor 1 includes a substrate layer 111, and a first trench 112 is provided on the substrate layer 111. The capacitive unit 12 is partially (or entirely) disposed in the first trench 112. The capacitive unit 12 includes a first capacitive conductive layer 121, a second capacitive conductive layer 122, and a dielectric layer 123 disposed between the first capacitive conductive layer 121 and the second capacitive conductive layer 122.

[0105] The carrier layer 11 of the sub-capacitor 1 further includes an upper insulating layer 113. The upper insulating layer 113 is disposed on the substrate layer 111 and covers the capacitive unit 12. The first electrode 131 and the second electrode 132 of the capacitive unit 12 are spaced apart and disposed on the upper insulating layer 113. First connection vias 114 and second connection vias 115 are provided on the upper insulating layer 113. The first connection via 114 is connected between the first electrode 131 and the first capacitive conductive layer 121, and the second connection via 115 is disposed between the second electrode 132 and the second capacitive conductive layer 122.

[0106] The substrate layer 111 may be a silicon substrate layer, the first capacitor conductive layer 121 and the second capacitor conductive layer 122 may be polysilicon (Poly) layers, or metal layers, such as copper or tungsten layers. The first connection vias 114 and the second connection vias 115 may both be through-silicon vias (TSVs), or other types of conductive holes, such as holes with metal layers covering the walls.

[0107] In some embodiments, as shown in FIG7 , the first capacitor conductive layer 121 fills the first trench 112 , and a plurality of second trenches 1211 are spaced apart on the first capacitor conductive layer 121 . The dielectric layer 123 includes a first dielectric layer 1231 and a second dielectric layer 1232 . The first dielectric layer 1231 covers the walls of the second trenches 1211 , and the second dielectric layer 1232 is disposed at the edges of the second trenches 1211 and connected to the first dielectric layer 1231 .

[0108] The second capacitor conductive layer 122 includes a filling layer 1221 and a connecting layer 1222. The filling layer 1221 is disposed on the first dielectric layer 1231. The filling layer 1221 and the first dielectric layer 1231 fill the second trench 1211. The connecting layer 1222 is disposed on the second dielectric layer 1232 and the filling layer 1221. The second connecting via 115 is connected between the connecting layer 1222 and the second electrode 132.

[0109] By providing a plurality of second grooves 1211 on the first capacitor conductive layer 121, and providing the dielectric layer 123 and the second capacitor conductive layer 122 in the second grooves 1211, this is equivalent to folding the plates of the capacitor unit 12 (i.e., the first capacitor conductive layer 121 and the second capacitor conductive layer 122), thereby expanding the area of ​​the substrate of the capacitor unit 12 and facilitating improving the capacitance value of the capacitor unit 12.

[0110] Among them, the first electrode 131 and the second electrode 132 of the capacitor unit 12 can be set as one or multiple. For example, as shown in Figure 7, the capacitor unit 12 has two first electrodes 131 and four second electrodes 132. Each first electrode 131 is electrically connected to the first capacitor conductive layer 121 through the first connecting via 114, and each second electrode 132 is electrically connected to the connecting layer 1222 through the second connecting via 115.

[0111] In some embodiments, as shown in Figures 8, 9 and 10, Figure 8 is a top view of the capacitor 120 in the first embodiment of the present application, Figure 9 is a BB cross-sectional view of the capacitor 120 in Figure 8, and Figure 10 is a CC cross-sectional view of the capacitor 120 in Figure 8.

[0112] In the first sub-capacitor 1a and the second sub-capacitor 1b, for any conductive via 2, the conductive via 2 penetrates the carrier layer 11 of the first sub-capacitor 1a, and the first end (the upper end shown in the figure) of the conductive via 2 is electrically connected to the electrode 13 of the first sub-capacitor 1a, and the second end (the lower end shown in the figure) of the conductive via 2 is electrically connected to the electrode 13 of the second sub-capacitor 1b via the interconnect structure 3. In other words, in two adjacent sub-capacitors 1, for any conductive via 2, the conductive via 2 penetrates the carrier layer 11 of one of the sub-capacitors 1, and the first end of the conductive via 2 is electrically connected to the electrode 13 of one of the sub-capacitors 1, and the second end of the conductive via 2 is electrically connected to the electrode 13 of the other sub-capacitor 1 via the interconnect structure 3.

[0113] By setting the interconnection structure 3, the interconnection structure 3 can electrically connect the conductive holes 2 at different positions to the electrodes 13 of the second sub-capacitor 1b, so that the conductive holes 2 do not need to be set at the positions corresponding to the electrodes 13 of the second sub-capacitor 1b, thereby facilitating the setting of the conductive holes 2.

[0114] In some embodiments, as shown in Figure 9, the first sub-capacitor 1a also includes a first redistribution layer 14, which covers the second end of the conductive hole 2; the first redistribution layer 14 includes a first insulating layer 141, and a first conductive layer 142 and a first via 143 embedded in the first insulating layer 141, the first via 143 is connected between the first conductive layer 142 and the second end of the conductive hole 2, and a portion of the interconnection structure 3 is arranged on the first insulating layer 141 and is electrically connected to the first conductive layer 142.

[0115] By setting the first redistribution layer 14, the first redistribution layer 14 can electrically connect the interconnection structure 3 at different positions to the second end of the conductive hole 2, so that the interconnection structure 3 does not need to be set at the position corresponding to the second end of the conductive hole 2, thereby facilitating the setting of the interconnection structure 3.

[0116] The first conductive layer 142 may be a linear conductive layer or a planar conductive layer, which is not specifically limited here; the first conductive layer 142 may be a metal layer, such as a copper layer.

[0117] In some embodiments, as shown in FIG9 , the first redistribution layer 14 further includes a fifth pad 144, which is embedded in the first insulating layer 141 and located at the second end of the conductive via 2. The first via 143 is connected between the fifth pad 144 and the first conductive layer 142. By providing the fifth pad 144 at the second end of the conductive via 2, the fifth pad 144 serves as a connection terminal for the conductive via 2. The fifth pad 144 can be configured to different sizes according to actual needs, thereby facilitating electrical connection with the first via 143 and avoiding inconvenience in connecting to the first via 143 due to a conductive via 2 having a small diameter.

[0118] The fifth pad 144 may be made of metal, such as copper or tungsten, which is not specifically limited herein. A first via 143 may be provided between the fifth pad 144 and the first conductive layer 142, as shown in FIG9 , or multiple first vias 143, such as two, may be provided.

[0119] In some embodiments, as shown in Figure 9, the second sub-capacitor 1b also includes a second redistribution layer 15, which covers the electrode 13 of the second sub-capacitor 1b; the second redistribution layer 15 includes a second insulating layer 151, and a second conductive layer 152 and a second via 153 embedded in the second insulating layer 151, the second via 153 is connected between the second conductive layer 152 and the electrode 13 of the second sub-capacitor 1b, and a portion of the interconnection structure 3 is arranged on the second insulating layer 151 and is electrically connected to the second conductive layer 152.

[0120] By setting up the second redistribution layer 15, the second redistribution layer 15 can electrically connect the interconnection structure 3 at different positions with the electrode 13 of the second sub-capacitor 1b, so that the interconnection structure 3 does not need to be set at the position corresponding to the electrode 13 of the second sub-capacitor 1b, thereby facilitating the setting of the interconnection structure 3.

[0121] The second conductive layer 152 may be a linear conductive layer or a planar conductive layer, which is not specifically limited here; the second conductive layer 152 may be a metal layer, such as a copper layer.

[0122] The specific structure of the interconnect structure 3 is not unique. FIG11 shows a first structural embodiment of the interconnect structure 3 in an embodiment of the present application. In this embodiment, the interconnect structure 3 includes a bump 31, a first pad 32, and a second pad 33. The first pad 32 is disposed on the first sub-capacitor 1a and is electrically connected to the second end of the conductive via 2. The second pad 33 is disposed on the second sub-capacitor 1b and is electrically connected to the electrode 13 of the second sub-capacitor 1b. The bump 31 is disposed between the first pad 32 and the second pad 33. For example, the bump 31 can be welded between the first pad 32 and the second pad 33. By configuring the interconnect structure 3 to include the bump 31, the design and manufacturing of the interconnect structure 3 is simplified, thereby helping to reduce the design and manufacturing costs of the capacitor 120.

[0123] 11 , the first pad 32 may be disposed on the first redistribution layer 14 and electrically connected to the first conductive layer 142 . The second pad 33 may be disposed on the second redistribution layer 15 and electrically connected to the second conductive layer 152 .

[0124] The bumps 31 may be spherical, but are not limited thereto. They may also be columnar or have other irregular shapes. The material of the bumps 31 includes at least one of Au, Ni, Cu, Pb, Sn, and In. The bumps 31 may be microbumps, with a maximum size of 10 μm to 20 μm.

[0125] Figure 12 shows a second structural embodiment of the interconnection structure 3 in the embodiment of the present application. In this embodiment, the interconnection structure 3 is a hybrid bonding structure and includes a plurality of third pads 34 and a plurality of fourth pads 35. Each third pad 34 is arranged on the first sub-capacitor 1a and is electrically connected to the second end of the conductive hole 2; each fourth pad 35 is arranged on the second sub-capacitor 1b and is electrically connected to the electrode 13 of the second sub-capacitor 1b. Each third pad 34 is in contact with the corresponding fourth pad 35 respectively.

[0126] By setting the interconnection structure 3 as a hybrid bonding structure, the following advantages are achieved: First, a shorter interconnection distance can be achieved. The interconnection is achieved through the contact between the third pad 34 and the fourth pad 35, which can narrow the gap between the two adjacent sub-capacitors 1 and prevent impurities from entering the gap between the two adjacent sub-capacitors 1 to affect the normal operation of the capacitor 120; Second, a higher interconnection density can be achieved. The size of the third pad 34 and the fourth pad 35 is relatively small, for example, it can be less than 10μm, which can achieve a higher interconnection density to facilitate the transmission of electrical signals in the interconnection structure 3.

[0127] 12 , the third pad 34 may be disposed on the first redistribution layer 14 and electrically connected to the first conductive layer 142 . The fourth pad 35 may be disposed on the second redistribution layer 15 and electrically connected to the second conductive layer 152 .

[0128] The material of the third and fourth pads 34 and 35 includes at least one of Au, Ni, Cu, Pb, Sn, and In. The shapes of the third and fourth pads 34 and 35 can be circular, but are not limited to this. They can also be polygonal, such as a square. The number of third and fourth pads 34 and 35 can be nine, but are not limited to this. The number of each can be nine or more, or less than nine, depending on the actual situation.

[0129] In some embodiments, as shown in Figures 8, 9, and 10, the first sub-capacitor 1a further includes a second redistribution layer 15, which covers the front surface 117a of the carrier layer 11; the second redistribution layer 15 includes a second insulating layer 151, and a second conductive layer 152 and a second via 153 embedded in the second insulating layer 151; the second conductive layer 152 includes a first sub-layer 1521 and a second sub-layer 1522. As shown in Figures 8 and 9, the first sub-layer 1521 is electrically connected to the first electrode 131 and a portion of the conductive vias 2 (such as the two conductive vias 2 on the left side of Figure 8) through the second via 153; as shown in Figures 8 and 10, the second sub-layer 1522 is electrically connected to the second electrode 132 and another portion of the conductive vias 2 (such as the two conductive vias 2 on the right side of Figure 8) through the second via 153.

[0130] By setting up the second redistribution layer 15, the second redistribution layer 15 can electrically connect the conductive holes 2 at different positions with the first electrode 131 and the second electrode 132. Then, the conductive holes 2 do not need to be set at the positions of the first electrode 131 and the second electrode 132, thereby facilitating the setting of the conductive holes 2.

[0131] In some embodiments, as shown in Figures 9 and 10, the second redistribution layer 15 also includes a sixth pad 154, which is embedded in the second insulating layer 151. The sixth pad 154 is arranged at the first end (the upper end shown in the figure) of the conductive hole 2 and is electrically connected to the corresponding second via 153.

[0132] By providing a sixth pad 154 at the first end of the conductive hole 2, the sixth pad 154 serves as a connection terminal of the conductive hole 2. The sixth pad 154 can be set to different sizes according to actual needs, so that it can be conveniently electrically connected to the second via 153, avoiding the inconvenience of connecting the conductive hole 2 to the second via 153 due to the small diameter of the conductive hole 2.

[0133] The sixth pad 154 may be made of metal, such as copper or tungsten, which is not specifically limited herein. A first via 143 may be provided between the sixth pad 154 and the second conductive layer 152, as shown in FIG9 , or multiple first vias 143, such as two, may be provided.

[0134] In some embodiments, as shown in Figures 9 and 10, in the sub-capacitor 1 (that is, the first sub-capacitor 1a) located at the end of the capacitor 120, a connecting terminal 4 is provided on the second redistribution layer 15, and the connecting terminal 4 is electrically connected to the second conductive layer 152. The connecting terminal 4 is an external terminal of the capacitor 120 and is used to electrically connect to the carrier substrate 110 of the chip 100.

[0135] Specifically, the connection terminal 4 includes a first connection terminal 41 and a second connection terminal 42 . The first connection terminal 41 is electrically connected to the first sub-layer 1521 , and the second connection terminal 42 is electrically connected to the second sub-layer 1522 .

[0136] 9 and 10 , the first connection terminal 41 and the second connection terminal 42 are both bumps. However, the present invention is not limited thereto, and the first connection terminal 41 and the second connection terminal 42 may also be configured in other structures.

[0137] In some embodiments, as shown in Figures 8, 9 and 10, in the first sub-capacitor 1a, a capacitor array 116 is provided on the carrier layer 11, the capacitor array 116 includes a plurality of capacitor units 12, and a first conductive hole 21 and a second conductive hole 22 are arranged between two adjacent capacitor units 12 in the capacitor array 116; wherein the first conductive hole 21 is a conductive hole 2 electrically connected to the first electrode 131, and the second conductive hole 22 is a conductive hole 2 electrically connected to the second electrode 132.

[0138] By arranging the first conductive via 21 and the second conductive via 22 between two adjacent capacitor units 12 in the capacitor array 116, the distance between adjacent first conductive vias 21 and second conductive vias 22 can be reduced, thereby reducing the mutual inductive coupling between adjacent first conductive vias 21 and second conductive vias 22. At the same time, the distances from the first conductive vias 21 and second conductive vias 22 to the capacitor units 12 can also be shortened, thereby facilitating electrical connection between the first conductive via 21 and the first electrode 131, and between the second conductive via 22 and the second electrode 132.

[0139] In some embodiments, as shown in FIG8 , in the capacitor array 116 , a plurality of capacitor units 12 are arranged along a first direction Y, and the first electrodes 131 of the capacitor units 12 form a first electrode array 133 , and the second electrodes 132 of the capacitor units 12 form a second electrode array 134 . The second electrode array 134 and the first electrode array 133 are arranged spaced apart along a second direction X, where the second direction X is perpendicular to the first direction Y. A first conductive via 21 is disposed between the first electrodes 131 of two adjacent capacitor units 12 , and a second conductive via 22 is disposed between the second electrodes 132 of two adjacent capacitor units 12 .

[0140] Such a configuration can shorten the distance between the first conductive via 21 and the adjacent first electrode 131, and shorten the distance between the second conductive via 22 and the adjacent second electrode 132, thereby facilitating the electrical connection between the first conductive via 21 and the adjacent first electrode 131, and facilitating the electrical connection between the second conductive via 22 and the adjacent second electrode 132.

[0141] As shown in FIG8 , the number of the capacitor array 116 may be one, but is not limited thereto. The number of the capacitor array 116 may also be multiple.

[0142] In some embodiments, as shown in Figures 8 and 9, the first sub-layer 1521 is strip-shaped and extends along the first direction Y. The projection of the first sub-layer 1521 on the carrier layer 11 overlaps with each first electrode 131 and each first conductive via 21. This configuration not only facilitates electrical connection between the first sub-layer 1521 and the first conductive via 21 and each first electrode 131, but also reduces the area occupied by the first sub-layer 1521 on the second redistribution layer 15, thereby facilitating the optimized layout of other structures on the second redistribution layer 15.

[0143] In some embodiments, as shown in Figures 8 and 10, the second sub-layer 1522 is strip-shaped and extends along the first direction Y. The projection of the second sub-layer 1522 on the carrier layer 11 overlaps with each second electrode 132 and each second conductive via 22. This configuration not only facilitates electrical connection between the second sub-layer 1522 and the second conductive via 22 and each second electrode 132, but also reduces the area occupied by the second sub-layer 1522 on the second redistribution layer 15, thereby facilitating the optimized layout of other structures on the second redistribution layer 15.

[0144] As shown in Figures 13 to 16, Figure 13 is a three-dimensional view of the capacitor 120 in the second embodiment of the present application, Figure 14a is a schematic diagram of the arrangement of the electrodes and conductive holes of the sub-capacitor in the second embodiment of the present application, Figure 14b is a schematic diagram of the arrangement of the electrodes, conductive holes, and second conductive layer 152 of the sub-capacitor in the second embodiment of the present application, Figure 15 is a DD cross-sectional view of the capacitor 120 in Figure 14b, and Figure 16 is an EE cross-sectional view of the capacitor 120 in Figure 14b. The main difference between the capacitor 120 in this embodiment and the capacitor 120 shown in Figures 5 to 12 is that the location and arrangement of the first conductive hole 21 and the second conductive hole 22 are different, as described below:

[0145] As shown in Figures 13 and 14a, in the capacitor array 116, multiple capacitor units 12 are arranged along the first direction Y, and the first electrodes 131 of the capacitor units 12 form a first electrode array 133, and the second electrodes 132 of the capacitor units 12 form a second electrode array 134. The second electrode array 134 and the first electrode array 133 are arranged alternately along the second direction X, and the second direction X is perpendicular to the first direction Y.

[0146] The first conductive holes 21 and the second conductive holes 22 are alternately arranged along the first direction Y to form a conductive hole array 23. The conductive hole array 23 is located between the first electrode array 133 and the second electrode array 134. The adjacent first conductive holes 21 and second conductive holes 22 in the conductive hole array 23 are respectively located on both sides of the corresponding capacitor unit 12.

[0147] By alternately arranging the first conductive vias 21 and the second conductive vias 22 along the first direction Y, the conductive via array 23 is located between the first electrode array 133 and the second electrode array 134. In this way, the distance between adjacent first conductive vias 21 and second conductive vias 22 in the conductive via array 23 is not restricted by the positions of the first electrodes 131 and the second electrodes 132. Therefore, the distance between adjacent first conductive vias 21 and second conductive vias 22 can be designed to be smaller, thereby further reducing the mutual inductive coupling between adjacent first conductive vias 21 and second conductive vias 22 in the conductive via array 23.

[0148] At the same time, since the conductive hole array 23 is located between the first electrode array 133 and the second electrode array 134, the first electrode array 133 and the second electrode array 134 can share the conductive hole array 23 (that is, the first electrode array 133 can be electrically connected to the first conductive hole 21 in the conductive hole array 23, and the second electrode array 134 can be electrically connected to the second conductive hole 22 in the conductive hole array 23), thereby reducing the number of conductive holes 2 set.

[0149] The number of capacitor arrays 116 may be one or more. For example, as shown in FIG14 a , there are three capacitor arrays 116 , and the three capacitor arrays 116 are arranged along the second direction X. The capacitor units 12 of two adjacent capacitor arrays 116 share an electrode 13 . Specifically, as shown in FIG14 a , the capacitor array 116 on the left and the capacitor array 116 in the middle share a second electrode array 134 , and the capacitor array 116 in the middle and the capacitor array 116 on the left share a first electrode array 133 .

[0150] In some embodiments, as shown in Figures 14b and 15, the first sublayer 1521 includes a first trace 1521a and a second trace 1521b connected to one side of the first trace 1521a. The first trace 1521a extends along the first direction Y, and its projection on the carrier layer 11 overlaps with each first electrode 131. The first trace 1521a is electrically connected to each first electrode 131 through a second via 153. The second trace 1521b has its projection on the carrier layer 11 overlap with the first conductive via 21, and the second trace 1521b is electrically connected to the first conductive via 21 through the second via 153. This configuration not only facilitates the electrical connection between the first sublayer 1521 and the first conductive via 21 and each first electrode 131, but also reduces the area occupied by the first sublayer 1521 on the second redistribution layer 15, thereby facilitating the optimized layout of other structures on the first redistribution layer 14.

[0151] In some embodiments, as shown in FIG14b and FIG16 , the second sublayer 1522 includes a third trace 1522a and a fourth trace 1522b connected to one side of the third trace 1522a. The third trace 1522a extends along the first direction Y, and its projection on the carrier layer 11 overlaps with each second electrode 132. The third trace 1522a is electrically connected to each second electrode 132 through a second via 153. The fourth trace 1522b has its projection on the carrier layer 11 overlap with the second conductive via 22, and the fourth trace 1522b is electrically connected to the second conductive via 22 through the second via 153. This configuration not only facilitates electrical connection between the second sublayer 1522 and the second conductive via 22 and each second electrode 132, but also reduces the area occupied by the second sublayer 1522 on the second redistribution layer 15, thereby facilitating the optimized layout of other structures on the second redistribution layer 15.

[0152] As shown in Figures 17 and 18, Figure 17 is a simplified structural diagram of the capacitor 120 in the third embodiment of the present application, and Figure 18 is a longitudinal cross-sectional view of the capacitor 120 in the third embodiment of the present application. The main difference between the capacitor 120 in this embodiment and the capacitor 120 shown in Figures 5 to 12 is that the number of sub-capacitors 1 in the capacitor 120 is different. The number of sub-capacitors 1 in the capacitor 120 shown in Figures 5 to 12 is two, while the number of sub-capacitors 1 in the capacitor 120 in this embodiment is three or more, as described below:

[0153] Capacitor 120 includes three stacked sub-capacitors 1, namely a first sub-capacitor 1a, a second sub-capacitor 1b, and a third sub-capacitor 1c. The first sub-capacitor 1a and the second sub-capacitor 1b are adjacent sub-capacitors 1, while the second sub-capacitor 1b and the third sub-capacitor 1c are adjacent sub-capacitors 1. The back surface 117b of the first sub-capacitor 1a is adjacent to the front surface 117a of the second sub-capacitor 1b, and the back surface 117b of the second sub-capacitor 1b is adjacent to the front surface 117a of the third sub-capacitor 1c. Capacitor units 12a, 12b, and 12c are positioned correspondingly.

[0154] For the first sub-capacitor 1a and the second sub-capacitor 1b, a conductive hole 2 is provided on the first sub-capacitor 1a, the capacitor unit 12a is located on the carrier layer 11 of the first sub-capacitor 1a, and the capacitor unit 12b is located on the carrier layer 11 of the second sub-capacitor 1b. The electrodes 13 of the capacitor unit 12a and the capacitor unit 12b are respectively electrically connected through the conductive hole 2 on the first sub-capacitor 1a, so that the capacitor unit 12a and the capacitor unit 12b are connected in parallel.

[0155] For the second sub-capacitor 1b and the third sub-capacitor 1c, a conductive hole 2 is provided on the second sub-capacitor 1b, and the capacitor unit 12c is located on the carrier layer 11 of the third sub-capacitor 1c. The electrodes 13 of the capacitor unit 12b and the capacitor unit 12c are respectively electrically connected through the conductive hole 2 on the second sub-capacitor 1b, so that the capacitor unit 12b and the capacitor unit 12c are connected in parallel.

[0156] The number of the capacitor unit 12 in each sub-capacitor 1 may be one or more, and the capacitor units 12 at corresponding positions in the multiple sub-capacitors 1 are connected in parallel through the conductive holes 2 .

[0157] The number of sub-capacitors 1 in the capacitor 120 of this embodiment is not limited to three, and can also be four or more, and can be set according to actual needs.

[0158] As shown in Figures 19 to 22, Figure 19 is a schematic structural diagram of the capacitor 120 in the fourth embodiment of the present application, Figure 20 is a top view of the capacitor 120 in the fourth embodiment of the present application, Figure 21 is an EE cross-sectional view of the capacitor 120 in Figure 20, and Figure 22 is a schematic structural diagram of the sub-capacitor 1 in the fourth embodiment of the present application.

[0159] The main difference between the capacitor 120 in this embodiment and the capacitor 120 shown in Figures 5 to 12 is that the arrangement of the electrode 13 of the capacitor unit 12 in the sub-capacitor 1 is different. The first electrode 131 and the second electrode 132 of the sub-capacitor 1 shown in Figures 5 to 12 are both arranged on the front surface 117a of the carrier layer 11 of the sub-capacitor 1, while in this embodiment, the second electrode 132 of the sub-capacitor 1 is arranged on the front surface 117a of the carrier layer 11, and the first electrode 131 of the sub-capacitor 1 is arranged on the back surface 117b of the carrier layer 11, as described below:

[0160] As shown in Figure 19, capacitor 120 includes two stacked sub-capacitors 1, namely a first sub-capacitor 1a and a second sub-capacitor 1b. The first sub-capacitor 1a and the second sub-capacitor 1b are adjacent sub-capacitors 1. Capacitor unit 12a is located on the carrier layer 11 of the first sub-capacitor 1a, with the second electrode 132 of capacitor unit 12a located on the front surface 117a of the carrier layer 11, and the first electrode 131 of capacitor unit 12a located on the back surface 117b of the carrier layer 11. Capacitor unit 12b is located on the carrier layer 11 of the second sub-capacitor 1b, with the second electrode 132 of capacitor unit 12b located on the front surface 117a of the carrier layer 11, and the first electrode 131 of capacitor unit 12b located on the back surface 117b of the carrier layer 11. The positions of capacitor units 12a and 12b correspond to each other.

[0161] The back surface 117b of the first sub-capacitor 1a is arranged adjacent to the front surface 117a of the second sub-capacitor 1b, the second electrode 132 of the capacitor unit 12a is electrically connected to the second electrode 132 of the capacitor unit 12b through the second conductive via 22, and the first electrode 131 of the capacitor unit 12a is electrically connected to the first electrode 131 of the capacitor unit 12b through the first conductive via 21, so that the capacitor unit 12a and the capacitor unit 12b are connected in parallel.

[0162] Specifically, the second conductive via 22 penetrates the carrier layer 11 of the first sub-capacitor 1a, and the first end (upper end in the figure) of the second conductive via 22 is electrically connected to the second electrode 132 of the capacitor unit 12a, and the second end (lower end in the figure) of the second conductive via 22 is electrically connected to the second electrode 132 of the capacitor unit 12b via the interconnect structure 3. The first conductive via 21 penetrates the carrier layer 11 of the second sub-capacitor 1b, and the first end (lower end in the figure) of the first conductive via 21 is electrically connected to the first electrode 131 of the capacitor unit 12b, and the second end (upper end in the figure) of the first conductive via 21 is electrically connected to the first electrode 131 of the capacitor unit 12a via the interconnect structure 3. That is, in two adjacent sub-capacitors 1, for any one conductive via 2, the conductive via 2 penetrates the carrier layer 11 of one sub-capacitor 1, and the first end of the conductive via 2 is electrically connected to the electrode 13 of one sub-capacitor 1, and the second end of the conductive via 2 is electrically connected to the electrode 13 of the other sub-capacitor 1 via the interconnect structure 3.

[0163] In some embodiments, as shown in Figures 20 and 21, a first redistribution layer 14 is provided on the back surface 117b of the first sub-capacitor 1a, covering the second end (the lower end in the figure) of the second conductive via 22. The first redistribution layer 14 is electrically connected to the second end of the second conductive via 22. The front surface 117a of the second sub-capacitor 1b is provided with a second redistribution layer 15 covering the second electrode 132 thereof. The second redistribution layer 15 is electrically connected to the second electrode 132 of the second sub-capacitor 1b. An interconnect structure 3 is provided between the first redistribution layer 14 and the second redistribution layer 15 to electrically connect the second end of the second conductive via 22 to the second electrode 132 of the second sub-capacitor 1b.

[0164] In some embodiments, as shown in Figure 21, the front side 117a of the first sub-capacitor 1a is provided with a second redistribution layer 15 covering the first end (the upper end in the figure) of the second conductive hole 22, and the second redistribution layer 15 electrically connects the first end of the second conductive hole 22 with the second electrode 132 of the first sub-capacitor 1a.

[0165] In some embodiments, as shown in Figures 20 and 21, the front surface 117a of the second sub-capacitor 1b is provided with a first redistribution layer 14 covering the second end (the upper end in the figure) of the first conductive via 21. The first redistribution layer 14 is electrically connected to the second end of the first conductive via 21. The back surface 117b of the first sub-capacitor 1a is provided with a second redistribution layer 15 covering the first electrode 131 thereof. The second redistribution layer 15 is electrically connected to the first electrode 131 of the first sub-capacitor 1a. An interconnect structure 3 is provided between the first redistribution layer 14 and the second redistribution layer 15 to electrically connect the second end of the first conductive via 21 to the first electrode 131 of the first sub-capacitor 1a.

[0166] In some embodiments, as shown in Figure 21, the back side 117b of the second sub-capacitor 1b is provided with a second redistribution layer 15 covering the first end (the lower end in the figure) of the first conductive hole 21, and the second redistribution layer 15 electrically connects the first end of the first conductive hole 21 with the first electrode 131 of the second sub-capacitor 1b.

[0167] In some embodiments, as shown in FIG21 , the first redistribution layer 14 and the second redistribution layer 15 on the back surface 117 b of the first sub-capacitor 1 a are the same redistribution layer and are manufactured using the same process. Alternatively, the first redistribution layer 14 and the second redistribution layer 15 on the back surface 117 b of the first sub-capacitor 1 a may be separated and manufactured using different processes.

[0168] In some embodiments, as shown in FIG21 , the first redistribution layer 14 and the second redistribution layer 15 on the front surface 117 a of the second sub-capacitor 1 b are the same redistribution layer and are manufactured using the same process. Alternatively, the first redistribution layer 14 and the second redistribution layer 15 on the front surface 117 a of the second sub-capacitor 1 b may be separated and manufactured using different processes.

[0169] In some embodiments, as shown in Figure 22, the supporting layer 11 of the sub-capacitor 1 includes a substrate layer 111, a first groove 112 is provided on the substrate layer 111, and a portion (or all) of the capacitor unit 12 is arranged in the first groove 112. The capacitor unit 12 includes a first capacitor conductive layer 121, a second capacitor conductive layer 122, and a dielectric layer 123 arranged between the first capacitor conductive layer 121 and the second capacitor conductive layer 122.

[0170] The carrier layer 11 of the sub-capacitor 1 also includes an upper insulating layer 113, which is arranged on the substrate layer 111 and covers the capacitor unit 12. The second electrode 132 of the capacitor unit 12 is arranged on the upper insulating layer 113. A second connecting via 115 is provided on the upper insulating layer 113, and the second connecting via 115 is connected between the second electrode 132 and the second capacitor conductive layer 122; the first electrode 131 of the capacitor unit 12 is provided on the lower surface of the substrate layer 111 (that is, the back side 117b of the carrier layer 11), and a first connecting via 114 is provided on the lower surface of the substrate layer 111, and the first connecting via 114 is provided between the first electrode 131 and the first capacitor conductive layer 121.

[0171] In some embodiments, as shown in FIG22 , the first capacitor conductive layer 121 fills the first trench 112 , and a plurality of second trenches 1211 are spaced apart on the first capacitor conductive layer 121 . The dielectric layer 123 includes a first dielectric layer 1231 and a second dielectric layer 1232 . The first dielectric layer 1231 covers the walls of the second trenches 1211 , and the second dielectric layer 1232 is disposed at the edges of the second trenches 1211 and connected to the first dielectric layer 1231 .

[0172] The second capacitor conductive layer 122 includes a filling layer 1221 and a connecting layer 1222. The filling layer 1221 is disposed on the first dielectric layer 1231. The filling layer 1221 and the first dielectric layer 1231 fill the second trench 1211. The connecting layer 1222 is disposed on the second dielectric layer 1232 and the filling layer 1221. The second connecting via 115 is connected between the connecting layer 1222 and the second electrode 132.

[0173] Among them, the first electrode 131 and the second electrode 132 of the capacitor unit 12 can be set as one or multiple. For example, as shown in Figure 22, the capacitor unit 12 has two first electrodes 131 and four second electrodes 132. Each first electrode 131 is electrically connected to the first capacitor conductive layer 121 through the first connecting via 114, and each second electrode 132 is electrically connected to the connecting layer 1222 through the second connecting via 115.

[0174] As shown in FIG23 , FIG23 is a simplified structural diagram of a capacitor 120 in the fifth embodiment of the present application. The main difference between the capacitor 120 in this embodiment and the capacitor 120 shown in FIG19 to FIG22 is that the number of sub-capacitors 1 in the capacitor 120 is different, as described below:

[0175] The capacitor 120 includes three sub-capacitors 1 arranged in a stacked manner, and the three sub-capacitors 1 are respectively a first sub-capacitor 1a, a second sub-capacitor 1b and a third sub-capacitor 1c. The first sub-capacitor 1a and the second sub-capacitor 1b are two adjacent sub-capacitors 1, and the second sub-capacitor 1b and the third sub-capacitor 1c are two adjacent sub-capacitors 1. The back surface 117b of the first sub-capacitor 1a is arranged adjacent to the front surface 117a of the second sub-capacitor 1b, and the back surface 117b of the second sub-capacitor 1b is arranged adjacent to the front surface 117a of the third sub-capacitor 1c.

[0176] Capacitor unit 12a is located on the carrier layer 11 of the first sub-capacitor 1a, with the second electrode 132 of capacitor unit 12a located on the front surface 117a of the carrier layer 11, and the first electrode 131 of capacitor unit 12a located on the back surface 117b of the carrier layer 11. Capacitor unit 12b is located on the carrier layer 11 of the second sub-capacitor 1b, with the second electrode 132 of capacitor unit 12b located on the front surface 117a of the carrier layer 11, and the first electrode 131 of capacitor unit 12b located on the back surface 117b of the carrier layer 11. Capacitor unit 12c is located on the carrier layer 11 of the third sub-capacitor 1c, with the second electrode 132 of capacitor unit 12c located on the front surface 117a of the carrier layer 11, and the first electrode 131 of capacitor unit 12c located on the back surface 117b of the carrier layer 11. The positions of capacitor units 12a, 12b, and 12c correspond to each other.

[0177] The first sub-capacitor 1 a is provided with a second conductive hole 22 , the second sub-capacitor 1 b is provided with a first conductive hole 21 and a second conductive hole 22 , and the third sub-capacitor 1 c is provided with a first conductive hole 21 .

[0178] For the first sub-capacitor 1a and the second sub-capacitor 1b, the second electrodes 132 of the capacitor unit 12a and the capacitor unit 12b are electrically connected through the second conductive hole 22 on the first sub-capacitor 1a, and the first electrodes 131 of the capacitor unit 12a and the capacitor unit 12b are electrically connected through the first conductive hole 21 on the second sub-capacitor 1b, so that the capacitor unit 12a and the capacitor unit 12b are connected in parallel.

[0179] For the second sub-capacitor 1b and the third sub-capacitor 1c, the second electrodes 132 of the capacitor unit 12b and the capacitor unit 12c are electrically connected through the second conductive hole 22 on the second sub-capacitor 1b, and the first electrodes 131 of the capacitor unit 12b and the capacitor unit 12c are electrically connected through the first conductive hole 21 on the third sub-capacitor 1c, so that the capacitor unit 12b and the capacitor unit 12c are connected in parallel.

[0180] The number of the capacitor unit 12 in each sub-capacitor 1 may be one or more, and the capacitor units 12 at corresponding positions in the multiple sub-capacitors 1 are connected in parallel through the conductive holes 2 .

[0181] In this embodiment, the number of sub-capacitors 1 in the capacitor 120 is not limited to three, and may be four or more, and may be set according to actual needs.

[0182] As shown in Figures 24a to 24g, Figures 24a to 24g are schematic diagrams showing the manufacturing process of the capacitor 120 in the first embodiment of the present application. The capacitor 120 includes a plurality of sub-capacitors 1, each of which includes a carrier layer 11 and a capacitor unit 12 embedded in the carrier layer 11, and the capacitor unit 12 has an electrode 13. As shown in Figure 25a, the manufacturing method of the capacitor 120 includes:

[0183] S200 , as shown in FIG. 24 f and FIG. 24 g , a plurality of sub-capacitors 1 are stacked.

[0184] At least one of the two adjacent sub-capacitors 1 is provided with a conductive hole 2 , and the conductive hole 2 electrically connects the electrodes 13 of the two adjacent sub-capacitors 1 , so that the capacitor units 12 of the two adjacent sub-capacitors 1 are connected in parallel.

[0185] For example, as shown in Figure 24f and Figure 24g, two adjacent sub-capacitors 1 are respectively the first sub-capacitor 1a and the second sub-capacitor 1b. A conductive hole 2 is provided on the carrying layer 11 of the first sub-capacitor 1a. The conductive hole 2 electrically connects the electrode 13 of the capacitor unit 12a of the first sub-capacitor 1a and the electrode 13 of the capacitor unit 12b in the second sub-capacitor 1b, so that the capacitor unit 12a is connected in parallel with the capacitor unit 12b.

[0186] The number of capacitor units 12 in the first sub-capacitor 1a and the second sub-capacitor 1b can be one or more. For example, as shown in Figure 24f and Figure 24g, the number of capacitor units 12 in the first sub-capacitor 1a and the second sub-capacitor 1b is two, and the capacitor units 12 in the first sub-capacitor 1a and the second sub-capacitor 1b with corresponding positions are electrically connected through the conductive hole 2.

[0187] In some embodiments, as shown in FIG25 a , before the two adjacent sub-capacitors 1 are stacked, the method further includes:

[0188] S100: As shown in FIG24a to FIG24d, a conductive via 2 is provided on at least one of two adjacent sub-capacitors 1. That is, the conductive via 2 is provided after the sub-capacitors 1 are manufactured, that is, the conductive via 2 is provided on the carrier layer 11 of the finished sub-capacitor 1.

[0189] Such an arrangement can reduce the damage to the conductive hole 2 caused by the production and transportation process of the sub-capacitor 1, thereby improving the conductive reliability of the conductive hole 2; at the same time, this can also improve the versatility of the sub-capacitor 1, that is: the sub-capacitor 1 without the conductive hole 2 can be used alone, and the sub-capacitor 1 with the conductive hole 2 can be stacked together to assemble into a capacitor 120.

[0190] Of course, the conductive hole 2 can also be provided during the manufacturing stage of the sub-capacitor 1 . For example, the conductive hole 2 can be provided on the carrier layer 11 after the capacitor unit 12 is provided on the carrier layer 11 .

[0191] In some embodiments, as shown in FIG. 25 b , for a sub-capacitor 1 to be provided with a conductive via 2 , providing the conductive via 2 on the sub-capacitor 1 includes:

[0192] S110 , as shown in FIG. 24 a , a blind hole 25 is provided on the front surface 117 a of the carrier layer 11 .

[0193] The blind hole 25 can be located between two adjacent capacitor units 12. The blind hole 25 can be formed by an etching process, such as laser etching. The diameter of the blind hole 25 is 1 to 10 μm, and the depth of the blind hole 25 is 30 to 150 μm. Of course, this is not limited to the above. The diameter and depth of the blind hole 25 can also be set to other values ​​according to actual conditions.

[0194] S120 , as shown in FIG. 24 b , disposing the conductor 24 in the blind hole 25 .

[0195] The conductor 24 may be made of metal, such as copper or tungsten, etc. The conductor 24 may be formed in the blind hole 25 by electroplating or directly filled in the blind hole 25, which is not specifically limited here.

[0196] When the conductor 24 can be formed in the blind hole 25 by electroplating, an insulating layer and a seed layer can be sequentially provided on the hole wall of the blind hole 25 before the conductor 24 is provided in the blind hole 25. The seed layer can provide conductivity to facilitate electroplating. The material of the seed layer can be titanium, copper, or gold, depending on the actual situation.

[0197] S130 , as shown in FIG. 24 d , the carrier layer 11 is thinned from the back side thereof so that the conductor 24 is exposed from the back side 117 b of the carrier layer 11 to form a conductive hole 2 .

[0198] The back surface 117b of the carrier layer 11 can be ground to thin the carrier layer 11. However, this is not limiting, and the back surface 117b of the carrier layer 11 can also be laser etched to thin the carrier layer 11. Along the thickness direction of the carrier layer 11, the front surface 117a is one side surface of the carrier layer 11, and the back surface 117b is the other side surface of the carrier layer 11.

[0199] In this embodiment, the conductive via 2 is formed by fabricating a blind via 25, providing a conductor 24, and thinning the back side of the carrier layer 11. The fabrication of the conductive via 2 causes minimal damage to other structures of the sub-capacitor 1, thereby ensuring the reliability of the sub-capacitor 1. Furthermore, the conductor 24 is disposed in the blind via 25. Before thinning the back side of the carrier layer 11, the bottom of the blind via 25 supports the conductor 24. This eliminates the need for additional structures to support the conductor 24, thereby simplifying the fabrication process of the conductive via 2.

[0200] Of course, the conductive hole 2 can also be made by other methods, for example, a second redistribution layer 15 is set on the front side 117a of the carrier layer 11, and then a through hole is set on the back side 117b of the carrier layer 11, the through hole passes through the carrier layer 11, and the second redistribution layer 15 covers the opening of the through hole; a conductor 24 is set in the through hole to form a conductive hole 2, wherein the conductor 24 is electrically connected to the second redistribution layer 15.

[0201] In some embodiments, as shown in Figures 24f and 24g, the electrodes 13 of the capacitor unit 12 are all arranged on the front side 117a of the carrier layer 11; the conductive holes 2 connected between the electrodes 13 of two adjacent sub-capacitors 1 are all arranged on the first sub-capacitor 1a and pass through the carrier layer 11 of the first sub-capacitor 1a.

[0202] The two adjacent sub-capacitors 1 are stacked, comprising:

[0203] S210 , as shown in FIG. 24 f and FIG. 24 g , electrically connect the electrode 13 of the second sub-capacitor 1 b to the conductive via 2 on the first sub-capacitor 1 a through the interconnection structure 3 , so that the first sub-capacitor 1 a and the second sub-capacitor 1 b are stacked.

[0204] The electrode 13 of the second sub-capacitor 1b is electrically connected to the conductive hole 2 on the first sub-capacitor 1a through the interconnection structure 3. In this way, the interconnection structure 3 can electrically connect the conductive holes 2 at different positions to the electrode 13 of the second sub-capacitor 1b. Then, the conductive hole 2 does not need to be set at the position corresponding to the electrode 13 of the second sub-capacitor 1b, thereby facilitating the setting of the conductive hole 2.

[0205] In some embodiments, electrically connecting the electrode 13 of the second sub-capacitor 1 b to the conductive via 2 on the first sub-capacitor 1 a through the interconnect structure 3 includes:

[0206] S211 , as shown in FIG. 24 e , disposing a first redistribution layer 14 on the back surface 117 b of the carrier layer 11 of the first sub-capacitor 1 a to electrically connect to the conductive via 2 .

[0207] S212 , as shown in FIG. 24 f , disposing a second redistribution layer 15 on the front surface 117 a of the carrier layer 11 of the second sub-capacitor 1 b to electrically connect to the electrode 13 of the second sub-capacitor 1 b .

[0208] S213 , as shown in FIG. 24 g , electrically connect the second redistribution layer 15 to the first redistribution layer 14 through the interconnect structure 3 .

[0209] Of course, the order of the above steps S211 and S212 can also be reversed, that is, S212 is executed first, and then S211 is executed.

[0210] By providing the first redistribution layer 14, the first redistribution layer 14 can electrically connect the interconnect structures 3 at different locations to the second ends of the conductive vias 2. This eliminates the need for the interconnect structures 3 to be located at locations corresponding to the second ends of the conductive vias 2, thereby facilitating the placement of the interconnect structures 3. By providing the second redistribution layer 15, the second redistribution layer 15 can electrically connect the interconnect structures 3 at different locations to the electrodes 13 of the second sub-capacitors 1b. This eliminates the need for the interconnect structures 3 to be located at locations corresponding to the electrodes 13 of the second sub-capacitors 1b, thereby facilitating the placement of the interconnect structures 3.

[0211] In some embodiments, before electrically connecting the second sub-capacitor 1b to the conductive hole 2 on the first sub-capacitor 1a through the interconnection structure 3, it also includes: as shown in Figure 24c, setting a second redistribution layer 15 on the front side 117a of the supporting layer 11 of the first sub-capacitor 1a to electrically connect the electrode 13 of the first sub-capacitor 1a and the conductive hole 2.

[0212] By setting up the second redistribution layer 15, the second redistribution layer 15 can electrically connect the conductive holes 2 at different positions with the electrodes 13 of the first sub-capacitor 1a, so that the conductive holes 2 do not need to be set at the positions of the electrodes 13 of the first sub-capacitor 1a, thereby facilitating the setting of the conductive holes 2.

[0213] In some embodiments, as shown in Figures 24b and 24c , after the conductor 24 is disposed in the blind via 25, the second redistribution layer 15 is disposed on the front surface 117a of the carrier layer 11 of the first sub-capacitor 1a. This eliminates the need to flip the first sub-capacitor 1a to install the first redistribution layer 14 after thinning the back surface 117b of the carrier layer 11. This reduces the number of flips required for the first sub-capacitor 1a and simplifies the capacitor manufacturing process.

[0214] Of course, after the conductive via 2 is formed on the first sub-capacitor 1 a , the second redistribution layer 15 may be disposed on the front surface 117 a of the carrier layer 11 of the first sub-capacitor 1 a .

[0215] The features that appear in the embodiment of the method for manufacturing the capacitor 120 and are the same as or similar to those in the above-mentioned product embodiment of the capacitor 120 can be specifically referred to the description in the above-mentioned product embodiment of the capacitor 120 and will not be repeated here.

[0216] The types of hatching in the drawings of this application are for distinguishing different components and should not be understood as limiting the materials of the components. The drawings of this application are mainly for illustrating the structure of the product and are not shown according to the actual scale of the product.

[0217] Although the description of this application will be introduced in conjunction with some embodiments, this does not mean that the features of this application are limited to these embodiments. On the contrary, the purpose of introducing the application in conjunction with the embodiments is to cover other options or modifications that may be extended based on the claims of this application. In order to provide a deep understanding of this application, the above description will contain many specific details. This application can also be implemented without using these details. In addition, in order to avoid confusion or blurring the focus of this application, some specific details will be omitted in the description. It should be noted that the embodiments in this application and the features in the embodiments can be combined with each other unless there is a conflict.

[0218] In the embodiments of the present application, the terms "first," "second," "third," "fourth," "fifth," and "sixth" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature specified as "first," "second," "third," "fourth," "fifth," and "sixth" may explicitly or implicitly include one or more of the features.

[0219] In the embodiments of this application, "and / or" is simply a description of the association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this document generally indicates that the related objects are in an "or" relationship.

[0220] In the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium. The directional terms mentioned in the embodiments of the present application, such as "up", "down", "left", "right", "inside", "outside", etc., are only reference to the directions of the accompanying drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the embodiments of the present application, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application. "Multiple" means at least two.

[0221] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in yet other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0222] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A capacitor, characterized in that: It comprises a plurality of sub-capacitors (1) arranged in a stacked manner; each of the plurality of sub-capacitors (1) comprises a carrier layer (11), a capacitor unit (12) embedded in the carrier layer (11), and the capacitor unit (12) has an electrode (13); Among the plurality of sub-capacitors (1), at least one of two adjacent sub-capacitors (1) is provided with a conductive hole (2), and the conductive hole (2) electrically connects the electrodes (13) of the two adjacent sub-capacitors (1) so that the capacitance units (12) of the two adjacent sub-capacitors (1) are connected in parallel.

2. The capacitor according to claim 1, characterized in that In the two adjacent sub-capacitors (1), for any one of the conductive holes (2), the conductive hole (2) penetrates the carrier layer (11) of one of the sub-capacitors (1), and the first end of the conductive hole (2) is electrically connected to the electrode (13) of one of the sub-capacitors (1), and the second end of the conductive hole (2) is electrically connected to the electrode (13) of the other sub-capacitor (1) through an interconnection structure (3).

3. The capacitor according to claim 2, characterized in that The interconnect structure (3) comprises a bump (31), a first pad (32) and a second pad (33); the first pad (32) is arranged on one of the sub-capacitors (1) and is electrically connected to the second end of the conductive hole (2); the second pad (33) is arranged on the other sub-capacitor (1) and is electrically connected to the electrode (13) of the other sub-capacitor (1); the bump (31) is arranged between the first pad (32) and the second pad (33).

4. The capacitor according to claim 2, characterized in that The interconnect structure (3) is a hybrid bonding structure and comprises a plurality of third pads (34) and a plurality of fourth pads (35), each of the third pads (34) being arranged on one of the sub-capacitors (1) and being electrically connected to the second end of the conductive hole (2); each of the fourth pads (35) being arranged on the other sub-capacitor (1) and being electrically connected to the electrode (13) of the other sub-capacitor (1), and each of the third pads (34) being in contact with the corresponding fourth pad (35).

5. The capacitor according to any one of claims 2 to 4, characterized in that: One of the sub-capacitors (1) further comprises a first redistribution layer (14), the first redistribution layer (14) covering the second end of the conductive hole (2); the first redistribution layer (14) comprises a first insulating layer (141), and a first conductive layer (142) and a first via hole (143) embedded in the first insulating layer (141), the first via hole (143) being connected between the first conductive layer (142) and the second end of the conductive hole (2); a portion of the interconnection structure (3) is disposed on the first insulating layer (141) and is electrically connected to the first conductive layer (142).

6. The capacitor according to claim 5, characterized in that The first redistribution layer (14) further comprises a fifth pad (144), wherein the fifth pad (144) is embedded in the first insulating layer (141), and the fifth pad (144) is arranged at the second end of the conductive hole (2), and the first via (143) is connected between the fifth pad (144) and the first conductive layer (142).

7. The capacitor according to any one of claims 2 to 6, characterized in that: The other sub-capacitor (1) further comprises a second redistribution layer (15), wherein the second redistribution layer (15) covers the electrode (13) of the other sub-capacitor (1); the second redistribution layer (15) comprises a second insulating layer (151), and a second conductive layer (152) and a second via hole (153) embedded in the second insulating layer (151), wherein the second via hole (153) is connected between the second conductive layer (152) and the electrode (13) of the other sub-capacitor (1); a portion of the interconnection structure (3) is disposed on the second insulating layer (151) and is electrically connected to the second conductive layer (152).

8. The capacitor according to any one of claims 1 to 6, characterized in that: The carrier layer (11) comprises a front side (117a) and a back side (117b) arranged opposite to each other, the electrode (13) comprises a first electrode (131) and a second electrode (132), and the first electrode (131) and the second electrode (132) are both arranged on the front side (117a) of the carrier layer (11); The two adjacent sub-capacitors (1) are respectively a first sub-capacitor (1a) and a second sub-capacitor (1b); the back surface (117b) of the first sub-capacitor (1a) and the front surface (117a) of the second sub-capacitor (1b) are arranged adjacent to each other; the conductive hole (2) connected between the first electrodes (131) of the two adjacent sub-capacitors (1) and the conductive hole (2) connected between the first electrodes (131) of the two adjacent sub-capacitors (1) The conductive holes (2) between the second electrodes (132) of the two adjacent sub-capacitors (1) are both arranged on the first sub-capacitor (1a) and penetrate the supporting layer (11) of the first sub-capacitor (1a).

9. The capacitor according to claim 8, characterized in that The first sub-capacitor (1a) further comprises a second redistribution layer (15), the second redistribution layer (15) covering the front surface (117a) of the carrier layer (11); the second redistribution layer (15) comprises a second insulating layer (151), and a second conductive layer (152) and a second via (153) embedded in the second insulating layer (151); The second conductive layer (152) comprises a first sublayer (1521) and a second sublayer (1522); the first sublayer (1521) is electrically connected to the first electrode (131) and a portion of the conductive holes (2) through the second via holes (153), and the second sublayer (1522) is electrically connected to the second electrode (132) and another portion of the conductive holes (2) through the second via holes (153).

10. The capacitor according to claim 9, characterized in that The second redistribution layer (15) further comprises a sixth pad (154), wherein the sixth pad (154) is embedded in the second insulating layer (151), and the sixth pad (154) is arranged at the first end of the conductive hole (2) and is electrically connected to the corresponding second via hole (153).

11. The capacitor according to claim 9 or 10, characterized in that: In the first sub-capacitor (1a), a capacitor array (116) is provided on the carrier layer (11), the capacitor array (116) comprises a plurality of capacitor units (12), and a first conductive hole (21) and a second conductive hole (22) are provided between two adjacent capacitor units (12) in the capacitor array (116); The first conductive hole (21) is the conductive hole (2) electrically connected to the first electrode (131), and the second conductive hole (22) is the conductive hole (2) electrically connected to the second electrode (132).

12. The capacitor according to claim 11, characterized in that In the capacitor array (116), a plurality of the capacitor units (12) are arranged along a first direction (Y), and the first electrodes (131) of the capacitor units (12) form a first electrode array (133), and the second electrodes (132) of the capacitor units (12) form a second electrode array (134), and the second electrode array (134) and the first electrode array (133) are arranged in a spaced relationship along a second direction (X), and the second direction (X) is perpendicular to the first direction (Y); Along the first direction (Y), the first conductive hole (21) is arranged between two adjacent first electrodes (131), and the second conductive hole (22) is arranged between two adjacent second electrodes (132).

13. The capacitor according to claim 11, characterized in that In the capacitor array (116), a plurality of the capacitor units (12) are arranged along a first direction (Y), and the first electrodes (131) of the capacitor units (12) form a first electrode array (133), and the second electrodes (132) of the capacitor units (12) form a second electrode array (134), and the second electrode array (134) and the first electrode array (133) are arranged in a spaced relationship along a second direction (X), and the second direction (X) is perpendicular to the first direction (Y); The first conductive holes (21) and the second conductive holes (22) are alternately arranged along the first direction (Y) to form a conductive hole array (23); the conductive hole array (23) is located between the first electrode array (133) and the second electrode array (134); and adjacent first conductive holes (21) and second conductive holes (22) in the conductive hole array (23) are respectively located on both sides of the corresponding capacitor unit (12).

14. A chip, characterized in that: It comprises a carrier substrate (110), a bare chip (130) arranged on the carrier substrate (110), and a capacitor (120) according to any one of claims 1 to 13, wherein the capacitor (120) is arranged on the carrier substrate (110).

15. The chip according to claim 14, characterized in that: The capacitor (120) is arranged on a side surface of the carrier substrate (110) away from the bare chip (130), and a projection of the capacitor (120) on the carrier substrate (110) at least partially overlaps with a projection of a core (135) of the bare chip (130) on the carrier substrate (110).

16. An electronic device, characterized in that: It comprises a circuit board (400) and the chip (100) according to claim 14 or 15, wherein the chip (100) is arranged on the circuit board (400).

17. The electronic device according to claim 16, characterized in that: A first capacitor (170) is provided on a surface of the circuit board (400) on a side away from the bare chip (130). A projection of the capacitor (170) on the carrier substrate (110) at least partially overlaps with a projection of the core (135) of the bare chip (130) on the carrier substrate (110).

18. A method for manufacturing a capacitor, characterized in that: The capacitor comprises a plurality of sub-capacitors (1), each of the plurality of sub-capacitors (1) comprising a carrier layer (11), a capacitor unit (12) embedded in the carrier layer (11), and the capacitor unit (12) having an electrode (13); The method for manufacturing the capacitor comprises: stacking the plurality of sub-capacitors (1); At least one of the two adjacent sub-capacitors (1) is provided with a conductive hole (2), and the conductive hole (2) electrically connects the electrodes (13) of the two adjacent sub-capacitors (1) so that the capacitor units (12) of the two adjacent sub-capacitors (1) are connected in parallel.

19. The method for manufacturing a capacitor according to claim 18, wherein: Before stacking the two adjacent sub-capacitors (1), the method further comprises: The conductive hole (2) is provided on at least one of the two adjacent sub-capacitors (1).

20. The method for manufacturing a capacitor according to claim 19, wherein: For a sub-capacitor (1) on which the conductive hole (2) is to be provided, providing the conductive hole (2) on the sub-capacitor (1), comprising: A blind hole (25) is provided on the front side (117a) of the bearing layer (11); placing a conductor (24) in the blind hole (25); The carrier layer (11) is thinned from the back side of the carrier layer (11) so that the conductor (24) is exposed from the back side (117b) of the carrier layer (11) to form the conductive hole (2).

21. The method for manufacturing a capacitor according to claim 19 or 20, characterized in that: The electrodes (13) of the capacitor units (12) are all arranged on the front side (117a) of the carrier layer (11); the two adjacent sub-capacitors (1) are respectively a first sub-capacitor (1a) and a second sub-capacitor (1b); the conductive holes (2) connected between the electrodes (13) of the two adjacent sub-capacitors (1) are all arranged on the first sub-capacitor (1a) and penetrate the carrier layer (11) of the first sub-capacitor (1a); The two adjacent sub-capacitors (1) are stacked and arranged, comprising: The electrode (13) of the second sub-capacitor (1b) is electrically connected to the conductive hole (2) on the first sub-capacitor (1a) through an interconnection structure (3), so that the first sub-capacitor (1a) and the second sub-capacitor (1b) are stacked.

22. The method for manufacturing a capacitor according to claim 21, characterized in that: The electrode (13) of the second sub-capacitor (1b) is electrically connected to the conductive hole (2) on the first sub-capacitor (1a) through an interconnection structure (3), comprising: A first redistribution layer (14) is provided on the back side (117b) of the carrier layer (11) of the first sub-capacitor (1a) to be electrically connected to the conductive hole (2); A second redistribution layer (15) is provided on the front side (117a) of the carrier layer (11) of the second sub-capacitor (1b) to be electrically connected to the electrode (13) of the second sub-capacitor (1b); The second redistribution layer (15) is electrically connected to the first redistribution layer (14) through the interconnection structure (3).

23. The method for manufacturing a capacitor according to claim 21, characterized in that: Before the second sub-capacitor (1b) is electrically connected to the conductive hole (2) on the first sub-capacitor (1a) through the interconnection structure (3), the method further comprises: A second redistribution layer (15) is provided on the front side (117a) of the carrier layer (11) of the first sub-capacitor (1a) to electrically connect the electrode (13) of the first sub-capacitor (1a) and the conductive hole (2).

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