Mixed doped silicon wafer

Abstract

The present application relates to a silicon wafer, wherein the silicon wafer comprises antimony and carbon, and the ratio of the doping concentration of the antimony to the doping concentration of the carbon is 1:0.1 - 1:12.5.

Description

A mixed doped silicon wafer Technical Field

[0001] The present application belongs to the technical field of Czochralski single crystal silicon, and relates to a mixed-doped silicon wafer and a method for preparing the mixed-doped silicon wafer, as well as to a battery and a battery assembly comprising the silicon wafer. Background Art

[0002] With the increasing depletion of traditional energy and people's increasing demands for the environment, solar cells, as a pollution-free clean energy source, have experienced rapid development. As crystalline silicon solar cells currently occupy the vast majority of the solar cell market, their manufacturing technology has always represented the level of the entire solar cell industry.

[0003] The operating principle of a solar cell is as follows: When sunlight strikes a solar cell, it absorbs the light energy, generating photogenerated electron-hole pairs. Under the action of the cell's built-in electric field, the photogenerated electrons and holes are separated, resulting in the accumulation of oppositely charged charges at the cell's ends, generating a "photovoltaic voltage"—the so-called "photovoltaic effect." If electrodes are connected to a load on either side of the built-in electric field, a "photocurrent" flows through the load, generating power output. In this way, sunlight energy is directly converted into usable electrical energy.

[0004] The most important factor in the performance of solar cells is the photoelectric conversion efficiency. The minority carrier lifetime of silicon wafers is closely related to the conversion efficiency. To achieve higher photoelectric conversion efficiency, silicon wafers with longer minority carrier lifetimes are required.

[0005] Summary of the Invention

[0006] The inventors of this application have developed a silicon wafer doped with antimony as the main Group V doping element, which has good performance. The inventors of this application have found that if other elements are further mixed with antimony elements, the minority carrier lifetime distribution of the silicon wafer can be further broadened, and the minority carrier lifetime is more stable. The minority carrier lifetime varies greatly with the battery process, so this field urgently needs to further develop mixed-doped silicon wafers to solve the above problems.

[0007] After in-depth research, the applicant of this application has obtained a silicon wafer with a minority carrier lifetime significantly superior to that of the prior art. Specifically, this application involves the following:

[0008] 1. A silicon wafer, wherein the silicon wafer comprises antimony and carbon, and the ratio of the doping concentration of the antimony to the doping concentration of the carbon is 1:0.1 to 1:12.5.

[0009] 2. The silicon wafer according to item 1, wherein the carbon doping concentration range is 4E+13cm -3 ~2.5E+17cm -3 .

[0010] 3. The silicon wafer according to item 1 or 2, wherein the doping concentration of antimony is in the range of 4E+14cm -3 ~2E+16cm -3 , preferably 4.3E+14cm -3 to 1.9E+16cm -3 , more preferably 4.45E+14cm -3 to 1.87E+16cm -3 .

[0011] 4. The silicon wafer according to any one of items 1 to 3, wherein the doping concentration of antimony is greater than or equal to 4E+14 cm -3 When the doping concentration of antimony element is less than or equal to a, the ratio of the doping concentration of antimony element to the doping concentration of carbon element is 1:b to 1:12.5, wherein a is selected from 8E+15cm -3 ~1.2E+16cm -3 , preferably a is selected from 9E+15cm -3 ~1.1E+16cm -3 , further preferably a is 1E+16cm -3 , b is greater than 0.1, preferably b is greater than 0.5, and more preferably b is greater than 0.7.

[0012] 5. The silicon wafer according to any one of items 1 to 3, wherein the doping concentration of antimony is greater than a and less than or equal to 2E+16 cm -3 When the doping concentration of antimony element and carbon element is 1:0.1 to 1:c, a is selected from 8E+15cm -3 ~1.2E+16cm -3 , preferably a is selected from 9E+15cm -3 ~1.1E+16cm -3 , further preferably a is 1E+16cm -3 , c is less than 0.8, preferably c is less than 0.5, and more preferably c is less than 0.3.

[0013] 6. The silicon wafer according to any one of items 1 to 5, wherein the resistivity of the silicon wafer is 0.3 to 10 Ω·cm, preferably 0.4 to 8 Ω·cm, and more preferably 0.5 to 6 Ω·cm.

[0014] 7. The silicon wafer according to any one of items 1 to 6, wherein the minority carrier lifetime of the silicon wafer is greater than or equal to 200 microseconds, preferably greater than or equal to 300 microseconds, and more preferably greater than or equal to 500 microseconds.

[0015] 8. The silicon wafer according to any one of items 1 to 7, wherein the resistivity change rate of the silicon wafer is ≤0.6; preferably the resistivity change rate is ≤0.5, and preferably the resistivity change rate is ≤0.4.

[0016] 9. The silicon wafer according to any one of items 1 to 8, wherein the total oxygen content in the silicon wafer is 25 ppma or less, preferably 18 ppma or less, and more preferably 14 ppma or less, or

[0017] The total oxygen content in the silicon wafer is greater than 2 ppma, preferably greater than 3 ppma, and more preferably greater than 4 ppma.

[0018] 10. The silicon wafer according to any one of items 1 to 9, further comprising at least one of phosphorus, gallium, and germanium.

[0019] 11. The silicon wafer according to any one of items 1 to 10, wherein the mechanical strength of the silicon wafer is greater than or equal to 70 MPa, and / or the dispersion of the mechanical strength of the silicon wafer is less than or equal to 0.9.

[0020] 12. The silicon wafer according to any one of items 1 to 11, wherein the side length of at least one side of the silicon wafer is greater than or equal to 156 mm.

[0021] 13. The silicon wafer according to any one of items 1 to 12, wherein the silicon wafer is rectangular, one side of the rectangle is 156 mm to 300 mm in length, and the other side of the rectangle is 83 mm to 300 mm in length.

[0022] 14. The silicon wafer according to any one of items 1 to 13, further comprising a chamfer connecting two adjacent sides of the silicon wafer, wherein the arc length projection length of the chamfer is 1 mm to 1 mm.

[0023] 15. The silicon wafer according to any one of items 1 to 14, wherein the thickness of the silicon wafer is 40 μm to 170 μm, preferably 70 μm to 160 μm, and more preferably 80 μm to 140 μm.

[0024] 16. A solar cell comprising the silicon wafer according to any one of items 1 to 15.

[0025] 17. The solar cell according to item 16, wherein the mechanical strength of the solar cell is greater than or equal to 50 MPa, preferably greater than or equal to 60 MPa, and preferably greater than or equal to 70 MPa.

[0026] 18. The solar cell according to item 16 or 17, wherein the thickness of the solar cell is 40 μm to 170 μm, preferably 70 μm to 160 μm, and more preferably 80 μm to 140 μm.

[0027] 19. The solar cell according to any one of items 16 to 18, wherein a side distance of the solar cell is 156 mm to 300 mm, and another side distance of the solar cell is 83 mm to 300 mm.

[0028] 20. A solar cell comprising a silicon substrate, wherein the silicon substrate comprises a silicon base and a doped region within at least one surface of the silicon substrate, the silicon substrate containing antimony and carbon, the doped region being doped with a doping element selected from a Group III element or a Group V element, and the ratio of the doping concentration of the antimony element to the doping concentration of the carbon element being 1:0.1 to 1:12.5.

[0029] 21. The solar cell according to item 20, wherein the carbon doping concentration of the silicon substrate is in the range of 4E+13cm -3 ~2.5E+17cm -3 .

[0030] 22. The solar cell according to item 20 or 21, wherein the doping concentration of antimony in the silicon substrate is 4E+14 cm -3 to 2E+16cm -3 , preferably 4.3E+14cm -3 to 1.9E+16cm -3 , more preferably 4.45E+14cm -3 to 1.87E+16cm -3 .

[0031] 23. The solar cell according to any one of items 20 to 22, wherein the doping concentration of antimony element is greater than or equal to 4E+14 cm -3 When the doping concentration of antimony element is less than or equal to a, the ratio of the doping concentration of antimony element to the doping concentration of carbon element is 1:b to 1:12.5, wherein a is selected from 8E+15cm -3 ~1.2E+16cm -3 , preferably a is selected from 9E+15cm -3 ~1.1E+16cm -3 , further preferably a is 1E+16cm -3 , b is greater than 0.1, preferably b is greater than 0.5, and more preferably b is greater than 0.7.

[0032] 24. The solar cell according to any one of items 20 to 23, wherein the doping concentration of the antimony element is greater than a and less than or equal to 2E+16 cm -3 When the doping concentration of antimony element and carbon element is 1:0.1 to 1:c, a is selected from 8E+15cm -3 ~1.2E+16cm -3 , preferably a is selected from 9E+15cm-3 ~1.1E+16cm -3 , further preferably a is 1E+16cm -3 , c is less than 0.8, preferably c is less than 0.5, and more preferably c is less than 0.3.

[0033] 25. The solar cell according to any one of items 20 to 24, wherein the resistivity of the silicon substrate is 0.3 to 10 Ω·cm, preferably 0.4 to 8 Ω·cm, and more preferably 0.5 to 6 Ω·cm.

[0034] 26. The solar cell according to any one of items 20 to 25, wherein the minority carrier lifetime of the silicon substrate is greater than or equal to 200 microseconds, preferably greater than or equal to 300 microseconds, and further preferably greater than or equal to 500 microseconds.

[0035] 27. The solar cell according to any one of items 20 to 26, wherein the resistivity change rate of the silicon substrate is ≤0.6, preferably the resistivity change rate is ≤0.5, and preferably the resistivity change rate is ≤0.4.

[0036] 28. A solar cell according to any one of items 20 to 27, wherein the total oxygen content in the silicon substrate is below 25 ppma, preferably below 18 ppma, and further preferably below 14 ppma; or, the total oxygen content in the silicon substrate is above 2 ppma, preferably above 3 ppma, and further preferably above 4 ppma.

[0037] 29. The solar cell according to any one of items 20 to 28, wherein the silicon substrate further comprises at least one of phosphorus, gallium, and germanium.

[0038] 30. The solar cell according to any one of items 20 to 29, wherein the silicon substrate has at least one doping layer on its surface on at least one side.

[0039] 31. The solar cell according to item 30, wherein at least one passivation layer is provided between the doping layer and the doping region.

[0040] 32. In the solar cell according to any one of items 20 to 31, the doping concentration of antimony element in the doping region is substantially constant in the thickness direction of the silicon substrate.

[0041] 33. The solar cell according to any one of items 20 to 32, wherein

[0042] In the doping region, the sum of the doping concentration of the antimony element and the doping concentration of the doping element is less than or equal to 1E+21cm -3 .

[0043] 34. The solar cell according to any one of items 20 to 33, wherein the solar cell comprises:

[0044] - a light absorber comprising the silicon substrate for absorbing light and generating photogenerated carriers and a region for separating the carriers generated by the silicon substrate; and

[0045] - an electrode formed on the light absorber, the electrode including a metal crystal portion in contact with the light absorber, the metal crystal portion including antimony element.

[0046] 35. The solar cell according to any one of items 20 to 34, wherein the mechanical strength of the cell is 50 MPa; preferably greater than or equal to 60 MPa; preferably greater than or equal to 70 MPa.

[0047] 36. A cell string comprising solar cells interconnected by conductive interconnects, at least one of the solar cells being the solar cell of any one of items 16 to 35.

[0048] 37. The cell string of item 36, wherein the curvature of the solar cells is less than or equal to 2 mm.

[0049] 38. The cell string according to item 36 or 37, wherein the connecting wires are bonded to the solar cells by welding or conductive bonding.

[0050] 39. A battery string according to any one of item 38, wherein the welding comprises a heating step.

[0051] 40. The battery string according to any one of item 39, wherein the temperature range of the heating step is 100-160 degrees Celsius, and the curvature of the solar cell is less than or equal to 1.5 mm.

[0052] 41. The battery string according to item 39, wherein the temperature range of the heating step is 165-200 degrees Celsius, and the curvature of the solar cell is less than or equal to 2 mm.

[0053] 42. The cell string according to any one of items 36 to 41, wherein the conductive interconnect comprises an electrical contact portion that contacts an electrode of the solar cell, the electrical contact portion comprising antimony.

[0054] 43. A solar cell assembly comprising a plurality of cells, an encapsulation layer, a cover plate and a back plate, wherein the sealing layer seals the plurality of cells and is located between the cover plate and the back plate; the cell is a solar cell according to any one of items 16 to 35.

[0055] 44. The solar module of item 43, wherein the curvature of the cell is less than or equal to 1.2 mm.

[0056] 45. The solar module according to item 43 or 44, further comprising a frame, wherein the edges of the cover plate and / or back plate are embedded in the mounting portion of the frame.

[0057] 46. ​​The solar module according to any one of items 43 to 45, wherein the cover sheet and / or back sheet is a transparent sheet.

[0058] 47. The solar module according to any one of items 43 to 45, wherein the back sheet is a non-transparent sheet.

[0059] 48. The solar module according to any one of items 43 to 47, wherein the cells protrude toward the cover plate to form a curved shape.

[0060] 49. The solar module according to any one of items 43 to 48, wherein a plurality of the solar modules are interconnected by a conductive interconnector, wherein the conductive interconnector comprises an electrical contact portion for contacting an electrode of the solar cell, wherein the electrical contact portion comprises antimony.

[0061] Effects of the Invention

[0062] The applicant of this application discovered through in-depth research that doping antimony in silicon wafers can significantly improve resistivity. By designing appropriate mixed-doped silicon wafers, it was found that the minority carrier lifetime after antimony doping can be further improved, and the uniformity of the minority carrier lifetime can be further significantly improved.

[0063] This application adopts a co-doping solution of Sb and C to improve the overall minority carrier lifetime and the uniformity of minority carrier lifetime distribution.

[0064] The battery manufactured using the silicon wafer of the present application can have good battery efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] FIG1 is a schematic diagram of a battery structure (TOPCon structure) provided in this application.

[0066] Figure 2 is a schematic diagram of the battery stringing process.

[0067] Figure 3 is another schematic diagram of the battery stringing process.

[0068] FIG4 is a schematic diagram of a specific structure of a battery assembly.

[0069] FIG5 is another specific structural diagram of a battery assembly.

[0070] FIG6 shows a method for testing the resistivity change rate of a silicon wafer. DETAILED DESCRIPTION

[0071] The following embodiments of the present application are intended only to illustrate specific implementation methods for implementing the present application and are not to be construed as limiting the present application. Any other changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principles of the present application are deemed equivalent replacements and fall within the scope of protection of the present application.

[0072] The specific embodiments of the present application will be described in more detail below. However, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0073] It should be noted that certain words are used in the specification and claims to refer to specific components. Those skilled in the art should understand that technicians may use different nouns to refer to the same component. This specification and claims do not use the difference in nouns as a way to distinguish components, but use the difference in the functions of the components as the criterion for distinction. As mentioned throughout the specification and claims, "including" or "comprising" is an open term, so it should be interpreted as "including but not limited to". The subsequent description of the specification is a preferred embodiment of the present application, but the description is based on the general principles of the specification and is not intended to limit the scope of the present application. The scope of protection of this application shall be as defined by the attached claims.

[0074] As used herein, "substantially free" with respect to a particular component is used herein to mean that the particular component is not purposefully formulated into the composition and / or is present only as a contaminant or in trace amounts. Thus, the total amount of the particular component resulting from any unintentional contamination of the composition is less than 0.05%, preferably less than 0.01%. Most preferred are compositions wherein the amount of the particular component is undetectable by standard analytical methods.

[0075] As used in this specification, "a" or "an" may mean one or more. As used in the claims, when used with the word "comprising", the word "a" or "an" may mean one or more than one.

[0076] The term "or" is used in the claims to mean "and / or" unless explicitly stated to refer only to alternatives or the alternatives are mutually exclusive, although this disclosure supports a definition referring only to alternatives and "and / or." As used herein, "another" can mean at least a second or more.

[0077] Those skilled in the art will understand that silicon wafers generally refer to raw material bare silicon wafers, and silicon substrates generally refer to the parts formed by silicon wafers in batteries. Light absorbers generally refer to functional bodies in batteries for absorbing photons, generating photogenerated carriers and separating photogenerated carriers, which include silicon substrates and regions for separating carriers generated by silicon substrates (such as tunneling layers and doped polycrystalline layers in TOPCon structures), wherein the silicon substrate is used to absorb light and generate photogenerated carriers. It is understandable that simple emission-reducing layers, other functional layers, and electrodes do not belong to light absorbers. Those skilled in the art will understand that light absorbers or silicon substrates can be recycled from batteries, and silicon substrates defined in this application can be obtained by peeling off different stacked structures. In this application, the doping concentration of antimony elements in silicon wafers or silicon substrates can be detected by any method known to those skilled in the art, and those skilled in the art can make a choice based on demand, for example, it can be detected by methods such as SIMS, ICP-MS, GDMS, etc., preferably by ICP-MS method. Those skilled in the art will understand that the antimony doping concentration in a silicon wafer or silicon substrate may refer to the antimony doping concentration at any location on the surface of the silicon wafer or silicon substrate, within the silicon wafer or silicon substrate, or in the middle of the silicon wafer or silicon substrate. Alternatively, it may refer to the average antimony doping concentration at multiple locations (e.g., the concentration at a midpoint, an edge, etc.) or the average antimony doping concentration across the entire silicon wafer or silicon substrate. Based on the test conditions, the instrument used, and actual conditions, a person skilled in the art may select any of the aforementioned locations for testing, or may test multiple locations and calculate the average of the multiple locations to use as the antimony doping concentration.

[0078] In the present application, the doping concentration of the carbon element in silicon wafer or silicon substrate can be detected by any method known to those skilled in the art, and these methods skilled in the art can be selected based on demand, for example, can be detected by methods such as SIMS, ICP-MS, GDMS, preferably detected by ICP-MS method. It will be understood by those skilled in the art that the doping concentration of the carbon element in silicon wafer or silicon substrate can refer to the doping concentration of the carbon element at any site on the surface of silicon wafer or silicon substrate, silicon wafer or silicon substrate, and of course it can also be the average value of the carbon element doping concentration at multiple positions (such as the concentration at positions such as midpoint, edge) or the average value of the carbon element doping concentration on the entire silicon wafer or silicon substrate. Those skilled in the art can select the above-mentioned arbitrary site to detect based on the conditions detected and the instrument used and based on actual conditions, or calculate the average value of multiple sites after detecting multiple sites, as the doping concentration of the carbon element.

[0079] In this application, the minority carrier lifetime of a silicon wafer or silicon substrate can be measured by any method known to those skilled in the art, for example, a BCT-400 instrument, a WCT-120 instrument, or a WT-2000 instrument. During the measurement, the carrier injection level needs to be set to 1E+15cm -3 ~3E+15cm -3 , and measure the minority carrier lifetime at this injection level. However, it is fully understood by those skilled in the art that the above-mentioned injection levels (1E+15cm -3 ~3E+15cm -3 ) is just a setting range. If it is set in other ranges, it can also be converted.

[0080] The specific conversion method can be, for example, as follows: first, set a certain carrier injection level to perform minority carrier lifetime test, and obtain an injection level-minority carrier lifetime curve with the injection level as the horizontal axis and the minority carrier lifetime as the vertical axis. Using this curve, other carrier injection conditions (for example, 5E+14cm -3 The minority carrier lifetime of the carrier injection level is converted to 1E+15cm -3 ~3E+15cm -3 The minority carrier lifetime value at the carrier injection level.

[0081] In this application, the mechanical strength testing method for silicon wafers or silicon substrates is based on GB / T 6569-2006, Test Method for Bending Strength of Fine Ceramics. In this test method, bending strength refers to the maximum stress at which a material breaks under bending load. This method can also be used to test the curvature of batteries.

[0082] In this application, the mechanical strength dispersion of a silicon wafer or silicon substrate is used to characterize the strength uniformity of different silicon wafers produced using the same process. Lower dispersion indicates smaller strength differences between different silicon wafers. This can be tested using testing methods known in the art, such as using a single-column electronic universal testing machine.

[0083] In the present application, the doped region can also be used to separate photogenerated carriers, such as the region in which the third main group element (boron element) is diffused in the TOPCon cell described below.

[0084] That is, the silicon substrate is obtained from a bare silicon wafer, and the silicon substrate includes a silicon base portion and a doped region portion, wherein the silicon base portion is the body region that is not doped during the battery process, and its performance is the same as that of the raw material bare silicon wafer. The doped region can be a doped region that has basically the same performance and parameters as the body region except for the doping element, such as a doped region formed by direct doping or internal diffusion doping inside the bare silicon wafer. In addition, in some cases, the doped region contains antimony and doping elements, such as the third main group elements and the fifth main group elements, such as boron (B) or phosphorus (P); in some cases, the doped region may be basically the same as the body region, that is, it mainly includes an antimony doped region.

[0085] In cells with at least a partial TOPCon structure (e.g., TOPCon cells, local TOPCon cells, back contact hybrid cells, and TBC cells), the silicon substrate generally includes a doped region formed within the surface of at least one side of the silicon substrate, and the performance of this doped region portion is the same as that of the raw material bare silicon wafer. The doped region may be a doped region having substantially the same performance and parameters as the body region (i.e., substantially the same properties as antimony element concentration, resistivity change rate, resistivity offset rate, etc.) except for the difference in doping elements. Such a doped region may be formed by directly doping the bare silicon wafer as described in detail below, or by doping the doping elements into the bare silicon wafer, for example, through a doped passivation layer and an interface passivation layer. In the present application, for cells with at least a partial TOPCon structure, the doped region generally refers to a region formed by direct doping or internal doping inside the raw silicon wafer, wherein the internal doping is formed by doping the polysilicon layer through a tunneling layer called a passivation layer into the interior of the bare silicon wafer.

[0086] In the case of crystalline silicon heterojunction cells (HJT / HIT) and full back electrode back contact heterojunction cells (HBC), the doped region also refers to the doped region within the internal surface of at least one side of the silicon substrate. In this case, the doped region includes antimony elements and doping elements, such as third main group elements and fifth main group elements, such as B or P, or the doped region may be substantially the same as the body region, that is, a doped region mainly including antimony elements. Furthermore, at least one side of the silicon substrate has a doped amorphous silicon layer as a doped layer and an intrinsic amorphous silicon layer as a passivation layer. In this case, the doping elements may or may not enter the raw silicon wafer.

[0087] In the present application, essentially unchanged means that the concentration of antimony elements in the thickness direction of the silicon substrate of the present application is uniform. Although the specific values ​​may vary to a certain extent with the change of the detection site, the overall difference in antimony concentration in the thickness direction will not exceed 50%, 40%, 30%, or 20%, 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2% or 1%, that is, the difference between the maximum value and the minimum value will not exceed 50%, 40%, 30%, or 20% of the minimum value, or will not exceed 15% of the minimum value, or will not exceed 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2% or 1% of the minimum value.

[0088] In the present application, the side length and thickness of the silicon wafer can be detected by methods for measuring length and thickness known in the art, for example, by measuring with a micrometer.

[0089] In the present application, the arc length projection length of the chamfer connecting two adjacent sides of the silicon wafer can also be detected by a length measurement method commonly used by those skilled in the art, for example, it can be measured by a micrometer.

[0090] In the present application, the total oxygen content in the silicon wafer or silicon substrate can be detected by any method known to those skilled in the art, and these methods can be selected by those skilled in the art based on their needs, for example, detection can be performed by SIMS method. In one specific embodiment of the present application, the total oxygen content in the silicon wafer or silicon substrate is tested using secondary ion mass spectrometry SIMS method.

[0091] The inventors of this application discovered that since the atomic radius of Sb and C elements is significantly different from that of Si (the Sb / Si atomic radius ratio is approximately 1.3, and the C / Si atomic radius ratio is approximately 0.65), by effectively adjusting the doping ratio of Sb and C elements, local lattice distortion can be significantly suppressed, and the increase in silicon wafer stress caused by doping can be reduced. At the same time, C atom doping has no significant effect on the Sb ionization energy and defect states, and can generally reduce the defect state density inside the silicon rod and increase the minority carrier lifetime.

[0092] Moreover, a single C atom has a low diffusion coefficient and poor migration ability in silicon wafers. However, by doping Sb-C in the form of a dimer, the migration of Sb can be limited to a certain extent, further improving the segregation problem and solving the problem of uneven distribution of minority carrier lifetimes in different rods in the same furnace and in different sections of the same rod. As a result, the minority carrier lifetimes of multiple silicon wafers obtained using silicon rods are very uniform.

[0093] The present application provides a silicon wafer, wherein the silicon wafer includes antimony and carbon, and the ratio of the doping concentration of the antimony element to the doping concentration of the carbon element is 1:0.1 to 1:12.5.

[0094] The ratio of the doping concentration of antimony element to the doping concentration of carbon element can be, for example, 1:0.1, 1:0.2, 1:0.3, 1:0.4, 1:0.5, 1:0.6, 1:0.7, 1:0.8, 1:0.9, 1:1, 1:1.5, 1:2, 1:2.5, 1:3, 1:3.5, 1:4, 1:4.5, 1:5, 1:5.5, 1:6, 1:6.5, 1:7, 1:7.5, 1:8, 1:8.5, 1:9, 1:9.5, 1:10, 1:10.5, 1:11, 1:11.5, 1:12, 1:12.5, and any range between these values.

[0095] This application adopts the scheme of co-doping of antimony and carbon elements (Sb-C co-doping) and reasonably controls the doping ratio of antimony and carbon elements, which can limit the migration of antimony elements, increase the minority carrier lifetime, and make the distribution of minority carrier lifetime uniform.

[0096] In a specific embodiment, the doping concentration of carbon element is in the range of 4E+13cm -3 ~2.5E+17cm -3 For example, the carbon doping concentration range can be 4E+13cm -3 、5.0E+13cm -3 、6.0E+13cm -3 、7.0E+13cm -3 、8.0E+13cm -3 、9.0E+13cm -3 、1.0E+14cm -3 , 2.0E+14cm -3 、3.0E+14cm -3 、4.0E+14cm -3 、5.0E+14cm -3 、6.0E+14cm -3 、7.0E+14cm -3 、8.0E+14cm -3 、9.0E+14cm -3 、1.0E+15cm -3 , 2.0E+15cm -3 、3.0E+15cm -3 、4.0E+15cm -3 、5.0E+15cm -3 、6.0E+15cm -3 、7.0E+15cm -3 , 8.0E+15cm -3 、9.0E+15cm -3 、1.0E+16cm-3 , 2.0E+16cm -3 、3.0E+16cm -3 、4.0E+16cm -3 、5.0E+16cm -3 、6.0E+16cm -3 、7.0E+16cm -3 、8.0E+16cm -3 、9.0E+16cm -3 、1.0E+17cm -3 , 2.0E+17cm -3 、2.5E+17cm -3 , and any ranges between these values.

[0097] In a specific embodiment, the doping concentration of antimony element is in the range of 4E+14cm -3 ~2E+16cm -3 For example, the doping concentration of antimony element can be in the range of 4.0E+14cm -3 、4.5E+14cm -3 、5.0E+14cm -3 、5.5E+14cm -3 、6.0E+14cm -3 、6.5E+14cm -3 、7.0E+14cm -3 、7.5E+14cm -3 、8.0E+14cm -3 、8.5E+14cm -3 、9.0E+14cm -3 、9.5E+14cm -3 、1.0E+15cm -3 、1.5E+15cm -3 , 2.0E+15cm -3 、2.5E+15cm -3 、3.0E+15cm -3 、3.5E+15cm -3 、4.0E+15cm -3 、4.5E+15cm -3 、5.0E+15cm -3 、5.5E+15cm -3 、6.0E+15cm -3 、6.5E+15cm -3 、7.0E+15cm -3 、7.5E+15cm -3 、8.0E+15cm-3 、8.5E+15cm -3 、9.0E+15cm -3 、9.5E+15cm -3 、1.0E+16cm -3 、1.5E+16cm -3 , 2.0E+16cm -3 , and any ranges between these values.

[0098] In a specific embodiment, the doping concentration of antimony element is greater than or equal to 4E+14cm -3 When the doping concentration of antimony element is less than or equal to a, the ratio of the doping concentration of antimony element to the doping concentration of carbon element is 1:b to 1:12.5, wherein a is selected from 8E+15cm -3 ~1.2E+16cm -3 , b is greater than 0.1.

[0099] For example, a can be 8.0E+15cm -3 、8.5E+15cm -3 、9.0E+15cm -3 、9.5E+15cm -3 、1.0E+16cm -3 、1.05E+16cm -3 、1.1E+16cm -3 、1.15E+16cm -3 、1.2E+16cm -3 , and any ranges between these values.

[0100] For example, b is greater than 0.1 and less than or equal to 12.5, and b can be 0.11, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1.0, 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 8.5, 9.0, 9.5, 10, 10.5, 11.0, 11.5, 12.0, 12.5, and any range therebetween.

[0101] In a specific embodiment, a is selected from 9E+15cm -3 ~1.1E+16cm -3 .

[0102] In a specific embodiment, a is 1E+16 cm -3 .

[0103] In one embodiment, b is greater than 0.5.

[0104] In a specific embodiment, b is greater than 0.7.

[0105] In a specific embodiment, a is selected from 9E+15cm -3 ~1.1E+16cm -3 , b is greater than 0.5.

[0106] In a specific embodiment, a is selected from 9E+15cm -3 ~1.1E+16cm -3 , b is greater than 0.7.

[0107] In a specific embodiment, a is 1E+16 cm -3 , b is greater than 0.5.

[0108] In a specific embodiment, a is 1E+16 cm -3 , b is greater than 0.7.

[0109] In a specific embodiment, when a is 1E+16 cm -3 When the doping concentration of antimony is greater than or equal to 4E+14cm -3 and less than or equal to 1E+16cm -3 .4, 1:1.5, 1:1.6, 1:1.7, 1:1.8, 1:1.9, 1:2.0, 1:2.1, 1:2.2, 1:2.3, 1:2.4, 1:2.5 and any range therebetween.

[0110] In a specific embodiment, the doping concentration of antimony element is greater than a and less than or equal to 2E+16cm -3 When the doping concentration of antimony element and carbon element is 1:0.1 to 1:c, a is selected from 8E+15cm -3 ~1.2E+16cm -3 , c is less than 0.8.

[0111] For example, a can be 8.0E+15cm -3、8.1E+15cm -3 、8.2E+15cm -3 、8.3E+15cm -3 、8.4E+15cm -3 、8.5E+15cm -3 、8.6E+15cm -3 、8.7E+15cm -3 、8.8E+15cm -3 、8.9E+15cm -3 、9.0E+15cm -3 、9.1E+15cm -3 、9.2E+15cm -3 、9.3E+15cm -3 、9.4E+15cm -3 、9.5E+15cm -3 、9.6E+15cm -3 、9.7E+15cm -3 、9.8E+15cm -3 、9.9E+15cm -3 、1.0E+16cm -3 、1.1E+16cm -3 、1.2E+16cm -3 and any ranges between these values.

[0112] For example, c is greater than or equal to 0.1 and less than 0.8, and c can be 0.1, 0.11, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, and any range therebetween.

[0113] In a specific embodiment, a is selected from 9E+15cm -3 ~1.1E+16cm -3 .

[0114] In a specific embodiment, a is 1E+16 cm -3 .

[0115] In a specific embodiment, c is less than 0.5.

[0116] In a specific embodiment, c is less than 0.3.

[0117] In a specific embodiment, a is selected from 9E+15cm -3 ~1.1E+16cm -3 , c is less than 0.5.

[0118] In a specific embodiment, a is selected from 9E+15cm -3 ~1.1E+16cm -3 , c is less than 0.3.

[0119] In a specific embodiment, a is 1E+16 cm -3 , c is less than 0.5.

[0120] In a specific embodiment, a is 1E+16 cm -3 , c is less than 0.3.

[0121] In a specific embodiment, when a is 1.0E+16 cm -3 When the doping concentration of antimony is greater than 1.0E+16cm -3 and less than or equal to 2E+16cm -3 , 1:0.75, 1:0.8, and any range between these values.

[0122] In a specific embodiment, the resistivity of the silicon wafer is 0.3 to 10 Ω·cm. For example, the resistivity of the silicon wafer can be 0.3 Ω·cm, 0.4 Ω·cm, 0.5 Ω·cm, 0.6 Ω·cm, 0.7 Ω·cm, 0.8 Ω·cm, 0.9 Ω·cm, 1 Ω·cm, 1.1 Ω·cm, 1.2 Ω·cm, 1.3 Ω·cm, 1.4 Ω·cm, 1.5 Ω·cm, 1.6 Ω·cm, 1.8 Ω·cm, 1.9 Ω·cm, 2.1 Ω·cm, 2.2 Ω·cm, 2.3 Ω·cm, 2.4 Ω·cm, 2.5 Ω·cm, 2.6 Ω·cm, 2.7 Ω·cm, 2.8 Ω·cm, 2.9 Ω·cm, 3.1 Ω·cm, 3. 7Ω·cm, 1.8Ω·cm, 1.9Ω·cm, 2Ω·cm, 2Ω·cm, 2.5Ω·cm, 3Ω·cm, 3.5Ω·cm, 4Ω·cm, 4.5Ω·cm, 5Ω·cm, 5.5Ω·cm, 6Ω·cm, 6.5Ω·cm, 7Ω·cm, 7.5Ω·cm, 8Ω·cm, 8.5Ω·cm, 9Ω·cm, 9.5Ω·cm, 10Ω·cm, and any ranges between these values.

[0123] In a specific embodiment, the resistivity of the silicon wafer is 0.4 to 8 Ω·cm.

[0124] In a specific embodiment, the resistivity of the silicon wafer is 0.5 to 6 Ω·cm.

[0125] In a specific embodiment, the minority carrier lifetime of the silicon wafer is greater than or equal to 200 microseconds, preferably greater than or equal to 300 microseconds, more preferably greater than or equal to 500 microseconds, and even more preferably greater than or equal to 1300 microseconds.

[0126] The minority carrier lifetime of the silicon wafer is greater than or equal to 200 microseconds, that is, at 1E+15cm -3 ~3E+15cm -3 Under the carrier injection level (including converting other carrier injection levels to 1E+15cm -3 ~3E+15cm -3The minority carrier lifetime calculated at the injection level is greater than or equal to 200 microseconds, for example, it can be 200 microseconds, 500 microseconds, 800 microseconds, 1000 microseconds, 1100 microseconds, 1200 microseconds, 1300 microseconds, 1400 microseconds, 1500 microseconds, 1600 microseconds, 1700 microseconds, 1800 microseconds, 1900 microseconds, 2000 microseconds, 2100 microseconds, 2200 microseconds, 2300 microseconds, 2400 microseconds, 2500 microseconds, 2600 microseconds, 2700 microseconds, 2800 microseconds, 2900 microseconds, 3000 microseconds, 31000 microseconds, 0 microseconds, 3200 microseconds, 3300 microseconds, 3400 microseconds, 3500 microseconds, 3600 microseconds, 3700 microseconds, 3800 microseconds, 3900 microseconds, 4000 microseconds, 4100 microseconds, 4200 microseconds, 4300 microseconds, 4400 microseconds, 4500 microseconds, 4600 microseconds, 4700 microseconds, 4800 microseconds, 4900 microseconds, 5000 microseconds, 5100 microseconds, 5200 microseconds, 5300 microseconds, 5400 microseconds, 5500 microseconds, 5600 microseconds, 5700 microseconds, 5800 microseconds, 5900 microseconds, 6000 microseconds, 6100 microseconds, 6200 microseconds, 6300 microseconds, 6400 microseconds, 6500 microseconds, 6600 microseconds, 6700 microseconds, 6800 microseconds, 6900 microseconds, 7000 microseconds, 7100 microseconds, 7200 microseconds, 7300 microseconds, 7400 microseconds, 7500 microseconds, 7600 microseconds, 7700 microseconds, 7800 microseconds, 7900 microseconds, 8000 microseconds, 8100 microseconds, 8200 microseconds, 8300 microseconds, 8400 microseconds, 8500 microseconds, 8600 microseconds, 8700 microseconds, 88 00 microseconds, 8900 microseconds, 9000 microseconds, 9100 microseconds, 9200 microseconds, 9300 microseconds, 9400 microseconds, 9500 microseconds, 9600 microseconds, 10000 microseconds, 15000 microseconds, 20000 microseconds, 30000 microseconds, 40000 microseconds, 50000 microseconds, 60000 microseconds, 70000 microseconds, 80000 microseconds, 90000 microseconds, 10000 microseconds, 110000 microseconds, 120000 microseconds, 125000 microseconds, 129000 microseconds, and any range between these values.

[0127] In a specific embodiment, the total oxygen content in the silicon wafer is below 25 ppma. The total oxygen content in the silicon wafer can be, for example, 25 ppma, 24 ppma, 23 ppma, 22 ppma, 21 ppma, 20 ppma, 19 ppma, 18 ppma, 17 ppma, 16 ppma, 15 ppma, 14 ppma, 13 ppma, 12 ppma, 11 ppma, 10 ppma, 9 ppma, 8 ppma, 7 ppma, 6 ppma, 5 ppma, 4 ppma, 3 ppma, 2 ppma, and any range therebetween.

[0128] In a specific embodiment, the total oxygen content in the silicon wafer is below 18 ppma.

[0129] In a specific embodiment, the total oxygen content in the silicon wafer is below 14 ppma.

[0130] In one embodiment, the total oxygen content in the silicon wafer is greater than 2 ppma. In one embodiment, the total oxygen content in the silicon wafer is greater than 3 ppma. In one embodiment, the total oxygen content in the silicon wafer is greater than 4 ppma.

[0131] In a specific embodiment, the total oxygen content in the silicon wafer is 2-25 ppma. In a specific embodiment, the total oxygen content in the silicon wafer is 3-25 ppma. In a specific embodiment, the total oxygen content in the silicon wafer is 4-25 ppma. In a specific embodiment, the total oxygen content in the silicon wafer is 2-23 ppma. In a specific embodiment, the total oxygen content in the silicon wafer is 3-23 ppma. In a specific embodiment, the total oxygen content in the silicon wafer is 4-23 ppma. In a specific embodiment, the total oxygen content in the silicon wafer is 2-22 ppma. In a specific embodiment, the total oxygen content in the silicon wafer is 3-22 ppma. In a specific embodiment, the total oxygen content in the silicon wafer is 4-22 ppma.

[0132] In a specific embodiment, when the ratio of the doping concentration of antimony element to the doping concentration of carbon element is 1:0.1 to 1:12.5, and the doping concentration range of carbon element is 4E+13cm -3 ~5E+16cm -3 , the doping concentration range of antimony element is 4E+14cm -3 ~2E+16cm -3 When the total oxygen content in the silicon wafer is 2-25 ppma.

[0133] In a specific embodiment, the silicon wafer further includes at least one of phosphorus, gallium, and germanium.

[0134] In a specific embodiment of the present application, the silicon wafer of the present application is doped with only antimony as a Group V doping element to replace phosphorus. In this case, those skilled in the art will understand that, depending on the source of the silicon wafer raw materials or by additional addition to the crystal pulling raw materials, the prepared silicon wafer may also contain other elements, such as any one, two, or three of phosphorus, gallium, and germanium, but only antimony is actively doped as a Group V doping element to replace phosphorus.

[0135] In one specific embodiment, phosphorus is included in the molten silicon used to manufacture silicon wafers, resulting in silicon wafers containing both phosphorus and antimony. Due to the different evaporation rates of antimony and phosphorus during the doping process, both dopants contribute to the resistivity of the silicon ingot in the early stages of crystal pulling. Over time, the contribution of antimony decreases. Once all antimony evaporates, i.e., in the later stages of crystal pulling, only the phosphorus dopant remains active, resulting in closer resistivity at the head and tail of the ingot. This improves axial resistivity uniformity, and consequently, resistivity uniformity across the silicon wafer.

[0136] In one specific embodiment, gallium is included in the molten silicon used to manufacture silicon wafers, and silicon wafers containing both gallium and antimony are obtained. Specifically, in the method for preparing single crystal silicon, on the one hand, an appropriate amount of gallium is added to the polycrystalline silicon material to introduce majority holes, thereby obtaining single crystal silicon with a preset resistivity; on the other hand, an appropriate amount of antimony is added to the polycrystalline silicon material to introduce free electrons, thereby compensating for the holes in the silicon crystal, especially at the tail of the single crystal silicon rod, and reducing the concentration of the tail of the single crystal silicon rod, so that the longitudinal resistivity distribution of the prepared single crystal silicon rod is more uniform, thereby extending the length of the single crystal silicon rod in production, and further improving the resistivity uniformity of the silicon wafers prepared by cutting the silicon rod.

[0137] In a specific embodiment, germanium is included in the molten silicon used to manufacture silicon wafers, and silicon wafers containing both germanium and antimony are obtained. Antimony is doped in the process of preparing single crystal silicon, which has a high volatilization rate and a large atomic radius, resulting in lattice changes. A trace amount of germanium is doped. The number of outermost electrons of the germanium element is the same as that of the silicon element, which is 4, and therefore will not affect the electrical properties of the silicon material. Instead, the effect of germanium and point defects (self-interstitial silicon atoms, vacancies) can be used to suppress native micro-defects in the silicon single crystal, especially void defects, which can effectively improve the quality and yield of the silicon single crystal, suppress native defects, and improve the crystal quality.

[0138] Usually the concentration of phosphorus in silicon wafers does not exceed 3E+16atom / cm 3 ; The concentration of gallium will not exceed 7E+16atom / cm 3 , the concentration of germanium will not exceed 1E+19atom / cm3 When doping simultaneously, the above concentration limits refer to the concentration limits of each element.

[0139] In a specific embodiment, the mechanical strength of the silicon wafer is greater than or equal to 70 MPa, and / or the mechanical strength dispersion of the silicon wafer is less than or equal to 0.9.

[0140] It should be noted that, when the side length of the silicon wafer is fixed, the mechanical strength of the silicon wafer increases with the increase of the silicon wafer thickness.

[0141] The mechanical strength of the silicon wafer can be, for example, 70 MPa, 80 MPa, 90 MPa, 100 MPa, 110 MPa, 120 MPa, 140 MPa, 160 MPa, 180 MPa, 200 MPa, 210 MPa, 230 MPa, 250 MPa, 280 MPa, 300 MPa, 310 MPa, 320 MPa, 330 MPa, 340 MPa, 350 MPa, 360 MPa, 370 MPa, 380 MPa, 400 MPa, 500 MPa, and any range between these values.

[0142] When conducting strength tests, a horizontal testing platform is set up and two support beams are installed on the horizontal testing platform. The silicon wafer is placed on the two support beams. The span between the two support beams is 60mm. The thickness of the silicon wafer is 40μm to 170μm. Then, a thrust is applied to the silicon wafer from top to bottom. The specific data of the applied pressure and the thrust distance are recorded by the sensor to measure the mechanical strength of the silicon wafer.

[0143] As competition in the photovoltaic industry intensifies, low cost becomes a key concern. Thinning can effectively reduce silicon wafer costs, minimize solar cell light decay, and produce cells with improved flexibility. However, this leads to poor light absorption and increased warping, significantly reducing mechanical strength. However, the silicon wafers of this application, by controlling the concentration of antimony, effectively hinder lattice slip, pinning dislocations and thus improving their mechanical strength.

[0144] In a specific embodiment, the mechanical strength dispersion of the silicon wafer is less than 0.9, for example, it can be 0.89, 0.85, 0.8, 0.75, 0.7, 0.65, 0.6, 0.55, 0.5, 0.45, 0.4, 0.35, 0.3, 0.25, 0.2, 0.15, 0.1, and any range between these values.

[0145] In the present application, there is no further limitation on the silicon wafer itself involved in the above-mentioned present application. It can be a silicon wafer obtained after machining and slicing after the silicon rod is drawn (it can also be called a bare silicon wafer). The silicon substrate in the present application can be a partial silicon substrate that is peeled off and recovered from the battery component, as long as it can have a certain shape and can be in the form of a sheet (that is, the size of one surface is larger than the size of the surface perpendicular to it), flat or plate-shaped. There is no limitation on the size of the silicon wafer or silicon substrate of the present application. The silicon wafer or silicon substrate can be a partial silicon substrate of any size after the light absorber is recovered from the battery component and other layer structures are peeled off. In addition, those skilled in the art will understand that during peeling, if the doped region is partially destroyed, as long as part of the doped region still exists, it should also be understood as the silicon substrate described in the present application, and the battery with such a silicon substrate is also a battery that meets the definition of the present application. For example, in a specific embodiment, the side length of at least one side of the silicon wafer or silicon substrate of the present application (including the partial silicon substrate after recovery and stripping of other layer structures) is greater than 156 mm, for example, it can be 158±2 mm, 160±2 mm, 165±2 mm, 170±2 mm, 175±2 mm, 180±2 mm, 185±2 mm, 190±2 mm, 195±2 mm, 200±2 mm, 205±2 mm, 210±2 mm, 215±2 mm, 220±2 mm, 225±2 mm, 230±2 mm, 235±2 mm, 240±2 mm, 245±2 mm, 250±2 mm, 255±2 mm, 260±2 mm, 265±2 mm, 270±2 mm, 275±2 mm, and any range between these values. For example, in a specific embodiment, the thickness of the silicon wafer or silicon substrate of the present application (including the portion of the silicon substrate after recovery and stripping of other layer structures) is at least 40 to 170 μm, for example, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, or 160 μm. In a specific embodiment, the size of the portion of the silicon substrate after recovery and stripping of other layer structures can be smaller than the above size, as long as the antimony concentration, resistivity, resistivity change rate, resistivity average offset rate, etc. detected therefor meet the requirements of the present application.

[0146] In a specific embodiment, the silicon wafer is rectangular, one side of the rectangle is 156 mm to 300 mm long, and the other side of the rectangle is 83 mm to 300 mm long.

[0147] In a specific embodiment, the silicon wafer is rectangular, and the length of one side of the rectangle can be, for example, 156mm, 160mm, 170mm, 180mm, 190mm, 200mm, 210mm, 220mm, 230mm, 240mm, 250mm, 260mm, 270mm, 280mm, 290mm, 300mm, and any range between these values, and the length of the other side of the rectangle can be, for example, 83mm, 85mm, 90mm, 95mm, 100mm, 110mm, 120mm, 130mm, 140mm, 150mm, 160mm, 170mm, 180mm, 190mm, 200mm, 210mm, 220mm, 230mm, 240mm, 250mm, 260mm, 270mm, 280mm, 290mm, 300mm, and any range between these values.

[0148] The specific size of the silicon wafer can be adjusted according to specific application requirements, for example, it can be the size that has been detailed in the silicon wafer involved in this application.

[0149] In a specific embodiment, the silicon wafer further includes a chamfer connecting two adjacent sides of the silicon wafer, and the arc length projection length of the chamfer is 1 mm to 10 mm. For example, the arc length projection length of the chamfer can be 1 mm, 2 mm, 3 mm, 4 mm, 5 mm, 6 mm, 7 mm, 8 mm, 9 mm, 10 mm, and any range between these values.

[0150] The present application relates to a battery prepared using the silicon wafer of the present application.

[0151] The present application relates to a solar cell, which includes the use of the silicon wafer described in detail in the present application in a solar cell. The detailed description of the silicon wafer is generally applicable. Specifically, the solar cell of the present application includes a silicon substrate, the silicon substrate including a silicon base and a doped region within at least one surface of the silicon substrate, the silicon substrate containing antimony and carbon, the doped region being doped with a doping element selected from a Group III element or a Group V element, and the ratio of the doping concentration of the antimony element to the doping concentration of the carbon element being 1:0.1 to 1:12.5.

[0152] In a specific embodiment, the mechanical strength of the solar cell is greater than or equal to 50 MPa. For example, the mechanical strength of the solar cell can be 50 MPa, 55 MPa, 60 MPa, 65 MPa, 70 MPa, 75 MPa, 80 MPa, 85 MPa, 90 MPa, 95 MPa, 100 MPa, 105 MPa, 110 MPa, 115 MPa, 120 MPa, 125 MPa, 130 MPa, 135 MPa, 140 MPa, 145 MPa, 150 MPa, 155 MPa, 160 MPa, 165 MPa, 170 MPa, 175 MPa, 180 MPa, 185 MPa, 190 MPa, 195 MPa, 200 MPa and above, and any ranges between these values.

[0153] The above descriptions of silicon wafers in this application are all applicable to the silicon substrate in this application.

[0154] In this application, because the silicon wafers described above rationally control the concentration of antimony elements, achieving uniform doping and thus uniform resistivity of the silicon wafers or bare silicon wafers themselves, batteries fabricated using such silicon wafers can reduce the lateral transport resistance of carriers, thereby ultimately achieving increased battery efficiency. Furthermore, due to the longer minority carrier lifetime of the silicon wafers described in this application, the short-circuit current of the solar cells fabricated therefrom is increased, further improving battery efficiency.

[0155] In a specific embodiment, the silicon wafer of the present application can be used to make silicon substrates for various types of solar cells, including aluminum back surface field cells (Al-BSF), passivated emitter and back contact cells (PERC), metal wrap-around cells (MWT), passivated emitter back localized diffused cells (PERL), passivated emitter back fully diffused cells (PERT), emitter wrap-around cells (EWT), tunneling oxide passivated cells (TOPCon), interdigitated back contact cells (IBC), crystalline silicon heterojunction cells (HJT / HIT), and full back electrode back contact heterojunction cells (HBC).

[0156] In a specific embodiment, the carbon doping concentration of the silicon substrate of the present application is in the range of 4E+13cm -3 ~2.5E+17cm -3 The doping concentration of antimony in the silicon substrate of this application is 4E+14cm -3 to 2E+16cm -3 , preferably 4.3E+14cm -3 to 1.9E+16cm -3 , more preferably 4.45E+14cm -3 to 1.87E+16cm-3 .

[0157] Those skilled in the art will understand that the silicon substrate is the structure formed after the silicon wafer of the present application is prepared into a cell. Those skilled in the art will understand that the solar cell covers all solar cells that can be applied to the silicon wafer of the present application, for example, crystalline silicon heterojunction cells (HJT / HIT), full back electrode back contact heterojunction cells (HBC), TOPCon cells, partial TOPCon cells, back contact hybrid cells and TBC cells, as well as any cell form well known to those skilled in the art.

[0158] In the above-mentioned battery configuration, at least one doped layer is provided on the surface of at least one side of the silicon substrate. Specifically, depending on the battery configuration, the doped layer can be selected based on requirements. For example, it can be an n-type amorphous or polycrystalline silicon carbide layer, such as phosphorus-doped silicon carbide, nitrogen-doped silicon carbide, phosphorus-doped amorphous silicon, or nitrogen-doped amorphous silicon; or it can be n-type amorphous or polycrystalline diamond-like carbon, such as nitrogen-doped diamond-like carbon. Those skilled in the art are fully free to make their selections based on their requirements, and as long as the requirements of this application are met, at least a portion of the surface of at least one side of the silicon substrate can have one doped layer, while other regions can have another doped layer.

[0159] In the above-described battery configuration, at least one passivation layer is provided between the doped layer and the doped region of the silicon substrate. Specifically, the passivation layer can be selected based on specific requirements, depending on the battery configuration. Generally, the thickness of the passivation layer should be less than 10 nm. Due to its very small thickness, there are no requirements for the conductivity of the passivation layer. Due to its small thickness, there are no absorption limitations. Commonly used passivation layers include silicon oxide, silicon nitride, intrinsic amorphous silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride, and the like. Those skilled in the art are fully free to select a passivation layer based on their requirements, as long as it meets the requirements of this application.

[0160] In a specific embodiment, the solar cell is a heterojunction cell, such as a crystalline silicon heterojunction cell (HJT / HIT) or a full back electrode back contact heterojunction cell (HBC). When the silicon wafer of the present application forms a silicon substrate for a heterojunction cell or a full back electrode back contact heterojunction cell, even after a heterojunction layer is stacked on the silicon substrate, the antimony concentration and resistivity change rate described in detail for the silicon wafer are still satisfied, that is, after the heterojunction layer is stacked, the antimony concentration in the silicon substrate is still 4E+14cm -3 to 2E+16cm -3 , and the resistivity change rate of the light absorber is still ≤0.6. All the above descriptions on the antimony concentration and resistivity change rate in the silicon wafer are applicable to this method.

[0161] For crystalline silicon heterojunction cells (HJT / HIT) and full back electrode back contact heterojunction cells (HBC), an intrinsic amorphous silicon layer and a doped amorphous silicon layer are usually further stacked on the silicon substrate of the present application, wherein the intrinsic amorphous silicon layer serves as a passivation layer. Due to the characteristics of the Sb element itself, the antimony element in the silicon substrate will not pass through the passivation layer into the doped amorphous silicon layer, and the doped amorphous silicon layer basically does not contain Sb, that is, the silicon substrate contains antimony element, while the doped amorphous silicon layer or the intrinsic amorphous silicon layer contains doping elements but does not contain Sb.

[0162] Specifically, for crystalline silicon heterojunction cells (HJT / HIT) and full back electrode back contact heterojunction cells (HBC), the concentration of antimony in the silicon substrate is 4.3E+14 cm -3 to 1.9E+16cm -3 More specifically, the concentration of antimony in the silicon substrate is 4.45E+14cm -3 to 1.87E+16cm -3 .

[0163] In a specific embodiment, for TOPCon cells, local TOPCon cells, back contact hybrid cells and TBC cells, the doped regions contain doping elements as described above, and the concentration of antimony elements in the doped regions in the thickness direction of the silicon substrate is substantially unchanged. In this way, the crystalline silicon lattice distortion caused by single element doping can be overcome, resulting in many defects in the heavily doped regions, and light absorption can also be improved, thereby increasing cell efficiency. Those skilled in the art will appreciate that, in the case of TOPCon cells, local TOPCon cells, back contact hybrid cells and TBC cells, in this application, the doped region refers to a region formed by direct doping inside the raw silicon wafer or indirectly doped through other layer structures. Therefore, in this case, the doped region is formed in the silicon substrate by the doping elements entering the silicon wafer. An interface passivation layer and a doped passivation layer can be further laminated on at least one side surface of the silicon substrate. In addition, those skilled in the art will also appreciate that as long as the solar cell structure has a structure as described in detail in this application, the difference in its name also falls within the scope of protection of this application.

[0164] In this application, an interfacial passivation layer refers to a layer that has a passivating effect and allows the passage of dopant elements, such as a tunneling layer. A doped passivation layer is a layer that forms a PN junction or a high-low junction with the silicon substrate. Examples include a doped amorphous silicon layer and a doped polysilicon layer.

[0165] Those skilled in the art will understand that, depending on the different application requirements of the silicon wafer, for example, when the silicon wafer is used in various solar cells, the silicon wafer can be further doped with various doping elements to form one or more doping regions. These doping elements can be Group III elements such as boron, aluminum, gallium, indium, and thallium, or Group V elements such as nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0166] In the present application, the antimony concentration and the like described for the above-mentioned silicon wafer are also applicable to the silicon substrate that has been installed in the solar cell as part of the light absorber. At this time, the above-mentioned parameters described for the antimony concentration and the like in the silicon wafer are applicable to the entire silicon substrate, that is, they are applicable to the body region that contains only antimony doping, to the doped region, and to the body region and the doped region as a whole. Those skilled in the art will understand that when the above-mentioned detection is performed only on the body region, the results measured or calculated for its antimony concentration, resistivity, resistivity change rate, and resistivity average offset rate are within the scope of the above-mentioned detailed description of the present application. When the above-mentioned detection is performed only on the doped region, the results measured or calculated for its antimony concentration are within the scope of the above-mentioned detailed description of the present application. When the boundary between the doped region and the body region is ignored and any position of the entire silicon substrate is detected, the above-mentioned results can also be obtained.

[0167] In a specific embodiment, the doping element can be doped into the doping region by direct doping, that is, the doping element is doped directly into the doping region without passing through other layer structures of the battery. The direct doping method can also be various methods known in the art, such as thermal diffusion, ion implantation, or coating a slurry containing a dopant and incorporating the dopant by a driving force (such as heat treatment, laser, etc.). Those skilled in the art can choose according to their needs. It also includes the case where aluminum is diffused into the silicon wafer through aluminum grid lines through heat treatment.

[0168] In a specific manner, in addition to the above-mentioned direct doping, the doping element can be doped into the doping region in such a way that the doping element passes through the layer structure stacked on the silicon wafer or silicon substrate and is doped into the silicon wafer or silicon substrate to form the above-mentioned doping region. Those skilled in the art will understand that, according to different application scenarios of the silicon wafer, such as when used in different solar cells, the layer structure can be adjusted accordingly. For example, the layer structure may itself contain a dopant that provides the doping element, and the doping element is doped through the layer structure. The layer structure itself may also not contain a dopant, but the adjacent area has an atmosphere that can provide the doping element, and is doped into the silicon wafer through the layer structure to form a doping region by, for example, thermal diffusion, ion implantation, etc. The above-mentioned atmosphere that can provide the doping element can be a gas atmosphere (such as a gas containing a dopant), a liquid (such as a slurry containing a dopant), or a solid (such as a layer including a dopant, such as a doped passivation layer, especially a doped polysilicon layer).

[0169] The layer structure can be a single layer (e.g., a passivation layer or tunneling layer) or multiple layers, such as a passivation layer and a doped layer. The layer structure can be a natural oxide layer formed by natural oxidation on a silicon substrate. Alternatively, the layer structure can be made of intrinsic amorphous silicon, i.e., intrinsic amorphous silicon is provided on one side of the silicon wafer to provide passivation.

[0170] Taking the TOPCon battery structure as an example, the layer structure may be a doped polysilicon layer (doped passivation layer), a tunneling layer (interface passivation layer), or a doped polysilicon layer and a tunneling layer acting together as a layer structure. Those skilled in the art will fully understand that the above enumeration is only for illustration, and both direct doping and doping via a layer structure are optional, and direct doping and doping via a layer structure can be targeted at a local part of one side of the silicon wafer, for example, direct doping is used to dope the doping elements locally, and at the same time, a TOPCon structure is stacked on other areas of the side surface to form a local TOPCon structure or a back-contact hybrid battery with a TOPCon structure. Or even one TOPCon structure can be used locally, and another TOPCon structure can be used in other locations to achieve doping separately, such as forming a TBC battery.

[0171] Those skilled in the art will understand that in the case of a TOPCon structure, a tunneling layer and a doped polysilicon layer are further stacked on the silicon substrate, and the concentration of antimony in the silicon substrate is 4E+14cm -3 to 2E+16cm -3 , preferably 4.3E+14cm -3 to 1.9E+16cm -3 , more preferably 4.45E+14cm -3 to 1.87E+16cm -3 The total oxygen content in the silicon substrate is below 35 ppma, preferably below 25 ppma, and further preferably below 18 ppma.

[0172] In a specific embodiment, in the case of direct doping, within a range of h thickness from the surface of the doping region away from the side of the silicon substrate (i.e., the doping region depth of the direct doping region), the concentration of the doping element is greater than the concentration of the antimony element on the above surface and at the same depth from the above surface.

[0173] And in the doping region, the sum of the concentration of antimony element and the concentration of doping element is less than or equal to 1E+21cm -3 The battery of the present application controls the range of the sum of the antimony concentration and the doping element concentration in the doping region, thereby facilitating carrier separation, reducing carrier recombination, and improving short-circuit current and open-circuit voltage.

[0174] In a specific manner, the above-mentioned doping element is a third main group element, and the above-mentioned h ranges from 30 to 650 nm. In a specific manner, the above-mentioned doping element is a third main group element, and the above-mentioned h is greater than or equal to 400 nm. In a specific manner, the above-mentioned doping element is a third main group element, and the above-mentioned h ranges from 30 nm to 100 nm. In a specific embodiment, the above-mentioned doping element is a fifth main group element, and the above-mentioned h ranges from 100 to 200 nm. As described above, the maximum range at the same depth from the above-mentioned surface should be the thickness h. For example, when the depth is 0, it is the concentration on the surface of the above-mentioned doping region. When the depth is 100 nm, for example, it can be that at a position 100 nm from the above-mentioned surface, the concentration of the doping element is greater than the concentration of the antimony element. In a specific manner, as described in Figure 1, the surface away from the side of the silicon substrate from the doping region is the front side of the doping region 2.

[0175] In a specific embodiment, the doping element is boron, and h is in the range of 30 to 650 nm or in the range of 30 nm to 100 nm. When only local doping is performed, only the location of the local doping needs to satisfy the above relationship.

[0176] In the present application, since the thickness of the doped region formed by direct doping in the silicon substrate of the solar cell is controlled, it is beneficial to the separation of carriers, while reducing carrier recombination and improving the short-circuit current and open-circuit voltage.

[0177] In some specific embodiments, if the thickness of the doped region formed by direct doping, for example, the thickness of the doped region in the case of doping the third main group element is further controlled to be even less than 100nm or even less than 50nm, the free carrier Auger recombination can be further reduced, and the short-circuit current can be further improved. In a specific embodiment, in the case of diffusion through a layer structure, within a range of m thickness from the surface of the doped region away from the silicon substrate side (i.e., the depth of the doped region in the case of diffusion through a layer structure), the concentration of the doping element on the above surface and at the same depth from the above surface is greater than the concentration of the antimony element. In a specific embodiment, as described in Figure 1, the surface away from the silicon substrate side of the doped region is the back side of the doped region 4.

[0178] In a specific manner, the doping element is a third main group element, and the range of m is 80 to 180 nm. In a specific embodiment, the doping element is a fifth main group element, and the range of m is 30 to 100 nm. As described above, the maximum range at the same depth from the surface should be less than or equal to m. For example, when the depth is 0, it is the concentration on the surface of the doped region. When the depth is 100 nm, for example, at a position 100 nm from the surface, the concentration of the doping element is greater than the concentration of the antimony element.

[0179] In a specific embodiment, the doping element is phosphorus, and m is in the range of 80 to 180 nm or in the range of 30 to 100 nm. When only local doping is performed, only the location of the local doping needs to satisfy the above relationship.

[0180] In the present application, the above-mentioned light absorber controls the thickness of the doped region formed by doping the layer structure, thereby retaining the passivation effect of the interface passivation layer and achieving effective doping of doped polysilicon, thereby increasing the short-circuit current and open-circuit voltage and improving the efficiency of the battery.

[0181] In a specific embodiment, the solar cell of the present application is, for example, a tunneling oxide passivation cell (TOPCon cell), a local TOPCon cell, a back contact hybrid cell or a TBC cell.

[0182] In a specific embodiment, the typical structure of a TOPCon cell is shown in FIG1 , which includes, from the front to the back, a silicon substrate 1 (with a second doped region 2 and a first doped region 4 formed inside its two side surfaces), a tunneling layer 5, a doped polysilicon layer 6, a passivation layer or a high-transmission thin film layer 7, and an electrode 8. It is fully understood by those skilled in the art that although the structure of the TOPCon cell is described with the aid of FIG1 , the structure of the TOPCon cell is not limited to that of FIG1 , as long as a tunneling layer and a doped polysilicon layer are present on the silicon substrate of the cell. The TOPCon structure can be formed on the entire silicon substrate or on at least a portion of the silicon substrate.

[0183] In a specific embodiment, the second doping region 2 is directly doped with boron, and the first doping region 4 is doped with phosphorus in the silicon substrate through the tunneling layer 5 and the doped polysilicon layer 6 .

[0184] A partial TOPCon cell refers to a cell in which a TOPCon structure (i.e., a first doped region, a tunneling layer, and a doped polysilicon layer) is formed in at least a portion of one side of the cell. The first doped region, the tunneling layer, and the doped polysilicon layer are located in the first partial region, while the rest of the cell is an additional doped region. The additional doped region and the first doped region are on the same surface, and the elements doped in the additional doped region and the first doped region have the same conductivity type. However, an element with an opposite conductivity type is doped on the other side to form a second doped region.

[0185] TBC battery refers to a battery with a TOPCon structure formed on the back side. There are two areas on the back side of this type of battery, each of which has a TOPCon structure with doping elements of opposite conductivity types.

[0186] A back-contact hybrid cell refers to a cell with a PERC or PERL structure in one region and a TOPCon structure in the other. For example, one region on the back has a TOPCon structure, and the other region has a PERL or PERC structure, and the two regions are doped with elements of opposite conductivity types. In some specific embodiments, when aluminum gate line doping is used, a metal layer is formed on the silicon substrate, and an alloy layer and a BSF layer are formed within the silicon substrate, where the BSF layer is the doped region. In this case, the surface of the BSF layer away from the silicon substrate on the side away from the doped region refers to the surface of the BSF layer away from the silicon substrate.

[0187] In the above four types of batteries, the above doping elements are doped into the silicon substrate through the layer structure on the silicon substrate to form the above doping region, the above doping region includes a first doping region and a second doping region, the layer structure on the above silicon substrate includes a tunneling layer and a doped polysilicon layer stacked in sequence on the surface of the side of the above first doping region away from the silicon substrate, wherein the first doping element is doped in the doped polysilicon layer, and the second doping region on the above silicon substrate is also doped with the second doping element, and the first doping region and the second doping region have opposite conductivity types.

[0188] In this application, the "first doping element" and the "second doping element" are different doping elements. For example, when the first doping element is a Group V element, the second doping element is a Group III element; when the first doping element is a Group III element, the second doping element is a Group V element.

[0189] In a specific embodiment, the first doping element is phosphorus, and the second doping element is boron.

[0190] When the solar cell of the present application is a TOPCon cell, a partial TOPCon cell, or a back-contact hybrid cell, the second doped region is obtained by directly doping a second doping element into the second doped region, wherein the first doping element is a Group V element (e.g., phosphorus) and the second doping element is a Group III element (e.g., boron).

[0191] In one specific embodiment, in the doped polysilicon layer, the concentration of the first doping element at a depth x (i.e., a first predetermined depth) from the surface of the doped polysilicon layer on the side away from the silicon substrate is greater than the concentration of the second doping element at a depth x (i.e., a first predetermined depth) from the surface of the second doping region. The thickness of the doped polysilicon layer ranges from 100 to 400 nm, where x is less than or equal to the thickness of the doped polysilicon layer. In this embodiment, since the concentration of the first doping element is greater than the concentration of the second doping element, free carrier Auger recombination can be further reduced, further improving short-circuit current. In one specific embodiment, in the tunneling layer, in the direction from the doped polysilicon layer to the tunneling layer, the concentration of the first doping element at a depth y (i.e., a second predetermined depth) from the surface of the doped polysilicon layer on the side away from the silicon substrate is greater than the concentration of the second doping element at a depth y (i.e., a second predetermined depth) from the surface of the second doping region. The thickness of the tunneling layer ranges from 0.5 to 5 nm, where y is less than or equal to the sum of the thicknesses of the doped polysilicon layer and the tunneling layer. In this method, since the concentration of the first doping element is greater than the concentration of the second doping element, the free carrier Auger recombination can be further reduced, and the short-circuit current can be further improved. On the other hand, the free carrier Auger recombination can be reduced without reducing the passivation effect of the tunneling layer, further improving the short-circuit current, open-circuit voltage, and improving the battery efficiency. In a specific method, in the direction from the doped polysilicon layer to the surface of the above-mentioned first doping region, in the silicon substrate, the concentration of the first doping element at the z depth (i.e., the third preset depth) from the surface of the doped polysilicon layer away from the silicon substrate is greater than the concentration of the second doping element at the z depth (i.e., the third preset depth) from the surface of the second doping region, the thickness of the first doping region ranges from 30 to 100 nm, and z is less than or equal to the sum of the thicknesses of the doped polysilicon layer, the tunneling layer, and the first doping region. In this method, since the concentration of the first doping element is greater than the concentration of the second doping element, the free carrier Auger recombination can be further reduced, and the short-circuit current can be further improved. On the other hand, it can reduce the free carrier Auger recombination without reducing the passivation effect of the tunneling layer, further improve the short-circuit current, open-circuit voltage, and improve battery efficiency.

[0192] The element concentration distribution of the doped region of the battery silicon substrate is described in detail as described above. The positions of x, y and z are described with the help of the TOPCon battery shown in Figure 1. As shown in Figure 1, the surface of the doped polysilicon layer away from the silicon substrate is the surface shown as D, the maximum value of x is the distance between D and C; the maximum value of y is the distance between D and B; the maximum value of z is the distance between D and A.

[0193] When the solar cell of the present application is a TBC cell, the first doping element is a Group V element (for example, phosphorus), the second doping element is a Group III element (for example, boron), and the layer structure on the above-mentioned silicon substrate also includes a second layer structure, and the above-mentioned second layer structure includes a tunneling layer and a doped polysilicon layer stacked in sequence on the surface of the side of the above-mentioned second doping region away from the silicon substrate; the second doping region is a doping region formed by the second doping element passing through the second layer structure on the above-mentioned silicon substrate.

[0194] In a specific embodiment, in the doped polysilicon layer, the concentration of the first doping element at a depth x (i.e., a first preset depth) away from the surface of the silicon substrate side of the doped polysilicon layer in the first doping region is greater than the concentration of the second doping element at a depth x (i.e., a first preset depth) away from the surface of the silicon substrate side of the doped polysilicon layer in the second doping region, the thickness of the doped polysilicon layer on the first doping region is in the range of 100 to 400 nm, the thickness of the doped polysilicon layer on the second doping region is in the range of 100 to 400 nm, and x is less than or equal to the thickness of the doped polysilicon layer on the first doping region. In a specific embodiment, a first doping element is doped in the tunneling layer of the above-mentioned first doping region, and a second doping element is doped in the tunneling layer of the second doping region. In the direction from the doped polysilicon layer to the tunneling layer, in the tunneling layer, the concentration of the first doping element at a depth y (i.e., a second preset depth) from the surface of the doped polysilicon layer of the first doping region away from the silicon substrate is greater than the concentration of the second doping element at a depth y (i.e., a second preset depth) from the surface of the doped polysilicon layer of the second doping region away from the silicon substrate. The thickness of the tunneling layer on the first doping region ranges from 0.5 to 5 nm, and the thickness of the tunneling layer on the second doping region ranges from 0.5 to 5 nm, and y is less than or equal to the sum of the thicknesses of the doped polysilicon layer and the tunneling layer on the first doping region. In a specific embodiment, in the direction from the doped polysilicon layer to the surface of the above-mentioned first doped region, in the silicon substrate, the concentration of the first doping element at the depth z (i.e., the third preset depth) of the surface of the doped polysilicon layer of the first doped region away from the silicon substrate is greater than the concentration of the second doping element at the depth z (i.e., the third preset depth) of the surface of the doped polysilicon layer of the second doped region away from the silicon substrate, the thickness range of the first doped region is 30 to 100 nm, and z is less than or equal to the sum of the thicknesses of the doped polysilicon layer, the tunneling layer and the first doped region on the first doped region.

[0195] In this application, whether it is a TOPCon cell, a local TOPCon cell, a back contact hybrid cell, or a TBC cell, since the antimony element and the doping element in the silicon substrate are uniformly doped and the resistivity of the silicon substrate and the light absorber is very uniform, it can effectively reduce the lateral transmission resistance of the carriers and improve the cell efficiency.

[0196] In one specific embodiment, the battery of the present application includes an electrode formed on a light absorber, the electrode including a metal crystal portion in contact with the light absorber, the metal crystal portion including antimony element, wherein the light absorber includes a silicon substrate and a region for separating carriers generated by the silicon substrate.

[0197] In the present application, the metal crystal refers to an alloy formed between the metal and silicon in the electrode during the electrode formation process.

[0198] In a specific embodiment, the metal crystal portion further includes a doping element, and the concentration of the doping element is greater than the concentration of the antimony element.

[0199] Since the metal crystal portion of the electrode of the battery of the present application contains antimony elements, the contact resistance of the solar cell can be reduced, and the contact resistance of the battery assembly can be further reduced.

[0200] In a specific embodiment, the mechanical strength of the solar cell of the present application is greater than or equal to 50 MPa.

[0201] The present application also includes a cell string structure, comprising a plurality of the above-mentioned solar cells of the present application interconnected by conductive interconnectors.

[0202] In a specific embodiment, the conductive interconnection member may be, for example, a conductive connection line (sometimes also referred to as a metal soldering ribbon), or may be a conductive line in a conductive backplane.

[0203] Specifically, before forming a photovoltaic module, cells need to go through a stringing (or string welding) step. Specifically, as shown in Figure 2, multiple cells are connected via multiple conductive wires, for example, in series. The conductive wires can be metal wires with circular or triangular cross-sections, and can be composed of a substrate and a bonding layer wrapped around the substrate.

[0204] In this application, whether the connection is made using a conductive connecting wire (metal welding ribbon) or a conductive circuit formed on a conductive backplane, as long as the battery is in contact with the conductive interconnect through the electrode and the contact part contains antimony elements, such a structure can further reduce the contact resistance of the battery string.

[0205] In the stringing step, welding is used for electrical connection, and the welding process requires a heating operation, the main purpose of which is to melt the bonding layer of the connecting wire to form an electrical connection with the battery. However, in the heating step, the stress of the battery may be uneven up and down, and this uneven stress up and down will cause bending. However, the greater the bending during the stringing process, the greater the risk of hidden cracks and fragments in the battery during lamination. However, the mechanical strength of the battery involved in this application is greater than 50Mpa, and its mechanical strength is large, which can suppress excessive bending of the battery cells when stringing, and to a certain extent, it can improve the yield of the component. Generally speaking, the curvature of the back-contact battery will be larger than that of the bifacial battery. This is because the stress difference between the upper and lower surfaces of the back contact will be larger, wherein the back-contact battery refers to a battery having an electrical interconnection structure only on one side, and the bifacial battery refers to a battery having an electrical interconnection structure on both opposite sides.

[0206] Specifically, referring to Figure 2, the curvature of the back-contact battery after being heated at 165-200 degrees Celsius and strung together is less than or equal to 2mm, and the curvature after being heated at a low temperature of 100-160 degrees Celsius and strung together is less than or equal to 1.5mm; referring to Figure 3, the curvature of the bifacial battery after being heated at 165-200 degrees Celsius and strung together is less than or equal to 1.2mm, and the curvature after being heated at a low temperature of 100-160 degrees Celsius and strung together is less than or equal to 1mm. It can be seen that the specially doped battery of the present invention has a smaller curvature, which can well control the problems of hidden cracks and fragments during lamination. It should be noted that the curvature involved in this application refers to the height or depth of the bulge or depression generated on the surface of the battery when the battery is bent, which can be obtained by measuring the curvature radius of the battery edge.

[0207] The present application also relates to a solar cell assembly, comprising a plurality of cells, an encapsulation layer, a cover plate and a back plate as described above. The encapsulation layer encapsulates the plurality of cells and is located between the cover plate and the back plate.

[0208] The battery strings of the present application are formed into battery assemblies through typesetting, stacking, lamination and other processes. The formed battery assemblies are shown in Figures 4 and 5. Among them, when performing the lamination process, it is necessary to apply pressure and heat to melt the encapsulation layer to seal the battery string and bond the cover plate and the back plate, and the encapsulation layer is located between the cover plate and the back plate. In the lamination process, due to the operation of applying pressure and heating, part of the stress of the battery is released and suppressed. For the back contact battery, see Figure 4, the curvature of the battery in the laminated battery assembly is less than or equal to 1.2 mm, and for the double-sided battery, see Figure 5, the curvature of the battery in the laminated battery assembly is less than or equal to 0.8 mm. It has been verified that the hidden cracks and fragmentation problems of the laminated batteries are significantly controlled. It can be seen from Figures 3 and 5 that the bending direction of the battery is toward the cover plate, that is, the battery protrudes toward the direction of the cover plate to form a curved shape.

[0209] Specifically, the encapsulation layer can be at least one of EVA, POE, silicone, and PVB. The cover plate is close to the light-receiving surface of the battery and is made of a transparent organic or inorganic material. Preferably, it can be low-iron embossed glass, and its thickness is preferably 2.0 or 3.2 mm. The back plate can be a transparent or non-transparent material. For double-glass modules, the back plate is a transparent material, which is preferably glass, while for single-glass modules, the back plate can be non-transparent, such as a TPC board. Furthermore, the battery assembly also includes a frame, which has a groove-shaped mounting portion for accommodating the laminate, and the edges of the cover plate and the back plate are embedded in the mounting portion of the frame.

[0210] In the present application, the resistivity of a silicon wafer or silicon substrate can be detected by any method known to those skilled in the art, and these methods can be selected by those skilled in the art based on demand, for example, by a four-probe tester, or by a non-contact eddy current method or other methods (for example, a terahertz offline two-dimensional imaging device (FalconWave-S) can be used for detection), preferably by a four-probe tester. It will be understood by those skilled in the art that the resistivity of a silicon wafer or silicon substrate can refer to the resistivity detection data of any site on the surface of a silicon wafer or silicon substrate, or in a silicon wafer or silicon substrate, or it can be the average value of the resistivity detection data of multiple locations or the average value of the resistivity on the entire silicon wafer or silicon substrate. Those skilled in the art can select the arbitrary site for detection based on the detection conditions and the instrument used and based on the actual situation, or can calculate the average value of multiple sites after detecting multiple sites, in order to serve as the resistivity of the silicon wafer or silicon substrate. In a specific embodiment, the resistivity of a silicon wafer or silicon substrate refers to the average value of the resistivity detected on the thickness of the silicon wafer or silicon substrate, for example, the resistivity of each site of the silicon wafer or silicon substrate is detected in a thickness direction using a four-probe tester, and the average value in this thickness direction is obtained.

[0211] In this application, the resistivity change rate of a silicon wafer or silicon substrate refers to the value obtained by subtracting the minimum value from the maximum value of the resistivity at any point in the silicon wafer or silicon substrate and dividing it by the average value of the resistivity at any point in the silicon wafer or silicon substrate. For example, a person skilled in the art can arbitrarily select any point on the surface of a silicon wafer or silicon substrate, or any point in the silicon wafer or silicon substrate, and use a non-contact eddy current method (for example, a terahertz offline two-dimensional imaging device (FalconWave-S)) or a four-probe tester to perform detection, and analyze the resistivity of the n tested points, select the maximum and minimum values ​​therefrom, and calculate the average value and the resistivity change rate of the silicon wafer or silicon substrate. Those skilled in the art will fully understand that n only needs to be a positive integer greater than or equal to 2, and can generally be, for example, a positive integer greater than 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80, 85, 90, 95 or 100. Alternatively, the entire surface of the silicon wafer or silicon substrate may be scanned, and the average resistivity of any point on the surface of the silicon wafer or silicon substrate in a direction perpendicular to the surface of the silicon wafer or silicon substrate may be obtained, and then the maximum resistivity value R may be selected based on the scan results of the entire surface. max And the minimum resistivity value R min , calculate the average resistivity value R v , and use the calculation formula of resistivity change rate (R max -R min ) / R v To calculate the resistivity change rate of the silicon wafer or silicon substrate. In actual operation, the resistivity change rate of the silicon wafer or silicon substrate can be measured by the following method, that is, using a terahertz offline two-dimensional imaging device (FalconWave-S) or a four-probe tester to perform a resistivity surface scan on the silicon wafer or silicon substrate, and selecting a line from the center point of the silicon wafer or silicon substrate to the edge of the silicon wafer or silicon substrate, as shown in Figure 6. The black line in Figure 6 represents the selected line, and the average resistivity value R of the silicon wafer or silicon substrate on the selected line is obtained. v , get the maximum resistivity value R on the selected line max And the minimum resistivity value R min , the resistivity change rate is (R max -R min ) / R v In addition, those skilled in the art will fully understand that the black lines shown in FIG6 are merely schematic, and any lines can be drawn on the silicon wafer or silicon substrate to detect the resistivity change rate of the silicon wafer or silicon substrate.

[0212] Example

[0213] This application provides general and / or specific descriptions of the materials and experimental methods used in the experiments. In the following examples, unless otherwise specified, % represents wt%, i.e., percentage by weight. All reagents or instruments used without manufacturer indication are commercially available conventional reagents.

[0214] Example 1

[0215] The polysilicon blocks are placed in the quartz crucible. For example, the solid silicon raw material is first piled into the quartz crucible, and then the quartz crucible filled with silicon material is placed in the single crystal furnace.

[0216] The single crystal furnace is vacuumed, and the single crystal furnace heater is turned on to gradually melt the solid silicon in the quartz crucible into a molten state.

[0217] After the solid silicon material in the quartz crucible is heated and melted, the actual volume occupied by the solid silicon material in the quartz crucible decreases, and the melted silicon material does not reach the maximum loading capacity of the quartz crucible. Therefore, it is necessary to use an external feeder, such as a quartz tube feeding cylinder, to fill the quartz crucible with silicon material for a second time. In this embodiment, a quartz tube is required for filling. During the filling process, the heater simultaneously melts the silicon material in the quartz crucible.

[0218] Add the Sb-containing dopant and silicon material into the quartz crucible. After the silicon material in the quartz crucible is completely melted, the temperature adjustment step is switched to insert the seed crystal into the silicon liquid. By controlling the power parameters, etc., the critical crystallization temperature of the liquid surface temperature is reached. Among them, the doping concentration of antimony element in the Sb-containing dopant is 4E+14cm -3 , the doping concentration of carbon element is 4E+13cm -3 The doping concentration ratio of antimony and carbon is 10:1.

[0219] After the seed crystal and the liquid level reach the crystallization temperature, the seed crystal is pulled upward.

[0220] When the seed crystal length reaches the required length of 15-20mm and the seed crystal diameter is within 5-10mm, the actual single crystal diameter is adjusted to the range of 252±1mm round rod diameter by adjusting parameters such as power and pulling speed; after the shoulder is placed, the shoulder rotation process is carried out to enter the silicon rod equalization process.

[0221] During the equal diameter process, adjust the pulling speed, power, etc. until the equal diameter length is 3800mm.

[0222] The silicon rod drawing is completed by reducing the diameter of the silicon rod and finishing.

[0223] The silicon rods are cut to the appropriate length by a cutting machine, and then transferred to a square cutting machine to be processed into square rods. The square rods are polished by a polishing machine and then transferred to a slicer to be cut into silicon wafers by diamond wire.

[0224] A total of 40 silicon wafers were obtained using the method of Example 1. The minority carrier lifetimes of these silicon wafers were tested using a WCT-120 instrument (the parameters corresponding to the silicon wafers were input and the 3E15 injection concentration test was selected). The minority carrier lifetimes of the 40 silicon wafers were tested and the average minority carrier lifetime was calculated. At the same time, the carbon and antimony doping concentrations of the silicon wafers were detected using the ICP-MS method. The obtained concentrations were consistent with the antimony and carbon concentrations in the aforementioned Sb-containing dopant.

[0225] The silicon wafer is rectangular. Micrometer measurement revealed one side of the rectangle to be 200 mm long, the other side to be 200 mm long, the arc length of the chamfered corner to be 5 mm, and the thickness of the wafer to be 100 μm. Secondary ion mass spectrometry (SIMS) revealed a total oxygen content below 18 ppma, and a four-probe resistivity tester to be 5 Ω·cm.

[0226] Example 2-11

[0227] Silicon wafers were prepared using exactly the same method as in Example 1, with only the doping concentrations of the antimony element and carbon element used in the dopant in Example 1 and their ratio being adjusted, while the rest remained unchanged. The minority carrier lifetime, mechanical strength, and cell efficiency of 40 silicon wafers obtained in each example were tested using a WCT-120 instrument (by inputting the parameters corresponding to the silicon wafer and selecting a 3E15 injection concentration test), and their average values ​​were calculated.

[0228] Comparative Example 1-2

[0229] Silicon wafers were prepared using exactly the same method as in Example 1, with only the amount of dopant used in Example 1 adjusted and the rest remaining unchanged. The minority carrier lifetime, mechanical strength, and cell efficiency of 40 silicon wafers obtained from each comparative example were tested using a WCT-120 instrument (entering the parameters corresponding to the silicon wafer and selecting a 3E15 injection concentration for testing), and their average values ​​were calculated.

[0230] Performance Testing

[0231] N-type TOPCon cells were prepared using the silicon wafers of Examples 1-11 and Comparative Examples 1-2, and the efficiency of the cells was measured.

[0232] The data of Examples 1-11 and Comparative Examples 1-2 are summarized in Table 1.

[0233] Table 1

[0234] Although the embodiments of the present application are described above, the present application is not limited to the above-mentioned specific embodiments and application fields. The above-mentioned specific embodiments are merely illustrative and instructive, and not restrictive. A person of ordinary skill in the art, under the guidance of this specification and without departing from the scope of protection of the claims of this application, can also make many forms, all of which fall within the scope of protection of this application.

Claims

1. A silicon wafer, wherein: The silicon wafer includes antimony element and carbon element, and the ratio of the doping concentration of the antimony element to the doping concentration of the carbon element is 1:0.1 to 1:12.

5.

2. The silicon wafer according to claim 1, wherein: The doping concentration of carbon element ranges from 4E+13cm -3 ~2.5E+17cm -3 .

3. The silicon wafer according to claim 1 or 2, wherein: The doping concentration range of antimony element is 4E+14cm -3 ~2E+16cm -3 , preferably 4.3E+14cm -3 To 1.9E+16cm -3 , and more preferably 4.45E+14cm -3 To 1.87E+16cm -3 .

4. The silicon wafer according to any one of claims 1 to 3, wherein The doping concentration range of antimony element is greater than or equal to 4E+14cm -3 When the doping concentration of antimony element is less than or equal to a, the ratio of the doping concentration of antimony element to the doping concentration of carbon element is 1:b to 1:12.5, wherein a is selected from 8E+15cm -3 ~1.2E+16cm -3 , preferably a is selected from 9E+15cm -3 ~1.1E+16cm -3 , and further preferably a is 1E+16cm -3 , b is greater than 0.1, preferably b is greater than 0.5, and more preferably b is greater than 0.

7.

5. The silicon wafer according to any one of claims 1 to 3, wherein: The doping concentration range of antimony element is greater than a and less than or equal to 2E+16cm -3 When the doping concentration of antimony element and carbon element is 1:0.1 to 1:c, a is selected from 8E+15cm -3 ~1.2E+16cm -3 , preferably a is selected from 9E+15cm -3 ~1.1E+16cm -3 , and further preferably a is 1E+16cm -3 , c is less than 0.8, preferably c is less than 0.5, and more preferably c is less than 0.

3.

6. The silicon wafer according to any one of claims 1 to 5, wherein: The resistivity of the silicon wafer is 0.3 to 10 Ω·cm, preferably 0.4 to 8 Ω·cm, and more preferably 0.5 to 6 Ω·cm.

7. The silicon wafer according to any one of claims 1 to 6, wherein: The minority carrier lifetime of the silicon wafer is greater than or equal to 200 microseconds, preferably greater than or equal to 300 microseconds, and more preferably greater than or equal to 500 microseconds.

8. The silicon wafer according to any one of claims 1 to 7, wherein: The resistivity change rate of the silicon wafer is ≤0.6, preferably the resistivity change rate is ≤0.5, and preferably the resistivity change rate is ≤0.

4.

9. The silicon wafer according to any one of claims 1 to 8, wherein: The total oxygen content in the silicon wafer is below 25 ppma, preferably below 18 ppma, and more preferably below 14 ppma, or The total oxygen content in the silicon wafer is greater than 2 ppma, preferably greater than 3 ppma, and more preferably greater than 4 ppma. 10 . The silicon wafer according to claim 1 , further comprising at least one of phosphorus, gallium and germanium. 11 . The silicon wafer according to claim 1 , wherein the mechanical strength of the silicon wafer is greater than or equal to 70 MPa, and / or the dispersion of the mechanical strength of the silicon wafer is less than or equal to 0.

9. 12 . The silicon wafer according to claim 1 , wherein the length of at least one side of the silicon wafer is greater than or equal to 156 mm. 13 . The silicon wafer according to claim 1 , wherein the silicon wafer is rectangular, one side of the rectangle is 156 mm to 300 mm long, and the other side of the rectangle is 83 mm to 300 mm long.

14. The silicon wafer according to any one of claims 1 to 13, further comprising a chamfer connecting two adjacent sides of the silicon wafer, wherein the arc length projection length of the chamfer is 1 mm to 10 mm. 15 . The silicon wafer according to claim 1 , wherein the thickness of the silicon wafer is 40 μm to 170 μm, preferably 70 μm to 160 μm, and more preferably 80 μm to 140 μm.

16. A solar cell comprising the silicon wafer according to any one of claims 1 to 15. 17 . The solar cell according to claim 16 , wherein the mechanical strength of the solar cell is greater than or equal to 50 MPa, preferably greater than or equal to 60 MPa, and preferably greater than or equal to 70 MPa. 18 . The solar cell according to claim 16 , wherein the thickness of the solar cell is 40 μm to 170 μm, preferably 70 μm to 160 μm, and more preferably 80 μm to 140 μm.

19. The solar cell according to any one of claims 16 to 18, wherein one side of the solar cell has a length of 156 mm to 300 mm, and the other side of the cell has a length of 83 mm to 300 mm.

20. A solar cell comprising a silicon substrate ， The silicon substrate comprises a silicon base and a doping region on at least one side of the surface of the silicon substrate, wherein the silicon substrate contains antimony and carbon elements, and the doping region is doped with doping elements, wherein the doping elements are selected from the third main group elements or the fifth main group elements, and the ratio of the doping concentration of the antimony element to the doping concentration of the carbon element is 1:0.1 to 1:12.

5.

21. The solar cell according to claim 20, wherein the carbon doping concentration range is 4E+13cm -3 ~2.5E+17cm -3 .

22. The solar cell according to claim 20 or 21, wherein the doping concentration of antimony element is 4E+14cm -3 To 2E+16cm -3 , preferably 4.3E+14cm -3 To 1.9E+16cm -3 , and more preferably 4.45E+14cm -3 To 1.87E+16cm -3 .

23. The solar cell according to any one of claims 20 to 22, wherein: The doping concentration range of antimony element is greater than or equal to 4E+14cm -3 When the doping concentration of antimony element is less than or equal to a, the ratio of the doping concentration of antimony element to the doping concentration of carbon element is 1:b to 1:12.5, wherein a is selected from 8E+15cm -3 ~1.2E+16cm -3 , preferably a is selected from 9E+15cm -3 ~1.1E+16cm -3 , and further preferably a is 1E+16cm -3 , b is greater than 0.1, preferably b is greater than 0.5, and more preferably b is greater than 0.

7.

24. The solar cell according to any one of claims 20 to 23, wherein: The doping concentration range of antimony element is greater than a and less than or equal to 2E+16cm -3 When the doping concentration of antimony element and carbon element is 1:0.1 to 1:c, a is selected from 8E+15cm -3 ~1.2E+16cm -3 , preferably a is selected from 9E+15cm -3 ~1.1E+16cm -3 , and further preferably a is 1E+16cm -3 , c is less than 0.8, preferably c is less than 0.5, and more preferably c is less than 0.

3.

25. The solar cell according to any one of claims 20 to 24, wherein the resistivity of the silicon substrate is 0.3 to 10 Ω·cm, preferably 0.4 to 8 Ω·cm, and more preferably 0.5 to 6 Ω·cm.

26. The solar cell according to any one of claims 20 to 25, wherein: The minority carrier lifetime of the silicon substrate is greater than or equal to 200 microseconds, preferably greater than or equal to 300 microseconds, and more preferably greater than or equal to 500 microseconds.

27. The solar cell according to any one of claims 20 to 26, wherein the resistivity change rate of the silicon substrate is ≤0.6, preferably the resistivity change rate is ≤0.5, preferably the resistivity change rate is ≤0.

4.

28. The solar cell according to any one of claims 20 to 27, wherein: The total oxygen content in the silicon substrate is below 25 ppma, preferably below 18 ppma, and further preferably below 14 ppma. Alternatively, the total oxygen content in the silicon substrate is above 2 ppma, preferably above 3 ppma, and further preferably above 4 ppma.

29. The solar cell according to any one of claims 20 to 28, wherein the silicon substrate further comprises at least one of phosphorus, gallium and germanium. 30 . The solar cell according to claim 20 , further comprising at least one doping layer on a surface of at least one side of the silicon substrate. The solar cell according to claim 30 , wherein at least one passivation layer is provided between the doping layer and the doping region.

32. The solar cell according to any one of claims 20 to 31, wherein the doping concentration of the antimony element in the doping region is substantially constant in the thickness direction of the silicon substrate.

33. The solar cell according to any one of claims 20 to 32, wherein: In the doping region, the sum of the doping concentration of the antimony element and the doping concentration of the doping element is less than or equal to 1E+21cm -3 .

34. The solar cell according to any one of claims 20 to 33, wherein: The solar cell comprises: - a light absorber comprising the silicon substrate for absorbing light and generating photogenerated carriers and a region for separating the carriers generated by the silicon substrate; and - an electrode formed on the light absorber, the electrode including a metal crystal portion in contact with the light absorber, the metal crystal portion including antimony element.

35. The solar cell according to any one of claims 20 to 34, wherein the mechanical strength of the solar cell is 50 MPa, preferably greater than or equal to 60 MPa, preferably greater than or equal to 70 MPa.

36. A cell string comprising solar cells interconnected by conductive interconnectors, at least one of the solar cells being the solar cell of any one of claims 16 to 35.

37. The battery string according to claim 36, wherein: The curvature of the solar cell is less than or equal to 2 mm.

38. The battery string according to claim 36 or 37, wherein the connecting wires are bonded to the solar cells by welding or conductive bonding.

39. The battery string of claim 38, wherein the welding comprises a heating step.

40. The battery string according to claim 39, wherein the temperature range of the heating step is 100-160 degrees Celsius, and the curvature of the solar cell is less than or equal to 1.5 mm.

41. The battery string according to claim 39, wherein the temperature range of the heating step is 165-200 degrees Celsius, and the curvature of the solar cell is less than or equal to 2 mm.

42. The cell string according to any one of claims 36 to 41, wherein the conductive interconnect comprises an electrical contact portion contacting an electrode of the solar cell, the electrical contact portion comprising antimony element.

43. A solar cell assembly, comprising a plurality of cells, a packaging layer, a cover plate and a back plate, wherein the packaging layer packages the plurality of cells and is located between the cover plate and the back plate, and the cell is a solar cell according to any one of claims 16 to 35.

44. The solar module of claim 43, wherein: The curvature of the battery is less than or equal to 1.2 mm.

45. The solar energy assembly according to claim 43 or 44, further comprising a frame, wherein the edge of the cover plate and / or the back plate is embedded in the mounting portion of the frame.

46. ​​The solar module according to any one of claims 43 to 45, wherein the cover sheet and / or the back sheet is a transparent sheet.

47. The solar module according to any one of claims 43 to 45, wherein the back sheet is a non-transparent sheet.

48. The solar module according to any one of claims 43 to 47, wherein the cells protrude toward the cover plate to form a curved shape.

49. The solar module of any one of claims 43-48, wherein the plurality of cells are interconnected by a conductive interconnect, the conductive interconnect comprising an electrical contact portion contacting an electrode of the solar cell, the electrical contact portion comprising antimony.

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