Display substrate and driving method and preparation method therefor, and display apparatus

Abstract

Disclosed are a display substrate and a driving method and preparation method therefor, and a display apparatus. The display substrate comprises a plurality of circuit units. At least one circuit unit comprises a pixel driving circuit, a sensing circuit and a photosensitive device. The pixel driving circuit comprises at least one light-emitting control transistor (T5, T6), and the sensing circuit at least comprises a sensing control transistor (T8). The sensing control transistor (T8) is connected to the photosensitive device, and the light-emitting control transistor (T5, T6) and the sensing control transistor (T8) are different types of transistors. In the at least one circuit unit, the light-emitting control transistor (T5, T6) and the sensing control transistor (T8) are connected to a same light-emitting signal line (24).

Description

Display substrate, driving method and manufacturing method thereof, and display device Technical Field

[0001] This article relates to but is not limited to the field of display technology, and specifically to a display substrate, a driving method and a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, the present disclosure provides a display substrate, comprising multiple circuit units, at least one circuit unit comprising a pixel driving circuit, a sensing circuit and a photosensitive device, the pixel driving circuit comprising at least a driving transistor and at least one light-emitting control transistor, the first end of the light-emitting control transistor being connected to a first power line, the second end of the light-emitting control transistor being connected to the first end of the driving transistor, or the first end of the light-emitting control transistor being connected to the second end of the driving transistor, and the second end of the light-emitting control transistor being connected to the light-emitting device; the sensing circuit comprising at least a sensing control transistor, the first end of the sensing control transistor being connected to the photosensitive device, the second end of the sensing control transistor being connected to a sensing signal line, the light-emitting control transistor and the sensing control transistor being transistors of different types; in at least one circuit unit, the light-emitting control transistor and the sensing control transistor are connected to the same light-emitting signal line, and the light-emitting signal line is configured to provide a light-emitting control signal to the pixel driving circuit.

[0006] In an exemplary embodiment, the light emission control transistor is a polysilicon transistor, and the sensing control transistor is an oxide transistor; or the light emission control transistor is an oxide transistor, and the sensing control transistor is a polysilicon transistor.

[0007] In an exemplary embodiment, the light emission control transistor includes at least a light emission control gate electrode, and the sensing control transistor includes at least a sensing control gate electrode. The light emission control gate electrode is directly connected to the light emission signal line, and the sensing control gate electrode is connected to the light emission signal line through a light emission connection electrode.

[0008] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes multiple conductive layers, the light-emitting control gate electrode and the light-emitting signal line are arranged in the same conductive layer, the sensing control gate electrode and the light-emitting signal line are arranged in different conductive layers, and the light-emitting connection electrode and the sensing control gate electrode are arranged in different conductive layers.

[0009] In an exemplary embodiment, the multiple conductive layers include at least a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged in sequence, the light-emitting signal line and the light-emitting control gate electrode are arranged in the first conductive layer and are an integrated structure connected to each other, the sensing control gate electrode is respectively arranged in the second conductive layer and the third conductive layer, the light-emitting connection electrode is arranged in the fourth conductive layer, and the light-emitting connection electrode is respectively connected to the light-emitting signal line and the sensing control gate electrode through vias.

[0010] In an exemplary embodiment, the sensing control gate electrode includes a bottom gate electrode and a top gate electrode, the bottom gate electrode is arranged in the second conductive layer, the top gate electrode is arranged in the third conductive layer, and the light-emitting connection electrode is connected to the bottom gate electrode and the top gate electrode respectively through vias.

[0011] In an exemplary embodiment, the photosensitive device includes at least a photosensitive first electrode, a photosensitive second electrode, and a photosensitive layer arranged between the first photosensitive electrode and the second photosensitive electrode, the first photosensitive electrode is connected to the sensing power line, and the second photosensitive electrode is connected to the first electrode of the sensing control transistor.

[0012] In an exemplary embodiment, the sensing control transistor includes at least a sensing active layer; in a direction perpendicular to the display substrate, the display substrate includes at least a first semiconductor layer arranged on a base and a second semiconductor layer arranged on a side of the first semiconductor layer away from the base, the photosensitive first electrode, the photosensitive second electrode and the photosensitive layer are arranged in the first semiconductor layer, and the sensing active layer is arranged in the second semiconductor layer.

[0013] In an exemplary embodiment, the photosensitive first electrode and the photosensitive second electrode are formed by conducting the first semiconductor layer, and the photosensitive layer is formed by doping the first semiconductor layer.

[0014] In an exemplary embodiment, at least one circuit unit further includes an eleventh connecting electrode and a thirty-first connecting electrode, and the first photosensitive electrode is connected to the sensing power line through the eleventh connecting electrode and the thirty-first connecting electrode.

[0015] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes multiple conductive layers, the eleventh connecting electrode, the thirty-first connecting electrode and the sensing power line are arranged in different conductive layers, the eleventh connecting electrode is connected to the photosensitive first electrode through a via hole, the thirty-first connecting electrode is connected to the eleventh connecting electrode through a via hole, and the sensing power line is connected to the thirty-first connecting electrode through a via hole.

[0016] In an exemplary embodiment, at least one circuit unit further includes a twelfth connecting electrode, and the second photosensitive electrode is connected to the first region of the sensing active layer through the twelfth connecting electrode.

[0017] In an exemplary embodiment, the twelfth connecting electrode is disposed on a side of the sensing active layer away from the substrate, the twelfth connecting electrode is connected to the second photosensitive electrode through a via hole, and the twelfth connecting electrode is connected to the first region of the sensing active layer through another via hole.

[0018] In an exemplary embodiment, at least one circuit unit further includes a thirteenth connecting electrode and a thirty-second connecting electrode, and the second region of the sensing active layer is connected to the sensing signal line through the thirteenth connecting electrode and the thirty-second connecting electrode.

[0019] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes multiple conductive layers, the thirteenth connecting electrode, the thirty-second connecting electrode, and the sensing signal line are arranged in different conductive layers, the thirteenth connecting electrode is connected to the second region of the sensing active layer through a via hole, the thirty-second connecting electrode is connected to the thirteenth connecting electrode through a via hole, and the sensing signal line is connected to the thirty-second connecting electrode through a via hole.

[0020] In an exemplary embodiment, the shape of the sensing power line is a straight line or a broken line extending in the second direction of the main body, and at least one circuit unit further includes a sensing power connection line, the shape of the sensing power connection line is a straight line or a broken line extending in the first direction of the main body, and the sensing power lines are connected to the sensing power connection lines to form a network connectivity structure.

[0021] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0022] On the other hand, the present disclosure further provides a method for driving a display substrate, wherein the display substrate includes a plurality of circuit units, at least one circuit unit includes a pixel driving circuit, a sensing circuit, and a photosensitive device, the pixel driving circuit includes at least a driving transistor and at least one light-emitting control transistor, the first end of the light-emitting control transistor being connected to a first power line, and the second end of the light-emitting control transistor being connected to the first end of the driving transistor, or the first end of the light-emitting control transistor being connected to the second end of the driving transistor, and the second end of the light-emitting control transistor being connected to the light-emitting device; the sensing circuit includes at least a sensing control transistor, the first end of the sensing control transistor being connected to the photosensitive device, and the second end of the sensing control transistor being connected to a sensing signal line, the light-emitting control transistor and the sensing control transistor being different types of transistors; in at least one circuit unit, the light-emitting control transistor and the sensing control transistor are connected to the same light-emitting signal line, and the light-emitting signal line is configured to provide a light-emitting control signal to the pixel driving circuit; the driving method includes:

[0023] In a first sensing period, the light emitting signal line controls the sensing circuit to generate a photosensitive current;

[0024] During the second sensing period, the light emitting signal line controls the pixel driving circuit to output a driving current.

[0025] In an exemplary embodiment, the light emitting signal line controls the sensing circuit to generate a photosensitive current, which includes: the light emitting signal line outputs a first signal, the light emitting control transistor is turned off, the sensing control transistor is turned on, and the sensing circuit generates the photosensitive current.

[0026] In an exemplary embodiment, the light emitting signal line controls the pixel driving circuit to output a driving current, including: the light emitting signal line outputs a second signal, the sensing control transistor is turned off, the light emitting control transistor is turned on, and the pixel driving circuit outputs a driving current.

[0027] In another aspect, the present disclosure further provides a method for preparing a display substrate, wherein the display substrate includes a plurality of circuit units, and the method includes:

[0028] A pixel driving circuit, a sensing circuit and a photosensitive device are formed in at least one circuit unit; the pixel driving circuit at least includes a driving transistor and at least one light-emitting control transistor, the first end of the light-emitting control transistor is connected to a first power line, and the second end of the light-emitting control transistor is connected to the first end of the driving transistor, or the first end of the light-emitting control transistor is connected to the second end of the driving transistor, and the second end of the light-emitting control transistor is connected to the light-emitting device; the sensing circuit at least includes a sensing control transistor, the first end of the sensing control transistor is connected to the photosensitive device, and the second end of the sensing control transistor is connected to a sensing signal line, and the light-emitting control transistor and the sensing control transistor are transistors of different types; in at least one circuit unit, the light-emitting control transistor and the sensing control transistor are connected to the same light-emitting signal line, and the light-emitting signal line is configured to provide a light-emitting control signal to the pixel driving circuit.

[0029] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0031] FIG1 is a schematic structural diagram of a display device;

[0032] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0033] FIG3 is a schematic diagram of a cross-sectional structure of a display substrate;

[0034] FIG4 is a schematic diagram of an equivalent circuit of a unit control circuit according to an exemplary embodiment of the present disclosure;

[0035] FIG5 is a driving timing diagram of the unit control circuit shown in FIG4 ;

[0036] FIG6 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0037] FIG7 is a schematic structural diagram of the sensing circuit and the photosensitive device in FIG6 ;

[0038] FIG8 is a schematic diagram showing a substrate after forming a first semiconductor layer pattern according to the present disclosure;

[0039] 9A and 9B are schematic diagrams showing a substrate after forming a first conductive layer pattern according to the present disclosure;

[0040] FIG10 is a schematic diagram of a substrate after a photosensitive layer pattern is formed on the substrate according to the present disclosure;

[0041] 11A and 11B are schematic diagrams showing a substrate after forming a second conductive layer pattern according to the present disclosure;

[0042] 12A and 12B are schematic diagrams showing a substrate after forming a second semiconductor layer pattern according to the present disclosure;

[0043] 13A and 13B are schematic diagrams showing a substrate after a third conductive layer pattern is formed thereon according to the present disclosure;

[0044] FIG14 is a schematic diagram showing a substrate after a sixth insulating layer pattern is formed according to the present disclosure;

[0045] 15A and 15B are schematic diagrams showing a substrate after a fourth conductive layer pattern is formed thereon according to the present disclosure;

[0046] FIG16 is a schematic diagram showing a substrate after forming a first planar layer pattern according to the present disclosure;

[0047] 17A and 17B are schematic diagrams showing a substrate after a fifth conductive layer pattern is formed thereon according to the present disclosure;

[0048] FIG18 is a schematic diagram showing a substrate after forming a second planar layer pattern according to the present disclosure;

[0049] 19A and 19B are schematic diagrams showing a substrate after a sixth conductive layer pattern is formed thereon according to the present disclosure.

[0050] Explanation of Reference Numerals: 11—first active layer; 12—second active layer; 13—third active layer; 14—fourth active layer; 15—fifth active layer; 16—sixth active layer; 17—seventh active layer; 18—eighth active layer; 19—photosensitive active layer; 21—first scanning signal line; 22—second scanning signal line; 23—third scanning signal line; 24—light-emitting signal line; 25—first electrode plate; 26—second electrode plate; 27—photosensitive shielding electrode; 28—opening; 29—electrode plate connecting bar; 31—first initial signal line; 32—second initial signal line; 33—first initial connecting line; 34—second initial connecting line; 35—shielding line; 36—eighth bottom gate electrode; 37—eighth top gate electrode; 40—photosensitive device; 41—photosensitive first electrode; 42—Photosensitive second electrode; 43—Photosensitive layer; 51—First connecting electrode; 52—Second connecting electrode; 53—Third connecting electrode; 54—Fourth connecting electrode; 55—Fifth connecting electrode; 56—Sixth connecting electrode; 57—Seventh connecting electrode; 61—Eleventh connecting electrode; 62—Twelfth connecting electrode; 63—Thirteenth connecting electrode; 64—Light-emitting connecting electrode; 71—Twenty-first connecting electrode; 72—Twenty-second connecting electrode; 73—Twenty-third connecting electrode; 74—Sensing power supply connecting line; 81—Thirty-first connecting electrode; 82—Thirty-second connecting electrode; 91—Data signal line; 92—First power supply line; 93—Anode connecting electrode; 94—Sensing power supply line; 95—Sensing signal line; 101—Substrate; 102—Drive structure layer; 103—Light-emitting structure layer; 104—Encapsulation structure layer. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0052] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0053] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0054] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0055] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0056] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0057] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0058] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0059] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0060] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0061] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0062] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0063] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit connected to the circuit unit. The circuit unit may include at least a pixel driving circuit, and the pixel driving circuit may be respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured as a shift register and may generate emission signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o may be a natural number. In an exemplary embodiment, the pixel array may be provided on a display substrate.

[0064] Figure 2 is a schematic diagram of a planar structure of a display substrate. As shown in Figure 2, the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, a third sub-pixel P3 emitting a third color light, and a fourth sub-pixel P4 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting unit is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0065] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, and the third subpixel P3 and the fourth subpixel P4 may be green subpixels (G) that emit green light. In an exemplary embodiment, the subpixels may be rectangular, diamond, pentagonal, or hexagonal in shape, and the four subpixels may be arranged horizontally, vertically, or in a square, etc., which is not limited in this disclosure.

[0066] In an exemplary embodiment, a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a triangular arrangement, which is not limited in the present disclosure.

[0067] Figure 3 is a schematic cross-sectional view of a display substrate, illustrating the structure of four sub-pixels in the display area. As shown in Figure 3, in a plane perpendicular to the display substrate, the display substrate may include a drive structure layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the drive structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in this disclosure.

[0068] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving structure layer 102 may include a plurality of circuit units, and the circuit unit may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, and the light-emitting unit may include at least a light-emitting device composed of an anode, an organic light-emitting layer and a cathode, the anode being connected to the pixel driving circuit, the organic light-emitting layer being connected to the anode, and the cathode being connected to the organic light-emitting layer, and the organic light-emitting layer emitting light of corresponding colors under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material laminated structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0069] An exemplary embodiment of the present disclosure provides a display substrate. In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate may include a driving structure layer arranged on a base and a light-emitting structure layer arranged on a side of the driving structure layer away from the base. On a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit may include a unit control circuit, the unit control circuit may include at least a pixel driving circuit, a sensing circuit and a photosensitive device, the pixel driving circuit is configured to output a driving current to the connected light-emitting device, the sensing circuit is connected to the photosensitive device, and the sensing circuit is configured to generate a photosensitive current according to the connected photosensitive device. The light-emitting structure layer may include a plurality of light-emitting units, at least one light-emitting unit may include a light-emitting device, and the light-emitting device is connected to the pixel driving circuit of the corresponding circuit unit. In an exemplary embodiment, the unit control circuit may be referred to as a pixel driving circuit compatible with a light-sensing function.

[0070] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to a unit control circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to a light-emitting device. In exemplary embodiments, the position and shape of the orthographic projection of the light-emitting unit on the substrate may correspond to the position and shape of the orthographic projection of the circuit unit on the substrate, or the position and shape of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position and shape of the orthographic projection of the circuit unit on the substrate.

[0071] In an exemplary embodiment, the pixel driving circuit may include at least a driving transistor and at least one emission control transistor, wherein a first terminal of the emission control transistor is connected to a first power line, and a second terminal of the emission control transistor is connected to the first terminal of the driving transistor, or alternatively, the first terminal of the emission control transistor is connected to the second terminal of the driving transistor, and the second terminal of the emission control transistor is connected to the light-emitting device. The sensing circuit may include at least a sensing control transistor, wherein a first terminal of the sensing control transistor is connected to the light-sensing device, and a second terminal of the sensing control transistor is connected to a sensing signal line. The emission control transistor and the sensing control transistor are different types of transistors, and in at least one circuit unit, the emission control transistor and the sensing control transistor are connected to the same emission signal line, and the emission signal line is configured to provide a light-emitting control signal to the pixel driving circuit.

[0072] In an exemplary embodiment, the light emission control transistor is a polysilicon transistor, and the sensing control transistor is an oxide transistor; or the light emission control transistor is an oxide transistor, and the sensing control transistor is a polysilicon transistor.

[0073] In an exemplary embodiment, the light emission control transistor includes at least a light emission control gate electrode, and the sensing control transistor includes at least a sensing control gate electrode. The light emission control gate electrode is directly connected to the light emission signal line, and the sensing control gate electrode is connected to the light emission signal line through a light emission connection electrode.

[0074] The display substrate of the exemplary embodiments of the present disclosure will be described below with reference to some examples.

[0075] Figure 4 is a schematic diagram of an equivalent circuit of a unit control circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 4, in an exemplary embodiment, the unit control circuit may include a pixel driving circuit, a sensing circuit, and a photosensitive device. The pixel driving circuit may include seven transistors (first transistor T1 to seventh transistor T7) and one storage capacitor C, forming a 7T1C structure. The pixel driving circuit is connected to eight signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, emission signal line EM, first initial signal line INIT1, second initial signal line INIT2, first power line VDD, and data signal line D). The sensing circuit may include one transistor (eighth transistor T8), which is connected to two signal lines (emission signal line EM and sensing signal line REF). The photosensitive device PD may include a first electrode, a photosensitive layer, and a second electrode. The first electrode of the photosensitive device PD is connected to the sensing power line VSE, and the second electrode of the photosensitive device PD is connected to the first electrode of the eighth transistor T8.

[0076] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, respectively; the second node N2 is connected to the second electrode of the first transistor T1, the second electrode of the second transistor T2, the first electrode of the third transistor T3, and the second electrode of the fifth transistor T5, respectively; the third node N3 is connected to the second electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the first electrode of the sixth transistor T6, respectively; and the fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively.

[0077] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , and a second end of the storage capacitor C is connected to the first power line VDD.

[0078] In an exemplary embodiment, the first transistor T1 may be referred to as a first initialization transistor, a gate electrode of the first transistor T1 is connected to the second scan signal line S2 , a first electrode of the first transistor T1 is connected to the first initial signal line INIT1 , and a second electrode of the first transistor T1 is connected to the second node N2 .

[0079] In an exemplary embodiment, the second transistor T2 may be referred to as a compensation transistor, a gate electrode of the second transistor T2 is connected to the third scan signal line S3 , a first electrode of the second transistor T2 is connected to the first node N1 , and a second electrode of the second transistor T2 is connected to the second node N2 .

[0080] In an exemplary embodiment, the third transistor T3 may be referred to as a driving transistor, a gate electrode of the third transistor T3 is connected to the first node N1 , a first electrode of the third transistor T3 is connected to the second node N2 , and a second electrode of the third transistor T3 is connected to the third node N3 .

[0081] In an exemplary embodiment, the fourth transistor T4 may be referred to as a data writing transistor, a gate electrode of the fourth transistor T4 is connected to the first scan signal line S1 , a first electrode of the fourth transistor T4 is connected to the data signal line D, and a second electrode of the fourth transistor T4 is connected to the third node N3 .

[0082] In an exemplary embodiment, the fifth transistor T5 may be referred to as a first light emission control transistor, a gate electrode of the fifth transistor T5 is connected to the light emission signal line EM, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2.

[0083] In an exemplary embodiment, the sixth transistor T6 may be referred to as a second light emission control transistor, a gate electrode of the sixth transistor T6 is connected to the light emission signal line EM, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0084] In an exemplary embodiment, the seventh transistor T7 may be referred to as a second initialization transistor, a gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0085] In an exemplary embodiment, a gate electrode of the eighth transistor T8 is connected to the emission signal line EM, a first electrode of the eighth transistor T8 is connected to the second electrode of the photosensitive device PD, and a second electrode of the eighth transistor T8 is connected to the sensing signal line REF.

[0086] In an exemplary embodiment, a first electrode of the light-emitting device EL is connected to the fourth node N4, and a second electrode of the light-emitting device EL is connected to the second power supply line VSS. The light-emitting device EL may be an OLED including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0087] In an exemplary embodiment, the signals of the first power line VDD and the sensing power line VSE are continuously provided high level signals, and the signal of the second power line VSS is continuously provided low level signal.

[0088] In an exemplary embodiment, the first to seventh transistors T1 to T7 in the pixel driving circuit may be P-type transistors or N-type transistors. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.

[0089] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 in the pixel driving circuit may be low-temperature polysilicon transistors, or oxide transistors, or both. The active layer of the low-temperature polysilicon transistor is made of low-temperature polysilicon (LTPS), while the active layer of the oxide transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating low-temperature polysilicon transistors and oxide transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can leverage the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0090] As shown in Figure 4, in this exemplary embodiment, the second transistor T2 in the pixel driving circuit and the eighth transistor T8 in the sensing circuit can be oxide transistors (N-type transistors), and the first transistor T1 and the third transistor T3 to the seventh transistor T7 can be low-temperature polysilicon transistors (P-type transistors).

[0091] FIG5 is a driving timing diagram of the unit control circuit shown in FIG4 , wherein the second transistor T2 and the eighth transistor T8 are N-type oxide transistors, and the first transistor T1 and the third transistor T3 to the seventh transistor T7 are P-type low-temperature polysilicon transistors. As shown in FIG5 , the operation process of the pixel driving circuit in the unit control circuit may include:

[0092] The first phase A1 is called the reset phase. The signal on the second scan signal line S2 is a low-level signal, and the signals on the first scan signal line S1, the third scan signal line S3, and the light-emitting signal line EM are high-level signals. The first transistor T1, the second transistor T2, and the seventh transistor T7 are turned on, and the other transistors are turned off.

[0093] The first transistor T1 is turned on, causing the first initial signal of the first initial signal line INIT1 to be supplied to the second node N2, thereby initializing (resetting) the second node N2. The second transistor T2 is turned on, causing electrical conduction between the first node N1 and the second node N2. The first initial signal initializes (resets) the first node N1, clearing the existing charge in the storage capacitor. The seventh transistor T7 is turned on, causing the second initial signal of the second initial signal line INIT2 to be supplied to the fourth node N4, thereby initializing (resetting) the first electrode of the light-emitting device EL, thereby clearing the existing charge in the first electrode of the light-emitting device EL.

[0094] The second phase A2 is called the data writing phase. The signal on the first scanning signal line S1 is a low-level signal, and the signals on the second scanning signal line S2, the third scanning signal line S3, and the light-emitting signal line EM are high-level signals. The second transistor T2 and the fourth transistor T4 are turned on, and the other transistors (except the third transistor T3) are turned off.

[0095] Since the first node N1 is at a low level, the third transistor T3 is continuously turned on during this phase. The fourth transistor T4 is turned on, causing the data signal of the data signal line D to be provided to the first node N1 through the third node N3 and the turned-on third transistor T3. The difference between the data voltage of the data signal and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The second transistor T2 is turned on, connecting the first node N1 and the second node N2. The potential of the second node N2 is the same as that of the first node N1.

[0096] The third phase A3 is called the second node N2 reset phase. The signals of the second scan signal line S2 and the third scan signal line S3 are low-level signals, the signals of the first scan signal line S1 and the light-emitting signal line EM are high-level signals, the first transistor T1 and the seventh transistor T7 are turned on, and the other transistors (except the third transistor T3) are turned off.

[0097] The first transistor T1 is turned on, causing the first initial signal of the first initial signal line INIT1 to be supplied to the second node N2, thereby resetting the second node N2. Since the third transistor T3 is continuously turned on during this stage, the first initial signal is supplied to the third node N3, thereby resetting the third node N3. The seventh transistor T7 is turned on, causing the second initial signal of the second initial signal line INIT2 to be supplied to the fourth node N4, thereby initializing the first electrode of the light-emitting device EL. Resetting the second node N2, the third node N3, and the fourth node N4 in this stage can eliminate and improve the hysteresis deviation caused by the grayscale difference between adjacent pixels, reduce the hysteresis deviation, and periodically reset the OLED anode to improve low-frequency flicker.

[0098] In the fourth phase A4, referred to as the light-emitting phase, the signals on the third scan signal line S3 and the light-emitting signal line EM are low-level signals, the signals on the first scan signal line S1 and the second scan signal line S2 are high-level signals, the fifth transistor T5 and the sixth transistor T6 are turned on, and the other transistors (except the third transistor T3) are turned off.

[0099] The fifth transistor T5 and the sixth transistor T6 are turned on so that the first power voltage output from the first power line VDD provides a driving current to the first electrode of the light emitting device EL through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the light emitting device EL to emit light.

[0100] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. The driving current of the third transistor T3 of each pixel driving circuit is not affected by the threshold voltage of the third transistor T3.

[0101] As shown in FIG5 , the operation process of the sensing circuit in the unit control circuit may include:

[0102] The first sensing period includes the first stage A1 (reset stage), the second stage A2 (data writing stage) and the third stage A3 (second node N2 reset stage) of the pixel driving circuit. The signal of the light-emitting signal line EM is a high-level signal, the eighth transistor T8 is turned on, and the sensing circuit generates a photosensitive current according to the connected photosensitive device PD.

[0103] The second sensing period includes the fourth phase A4 (light emitting phase) of the pixel driving circuit, the signal of the light emitting signal line EM is a low level signal, the eighth transistor T8 is disconnected, and the sensing circuit does not work.

[0104] In an exemplary embodiment, the sensing circuit and the photosensitive device PD can be used for fingerprint identification and can be called a fingerprint sensor. The eighth transistor T8 can be called a switching transistor of the fingerprint sensor. The light-emitting signal line EM that provides a light-emitting control signal to the pixel driving circuit can be multiplexed as a control signal of the fingerprint sensor.

[0105] In an exemplary embodiment, the cell control circuit of the present disclosure includes two functional components. Transistors T1 through T7 serve as display switching transistors, while transistor T8 serves as a fingerprint recognition switching transistor. These two functional components share a gate driver circuit (GOA) that outputs emission control signals. The emission signal line EM serves as both a display emission control signal and a fingerprint recognition control signal. When the emission signal line EM is high, the pixel driver circuit resets and writes data, and the fingerprint sensor scans and samples fingerprint signals. When the emission signal line EM is low, the pixel driver circuit outputs a drive current, and the fingerprint sensor stops sampling.

[0106] In an exemplary embodiment, the fingerprint sensor provides two DC signals: a light-sensing power supply signal (Vsensor) and a light-sensing signal (Vref). The light-sensing power supply signal can range from 1V to 10V, while the light-sensing signal reference voltage can be preset to approximately 0.2V. For a cell row, when the luminescence signal line EM outputs a high-level signal, the pixel driver circuit for that cell row resets and writes data. The eighth transistor T8 in the sensor circuit turns on, and light emitted by the light-emitting cells reflects off the peaks and valleys of the fingerprint wave and enters the fingerprint sensor within the circuit unit, sampling the light-sensing current signal controlled by that cell row. The luminescence signal line EM sequentially scans each cell row, generating different light-sensing currents at fingerprint sensors at different locations on the display substrate. These currents are transmitted via the sensor signal line to an external processing unit (such as an analog-to-digital converter (ADC) unit), effectively determining fingerprint distribution and enabling fingerprint recognition. Because the fingerprint sensor is located within the circuit unit, the pitch between the fingerprint sensor and the pixel driver circuit is the same, resulting in high fingerprint sensing accuracy. Since the scanning width of the gate drive circuit that outputs the luminous signal is adjustable, the fingerprint sampling time and period can be flexibly adjusted, effectively improving the sampling accuracy.

[0107] FIG6 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the display substrate may include a plurality of circuit units, which may form a plurality of unit rows and a plurality of unit columns. The plurality of circuit units in each unit row are sequentially arranged along a first direction X, and the plurality of unit rows are sequentially arranged along a second direction Y, forming an array of circuit units arranged in an array, where the first direction X intersects the second direction Y. As shown in FIG6 , at least one circuit unit may include a unit control circuit, which may include at least a pixel drive circuit, a sensor circuit, and a photosensitive device. The sensor circuit is connected to the photosensitive device, the pixel drive circuit is configured to output a drive current to the connected light-emitting device, and the sensor circuit is configured to generate a photosensitive current based on the connected photosensitive device.

[0108] In an exemplary embodiment, the pixel driving circuit of at least one circuit unit may include at least a storage capacitor and multiple transistors. The storage capacitor may include a stacked first and second plates. The multiple transistors may include a first transistor T1 serving as a first initialization transistor, a second transistor T2 serving as a compensation transistor, a third transistor T3 serving as a drive transistor, a fourth transistor T4 serving as a data write transistor, a fifth transistor T5 serving as a first emission control transistor, a sixth transistor T6 serving as a second emission control transistor, and a seventh transistor T7 serving as a second initialization transistor. The sensing circuit of at least one circuit unit may include an eighth transistor T8 serving as a sensing control transistor. The second transistor T2 and the eighth transistor T8 are oxide transistors, and the first transistor T1, the third transistor T3, the third transistor T4, the fourth transistor T5, the fifth transistor T5, the fifth transistor T6, the sixth transistor T6, the sixth transistor T6, the seventh transistor T7, the seventh transistor T7, the eighth transistor T7, and the eighth transistor T8 are low-temperature polysilicon transistors.

[0109] In an exemplary embodiment, a gate electrode of the first transistor T1 is connected to the second scan signal line 22 , a first electrode of the first transistor T1 is connected to the first initial signal line 31 , and a second electrode of the first transistor T1 is connected to a first electrode of the third transistor T3 .

[0110] In an exemplary embodiment, a gate electrode of the second transistor T2 is connected to the third scan signal line 23 , a first electrode of the second transistor T2 is connected to a gate electrode of the third transistor T3 , and a second electrode of the second transistor T2 is connected to a first electrode of the third transistor T3 .

[0111] In an exemplary embodiment, the gate electrode of the third transistor T3 may serve as a first plate of the storage capacitor, and the first electrode of the third transistor T3 is connected to the second electrode of the first transistor T1 and the second electrode of the second transistor T2 .

[0112] In an exemplary embodiment, a gate electrode of the fourth transistor T4 is connected to the first scan signal line 21 , a first electrode of the fourth transistor T4 is connected to the data signal line 91 , and a second electrode of the fourth transistor T4 is connected to the second electrode of the third transistor T3 .

[0113] In an exemplary embodiment, a gate electrode of the fifth transistor T5 is connected to the light emitting signal line 24 , a first electrode of the fifth transistor T5 is connected to the first power line 92 , and a second electrode of the fifth transistor T5 is connected to the first electrode of the third transistor T3 .

[0114] In an exemplary embodiment, a gate electrode of the sixth transistor T6 is connected to the light emitting signal line 24 , a first electrode of the sixth transistor T6 is connected to the second electrode of the third transistor T3 , and a second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7 .

[0115] In an exemplary embodiment, a gate electrode of the seventh transistor T7 is connected to the second scan signal line 22 , a first electrode of the seventh transistor T7 is connected to the second initial signal line 32 , and a second electrode of the seventh transistor T7 is connected to the second electrode of the sixth transistor T6 .

[0116] In an exemplary embodiment, a gate electrode of the eighth transistor T8 is connected to the light emitting signal line 24 , a first electrode of the eighth transistor T8 is connected to the photosensitive device, and a second electrode of the eighth transistor T8 is connected to the sensing signal line 95 .

[0117] In an exemplary embodiment, the photosensitive device 40 of at least one circuit unit may include a photosensitive first electrode, a photosensitive second electrode, and a photosensitive layer arranged between the first photosensitive electrode and the second photosensitive electrode, the photosensitive first electrode is connected to the sensing power line 94, and the photosensitive second electrode is connected to the first electrode of the eighth transistor T8.

[0118] In an exemplary embodiment, the shapes of the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the light-emitting signal line 24, the first initial signal line 31, and the second initial signal line 32 can be straight lines or broken lines with the main parts extending along the first direction X, and the shapes of the data signal line 91, the first power line 92, the sensing power line 94, and the sensing signal line 95 can be straight lines or broken lines with the main parts extending along the second direction Y.

[0119] In this disclosure, "A extends along direction B" means that A can include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In the following description, "A extends along direction B" means "the main portion of A extends along direction B."

[0120] In an exemplary embodiment, at least one circuit unit may further include a sensing power connection line 74 extending from the main body portion along the first direction X, and the sensing power connection line 74 extending from the main body portion along the first direction X and the sensing power line 94 extending from the main body portion along the second direction Y are interconnected to form a network connection structure for transmitting a photosensitive power signal on the display substrate.

[0121] In an exemplary embodiment, at least one circuit unit may further include a first initial connection line 33 extending from the main body portion along the second direction Y, and the first initial signal line 31 extending from the main body portion along the first direction X is connected to the first initial connection line 33 extending from the main body portion along the second direction Y, forming a network connection structure for transmitting the first initial signal on the display substrate.

[0122] In an exemplary embodiment, at least one circuit unit may further include a second initial connection line 34 extending from the main body portion along the second direction Y, and the second initial signal line 32 extending from the main body portion along the first direction X is connected to the second initial connection line 34 extending from the main body portion along the second direction Y, forming a network connection structure for transmitting the second initial signal on the display substrate.

[0123] In an exemplary embodiment, in at least one circuit unit, the fifth transistor T5 and the sixth transistor T6 of the pixel driving circuit and the eighth transistor T8 of the sensing circuit are connected to the same light emitting signal line 24, and the same light emitting signal line 24 controls the conduction and disconnection of the fifth transistor T5, the sixth transistor T6 and the eighth transistor T8.

[0124] In an exemplary embodiment, when the light-emitting signal line 24 outputs a first signal, the fifth and sixth transistors T5 and T6 are turned off, the eighth transistor T8 is turned on, and the sensing circuit generates a light-sensing current. When the light-emitting signal line 24 outputs a second signal, the eighth transistor T8 is turned off, the fifth and sixth transistors T5 and T6 are turned on, and the pixel driving circuit outputs a driving current. For example, during a first sensing period, the light-emitting signal line 24 controls the sensing circuit to generate a light-sensing current; during a second sensing period, the light-emitting signal line 24 controls the pixel driving circuit to output a driving current.

[0125] In an exemplary embodiment, the fifth transistor T5 and the sixth transistor T6 are transistors of one type, and the eighth transistor T8 is a transistor of another type. For example, the fifth transistor T5 and the sixth transistor T6 may be polysilicon transistors (P-type transistors), and the eighth transistor T8 may be an oxide transistor (N-type transistor). For another example, the fifth transistor T5 and the sixth transistor T6 may be oxide transistors (N-type transistors), and the eighth transistor T8 may be a polysilicon transistor (P-type transistor).

[0126] FIG7 is a schematic diagram of the structure of the sensing circuit and photosensitive device in FIG6 . As shown in FIG6 and FIG7 , in an exemplary embodiment, the fifth transistor T5 may include at least a fifth gate electrode, and the sixth transistor T6 may include at least a sixth gate electrode. The fifth and sixth gate electrodes may serve as the light-emission control gate electrodes of the present disclosure. The eighth transistor T8 may include at least an eighth active layer 18, an eighth bottom gate electrode 36, and an eighth top gate electrode 37. The eighth bottom gate electrode 36 and eighth top gate electrode 37 may serve as the sensing control gate electrodes of the present disclosure. The fifth and sixth gate electrodes may be directly connected to the light-emission signal line 24, while the eighth bottom gate electrode 36 and eighth top gate electrode 37 may be connected to the light-emission signal line 24 via the light-emission connection electrode 64.

[0127] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include multiple conductive layers, the fifth gate electrode, the sixth gate electrode and the light-emitting signal line 24 may be arranged in the same conductive layer, the light-emitting signal line 24 and the eighth bottom gate electrode 36 and the eighth top gate electrode 37 may be arranged in different conductive layers, and the light-emitting connection electrode 64 and the eighth bottom gate electrode 36 and the eighth top gate electrode 37 may be arranged in different conductive layers.

[0128] In an exemplary embodiment, the plurality of conductive layers may include at least a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer, sequentially arranged in a direction away from the substrate. The fifth gate electrode, the sixth gate electrode, and the light-emitting signal line 24 may be disposed in the first conductive layer, and the fifth gate electrode, the sixth gate electrode, and the light-emitting signal line 24 may be interconnected as an integral structure. The eighth bottom gate electrode 36 may be disposed in the second conductive layer, the eighth top gate electrode 37 may be disposed in the third conductive layer, and the light-emitting connection electrode 64 may be disposed in the fourth conductive layer. The light-emitting connection electrode 64 is connected to the light-emitting signal line 24, the eighth bottom gate electrode 36, and the eighth top gate electrode 37 through vias.

[0129] In an exemplary embodiment, the photosensitive device 40 may include at least a photosensitive first electrode 41, a photosensitive second electrode 42, and a photosensitive layer 43 arranged between the first photosensitive electrode 41 and the second photosensitive electrode 42. The photosensitive first electrode 41, the photosensitive layer 43 and the photosensitive second electrode 42 may be arranged along a first direction X. The photosensitive first electrode 41 may be arranged on a side of the photosensitive layer 43 in the opposite direction of the first direction X, and the photosensitive second electrode 42 may be arranged on a side of the photosensitive layer 43 in the first direction X to form a laterally structured photodiode.

[0130] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include a first semiconductor layer and a second semiconductor layer arranged on a side of the first semiconductor layer away from the substrate, the photosensitive first electrode 41 and the photosensitive second electrode 42 may be formed by conducting the first semiconductor layer, the photosensitive layer 43 may be formed by doping the first semiconductor layer, and the eighth active layer 18 serving as a sensing active layer may be arranged in the second semiconductor layer.

[0131] In an exemplary embodiment, at least one circuit unit may further include an eleventh connecting electrode 61 and a thirty-first connecting electrode 81 , and the first photosensitive electrode 41 may be connected to the sensing power line 94 through the eleventh connecting electrode 61 and the thirty-first connecting electrode 81 .

[0132] In an exemplary embodiment, at least one circuit unit may further include a twelfth connection electrode 62 , and the second photosensitive electrode 42 may be connected to the first region of the eighth active layer 18 through the twelfth connection electrode 62 .

[0133] In an exemplary embodiment, at least one circuit unit may further include a thirteenth connection electrode 63 and a thirty-second connection electrode 82 , and the second region of the eighth active layer 18 may be connected to the sensing signal line 95 through the thirteenth connection electrode 63 and the thirty-second connection electrode 82 .

[0134] In an exemplary embodiment, the eleventh connecting electrode 61 , the twelfth connecting electrode 62 , and the thirteenth connecting electrode 63 may be disposed in the same layer as the light emitting connecting electrode 64 and may be simultaneously formed through the same patterning process.

[0135] In an exemplary embodiment, the display substrate may further include a fifth conductive layer disposed on a side of the fourth conductive layer away from the substrate, and a sixth conductive layer disposed on a side of the fifth conductive layer away from the substrate, in a direction perpendicular to the display substrate. The thirty-first connecting electrode 81 and the thirty-second connecting electrode 82 may be disposed in the fifth conductive layer, with the thirty-first connecting electrode 81 connected to the eleventh connecting electrode 61 via a via, and the thirty-second connecting electrode 82 connected to the thirteenth connecting electrode 63 via a via. A sensing power line 94 and a sensing signal line 95 may be disposed in the sixth conductive layer, with the sensing power line 94 connected to the thirty-first connecting electrode 81 via a via, and the sensing signal line 95 connected to the thirty-second connecting electrode 82 via a via.

[0136] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes the deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes for metal materials, inorganic materials or transparent conductive materials, and includes the coating of organic materials, mask exposure and development and other processes for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0137] In an exemplary embodiment, taking four circuit units (two unit rows and two unit columns) as an example, the preparation process of the display substrate may include the following operations.

[0138] (1) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on a substrate, patterning the first semiconductor film through a patterning process to form a first insulating layer disposed on the substrate, and a first semiconductor layer pattern disposed on the first insulating layer, as shown in FIG. 8 .

[0139] In an exemplary embodiment, the first semiconductor layer pattern of each circuit unit may include at least the first active layer 11 of the first transistor T1, the third active layer 13 of the third transistor T3 to the seventh active layer 17 of the seventh transistor T7, and the third active layer 13 to the seventh active layer 17 are an integral structure connected to each other.

[0140] In an exemplary embodiment, in the first direction X, the fourth active layer 14 and the sixth active layer 16 may be located on one side of the third active layer 13 in the present circuit unit, and the first active layer 11 and the fifth active layer 15 may be located on the other side of the third active layer 13 in the present circuit unit. In the second direction Y, the fifth active layer 15, the sixth active layer 16, and the seventh active layer 17 may be located on one side of the third active layer 13 in the present circuit unit in the second direction Y, and the first active layer 11 and the fourth active layer 14 may be located on a side of the third active layer 13 in the present circuit unit in the opposite direction to the second direction Y.

[0141] In an exemplary embodiment, the first active layer 11 of the pixel driving circuit in this circuit unit can be disposed in the circuit unit of the previous unit row and located on one side of the seventh active layer 17 in the circuit unit of the previous unit row in the first direction X or on the side opposite to the first direction X. For example, the first active layer 11 of the pixel driving circuit in the circuit unit of the mth unit row can be disposed in the circuit unit of the m-1th unit row. For another example, the first active layer 11 of the pixel driving circuit in the circuit unit of the m+1th unit row can be disposed in the circuit unit of the mth unit row.

[0142] In an exemplary embodiment, the third active layer 13 may have an Ω shape, the first active layer 11, the fifth active layer 15, and the seventh active layer 17 may have an I shape, and the fourth active layer 14 and the sixth active layer 16 may have an L shape.

[0143] In an exemplary embodiment, the first active layer 11 and the third to seventh active layers 13 to 17 may each include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the first region 13-1 of the third active layer and the second region 15-2 of the fifth active layer are interconnected, and the first region 13-1 of the third active layer may serve as the second region 15-2 of the fifth active layer. The second region 13-2 of the third active layer, the second region 14-2 of the fourth active layer, and the first region 16-1 of the sixth active layer are interconnected, and the second region 13-2 of the third active layer may serve as both the second region 14-2 of the fourth active layer and the first region 16-1 of the sixth active layer. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer are interconnected, and the second region 16-2 of the sixth active layer may serve as the second region 17-2 of the seventh active layer. The first region 11-1 of the first active layer, the second region 11-2 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, and the first region 17-1 of the seventh active layer may be separately provided.

[0144] In an exemplary embodiment, the first semiconductor layer may further include a photosensitive active layer 19. The photosensitive active layer 19 may be in a block shape and may be disposed in the circuit unit of the nth unit column and located on one side of the seventh active layer 17 in the first direction X.

[0145] In an exemplary embodiment, the photosensitive active layer 19 may include a photosensitive first region 19-1, a photosensitive second region 19-2, and a photosensitive region 19-3 located between the photosensitive first region 19-1 and the photosensitive second region 19-2. The photosensitive first region 19-1 may be arranged on a side of the photosensitive region 19-3 in the opposite direction of the first direction X (the side close to the seventh active layer 17), and the photosensitive first region 19-1 is configured to be connected to an eleventh connecting electrode formed subsequently. The photosensitive second region 19-2 may be arranged on a side of the photosensitive region 19-3 in the first direction X (the side away from the seventh active layer 17), and the photosensitive second region 19-2 is configured to be connected to a twelfth connecting electrode formed subsequently.

[0146] In an exemplary embodiment, the first active layer 11 and the third active layer 13 to the seventh active layer 17 of adjacent unit columns may be mirror-symmetrical with respect to a center line, which is a straight line located between adjacent unit columns and extending along the second direction Y. For example, the first active layer 11 and the third active layer 13 to the seventh active layer 17 of the nth unit column and the (n+1)th unit column may be mirror-symmetrical with respect to the center line.

[0147] In an exemplary embodiment, the first semiconductor layer may be made of polycrystalline silicon (p-Si), meaning that the first transistor T1 and the third transistor T3 through the seventh transistor T7 are LTPS transistors. In an exemplary embodiment, patterning the first semiconductor film through a patterning process may include: first forming an amorphous silicon (a-Si) film on the first insulating film, performing a dehydrogenation treatment on the amorphous silicon film, and then crystallizing the dehydrogenated amorphous silicon film to form a polycrystalline silicon film. Subsequently, patterning the polycrystalline silicon film to form a first semiconductor layer pattern.

[0148] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG9A and FIG9B , FIG9B being a planar schematic diagram of the first conductive layer in FIG9A . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0149] In an exemplary embodiment, the first conductive layer pattern of each circuit unit includes at least a first scan signal line 21 , a second scan signal line 22 , a light emitting signal line 24 , and a first plate 25 of a storage capacitor.

[0150] In an exemplary embodiment, the first electrode plate 25 may be rectangular, with chamfered corners. The orthographic projection of the first electrode plate 25 on the substrate at least partially overlaps the orthographic projection of the third active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode plate 25 may serve as both a plate of the storage capacitor and a gate electrode of the third transistor T3.

[0151] In an exemplary embodiment, the shape of the first scanning signal line 21 can be a straight line or a broken line with the main portion extending along the first direction X. The first scanning signal line 21 can be located on the side of the first electrode 25 in the opposite direction of the second direction Y. The area where the first scanning signal line 21 overlaps with the fourth active layer serves as the gate electrode of the fourth transistor T4.

[0152] In an exemplary embodiment, the shape of the second scanning signal line 22 can be a straight line or a broken line with the main portion extending along the first direction X. The second scanning signal line 22 can be located on one side of the first electrode 25 in the second direction Y. The area where the second scanning signal line 22 overlaps with the first active layer serves as the gate electrode of the first transistor T1, and the area where the second scanning signal line 22 overlaps with the seventh active layer serves as the gate electrode of the seventh transistor T7.

[0153] In an exemplary embodiment, since the first active layer of the present circuit unit is arranged in the previous unit row, in the pixel driving circuit of the present circuit unit, the first transistor T1 is controlled by the second scanning signal line 22 of the previous unit row, and the seventh transistor T7 is controlled by the second scanning signal line 22 of the present unit row, that is, the second scanning signal line 22 of the present unit row controls the conduction and disconnection of the seventh transistor T7 of the pixel driving circuit in the circuit unit of the present unit row, and controls the conduction and disconnection of the first transistor T1 of the pixel driving circuit in the circuit unit of the next unit row.

[0154] In an exemplary embodiment, the shape of the light-emitting signal line 24 can be a straight line or a broken line with the main portion extending along the first direction X. The light-emitting signal line 24 can be located between the first electrode 25 and the second scanning signal line 22. The area where the light-emitting signal line 24 overlaps with the fifth active layer serves as the gate electrode of the fifth transistor T5, and the area where the light-emitting signal line 24 overlaps with the sixth active layer serves as the gate electrode of the sixth transistor T6.

[0155] In an exemplary embodiment, the light-emitting signal line 24 may be provided with a light-emitting connection block 24-1. The light-emitting connection block 24-1 may be in a block shape (e.g., rectangular) and may be provided on a side of the light-emitting signal line 24 away from the first electrode plate 25 and connected to the light-emitting signal line 24. The light-emitting connection block 24-1 is configured to be connected to a light-emitting connection electrode formed subsequently.

[0156] In an exemplary embodiment, the lighting signal line 24 and the lighting connection block 24 - 1 may be an integral structure connected to each other.

[0157] In an exemplary embodiment, the first scanning signal line 21 and the light-emitting signal line 24 can be designed with non-equal widths, and the widths of the first scanning signal line 21 and the light-emitting signal line 24 are the dimensions in the second direction Y, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines. This is not limited in the present disclosure.

[0158] In an exemplary embodiment, the first scan signal line 21 may include an area overlapping with the first semiconductor layer and an area not overlapping with the first semiconductor layer, and the width of the first scan signal line 21 in the area overlapping with the first semiconductor layer may be greater than the width of the first scan signal line 21 in the area not overlapping with the first semiconductor layer.

[0159] In an exemplary embodiment, the light emitting signal line 24 may include an area overlapping with the first semiconductor layer and an area not overlapping with the first semiconductor layer, and the width of the first scanning signal line 21 in the area overlapping with the first semiconductor layer may be greater than the width of the first scanning signal line 21 in the area not overlapping with the first semiconductor layer.

[0160] In an exemplary embodiment, the first conductive layer may further include a light-shielding electrode 27 .

[0161] In an exemplary embodiment, the photosensitive shielding electrode 27 may be in the shape of a strip with a main portion extending along the second direction Y. The electrode may be disposed in the circuit unit of the nth unit column and located on one side of the seventh active layer 17 in the first direction X. The orthographic projection of the photosensitive shielding electrode 27 on the substrate at least partially overlaps with the orthographic projection of the photosensitive region 19 - 3 of the photosensitive active layer 19 on the substrate.

[0162] In an exemplary embodiment, the first conductive layers of adjacent cell columns (excluding the light-shielding electrode 27) may be mirror-symmetrical with respect to the center line. For example, the first conductive layer of the nth cell column and the first conductive layer of the (n+1)th cell column may be mirror-symmetrical with respect to the center line.

[0163] (3) Forming a photosensitive layer of a photosensitive device. In an exemplary embodiment, forming a photosensitive layer of a photosensitive device may include: on a substrate on which the aforementioned pattern is formed, first using a first conductive layer pattern as a shield to perform a conductorization process, and the first semiconductor layer not shielded by the first conductive layer is conductorized. Among them, the first transistor T1, the first region and the second region of the third transistor T3 to the seventh active layer are conductorized, and the first photosensitive region 19-1 and the second photosensitive region 19-2 of the photosensitive active layer 19 are conductorized to form the first photosensitive electrode 41 and the second photosensitive electrode 42 of the photosensitive device. The first semiconductor layer shielded by the first conductive layer forms the channel region of the first transistor T1, the third transistor T3 to the seventh transistor T7. Since the photosensitive shielding electrode 27 shields the photosensitive region 19-3, the photosensitive region 19-3 is not conductorized. Subsequently, photoresist is coated, and a photoresist pattern is formed through masking, exposure and development. The photoresist pattern exposes the photosensitive blocking electrode 27. The photosensitive blocking electrode 27 is first etched away through an etching process to expose the photosensitive area 19-3, and then the photosensitive area 19-3 is doped to form a photosensitive layer 43 of the photosensitive device, as shown in Figure 10.

[0164] In an exemplary embodiment, the photosensitive device 40 may include a photosensitive first electrode 41, a photosensitive second electrode 42 and a photosensitive layer 43. The photosensitive first electrode 41, the photosensitive layer 43 and the photosensitive second electrode 42 may be arranged along a first direction X. The photosensitive first electrode 41 may be arranged on a side of the photosensitive layer 43 in the opposite direction of the first direction X, and the photosensitive second electrode 42 may be arranged on a side of the photosensitive layer 43 in the first direction X to form a laterally structured photodiode.

[0165] (4) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate having the aforementioned pattern formed thereon, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer and the I-type layer 82, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIG11A and FIG11B , where FIG11B is a plan view schematic diagram of the second conductive layer in FIG11A . In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0166] In an exemplary embodiment, the second conductive layer pattern of each circuit unit includes at least: a second plate 26 of the storage capacitor, a first initial signal line 31 , and a shielding line 35 .

[0167] In an exemplary embodiment, the outline of the second electrode plate 26 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate 26 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 25 on the substrate. The second electrode plate 26 can serve as another electrode plate of the storage capacitor, and the first electrode plate 25 and the second electrode plate 26 constitute the storage capacitor of the pixel driving circuit.

[0168] In an exemplary embodiment, an opening 28 is provided on the second electrode plate 26. Opening 28 can be rectangular and located in the middle of the second electrode plate 26, forming an annular structure. Opening 28 exposes the third insulating layer covering the first electrode plate 25, and the orthographic projection of the first electrode plate 25 on the substrate includes the orthographic projection of opening 28 on the substrate. In an exemplary embodiment, opening 28 is configured to accommodate a tenth via hole to be formed later. The tenth via hole is located within opening 28 and exposes the first electrode plate 25, allowing a first connecting electrode to be formed later to be connected to the first electrode plate 25.

[0169] In an exemplary embodiment, the second electrode plate 26 may be provided with a plate connecting bar 29. The plate connecting bar 29 may be in the shape of a bar extending along the first direction X and may be provided on one side of the second electrode plate 26 in the first direction X or on a side opposite to the first direction X. The first end of the plate connecting bar 29 is connected to the second electrode plate 26 in the current single-circuit cell, and the second end of the plate connecting bar 29 is connected to the second electrode plate 26 in the adjacent single-circuit cell in the first direction X, thereby interconnecting the second electrode plates 26 in adjacent circuit cells in a cell row.

[0170] In an exemplary embodiment, the second electrode plates 26 and the electrode connecting bars 29 in one cell row may be an integral structure connected to each other.

[0171] In an exemplary embodiment, since the second electrode plate 26 in each circuit unit is connected to the first power line formed subsequently, by forming the second electrodes 26 of adjacent circuit units into an integrated structure that is interconnected, the second electrodes of the integrated structure can be reused as power signal lines, which can ensure that the multiple second electrodes in a unit row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0172] In an exemplary embodiment, the shape of the first initial signal line 31 can be a straight line or a broken line with the main portion extending along the first direction X. The first initial signal line 31 can be located on one side of the second electrode 26 in the second direction Y. The first initial signal line 31 is configured to be connected to the first region of the first active layer through a sixth connecting electrode formed subsequently.

[0173] In an exemplary embodiment, since the first active layer of the present circuit unit is arranged in the previous unit row, the first region of the first active layer in the pixel driving circuit of the present circuit unit is connected to the first initial signal line 31 of the previous unit row, and the first initial signal line 31 of the present unit row is connected to the first region of the first active layer of the pixel driving circuit in the next unit row circuit unit.

[0174] In an exemplary embodiment, the shape of the shielding line 35 can be a straight line or a broken line with the main part extending along the first direction X, and can be located between the first scanning signal line 21 and the second electrode 26. The shielding line 35 is configured as a shielding layer of the second transistor T2, shielding the channel region of the second transistor T2, ensuring the electrical performance of the oxide second transistor T2, and at the same time being configured as the bottom gate electrode of the second transistor T2.

[0175] In exemplary embodiments, the second conductive layer pattern may further include an eighth bottom gate electrode 36 .

[0176] In an exemplary embodiment, the eighth bottom-gate electrode 36 may be in the shape of a strip extending along the second direction Y. In the first direction X, the eighth bottom-gate electrode 36 may be located on one side of the photosensitive device 40 in the first direction X. In the second direction Y, the eighth bottom-gate electrode 36 may be located between the second scanning signal line 22 and the first initial signal line 31. In an exemplary embodiment, the eighth bottom-gate electrode 36 is configured to serve as the bottom gate electrode of the eighth transistor T8 and also as a shielding layer for the eighth transistor T8, shielding the channel region of the second transistor T8 and ensuring the electrical performance of the oxide eighth transistor T8.

[0177] In an exemplary embodiment, the second conductive layers of adjacent cell columns (excluding the eighth bottom gate electrode 36) may be mirror-symmetrical with respect to the center line. For example, the second conductive layer of the nth cell column and the second conductive layer of the (n+1)th cell column may be mirror-symmetrical with respect to the center line.

[0178] (5) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include: sequentially depositing a fourth insulating film and a second semiconductor film on the substrate having the aforementioned pattern formed thereon, patterning the second semiconductor film through a patterning process to form a fourth insulating layer covering the substrate, and a second semiconductor layer pattern disposed on the fourth insulating layer, as shown in FIG12A and FIG12B , where FIG12B is a plan view schematic diagram of the second semiconductor layer in FIG12A .

[0179] In an exemplary embodiment, the second semiconductor layer pattern of each circuit unit includes at least the second active layer 12 of the second transistor T2 .

[0180] In an exemplary embodiment, the second active layer 12 can be in the shape of a strip extending along the second direction Y, and can be located on the side of the first scanning signal line 21 close to the second electrode plate 26, and the orthographic projection of the second active layer 12 on the substrate at least partially overlaps with the orthographic projection of the shielding line 35 on the substrate.

[0181] In an exemplary embodiment, the second active layer 12 may include a first region, a second region, and a channel region between the first region and the second region. The first region 12-1 of the second active layer may be located on a side of the shielding line 35 away from the first scan signal line 21, and the second region 12-2 of the second active layer may be located on a side of the shielding line 35 close to the first scan signal line 21.

[0182] In exemplary embodiments, the second semiconductor layer pattern may further include an eighth active layer 18 of the eighth transistor T8 .

[0183] In an exemplary embodiment, the shape of the eighth active layer 18 can be a strip shape extending along the first direction X, and can be located between the second scan signal line 22 and the first initial signal line 31, and the orthographic projection of the eighth active layer 18 on the substrate at least partially overlaps with the orthographic projection of the eighth bottom gate electrode 36 on the substrate.

[0184] In an exemplary embodiment, the eighth active layer 18 may include a first region, a second region, and a channel region between the first region and the second region. The first region 18-1 of the eighth active layer 18 may be located on a side of the eighth bottom gate electrode 36 close to the photosensitive device 40, and the second region 18-2 of the eighth active layer 18 may be located on a side of the eighth bottom gate electrode 36 away from the photosensitive device 40.

[0185] In an exemplary embodiment, the second active layers of adjacent cell columns may be mirror-symmetrical with respect to the center line. For example, the second active layer of the nth cell column and the second active layer of the (n+1)th cell column may be mirror-symmetrical with respect to the center line.

[0186] In an exemplary embodiment, the second semiconductor layer may be made of oxide, that is, the second transistor T2 and the eighth transistor T8 are oxide transistors. In an exemplary embodiment, the second semiconductor thin film may be made of indium gallium zinc oxide (IGZO), which has higher electron mobility than amorphous silicon.

[0187] (6) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: sequentially depositing a fifth insulating film and a third conductive film on the substrate having the aforementioned pattern formed thereon, patterning the third conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer, and a third conductive layer pattern disposed on the fifth insulating layer, as shown in FIG13A and FIG13B , where FIG13B is a plan view schematic diagram of the third conductive layer in FIG13A . In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0188] In an exemplary embodiment, the third conductive layer pattern of each circuit unit includes at least a third scan signal line 23 and a second preliminary signal line 32 .

[0189] In an exemplary embodiment, the shape of the third scan signal line 23 can be a straight line or a broken line with the main portion extending along the first direction X, and can be located between the first scan signal line 21 and the second electrode plate 26. The area where the third scan signal line 23 overlaps with the second active layer serves as the gate electrode of the second transistor T2.

[0190] In an exemplary embodiment, the orthographic projection of the third scan signal line 23 on the substrate at least partially overlaps with the orthographic projection of the shielding line 35 on the substrate, and the shielding line 35 and the third scan signal line 23 can be connected to the same signal source, so that the shielding line 35 can serve as the bottom gate electrode of the second transistor T2, and the third scan signal line 23 can serve as the top gate electrode of the second transistor T2, forming a second transistor T2 with a bottom gate and top gate structure.

[0191] In an exemplary embodiment, the shape of the second initial signal line 32 can be a straight line or a broken line with the main portion extending along the first direction X, and can be located on the side of the light-emitting signal line 24 away from the second electrode 26. The second initial signal line 32 is configured to be connected to the first region of the seventh active layer through a seventh connecting electrode formed subsequently.

[0192] In exemplary embodiments, the third conductive layer pattern may further include an eighth top gate electrode 37 .

[0193] In an exemplary embodiment, the eighth top gate electrode 37 may be in a strip shape extending along the second direction Y, and an orthographic projection of the eighth top gate electrode 37 on the substrate at least partially overlaps an orthographic projection of the eighth active layer 18 on the substrate.

[0194] In an exemplary embodiment, the orthographic projection of the eighth top gate electrode 37 on the substrate at least partially overlaps with the orthographic projection of the eighth bottom gate electrode 36 on the substrate, the eighth bottom gate electrode 36 is configured to serve as the bottom gate electrode of the eighth transistor T8, and the eighth top gate electrode 37 is configured to serve as the top gate electrode of the eighth transistor T8, forming the eighth transistor T8 with a bottom-gate-top-gate structure.

[0195] In an exemplary embodiment, the third scan signal line 23 and the second initial signal line 32 of adjacent unit columns may be mirror-symmetrical with respect to the center line. For example, the third scan signal line 23 and the second initial signal line 32 of the nth unit column and the n+1th unit column may be mirror-symmetrical with respect to the center line.

[0196] (7) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming the sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fifth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer, wherein the sixth insulating layer is provided with a plurality of vias, as shown in FIG. 14 .

[0197] In an exemplary embodiment, the multiple vias of each circuit unit include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12 and a thirteenth via V13.

[0198] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed sixth connecting electrode to the first region of the first active layer through the via hole.

[0199] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second region of the first active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the second region of the first active layer, and the second via hole V2 is configured to connect a subsequently formed second connecting electrode to the second region of the first active layer through the via hole.

[0200] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer in the third via hole V3 are etched away to expose the surface of the first region of the second active layer, and the third via hole V3 is configured to connect a subsequently formed first connecting electrode to the first region of the second active layer through the via hole.

[0201] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer in the fourth via hole V4 are etched away to expose the surface of the second region of the second active layer, and the fourth via hole V4 is configured to connect a subsequently formed second connecting electrode to the second region of the second active layer through the via hole.

[0202] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first area of ​​the third active layer (also the second area of ​​the fifth active layer) on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the first area of ​​the third active layer (also the second area of ​​the fifth active layer), and the fifth via hole V5 is configured to connect the subsequently formed second connecting electrode to the first area of ​​the third active layer (also the second area of ​​the fifth active layer) through the via hole.

[0203] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the first area of ​​the fourth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the first area of ​​the fourth active layer. The sixth via hole V6 is configured to connect a subsequently formed third connecting electrode to the first area of ​​the fourth active layer through the via hole.

[0204] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the first area of ​​the fifth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the first area of ​​the fifth active layer, and the seventh via hole V7 is configured to connect a subsequently formed fourth connecting electrode to the first area of ​​the fifth active layer through the via hole.

[0205] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the eighth via V8 are etched away to expose the surface of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer), and the eighth via V8 is configured to connect the subsequently formed fifth connecting electrode to the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) through the via hole.

[0206] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the ninth via hole V9 are etched away to expose the surface of the first region of the seventh active layer. The ninth via hole V9 is configured to connect the subsequently formed seventh connecting electrode to the first region of the seventh active layer through the via hole.

[0207] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the opening 28 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the tenth via hole V10 are etched away to expose the surface of the first electrode plate 25. The tenth via hole V10 is configured to connect the subsequently formed first connecting electrode to the first electrode plate 25 through the via hole.

[0208] In an exemplary embodiment, the orthographic projection of the eleventh via V11 on the substrate is within the range of the orthographic projection of the plate connecting bar 29 on the substrate. The sixth insulating layer, the fifth insulating layer, and the fourth insulating layer within the eleventh via V11 are etched away, exposing the surface of the plate connecting bar 29. The eleventh via V11 is configured to connect a subsequently formed fourth connecting electrode to the plate connecting bar 29 through the via. In an exemplary embodiment, the eleventh via V11 can be provided between two adjacent circuit units, and the two adjacent circuit units can share the same eleventh via V11.

[0209] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the first initial signal line 31 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the twelfth via hole V12 are etched away to expose the surface of the first initial signal line 31, and the twelfth via hole V12 is configured to connect the subsequently formed sixth connecting electrode to the first initial signal line 31 through the via hole.

[0210] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the second initial signal line 32 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the thirteenth via hole V13 are etched away to expose the surface of the second initial signal line 32, and the thirteenth via hole V13 is configured to connect the subsequently formed seventh connecting electrode to the second initial signal line 32 through the via hole.

[0211] In an exemplary embodiment, the sixth insulating layer may further include a twenty-first via hole V21 , a twenty-second via hole V22 , a twenty-third via hole V23 , a twenty-fourth via hole V24 , a twenty-fifth via hole V25 , a twenty-sixth via hole V26 , and a twenty-seventh via hole V27 .

[0212] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the first region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer within the twenty-first via hole V21 are etched away to expose the surface of the first region of the eighth active layer, and the twenty-first via hole V21 is configured to connect the subsequently formed twelfth connecting electrode to the first region of the eighth active layer through the via hole.

[0213] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the second region of the eighth active layer on the substrate, the sixth insulating layer and the fifth insulating layer within the twenty-second via hole V22 are etched away to expose the surface of the second region of the eighth active layer, and the twenty-second via hole V22 is configured to connect the subsequently formed thirteenth connecting electrode to the second region of the eighth active layer through the via hole.

[0214] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the eighth bottom gate electrode 36 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the twenty-third via hole V23 are etched away to expose the surface of the eighth bottom gate electrode 36, and the twenty-third via hole V23 is configured to connect the subsequently formed light-emitting connecting electrode to the eighth bottom gate electrode 36 through the via hole.

[0215] In an exemplary embodiment, the orthographic projection of the twenty-fourth via V24 on the substrate is located within the range of the orthographic projection of the eighth top gate electrode 37 on the substrate, the sixth insulating layer in the twenty-fourth via V24 is etched away to expose the surface of the eighth top gate electrode 37, and the twenty-fourth via V24 is configured to connect the subsequently formed light-emitting connecting electrode to the eighth top gate electrode 37 through the via.

[0216] In an exemplary embodiment, the orthographic projection of the twenty-fifth via hole V25 on the substrate is located within the range of the orthographic projection of the light-emitting connection block 24-1 of the light-emitting signal line 24 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the twenty-fifth via hole V25 are etched away to expose the surface of the light-emitting connection block 24-1. The twenty-fifth via hole V25 is configured to connect the subsequently formed light-emitting connection electrode to the light-emitting connection block 24-1 through the via hole.

[0217] In an exemplary embodiment, the orthographic projection of the twenty-sixth via V26 on the substrate is located within the range of the orthographic projection of the photosensitive first electrode 41 of the photosensitive device 40 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the twenty-sixth via V26 are etched away to expose the surface of the photosensitive first electrode 41, and the twenty-sixth via V26 is configured to connect the subsequently formed eleventh connecting electrode to the photosensitive first electrode 41 through the via.

[0218] In an exemplary embodiment, the orthographic projection of the twenty-seventh via V27 on the substrate is located within the range of the orthographic projection of the photosensitive second electrode 42 of the photosensitive device 40 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the twenty-seventh via V27 are etched away to expose the surface of the photosensitive second electrode 42, and the twenty-seventh via V27 is configured to connect the subsequently formed twelfth connecting electrode to the photosensitive second electrode 42 through the via.

[0219] In an exemplary embodiment, the first through thirteenth vias V1 to V13 of adjacent unit columns may be mirror-symmetrical with respect to the center line. For example, the first through thirteenth vias V1 to V13 of the nth unit column and the first through thirteenth vias V1 to V13 of the (n+1)th unit column may be mirror-symmetrical with respect to the center line.

[0220] (8) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the sixth insulating layer, as shown in FIG15A and FIG15B , where FIG15B is a plan view schematic diagram of the fourth conductive layer in FIG15A . In an exemplary embodiment, the fourth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0221] In an exemplary embodiment, the fourth conductive layer of each circuit unit includes at least first, second, third, fourth, fifth, sixth, and seventh connection electrodes 51 , 52 , 53 , 54 , 55 , 56 , and 57 .

[0222] In an exemplary embodiment, the first connection electrode 51 may be in the shape of a strip with a main portion extending along the first direction X. A first end of the first connection electrode 51 is connected to the first region of the second active layer via a third via hole V3, and a second end of the first connection electrode 51 is connected to the first electrode plate 25 via a tenth via hole V10. In an exemplary embodiment, because the first electrode plate 25 serves as the gate electrode of the third transistor T3, the first connection electrode 51 causes the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 25 of the storage capacitor to have the same potential, thereby serving as the first node N1 of the pixel driving circuit.

[0223] In an exemplary embodiment, the second connection electrode 52 may be L-shaped. A first end of the second connection electrode 52 is connected to the second region of the first active layer via a second via V2. A second end of the second connection electrode 52 is connected to the first region of the third active layer (also the second region of the fifth active layer) via a fifth via V5. The first and second ends of the second connection electrode 52 are connected to the second region of the second active layer via a fourth via V4. In an exemplary embodiment, the second connection electrode 52 causes the second electrode of the first transistor T1, the second electrode of the second transistor T2, the first electrode of the third transistor T3, and the second electrode of the fifth transistor T5 to have the same potential, serving as the second node N2 of the pixel driving circuit.

[0224] In an exemplary embodiment, the third connection electrode 53 may be in a block shape (e.g., a rectangular shape) and is connected to the first region of the fourth active layer through a sixth via hole V6. In an exemplary embodiment, the third connection electrode 53 may serve as a first electrode of the fourth transistor T4 and is configured to be connected to a subsequently formed twenty-first connection electrode.

[0225] In an exemplary embodiment, the fourth connection electrode 54 may be L-shaped. A first end of the fourth connection electrode 54 is connected to the first region of the fifth active layer via a seventh via V7, and a second end of the fourth connection electrode 54 is connected to the plate connection bar 29 via an eleventh via V11. The fourth connection electrode 54 is configured to be connected to a subsequently formed twenty-second connection electrode. In an exemplary embodiment, because the plate connection bar 29 is connected to the second plate 26, the fourth connection electrode 54 ensures that the first electrode of the fifth transistor T5 in the circuit unit and the second plate 26 of the storage capacitor have the same potential.

[0226] In an exemplary embodiment, in at least one cell row, the fourth connection electrode 54 in the nth cell column and the fourth connection electrode 54 in the N+1th column may be interconnected as an integrated structure. In an exemplary embodiment, since the fourth connection electrode 54 in each circuit cell is connected to a first power line formed later, by forming the fourth connection electrodes 54 of adjacent circuit cells into an interconnected integrated structure, the fourth connection electrodes 54 of adjacent circuit cells can be ensured to have the same potential. As a result, the first electrodes of the fifth transistors T5 in adjacent circuit cells have the same potential, and the second plates 26 of the storage capacitors in adjacent circuit cells have the same potential. This helps improve the uniformity of the panel, avoid display defects on the display substrate, and ensure the display quality of the display substrate.

[0227] In an exemplary embodiment, the fifth connection electrode 55 may be in a block shape (e.g., a rectangle) and is connected to the second region of the sixth active layer (also the second region of the seventh active layer) via an eighth via hole V8. In an exemplary embodiment, the fifth connection electrode 55 may simultaneously serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The sixth connection electrode 56 is configured to be connected to a subsequently formed twenty-third connection electrode.

[0228] In an exemplary embodiment, the shape of the sixth connection electrode 56 can be a strip shape extending along the second direction Y, the first end of the sixth connection electrode 56 is connected to the first region of the first active layer through the first via hole V1, and the second end of the sixth connection electrode 56 is connected to the first initial signal line 31 through the twelfth via hole V12, so that the first initial signal transmitted by the first initial signal line 31 is written into the first electrode of the first transistor T1.

[0229] In an exemplary embodiment, since the first active layer of the present circuit unit is arranged in the previous unit row, the first region of the first active layer in the pixel driving circuit of the present circuit unit is connected to the first initial signal line 31 of the previous unit row, and the first initial signal line 31 of the present unit row is connected to the first region of the first active layer of the pixel driving circuit in the next unit row circuit unit.

[0230] In an exemplary embodiment, the shape of the seventh connection electrode 57 can be a strip shape extending along the second direction Y, the first end of the seventh connection electrode 57 is connected to the first region of the seventh active layer through the ninth via hole V9, and the second end of the seventh connection electrode 57 is connected to the second initial signal line 32 through the thirteenth via hole V13, so that the initial signal transmitted by the second initial signal line 32 is written into the first electrode of the seventh transistor T7.

[0231] In an exemplary embodiment, the fourth conductive layer may further include a first preliminary connection line 33 , a first preliminary connection block 33 - 1 , a second preliminary connection line 34 , and a second preliminary connection block 34 - 1 .

[0232] In an exemplary embodiment, the first initial connection line 33 may be in the shape of a straight line or a zigzag line, with its main portion extending along the second direction Y, and may be disposed in the nth unit column. The first initial connection block 33-1 may be in the shape of a bar, with its main portion extending along the first direction X. The first end of the first initial connection block 33-1 is connected to the first initial connection line 33, and the second end of the first initial connection block 33-1 is connected to the sixth connection electrode 56. Because the sixth connection electrode 56 is connected to the first initial signal line 31 through a via, the first initial signal line 31, whose main portion extends along the first direction X, and the first initial connection line 33, whose main portion extends along the second direction Y, are interconnected, forming a network connection structure on the display substrate for transmitting the first initial signal. This minimizes the resistance of the first initial signal line and reduces the voltage drop of the first initial signal, effectively improving the uniformity of the first initial signal across the display substrate, effectively improving display uniformity, and enhancing display quality.

[0233] In an exemplary embodiment, in at least one circuit unit, the first preliminary connection line 33 , the first preliminary connection block 33 - 1 , and the sixth connection electrode 56 may be an integral structure connected to each other.

[0234] In an exemplary embodiment, the second initial connection line 34 may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y, and may be disposed in the (n+1)th unit column. The second initial connection block 34-1 may be in the shape of a bar, with the main portion extending along the first direction X. The first end of the second initial connection block 34-1 is connected to the second initial connection line 34, and the second end of the second initial connection block 34-1 is connected to the seventh connection electrode 57. Because the seventh connection electrode 57 is connected to the second initial signal line 32 through a via, the second initial signal line 32, whose main portion extends along the first direction X, and the second initial connection line 34, whose main portion extends along the second direction Y, are interconnected, forming a network connection structure on the display substrate for transmitting the second initial signal. This minimizes the resistance of the second initial signal line and reduces the voltage drop of the second initial signal, effectively improving the uniformity of the second initial signal across the display substrate, effectively improving display uniformity, and enhancing display quality.

[0235] In an exemplary embodiment, in at least one circuit unit, the second preliminary connection line 34 , the second preliminary connection block 34 - 1 , and the seventh connection electrode 57 may be an integral structure connected to each other.

[0236] In an exemplary embodiment, only one of the first initial connection line 33 and the second initial connection line 34 may be provided in one unit column, and the first initial connection line 33 and the second initial connection line 34 are alternately provided in the first direction X. For example, the first initial connection line 33 may be provided in the nth unit column and the n+2th unit column, and the second initial connection line 34 may be provided in the n+1th unit column and the n+3th unit column.

[0237] In an exemplary embodiment, the first initial connection lines 33 of adjacent cell columns may be interconnected as an integral structure, or adjacent cell columns may share the same first initial connection line 33. For example, the n-1th cell column and the nth cell column may share the same first initial connection line 33.

[0238] In an exemplary embodiment, the second initial connection lines 34 of adjacent cell columns may be interconnected as an integral structure, or adjacent cell columns may share the same second initial connection line 34. For example, the (n+1)th cell column and the (n+2)th cell column may share the same second initial connection line 34.

[0239] In an exemplary embodiment, the fourth conductive layer may further include an eleventh connection electrode 61 , a twelfth connection electrode 62 , a thirteenth connection electrode 63 and a light emitting connection electrode 64 .

[0240] In an exemplary embodiment, the shape of the eleventh connecting electrode 61 can be block-shaped (such as rectangular), and the eleventh connecting electrode 61 is connected to the photosensitive first electrode 41 through the twenty-sixth via V26. The eleventh connecting electrode 61 is configured to be connected to the thirty-first connecting electrode formed subsequently.

[0241] In an exemplary embodiment, the twelfth connecting electrode 62 may be in the shape of a strip extending along the second direction Y. The middle portion of the twelfth connecting electrode 62 is connected to the first region of the eighth active layer via a twenty-first via hole V21, and both ends of the twelfth connecting electrode 62 are connected to the second photosensitive electrode 42 via a twenty-seventh via hole V27. In an exemplary embodiment, the twelfth connecting electrode 62 connects the first electrode of the eighth transistor T8 to the second photosensitive electrode 42 of the photosensitive device.

[0242] In an exemplary embodiment, the shape of the thirteenth connecting electrode 63 can be block-shaped (such as rectangular), the thirteenth connecting electrode 63 is connected to the second region of the eighth active layer through the twenty-second via V22, and the thirteenth connecting electrode 63 is configured to be connected to the subsequently formed thirty-second connecting electrode.

[0243] In an exemplary embodiment, the light-emitting connection electrode 64 may be in the shape of a strip extending along the second direction Y. A first end of the light-emitting connection electrode 64 is connected to the light-emitting connection block 24-1 via a twenty-fifth via hole V25, a second end of the light-emitting connection electrode 64 is connected to the eighth top gate electrode 37 via a twenty-fourth via hole V24, and a portion between the first and second ends of the light-emitting connection electrode 64 is connected to the eighth bottom gate electrode 36 via a twenty-third via hole V23. In an exemplary embodiment, since the light-emitting connection block 24-1 is connected to the light-emitting signal line 24, the light-emitting signal line 24 can control the on and off state of the eighth transistor T8.

[0244] In an exemplary embodiment, the first to seventh connection electrodes 51 to 57 of adjacent unit columns may be mirror-symmetrical with respect to the center line.

[0245] (9) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the fourth conductive layer pattern, wherein a plurality of vias are provided on the first planar layer, as shown in FIG. 16 .

[0246] In an exemplary embodiment, the plurality of vias in each circuit unit includes at least a thirty-first via V31 , a thirty-second via V32 , and a thirty-third via V33 .

[0247] In an exemplary embodiment, the orthographic projection of the thirty-first via hole V31 on the substrate is located within the range of the orthographic projection of the third connecting electrode 53 on the substrate, the first flat layer within the thirty-first via hole V31 is etched away to expose the surface of the third connecting electrode 53, and the thirty-first via hole V31 is configured to connect the subsequently formed twenty-first connecting electrode to the third connecting electrode 53 through the via hole.

[0248] In an exemplary embodiment, the orthographic projection of the thirty-second via hole V32 on the substrate is located within the range of the orthographic projection of the fourth connecting electrode 54 on the substrate, the first flat layer within the thirty-second via hole V32 is etched away to expose the surface of the fourth connecting electrode 54, and the thirty-second via hole V32 is configured to connect the subsequently formed twenty-second connecting electrode to the fourth connecting electrode 54 through the via hole.

[0249] In an exemplary embodiment, the orthographic projection of the thirty-third via hole V33 on the substrate is located within the range of the orthographic projection of the fifth connecting electrode 55 on the substrate, the first flat layer in the thirty-third via hole V33 is etched away to expose the surface of the fifth connecting electrode 55, and the thirty-third via hole V33 is configured to connect the subsequently formed twenty-third connecting electrode to the fifth connecting electrode 55 through the via hole.

[0250] In an exemplary embodiment, the first planar layer may further include a forty-first via hole V41 and a forty-second via hole V42 .

[0251] In an exemplary embodiment, the orthographic projection of the forty-first via hole V41 on the substrate is located within the range of the orthographic projection of the eleventh connecting electrode 61 on the substrate, the first flat layer within the forty-first via hole V41 is etched away to expose the surface of the eleventh connecting electrode 61, and the forty-first via hole V41 is configured to connect the subsequently formed thirty-first connecting electrode to the eleventh connecting electrode 61 through the via hole.

[0252] In an exemplary embodiment, the orthographic projection of the forty-second via hole V42 on the substrate is located within the range of the orthographic projection of the thirteenth connecting electrode 63 on the substrate, the first flat layer within the forty-second via hole V42 is etched away to expose the surface of the thirteenth connecting electrode 63, and the forty-second via hole V42 is configured to connect the subsequently formed thirty-second connecting electrode to the thirteenth connecting electrode 63 through the via hole.

[0253] In an exemplary embodiment, the thirty-first to thirty-third via holes V31 to V33 on the first planar layer of adjacent cell columns may be mirror-symmetrical with respect to the center line.

[0254] (10) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on the first flat layer, as shown in FIG17A and FIG17B , where FIG17B is a planar schematic diagram of the fifth conductive layer in FIG17A . In an exemplary embodiment, the fifth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0255] In an exemplary embodiment, the fifth conductive layer of each circuit unit includes at least a twenty-first connection electrode 71 , a twenty-second connection electrode 72 , a twenty-third connection electrode 73 and a sensing power connection line 74 .

[0256] In an exemplary embodiment, the shape of the twenty-first connection electrode 71 may be block-shaped (eg, rectangular), the twenty-first connection electrode 71 is connected to the third connection electrode 53 through the thirty-first via hole V31, and the twenty-first connection electrode 71 is configured to be connected to a subsequently formed data signal line.

[0257] In an exemplary embodiment, the 22nd connection electrode 72 may be in an L shape. The 22nd connection electrode 72 is connected to the fourth connection electrode 54 through the 32nd via hole V32 . The 22nd connection electrode 72 is configured to be connected to a first power line formed subsequently.

[0258] In an exemplary embodiment, the twenty-second connecting electrode 72 can also serve as a shielding electrode. The orthographic projection of the twenty-second connecting electrode 72 on the substrate at least partially overlaps with the orthographic projection of the first connecting electrode 51 on the substrate. The orthographic projection of the twenty-second connecting electrode 72 on the substrate at least partially overlaps with the orthographic projections of the second region of the first active layer and the first region of the second active layer on the substrate. In an exemplary embodiment, the twenty-second connecting electrode 72 can block the light emitted by the light-emitting device and the light reflected by the film layer from reaching the oxide transistor, preventing the characteristics of the oxide transistor from drifting due to light exposure, thereby improving the electrical characteristics of the oxide transistor. Because the twenty-second connecting electrode 72 is connected to the first power line formed later, the twenty-second connecting electrode, which has a constant potential, can effectively shield the first node N1 in the pixel driving circuit from the effects of data voltage jumps and other signals, preventing the data voltage jumps and other signals from affecting the potential of the first node N1 and effectively preventing the deterioration of crosstalk.

[0259] In an exemplary embodiment, the twenty-second connection electrodes 72 of adjacent circuit unit columns in the first direction X may be interconnected as an integral structure. For example, the twenty-second connection electrodes 72 of the (n-1)th unit column and the twenty-second connection electrodes 72 of the nth unit column may be interconnected as an integral structure. For another example, the twenty-second connection electrodes 72 of the (n+1)th unit column and the twenty-second connection electrodes 72 of the (n+2)th unit column may be interconnected as an integral structure.

[0260] In an exemplary embodiment, the shape of the twenty-third connecting electrode 73 can be a strip shape with the main portion extending along the second direction Y, the twenty-third connecting electrode 73 is connected to the fifth connecting electrode 55 through the thirty-third via V33, and the twenty-third connecting electrode 73 is configured to be connected to the subsequently formed anode connecting electrode.

[0261] In an exemplary embodiment, the shape of the sensing power connection line 74 can be a straight line or a broken line with the main part extending along the first direction X, and can be located on the side of the luminous signal line 24 away from the second electrode plate 26. The sensing power connection line 74 is configured to be connected to the sensing power line formed subsequently.

[0262] In exemplary embodiments, the fifth conductive layer may further include a thirty-first connection electrode 81 and a thirty-second connection electrode 82 .

[0263] In an exemplary embodiment, the shape of the thirty-first connecting electrode 81 can be block-shaped (such as rectangular) and can be arranged in the circuit unit of the nth unit column. The thirty-first connecting electrode 81 is connected to the eleventh connecting electrode 61 through the forty-first via V41, and the thirty-first connecting electrode 81 is configured to be connected to the sensing power line formed subsequently.

[0264] In an exemplary embodiment, the shape of the thirty-second connecting electrode 82 can be block-shaped (such as rectangular) and can be arranged in the circuit unit of the n+1th unit column. The thirty-second connecting electrode 82 is connected to the thirteenth connecting electrode 63 through the forty-second via V42, and the thirty-second connecting electrode 82 is configured to be connected to the sensing signal line formed subsequently.

[0265] In an exemplary embodiment, the twenty-first to twenty-third connection electrodes 71 to 73 and the sensing power connection line 74 of adjacent unit columns may be mirror-symmetrical with respect to the center line.

[0266] (11) Forming a second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern may include: coating a second planar film on the substrate having the aforementioned pattern formed thereon, patterning the second planar film using a patterning process to form a second planar layer covering the fifth conductive layer pattern, wherein a plurality of vias are provided on the second planar layer, as shown in FIG. 18 .

[0267] In an exemplary embodiment, the plurality of vias in each circuit unit includes at least a fifty-first via V51 , a fifty-second via V52 , and a fifty-third via V53 .

[0268] In an exemplary embodiment, the orthographic projection of the fifty-first via hole V51 on the substrate is located within the range of the orthographic projection of the twenty-first connecting electrode 71 on the substrate, the second flat layer within the fifty-first via hole V51 is etched away to expose the surface of the twenty-first connecting electrode 71, and the fifty-first via hole V51 is configured to connect a subsequently formed data signal line to the twenty-first connecting electrode 71 through the via hole.

[0269] In an exemplary embodiment, the orthographic projection of the fifty-second via hole V52 on the substrate is located within the range of the orthographic projection of the twenty-second connecting electrode 72 on the substrate, the second flat layer within the fifty-second via hole V52 is etched away to expose the surface of the twenty-second connecting electrode 72, and the fifty-second via hole V52 is configured to connect a subsequently formed first power line to the twenty-second connecting electrode 72 through the via hole.

[0270] In an exemplary embodiment, the orthographic projection of the fifty-third via V53 on the substrate is located within the range of the orthographic projection of the twenty-third connecting electrode 73 on the substrate, the second flat layer within the fifty-third via V53 is etched away to expose the surface of the twenty-third connecting electrode 73, and the fifty-third via V53 is configured to connect the subsequently formed anode connecting electrode to the twenty-third connecting electrode 73 through the via.

[0271] In an exemplary embodiment, the second planar layer may further include a sixty-first via hole V61 , a sixty-second via hole V62 , and a sixty-third via hole V63 .

[0272] In an exemplary embodiment, the orthographic projection of the sixty-first via hole V61 on the substrate is located within the range of the orthographic projection of the thirty-first connecting electrode 81 on the substrate, the second flat layer within the sixty-first via hole V61 is etched away to expose the surface of the thirty-first connecting electrode 81, and the sixty-first via hole V61 is configured to connect a subsequently formed sensing power line to the thirty-first connecting electrode 81 through the via hole.

[0273] In an exemplary embodiment, the orthographic projection of the sixty-second via hole V62 on the substrate is located within the range of the orthographic projection of the thirty-second connecting electrode 82 on the substrate, the second flat layer within the sixty-second via hole V62 is etched away to expose the surface of the thirty-second connecting electrode 82, and the sixty-second via hole V62 is configured to connect a subsequently formed sensing signal line to the thirty-second connecting electrode 82 through the via hole.

[0274] In an exemplary embodiment, the orthographic projection of the sixty-third via V63 on the substrate is located within the range of the orthographic projection of the sensing power connection line 74 on the substrate, the second flat layer in the sixty-third via V63 is etched away to expose the surface of the sensing power connection line 74, and the sixty-third via V63 is configured to connect the subsequently formed sensing power connection line to the sensing power connection line 74 through the via.

[0275] In an exemplary embodiment, the fifty-first to fifty-third via holes V51 to V53 of adjacent unit columns may be mirror-symmetrical with respect to the center line.

[0276] (12) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming the sixth conductive layer may include: depositing a sixth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the sixth conductive film using a patterning process to form a sixth conductive layer disposed on the second flat layer, as shown in FIG. 19A and FIG. 19B , where FIG. 19B is a plan view schematic diagram of the sixth conductive layer in FIG. 19A . In an exemplary embodiment, the sixth conductive layer may be referred to as a third source / drain metal (SD3) layer.

[0277] In an exemplary embodiment, the sixth conductive layer of each circuit unit includes at least a data signal line 91 , a first power line 92 , and an anode connection electrode 93 .

[0278] In an exemplary embodiment, the data signal line 91 may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y. The data signal line 91 is connected to the 21st connection electrode 71 through the 51st via hole V51. Since the 21st connection electrode 71 is connected to the third connection electrode 53 through the via hole, and the third connection electrode 53 is connected to the first region of the fourth active layer through the via hole, the data signal line 91 is connected to the first electrode of the fourth transistor T4. The data signal line 91 can write a data signal to the first electrode of the fourth transistor T4.

[0279] In an exemplary embodiment, since the data signal line is arranged in the third source-drain metal (SD3) layer and is separated from the corresponding signal line by the thicker first and second planar layers, the distance between the data signal line and the corresponding signal line is increased, and the parasitic capacitance between the data signal line and the corresponding signal line is reduced, thereby effectively reducing the capacitive load of the data signal line.

[0280] In an exemplary embodiment, the first power line 92 may be shaped as a straight line or a zigzag line, with the main portion extending along the second direction Y. The first power line 92 is connected to the twenty-second connection electrode 72 via the fifty-second via hole V52. Since the twenty-second connection electrode 72 is connected to the fourth connection electrode 54 via the via hole, and the fourth connection electrode 54 is connected to the first region of the fifth active layer and the second electrode plate 26 via the via hole, the first power line 92 is connected to the first electrode and the second electrode plate 26 of the fifth transistor T5. The first power line 92 can write the first power signal to the first electrode of the fifth transistor T5 and the second electrode plate 26 of the storage capacitor.

[0281] In an exemplary embodiment, the first power line 92 may be a zigzag line of unequal width, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the first power line and the data signal line.

[0282] In an exemplary embodiment, the first power lines 92 of adjacent circuit unit columns in the first direction X may be interconnected as an integrated structure, or adjacent unit columns may share the same first power line 92. For example, the first power lines 92 of the (n-1)th unit column and the nth unit column may be interconnected as an integrated structure. For another example, the first power lines 92 of the (n+1)th unit column and the (n+2)th unit column may be interconnected as an integrated structure.

[0283] In an exemplary embodiment, the anode connection electrode 93 may be in a block shape (e.g., a rectangular shape). The anode connection electrode 93 is connected to the twenty-third connection electrode 73 via a fifty-third via hole V53. The anode connection electrode 93 is configured to be connected to a subsequently formed anode. Since the twenty-third connection electrode 73 is connected to the fifth connection electrode 55 via a via hole, and the fifth connection electrode 55 is connected to the second region of the sixth active layer and the second region of the seventh active layer via a via hole, the subsequently formed anode can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the pixel driving circuit can drive the light-emitting device to emit light.

[0284] In an exemplary embodiment, the sixth conductive layer may further include a sensing power line 94 and a sensing signal line 95 .

[0285] In an exemplary embodiment, a sensing power line 94 may be provided in the circuit unit of the nth unit column. The sensing power line 94 may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y. The sensing power line 94 is connected to the 31st connection electrode 81 via the 61st via hole V61. Since the 31st connection electrode 81 is connected to the 11th connection electrode 61 via the via hole, and the 11th connection electrode 61 is connected to the first photosensitive electrode 41 via the via hole, the sensing power line 94 is connected to the first photosensitive electrode 41 of the photosensitive device.

[0286] In an exemplary embodiment, the sensing power line 94 is also connected to the sensing power connection line 74 through the sixty-third via V63, so that the sensing power connection line 74 of the main body extending along the first direction X and the sensing power line 94 of the main body extending along the second direction Y are connected to each other, forming a sensing power line with a network connection structure on the display substrate, which not only minimizes the resistance of the sensing power line, reduces the voltage drop of the photosensitive power signal, effectively improves the uniformity of the photosensitive power signal in the display substrate, and effectively improves the photosensitivity uniformity of the photosensitive device.

[0287] In an exemplary embodiment, a sensing signal line 95 may be provided in the circuit unit of the (n+1)th unit column. The sensing signal line 95 may be in the shape of a straight line or a zigzag line, with a main portion extending along the second direction Y. The sensing signal line 95 is connected to the 32nd connection electrode 82 via the 62nd via hole V62. Since the 32nd connection electrode 82 is connected to the 13th connection electrode 63 via the via hole, and the 13th connection electrode 63 is connected to the second region of the eighth active layer via the via hole, the sensing signal line 95 is connected to the second electrode of the eighth transistor T8.

[0288] In an exemplary embodiment, the data signal lines 91 , the first power lines 92 , and the anode connection electrodes 93 of adjacent cell columns may be mirror-symmetrical with respect to the center line.

[0289] In an exemplary embodiment, the sensing signal line 95 may be led out to the binding area or the bezel area.

[0290] (13) Forming a third flat layer pattern. In an exemplary embodiment, forming the third flat layer pattern may include: coating a third flat film on the substrate on which the aforementioned pattern is formed, patterning the third flat film using a patterning process to form a third flat layer covering the sixth conductive layer pattern, wherein the third flat layer is provided with an anode via hole, wherein the orthographic projection of the anode via hole on the substrate is located within the range of the orthographic projection of the anode connection electrode 93 on the substrate, the anode via hole exposes the surface of the anode connection electrode 93, and the anode via hole is configured to connect a subsequently formed anode to the anode connection electrode 93 through the via hole.

[0291] At this point, the driving structure layer is prepared on the substrate. In a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units, each circuit unit may include a pixel driving circuit, a sensing circuit and a photosensitive device, a first scanning signal line, a second scanning signal line, a third scanning signal line, a light-emitting signal line, a first initial signal line, a second initial signal line, a first power line and a data signal line connected to the pixel driving circuit, and a sensing power line and a sensing signal line connected to the sensing circuit and the photosensitive device. In a plane perpendicular to the display substrate, the driving structure layer may include a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a first flat layer, a fifth conductive layer, a second flat layer, a sixth conductive layer and a third flat layer arranged in sequence on the substrate. The first semiconductor layer may include at least the active layers of the first transistor, the third transistor to the seventh transistor, and the photosensitive active layer, the first conductive layer may include at least the first scanning signal line, the second scanning signal line, the light-emitting signal line and the first plate of the storage capacitor, the second conductive layer may include at least the first initial signal line, the second plate of the storage capacitor and the eighth bottom gate electrode, the second semiconductor layer may include at least the active layers of the second transistor and the eighth transistor, the third conductive layer may include at least the third scanning signal line, the second initial signal line and the eighth top gate electrode, the fourth conductive layer may include at least multiple connecting electrodes, the fifth conductive layer may include at least the sensing power connection line, and the sixth conductive layer may include at least the data signal line, the first power line, the sensing power line and the sensing signal line.

[0292] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-Si).

[0293] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multi-layer, or a composite layer. The first planarizing layer, the second planarizing layer, and the third planarizing layer can be made of an organic material, such as a resin.

[0294] In an exemplary embodiment, the pixel driving circuits in two adjacent circuit units in a unit row may be substantially mirror-symmetrical with respect to a center line. For example, the pixel driving circuit in the nth unit column and the pixel driving circuit in the (n+1)th unit column may be mirror-symmetrical with respect to the center line.

[0295] In an exemplary embodiment, after the driving structure layer is prepared, the light emitting structure layer is first prepared on the driving structure layer, and then the encapsulation structure layer is prepared on the light emitting structure layer, which will not be described in detail here.

[0296] In an exemplary embodiment, the sensing circuit and the photosensitive device can be set in some circuit units to realize the in-screen fingerprint function, or the sensing circuit and the photosensitive device can be set in all circuit units to realize the full-screen fingerprint function, which is not limited in the present disclosure.

[0297] The exemplary embodiments of the present disclosure provide a display substrate equipped with an LTPO circuit compatible with fingerprint sensor functionality. By arranging a pixel drive circuit, a sensor circuit, and a photosensitive device within the circuit unit, a full-screen fingerprint sensor function can be realized. The display substrate disclosed herein utilizes a shared light signal line between the pixel drive circuit and the sensor circuit. This high-level signal line maintains a stable duration, preventing overlap in acquisition time. Furthermore, low-grayscale display duration is extended, resulting in more complete signal acquisition. This effectively meets the driving requirements of the light sensor, enabling progressive scanning of the light sensor and realizing a full-screen fingerprint sensor function.

[0298] By placing the sensing circuit and photosensitive device within a circuit unit, the present invention achieves a uniform spacing between the fingerprint sensor formed by the sensing circuit and photosensitive device and the pixel drive circuit, resulting in high fingerprint sensing accuracy. Because the gate drive circuit that outputs the luminous signal has an adjustable scan width, the fingerprint sampling time and cycle can be flexibly adjusted, effectively improving sampling accuracy.

[0299] The present invention adopts mirror symmetry of the pixel drive circuit, places the sensor circuit and photosensitive device between adjacent cell columns, and effectively utilizes the layout space. The present invention connects the luminescent connection electrode to the luminescent signal line, so that the luminescent signal line controls the conduction and disconnection of the eighth transistor.

[0300] The present invention forms a network-connected structure of sensor power lines on the display substrate, which not only minimizes the resistance of the sensor power lines and reduces the voltage drop of the photosensitive power signal, but also effectively improves the uniformity of the photosensitive power signal in the display substrate and the photosensitivity uniformity of the photosensitive device.

[0301] The present disclosure forms a network connection structure for transmitting a first initial signal and a network connection structure for transmitting a second initial signal on a display substrate, thereby minimizing the resistance of the initial signal line and reducing the voltage drop of the initial signal, thereby effectively improving the uniformity of the initial signal in the display substrate, effectively improving the display uniformity, and improving the display quality.

[0302] The present disclosure provides a shielding electrode. On the one hand, the shielding electrode can block the light emitted by the light-emitting device and the light reflected by the film layer from irradiating the oxide transistor, thereby preventing the characteristics of the oxide transistor from drifting due to light, thereby improving the electrical characteristics of the oxide transistor. On the other hand, the shielding electrode can effectively shield the influence of data voltage jumps and other signals on the first node N1 in the pixel driving circuit, thereby effectively avoiding the deterioration of crosstalk.

[0303] The preparation process disclosed in the present invention is well compatible with existing preparation processes, is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0304] The structure and preparation process shown above in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. For example, the first transistor T1, the third transistor T3 to the seventh transistor T7 can be set as oxide transistors, and the second transistor T2 and the eighth transistor T8 can be set as polysilicon transistors. For another example, the first transistor T1 to the seventh transistor T7 can be set as polysilicon transistors, and the eighth transistor T8 can be set as an oxide transistor. For another example, the pixel driving circuit and the sensing circuit can share the first scanning signal line, the second scanning signal line or the third scanning signal line, which is not limited in the present disclosure.

[0305] In an exemplary embodiment, the display substrate of the present disclosure may be applied to other display devices having a pixel driving circuit, such as a quantum dot display, etc., which is not limited in the present disclosure.

[0306] The present disclosure also provides a driving method for a display substrate to drive the display substrate provided by the above embodiment. In an exemplary embodiment, the display substrate includes a plurality of circuit units, at least one circuit unit includes a pixel driving circuit, a sensing circuit and a photosensitive device, the pixel driving circuit includes at least a driving transistor and at least one light-emitting control transistor, the first end of the light-emitting control transistor is connected to the first power line, the second end of the light-emitting control transistor is connected to the first end of the driving transistor, or the first end of the light-emitting control transistor is connected to the second end of the driving transistor, and the second end of the light-emitting control transistor is connected to the light-emitting device; the sensing circuit includes at least a sensing control transistor, the first end of the sensing control transistor is connected to the photosensitive device, the second end of the sensing control transistor is connected to the sensing signal line, the light-emitting control transistor and the sensing control transistor are different types of transistors; in at least one circuit unit, the light-emitting control transistor and the sensing control transistor are connected to the same light-emitting signal line, and the light-emitting signal line is configured to provide a light-emitting control signal to the pixel driving circuit. The driving method may include:

[0307] Step 1: In a first sensing period, the light-emitting signal line controls the sensing circuit to generate a photosensitive current;

[0308] Step 2: During the second sensing period, the light emitting signal line controls the pixel driving circuit to output a driving current.

[0309] In an exemplary embodiment, step 1 may include: in a first sensing period, the light emission signal line outputs a first signal, the light emission control transistor is turned off, the sensing control transistor is turned on, and the sensing circuit generates a photosensitive current.

[0310] In an exemplary embodiment, during the first sensing period, the pixel driving circuit performs resetting and data writing.

[0311] In an exemplary embodiment, step 2 may include: in a second sensing period, the light emission signal line outputs a second signal, the sensing control transistor is turned off, the light emission control transistor is turned on, and the pixel driving circuit outputs a driving current.

[0312] In an exemplary embodiment, the first signal may be a high-level signal, and the second signal may be a low-level signal.

[0313] The present disclosure also provides a method for preparing a display substrate to produce the display substrate provided in the above embodiment. In an exemplary embodiment, the display substrate includes a plurality of circuit units, and the preparation method may include:

[0314] A pixel driving circuit, a sensing circuit and a photosensitive device are formed in at least one circuit unit; the pixel driving circuit at least includes a driving transistor and at least one light-emitting control transistor, the first end of the light-emitting control transistor is connected to a first power line, and the second end of the light-emitting control transistor is connected to the first end of the driving transistor, or the first end of the light-emitting control transistor is connected to the second end of the driving transistor, and the second end of the light-emitting control transistor is connected to the light-emitting device; the sensing circuit at least includes a sensing control transistor, the first end of the sensing control transistor is connected to the photosensitive device, and the second end of the sensing control transistor is connected to a sensing signal line, and the light-emitting control transistor and the sensing control transistor are transistors of different types; in at least one circuit unit, the light-emitting control transistor and the sensing control transistor are connected to the same light-emitting signal line, and the light-emitting signal line is configured to provide a light-emitting control signal to the pixel driving circuit.

[0315] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0316] While the embodiments disclosed herein are as described above, it should be noted that the above embodiments are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, comprising a plurality of circuit units, at least one circuit unit comprising a pixel driving circuit, a sensing circuit and a photosensitive device, wherein the pixel driving circuit at least comprises a driving transistor and at least one light-emitting control transistor, wherein a first end of the light-emitting control transistor is connected to a first power line, and a second end of the light-emitting control transistor is connected to a first end of the driving transistor, or a first end of the light-emitting control transistor is connected to a second end of the driving transistor, and a second end of the light-emitting control transistor is connected to a light-emitting device; the sensing circuit at least comprises a sensing control transistor, wherein a first end of the sensing control transistor is connected to the photosensitive device, and a second end of the sensing control transistor is connected to a sensing signal line, and the light-emitting control transistor and the sensing control transistor are transistors of different types; in at least one circuit unit, the light-emitting control transistor and the sensing control transistor are connected to the same light-emitting signal line, and the light-emitting signal line is configured to provide a light-emitting control signal to the pixel driving circuit.

2. The display substrate according to claim 1, wherein: The light emission control transistor is a polysilicon transistor, and the sensing control transistor is an oxide transistor; or, the light emission control transistor is an oxide transistor, and the sensing control transistor is a polysilicon transistor.

3. The display substrate according to claim 1, wherein: The light emitting control transistor at least includes a light emitting control gate electrode, and the sensing control transistor at least includes a sensing control gate electrode. The light emitting control gate electrode is directly connected to the light emitting signal line, and the sensing control gate electrode is connected to the light emitting signal line through a light emitting connection electrode.

4. The display substrate according to claim 3, wherein: In a direction perpendicular to the display substrate, the display substrate includes multiple conductive layers, the light-emitting control gate electrode and the light-emitting signal line are arranged in the same conductive layer, the sensing control gate electrode and the light-emitting signal line are arranged in different conductive layers, and the light-emitting connection electrode and the sensing control gate electrode are arranged in different conductive layers.

5. The display substrate according to claim 4, wherein: The multiple conductive layers include at least a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer which are arranged in sequence; the light-emitting signal line and the light-emitting control gate electrode are arranged in the first conductive layer and are an integrated structure connected to each other; the sensing control gate electrode is respectively arranged in the second conductive layer and the third conductive layer; the light-emitting connection electrode is arranged in the fourth conductive layer, and the light-emitting connection electrode is respectively connected to the light-emitting signal line and the sensing control gate electrode through vias.

6. The display substrate according to claim 5, wherein: The sensing control gate electrode includes a bottom gate electrode and a top gate electrode, the bottom gate electrode is arranged in the second conductive layer, the top gate electrode is arranged in the third conductive layer, and the light emitting connection electrode is respectively connected to the bottom gate electrode and the top gate electrode through via holes.

7. The display substrate according to any one of claims 1 to 6, wherein: The photosensitive device at least includes a first photosensitive electrode, a second photosensitive electrode, and a photosensitive layer arranged between the first photosensitive electrode and the second photosensitive electrode. The first photosensitive electrode is connected to a sensing power line, and the second photosensitive electrode is connected to a first electrode of the sensing control transistor.

8. The display substrate according to claim 7, wherein: The sensing control transistor at least includes a sensing active layer; in a direction perpendicular to the display substrate, the display substrate at least includes a first semiconductor layer arranged on a base and a second semiconductor layer arranged on a side of the first semiconductor layer away from the base, the photosensitive first electrode, the photosensitive second electrode and the photosensitive layer are arranged in the first semiconductor layer, and the sensing active layer is arranged in the second semiconductor layer.

9. The display substrate according to claim 8, wherein: The photosensitive first electrode and the photosensitive second electrode are formed by conducting the first semiconductor layer, and the photosensitive layer is formed by doping the first semiconductor layer.

10. The display substrate according to claim 8, wherein: At least one circuit unit further includes an eleventh connecting electrode and a thirty-first connecting electrode, and the photosensitive first electrode is connected to the sensing power line through the eleventh connecting electrode and the thirty-first connecting electrode.

11. The display substrate according to claim 10, wherein: In a direction perpendicular to the display substrate, the display substrate includes multiple conductive layers, the eleventh connecting electrode, the thirty-first connecting electrode and the sensing power line are arranged in different conductive layers, the eleventh connecting electrode is connected to the photosensitive first electrode through a via hole, the thirty-first connecting electrode is connected to the eleventh connecting electrode through a via hole, and the sensing power line is connected to the thirty-first connecting electrode through a via hole.

12. The display substrate according to claim 8, wherein: At least one circuit unit further includes a twelfth connecting electrode, and the second photosensitive electrode is connected to the first region of the sensing active layer through the twelfth connecting electrode.

13. The display substrate according to claim 12, wherein: The twelfth connecting electrode is arranged on a side of the sensing active layer away from the substrate, the twelfth connecting electrode is connected to the second photosensitive electrode through a via hole, and the twelfth connecting electrode is connected to the first area of ​​the sensing active layer through another via hole.

14. The display substrate according to claim 8, wherein: At least one circuit unit further includes a thirteenth connection electrode and a thirty-second connection electrode, and the second region of the sensing active layer is connected to the sensing signal line through the thirteenth connection electrode and the thirty-second connection electrode.

15. The display substrate according to claim 14, wherein: In a direction perpendicular to the display substrate, the display substrate includes multiple conductive layers, the thirteenth connecting electrode, the thirty-second connecting electrode and the sensing signal line are arranged in different conductive layers, the thirteenth connecting electrode is connected to the second area of ​​the sensing active layer through a via hole, the thirty-second connecting electrode is connected to the thirteenth connecting electrode through a via hole, and the sensing signal line is connected to the thirty-second connecting electrode through a via hole.

16. The display substrate according to claim 7, wherein: The shape of the sensing power line is a straight line or a broken line extending in the second direction of the main part. At least one circuit unit also includes a sensing power connection line. The shape of the sensing power connection line is a straight line or a broken line extending in the first direction of the main part. The sensing power lines are connected to the sensing power connection lines to form a network connectivity structure.

17. A display device comprising the display substrate according to any one of claims 1 to 16.

18. A method for driving a display substrate, wherein the display substrate comprises a plurality of circuit units, at least one circuit unit comprises a pixel driving circuit, a sensing circuit and a photosensitive device, the pixel driving circuit comprises at least a driving transistor and at least one light-emitting control transistor, the first end of the light-emitting control transistor is connected to a first power line, the second end of the light-emitting control transistor is connected to the first end of the driving transistor, or the first end of the light-emitting control transistor is connected to the second end of the driving transistor, and the second end of the light-emitting control transistor is connected to the light-emitting device; the sensing circuit comprises at least a sensing control transistor, the first end of the sensing control transistor is connected to the photosensitive device, the second end of the sensing control transistor is connected to a sensing signal line, and the light-emitting control transistor and the sensing control transistor are transistors of different types; In at least one circuit unit, the light emission control transistor and the sensing control transistor are connected to the same light emission signal line, and the light emission signal line is configured to provide a light emission control signal to the pixel driving circuit; The driving method comprises: In the first sensing period, the light emitting signal line controls the sensing circuit to generate a photosensitive current; In the second sensing period, the light emitting signal line controls the pixel driving circuit to output a driving current.

19. The driving method according to claim 18, wherein: The light-emitting signal line controls the sensing circuit to generate a photosensitive current, including: the light-emitting signal line outputs a first signal, the light-emitting control transistor is turned off, the sensing control transistor is turned on, and the sensing circuit generates a photosensitive current.

20. The driving method according to claim 18, wherein: The light emitting signal line controls the pixel driving circuit to output a driving current, including: the light emitting signal line outputs a second signal, the sensing control transistor is turned off, the light emitting control transistor is turned on, and the pixel driving circuit outputs a driving current.

21. A method for preparing a display substrate, wherein the display substrate comprises a plurality of circuit units, the method comprising: forming a pixel driving circuit, a sensing circuit and a photosensitive device in at least one circuit unit; The pixel driving circuit at least includes a driving transistor and at least one light emitting control transistor, wherein a first end of the light emitting control transistor is connected to a first power line, and a second end of the light emitting control transistor is connected to a first end of the driving transistor, or The first end of the light control transistor is connected to the second end of the driving transistor, and the second end of the light control transistor is connected to the light emitting device; the sensing circuit at least includes a sensing control transistor, the first end of the sensing control transistor is connected to the light sensing device, the second end of the sensing control transistor is connected to the sensing signal line, and the light control transistor and the sensing control transistor are different types of transistors; In at least one circuit unit, the light emission control transistor and the sensing control transistor are connected to the same light emission signal line, and the light emission signal line is configured to provide a light emission control signal to the pixel driving circuit.

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