Magnetoresistive element, storage device, and electronic appliance

Abstract

A magnetoresistive element according to one embodiment of the present disclosure comprises: a reference layer; a barrier layer laminated on the reference layer; a storage layer laminated on the barrier layer; and a cap layer laminated on the storage layer. The storage layer or the cap layer has a first oxide layer, a metal layer laminated on the first oxide layer, and a second oxide layer laminated on the metal layer.

Description

Magnetoresistive element, memory device and electronic device

[0001] The present disclosure relates to a magnetoresistive element, a memory device, and an electronic device.

[0002] A Q-I (Quad-interface) type MTJ (Magnetic Tunnel Junction) element has been proposed as a magnetoresistive element with high retention characteristics (Δ) (see, for example, Patent Document 1). A Q-I type MTJ element is configured by stacking, for example, a reference layer, a barrier layer, a first magnetic layer, an intermediate layer, a second magnetic layer, and a cap layer in the listed order. The first magnetic layer, the intermediate layer, and the second magnetic layer function as a memory layer. A nonmagnetic layer (e.g., MgO) is used for the barrier layer, the intermediate layer, and the cap layer. Therefore, there are four interfaces where the first magnetic layer and the second magnetic layer contact the nonmagnetic layer.

[0003] The interfacial magnetic anisotropy occurring at the interface between the aforementioned first and second magnetic layers is utilized to form perpendicular magnetization layers. The first and second magnetic layers are magnetically coupled via an intermediate layer, apparently functioning as a single magnetic layer. Therefore, the total volume of the magnetic material in a Q-I MTJ element is increased, resulting in improved retention characteristics compared to a typical DI (double-interface) MTJ element. In a DI MTJ element, the storage layer is a single magnetic layer, and there are two interfaces where the magnetic layer and nonmagnetic layer meet. Furthermore, in a Q-I MTJ element, increasing the thickness of the intermediate layer increases the interfacial magnetic anisotropy, further improving retention characteristics.

[0004] International Publication No. 2019 / 187674

[0005] However, in magnetoresistive elements such as the Q-I type, if the thickness of the intermediate layer (e.g., MgO) is increased to improve retention characteristics, parasitic resistance caused by the intermediate layer (e.g., caused by MgO) will appear, resulting in a decrease in the TMR ratio (tunneling magnetoresistance ratio).

[0006] Therefore, the present disclosure provides a magnetoresistive element, a memory device, and an electronic device that can improve the retention characteristics and suppress the decrease in the TMR ratio.

[0007] A magnetoresistive element according to one embodiment of the present disclosure comprises a reference layer, a barrier layer stacked on the reference layer, a memory layer stacked on the barrier layer, and a cap layer stacked on the memory layer, wherein the memory layer or the cap layer has a first oxide layer, a metal layer stacked on the first oxide layer, and a second oxide layer stacked on the metal layer.

[0008] A memory device according to one embodiment of the present disclosure includes a magnetoresistive element, the magnetoresistive element including a reference layer, a barrier layer stacked on the reference layer, a memory layer stacked on the barrier layer, and a cap layer stacked on the memory layer, and the memory layer or the cap layer has a first oxide layer, a metal layer stacked on the first oxide layer, and a second oxide layer stacked on the metal layer.

[0009] An electronic device according to one embodiment of the present disclosure includes a memory device having a magnetoresistive element, the magnetoresistive element including a reference layer, a barrier layer stacked on the reference layer, a memory layer stacked on the barrier layer, and a cap layer stacked on the memory layer, and the memory layer or the cap layer has a first oxide layer, a metal layer stacked on the first oxide layer, and a second oxide layer stacked on the metal layer.

[0010] 1 is a diagram showing a configuration example of a memory device according to a first embodiment; FIG. 2 is a diagram showing a configuration example of a memory cell according to the first embodiment; FIG. 3 is a diagram showing another configuration example of a memory cell according to the first embodiment; FIG. 4 is a diagram showing a configuration example of a magnetoresistive element according to the first embodiment; FIG. 5 is a diagram showing a configuration example of a magnetoresistive element according to an example of the first embodiment; FIG. 6 is a diagram showing a configuration example of a magnetoresistive element according to a comparative example of the first embodiment; FIG. 7 is a graph showing the relationship between the resistance RA and the thickness of the intermediate layer of the magnetoresistive elements according to the example of the first embodiment and the comparative example; FIG. 8 is a graph showing the relationship between the magnetoresistive ratio MR and the thickness of the intermediate layer of the magnetoresistive elements according to the example of the first embodiment and the comparative example; FIG. 9 is a graph showing the relationship between the thermal stability index Δ and the thickness of the intermediate layer of the magnetoresistive elements according to the example of the first embodiment and the comparative example; FIG. 10 is a graph showing the relationship between the resistance RA and the thickness of the TaOx layer of the magnetoresistive element according to the example of the first embodiment; FIG. 11 is a graph showing the relationship between the magnetoresistive ratio MR and the thickness of the TaOx layer of the magnetoresistive element according to the example of the first embodiment; 1 is a graph showing the relationship between the resistance RA of a magnetoresistive element according to an example of the first embodiment and the thickness of the MgO layer; FIG. 2 is a graph showing the relationship between the magnetoresistive ratio MR of a magnetoresistive element according to an example of the first embodiment and the thickness of the MgO layer; FIG. 3 is a cross-sectional view showing a specific example of an insertion position of a magnetoresistive element according to the first embodiment into a chip; FIG. 4 is a diagram showing an example of the configuration of a magnetoresistive element according to a second embodiment; FIG. 5 is a diagram showing an application example of a storage device according to any of the above-mentioned embodiments; FIG. 6 is a diagram showing an example of the configuration of an imaging device according to an application example; FIG. 7 is a diagram showing an example of the configuration of a distance measuring device according to an application example.

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The embodiments include examples and modified examples. Note that the elements, devices, equipment, methods, etc. according to the present disclosure are not limited to the embodiments of the present disclosure. Furthermore, in the following embodiments, essentially identical components are designated by the same reference numerals, and redundant explanations will be omitted.

[0012] One or more of the following embodiments can be implemented independently. However, at least a portion of the following embodiments may be implemented in appropriate combination with at least a portion of another embodiment. These embodiments may include novel features that are different from one another. Therefore, each embodiment may contribute to solving different objectives or problems, and may achieve different effects. The effects of each embodiment are merely examples and are not intended to be limiting, and other effects may also be achieved.

[0013] The present disclosure will be described in the following order: 1. First Embodiment 1-1. Configuration Example of Memory Device 1-2. Configuration Example of Memory Cell 1-3. Configuration Example of Magnetoresistive Element 1-4. Example of Magnetoresistive Element 1-4-1. Examples and Comparative Examples 1-4-2. Thickness Range of TaOx Layer 1-4-3. Thickness Range of CoFeB Layer 1-4-4. Thickness Range of MgO Layer 1-5. Specific Example of Intermediate Layer 1-6. Specific Example of Insertion Position of Magnetoresistive Element into Chip 2. Second Embodiment 2-1. Configuration Example of Magnetoresistive Element 3. Functions and Effects According to Each Embodiment 4. Other Embodiments 5. Application Examples 5-1. Various Devices 5-2. Imaging Device 5-3. Range Finder 6. Supplementary Notes

[0014] 1. First Embodiment 1-1. Configuration Example of Storage Device An example of the configuration of a storage device 10 according to this embodiment will be described with reference to Fig. 1. Fig. 1 is a diagram showing an example of the configuration of a storage device 10 according to this embodiment.

[0015] 1, a memory device 10 includes a memory cell array 11. The memory device 10 is an example of a memory device that stores data based on the magnetization direction of a magnetic material.

[0016] The memory cell array 11 includes a plurality of memory cells 100 arranged in a matrix. These memory cells 100 are connected to bit lines BL, source lines SL, and word lines WL, respectively. For example, the plurality of word lines WL are wired to extend in the row direction, and the plurality of bit lines BL and the plurality of source lines SL are wired to extend in the column direction. The bit lines BL, source lines SL, and word lines WL each function as control lines.

[0017] Each memory cell 100 has a magnetoresistive element (magnetoresistive effect element) 110 and a selection element 120. The magnetoresistive element 110 is, for example, a magnetic tunnel junction (MTJ) element. The selection element 120 is connected to one end of the magnetoresistive element 110 and controls the application of voltage, current, etc. to the magnetoresistive element 110. For example, various transistors can be used as this selection element 120. Furthermore, for example, a spin transfer torque (STT)-magnetoresistive random access memory (MRAM) cell or a VC-MRAM cell can be used as the memory cell 100.

[0018] 1, the memory cells 100 share one source line SL for every two columns in the column direction, i.e., the memory cells 100 arranged in two columns are connected to two bit lines BL and one source line SL (2BL / 1SL).

[0019] In addition to the memory cell array 11, the memory device 10 includes a peripheral circuit 20. In the example of Fig. 1, the peripheral circuit 20 includes an I / O (input / output circuit) 21, a control circuit 22, a voltage generation circuit 23, a write circuit 24, a read circuit 25, a bit line address decoder 26, a bit line control circuit 27, a word line address decoder 28, a word line control circuit 29, and a sense amplifier 30. The bit line control circuit 27 is connected to the bit line BL, the word line control circuit 29 is connected to the word line WL, and the sense amplifier 30 is connected to the source line SL. The basic configuration of such a memory is well known, so the basic configuration will be briefly described.

[0020] The I / O 21 enables the exchange of commands related to reading and writing data, addresses of memory cells 100 to be accessed, data, etc. between an external circuit (e.g., an arithmetic circuit) of the memory device 10 and the control circuit 22 of the memory device 10.

[0021] In response to a command, the control circuit 22 controls the writing and reading of data to and from the memory cell 100. For example, the control circuit 22 receives a command (such as a write or read command) from an external circuit, and controls the writing and reading of data based on the received command.

[0022] The voltage generating circuit 23 generates a voltage (e.g., a pulse voltage) used to write and read data to the memory cell 100, and supplies the generated voltage to the write circuit 24 and the read circuit 25. Note that voltages required for circuit operation are provided separately.

[0023] The write circuit 24 controls the voltage and current (for example, pulse voltage and pulse current) used to write data to the memory cell 100. The write circuit 24 functions as a write unit.

[0024] The read circuit 25 controls the reading of data from the memory cell 100. Specifically, the read circuit 25 controls a voltage (for example, a pulse voltage) used to detect the resistance value of the magnetoresistive element 110. The read circuit 25 functions as a read unit.

[0025] The bit line address decoder 26 obtains the address of the bit line BL corresponding to the address received at the I / O 21 described above.

[0026] The bit line control circuit 27 selects and controls the bit line BL corresponding to the address of the bit line address decoder 26. For example, writing data to the memory cell 100 by the write circuit 24 and reading data from the memory cell 100 by the read circuit 25 are performed via the bit line control circuit 27 etc.

[0027] The word line address decoder 28 obtains the address of the word line WL corresponding to the address received at the I / O 21 described above.

[0028] The word line control circuit 29 selects and controls the word line WL corresponding to the address of the word line address decoder 28 .

[0029] The sense amplifier 30 detects the data read from the memory cell 100 by the read circuit 25 , specifically the resistance value of the magnetoresistive element 110 .

[0030] <1-2. Configuration Example of Memory Cell> A configuration example of the memory cell 100 according to this embodiment will be described with reference to Fig. 2 and Fig. 3. Fig. 2 and Fig. 3 are diagrams each showing a configuration example of the memory cell 100 according to this embodiment.

[0031] 2 and 3, the magnetoresistive element 110 and the selection element 120 of the memory cell 100 are connected in series, and the selection element 120 has a drain (drain terminal), a source (source terminal), and a gate (gate terminal). The contact layers 103 and 104 correspond to, for example, electrode layers or connection layers.

[0032] 2, the magnetoresistive element 110 of the memory cell 100 is connected to the wiring 101 via the contact layer 103, and to the selection element 120 via the contact layer 104. The drain of the selection element 120 is connected to the contact layer 104, and the source is connected to the source line SL. The gate of the selection element 120 is connected to the word line WL. The contact layer 103 is connected to the wiring 101 that constitutes the bit line BL. By applying an on-voltage to the word line WL, the selection element 120 becomes conductive, and a voltage (current) can be applied to the magnetoresistive element 110.

[0033] 3, the magnetoresistive element 110 of the memory cell 100 is connected to the wiring 102 via the contact layer 104, for example, and to the selection element 120 via the contact layer 103. The drain of the selection element 120 is connected to the bit line BL, and its source is connected to the contact layer 103. The gate of the selection element 120 is connected to the word line WL. The contact layer 104 is connected to the wiring 102 that constitutes the source line SL. By applying an on-voltage to the word line WL, the selection element 120 becomes conductive, allowing a voltage (current) to be applied to the magnetoresistive element 110.

[0034] As described above, the bit line BL is connected to the bit line control circuit 27 (see FIG. 1). The word line WL is connected to the word line control circuit 29 (see FIG. 1). The source line SL is connected to the sense amplifier 30 (see FIG. 1). By applying a voltage between the bit line BL and the source line SL and also applying an on-voltage to the word line WL that turns on the selection element 120, a voltage (current) for writing or reading can be applied to the magnetoresistive element 110.

[0035] <1-3. Configuration Example of Magnetoresistive Element> A configuration example of the magnetoresistive element 110 according to this embodiment will be described with reference to Fig. 4. Fig. 4 is a diagram showing a configuration example of the magnetoresistive element 110 according to this embodiment.

[0036] As shown in Fig. 4, the magnetoresistive element 110 has a reference layer 111, a barrier layer 112, a memory layer 113, and a cap layer 114. In the example of Fig. 4, the reference layer 111, the barrier layer 112, the memory layer 113, and the cap layer 114 are stacked in this order to form the magnetoresistive element 110. The reference layer 111 and the barrier layer 112 are adjacent to each other, the barrier layer 112 and the memory layer 113 are adjacent to each other, and the memory layer 113 and the cap layer 114 are adjacent to each other. Adjacent layers share a boundary surface, for example.

[0037] The reference layer 111 is a layer that has magnetic anisotropy and an invariable magnetization direction. This reference layer 111 is also referred to as, for example, a pinned layer or a magnetization pinned layer. The reference layer 111 may be composed of, for example, CoFeB, a CoFeC alloy, a NiFeB alloy, or a NiFeC alloy. The reference layer 111 may also be composed of, for example, a laminated ferri-pinned structure in which multiple ferromagnetic layers are stacked with a nonmagnetic layer interposed therebetween. Materials for the ferromagnetic layers that constitute the reference layer 111 of this laminated ferri-pinned structure can include, for example, Co, CoFe, CoFeB, Ni, Pd, and Pt. Materials for the nonmagnetic layers can include, for example, Ru, Re, Ir, and Os.

[0038] Furthermore, the reference layer 111 may have a fixed magnetization direction by utilizing antiferromagnetic coupling between an antiferromagnetic layer and a ferromagnetic layer. Examples of materials that can be used for the antiferromagnetic layer include magnetic materials such as FeMn alloys, PtMn alloys, PtCrMn alloys, NiMn alloys, IrMn alloys, NiO, and Fe2O3. Nonmagnetic elements such as Ag, Cu, Au, Al, Si, Bi, Ta, B, C, O, N, Pd, Pt, Zr, Hf, Ir, W, Mo, and Nb can also be added to these magnetic materials.

[0039] The barrier layer 112 is a layer disposed adjacent to the memory layer 113. This barrier layer 112 functions, for example, as a tunnel barrier layer. The barrier layer 112 may be composed of, for example, an oxide of at least one element selected from the group consisting of Mg, Al, Ti, Si, Zn, Zr, Hf, Ta, Bi, Cr, Ga, La, Gd, Sr, and Ba, or a nitride of at least one element selected from the group consisting of Mg, Al, Ti, Si, Zn, Zr, Hf, Ta, Bi, Cr, Ga, La, Gd, Sr, and Ba. The barrier layer 112 may also be composed of an insulator, dielectric, or semiconductor such as MgF2, CaF, SrTiO2, AlLaO3, or AlNO, or may have a structure in which these layers are stacked.

[0040] The memory layer 113 is a layer that has magnetic anisotropy and a variable magnetization direction. This memory layer 113 is also called, for example, a free layer. A state in which the magnetization direction of the memory layer 113 is the same as the magnetization direction of the reference layer 111 is called a parallel state, and a state in which the magnetization direction of the memory layer 113 is different from the magnetization direction of the reference layer 111 is called an antiparallel state. The magnetoresistive element 110 is in a low resistance state when in the parallel state, and in a high resistance state when in the antiparallel state. As described above, the magnetization direction of the memory layer 113 can be changed by applying a voltage (current) to the magnetoresistive element 110.

[0041] 4, the first magnetic layer 113a, the intermediate layer 113b, and the second magnetic layer 113c are stacked in this order to form the memory layer 113. The first magnetic layer 113a and the intermediate layer 113b are adjacent to each other, and the intermediate layer 113b and the second magnetic layer 113c are adjacent to each other.

[0042] The first magnetic layer 113a is in contact with the non-magnetic layers of the barrier layer 112 and the intermediate layer 113b, and is disposed so as to be sandwiched between these non-magnetic layers. The second magnetic layer 113c is in contact with the non-magnetic layers of the intermediate layer 113b and the cap layer 114, and is disposed so as to be sandwiched between these non-magnetic layers. There are four interfaces where the first magnetic layer 113a and the second magnetic layer 113c contact the non-magnetic layers. Due to this arrangement, the magnetoresistive element 110 according to this embodiment is called a Q-I type magnetoresistive element.

[0043] The first magnetic layer 113 a and the second magnetic layer 113 c are magnetically coupled via the non-magnetic intermediate layer 113 b, and apparently function as a single magnetic layer, due to the interfacial magnetic anisotropy that occurs at the interface between the magnetic layer and the non-magnetic layer.

[0044] The first magnetic layer 113a or the second magnetic layer 113c may be composed of, for example, CoFeB, CoFe, Fe, or FeB. The first magnetic layer 113a or the second magnetic layer 113c may also contain, for example, a transition metal (Hf, Ta, W, Re, Ir, Pt, Au, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Ti, V, Cr, Mn, Ni, or Cu). The first magnetic layer 113a or the second magnetic layer 113c may also contain, for example, a nitride or oxide. Materials that induce a proximity magnetic moment in a magnetic substance may include, for example, Ir or Os. The magnetic anisotropy effect can also be improved by adding a heavy metal to the first magnetic layer 113a or the second magnetic layer 113c.

[0045] The intermediate layer 113b has a first oxide layer 1131, a metal layer 1132, and a second oxide layer 1133. In the example of Fig. 4, the first oxide layer 1131, the metal layer 1132, and the second oxide layer 1133 are stacked in this order to form the intermediate layer 113b. The first oxide layer 1131 and the metal layer 1132 are adjacent to each other, and the metal layer 1132 and the second oxide layer 1133 are adjacent to each other.

[0046] The first oxide layer 1131 or the second oxide layer 1133 may be composed of an oxide of one or more non-magnetic elements selected from, for example, Mg, Ta, Mo, W, Ti, Zr, Hf, Al, etc. The metal layer 1132 preferably contains, for example, B, and may be composed of a boride in which B is combined with a metal material selected from, for example, Co, Fe, Mo, Ti, W, etc.

[0047] The cap layer 114 is a layer that protects the other layers, and is a layer that prevents metal diffusion from, for example, wiring members. The cap layer 114 may be composed of a metal such as Cr, Ta, Ru, Au, Ag, Cu, Al, Ti, V, Mo, Zr, Hf, Re, W, Pt, Pd, Ir, or Rh. The cap layer 114 may also be composed of an alloy containing these metals or a layer made of a transition metal element. The cap layer 114 may also be composed of a stack of these metals. The cap layer 114 may also be composed of a conductive nitride such as TiN.

[0048] The magnetoresistive element 110 may include layers other than the aforementioned layers, such as a magnetic field generation layer that functions as a bias layer. The magnetic field generation layer generates a magnetic field in an in-plane direction (horizontal direction), for example. The in-plane direction is, for example, a direction perpendicular to the stacking direction (thickness direction) of the aforementioned layers. Furthermore, methods other than the magnetic field generation layer may be used to generate the magnetic field. For example, a method of providing a magnet layer above or below the magnetoresistive element 110 or a method of arranging a permanent magnet around the magnetoresistive element 110 may be used.

[0049] The various layers described above may be formed by, for example, a physical vapor deposition (PVD) method such as sputtering, ion beam deposition, or vacuum evaporation, or a chemical vapor deposition (CVD) method such as atomic layer deposition (ALD). Furthermore, the layers may be patterned by reactive ion etching (RIE), ion milling, or the like. It is preferable that the various layers are formed successively in a vacuum apparatus, and that the layers are patterned after they are formed.

[0050] As mentioned above, the basic structure of the magnetoresistive element 110 is a sandwich structure in which a nonmagnetic layer, the barrier layer 112, is sandwiched between two magnetic layers, the reference layer 111 and the storage layer 113. This structure is called a magnetic tunnel junction (MTJ). Because the nonmagnetic layer is very thin, for example, on the order of a few nanometers, a tunnel current flows when a voltage is applied across the magnetoresistive element 110. The magnitude of this tunnel current is characterized by its dependence on the relative angle between the magnetization directions of the two magnetic layers. This is called the TMR (Tunnel Magneto Resistance) effect.

[0051] The magnetization direction of one of the two magnetic layers (reference layer 111) is fixed, and the magnetization direction of the other magnetic layer (storage layer 113) is controlled by an external field. The magnetoresistive element 110 is in a low resistance state when the magnetization directions of the magnetic layers are parallel, that is, the same, and in a high resistance state when the magnetization directions of the magnetic layers are antiparallel, that is, the different. Therefore, the resistance state (resistance value) of the magnetoresistive element 110 is switched between a low resistance state (low resistance value) and a high resistance state (high resistance value), thereby writing data (e.g., 0 or 1) to the memory cell 100. Note that, for example, a method utilizing the STT effect or a method utilizing the VCMA effect can be used as the external field used to control the magnetization direction. Furthermore, for example, a method utilizing the TMR effect can be used to read data.

[0052] For example, in an STT-MRAM, the magnetization direction of the storage layer 113 is reversed by spin torque magnetization reversal. Writing is performed by applying a current to the storage layer 113 to cause spin torque magnetization reversal. That is, when a write current that flows in the stacking direction of the reference layer 111 and the storage layer 113 is applied to the magnetoresistive element 110, the magnetization direction of the storage layer 113 changes, and data is stored in the storage layer 113. Note that the magnetization direction of the reference layer 111 is fixed and is used as a reference for the data (magnetization direction) of the storage layer 113.

[0053] <1-4. Examples of Magnetoresistive Element> <1-4-1. Examples and Comparative Examples> Examples and comparative examples of the magnetoresistive element 110 according to this embodiment will be described with reference to FIGS. 5 to 9. FIG.

[0054] Fig. 5 is a diagram showing a configuration example of a magnetoresistive element 110 according to an example of this embodiment. Fig. 6 is a diagram showing a configuration example of a magnetoresistive element 110A as a comparative example according to this embodiment.

[0055] As shown in FIG. 5 , the magnetoresistive element 110 according to the example includes a reference layer 111, a barrier layer 112, a memory layer 113, and a cap layer 114, as described above. The memory layer 113 includes a first magnetic layer 113a, an intermediate layer 113b, and a second magnetic layer 113c. The intermediate layer 113b includes a first oxide layer 1131, a metal layer 1132, and a second oxide layer 1133. In this configuration, the first oxide layer 1131 is made of TaOx (TaOx layer), the metal layer 1132 is made of CoFeB (CoFeB layer), and the second oxide layer 1133 is made of MgO (MgO layer). This three-layer stacked structure is sometimes referred to as TaOx / CoFeB / MgO, for example.

[0056] 6, the magnetoresistive element 110A of the comparative example has a reference layer 111, a barrier layer 112, a memory layer 113, and a cap layer 114, similar to the above-described example. The memory layer 113 is composed of a first magnetic layer 113a, an intermediate layer 113b, and a second magnetic layer 113c. However, the intermediate layer 113b is a single layer, and the single layer of the intermediate layer 113b is made of MgO (MgO layer).

[0057] FIG. 7 shows the resistance RA (Ω·μm) of the magnetoresistive element 110 according to the example and the magnetoresistive element 110A according to the comparative example. ２ ) and the thickness (nm) of the intermediate layer 113b. Fig. 8 is a graph showing the relationship between the magnetoresistance ratio MR (%) and the thickness (nm) of the intermediate layer 113b for the magnetoresistance element 110 according to the example and the magnetoresistance element 110A according to the comparative example. Fig. 9 is a graph showing the relationship between the thermal stability index Δ and the thickness (nm) of the intermediate layer 113b for the magnetoresistance element 110 according to the example and the magnetoresistance element 110A according to the comparative example.

[0058] Graph G1a in Fig. 7, graph G1b in Fig. 8, and graph G1c in Fig. 9 are graphs relating to the magnetoresistive element 110A of the comparative example. Graph G2a in Fig. 7, graph G2b in Fig. 8, and graph G2c in Fig. 9 are graphs relating to the magnetoresistive element 110 of the example in which the TaOx layer has a thickness of 1.05 nm. Graph G3a in Fig. 7, graph G3b in Fig. 8, and graph G3c in Fig. 9 are graphs relating to the magnetoresistive element 110 of the example in which the TaOx layer has a thickness of 2.55 nm.

[0059] In the graph G1a of the comparative example shown in Fig. 7, the resistance RA (=resistance RL) gradually increases as the thickness of the intermediate layer 113b (thickness of the MgO layer) increases, and then increases sharply when the thickness exceeds 1.4 nm. In the graph G1b of the comparative example shown in Fig. 8, the magnetoresistance ratio MR tends to decrease monotonically and sharply when the thickness of the intermediate layer 113b exceeds 0.8 nm. In the graph G1c of the comparative example shown in Fig. 9, the thermal stability index Δ increases sharply as the thickness of the intermediate layer 113b increases, and then decreases when the thickness exceeds 0.8 nm.

[0060] Here, the magnetoresistance ratio MR is expressed as a magnetoresistance ratio, for example, MR=((RH-RL) / RL)×100(%), where RL is the resistance when the magnetization directions of the reference layer 111 and the memory layer 113 (the first magnetic layer 113a and the second magnetic layer 113c) are parallel, and RH is the resistance when the magnetization directions of the reference layer 111 and the memory layer 113 (the first magnetic layer 113a and the second magnetic layer 113c) are antiparallel. Note that the magnetoresistance ratio MR is the TMR ratio (tunneling magnetoresistance ratio). The TMR ratio represents the magnitude of the TMR effect (for example, the rate of change in the ease of current flow).

[0061] When the thickness of the intermediate layer 113b increases, an additional resistance Ra is superimposed on each of RH and RL, and the magnetoresistance ratio MR becomes (((RH+Ra)-(RL+Ra)) / (RL+Ra))×100(%). Therefore, as the additional resistance Ra increases, the magnetoresistance ratio MR decreases.

[0062] In the structure of the magnetoresistive element 110A of the comparative example, the thickness range of the intermediate layer 113b exhibiting a high magnetoresistance ratio (MR) is limited to a very narrow thickness range of approximately 0.55 nm to 0.7 nm, as shown in the graph G1b of the comparative example in FIG. 8 . It is difficult to control the thickness of the intermediate layer 113b within this very narrow thickness range, for example, by RF (radio frequency) sputtering using a PVD (physical vapor deposition) film formation device. Furthermore, as shown in the graph G1c of the comparative example in FIG. 9 , there are situations where the thermal stability index Δ is low. Furthermore, as described above, increasing the thickness of the intermediate layer 113b (the thickness of the MgO layer) to increase the interfacial magnetic anisotropy results in a decrease in the magnetoresistance ratio (MR).

[0063] On the other hand, in the graph G2a of the embodiment shown in FIG. 7 , the resistance RA does not increase with increasing thickness of the intermediate layer 113b, but remains almost constant, and then increases sharply when the thickness exceeds 4.2 nm. In this case, the thickness range in which the resistance RA remains almost constant is 3.4 nm or more and 4.2 nm or less. Also, in the graph G3a of the embodiment shown in FIG. 7 , the resistance RA does not increase with increasing thickness of the intermediate layer 113b, but remains almost constant, and then increases sharply when the thickness exceeds 5.7 nm. The thickness range in which the resistance RA remains almost constant is 4.9 nm or more and 5.7 nm or less. Thus, the thickness range in which the resistance RA remains almost constant can be secured as 0.8 nm, i.e., approximately 1 nm.

[0064] In the graph G1a of the comparative example and the graphs G2a and G3a of the examples, there is a thickness range in which the resistance RA is almost constant, but the thickness range of each of the graphs G2a and G3a of the examples is wider than the thickness range of the comparative example. Also, as shown in the graph G1a of the comparative example and the graphs G2a and G3a of the examples, even if the thickness of the intermediate layer 113b of the examples is several times thicker than the thickness of the intermediate layer 113b of the comparative example, the resistance RA is 10 Ω μm ２ The following is the result.

[0065] In the graph G2b of the example shown in Figure 8, the magnetoresistance ratio MR does not increase with increasing thickness of the intermediate layer 113b, but remains almost constant, and then suddenly decreases when the thickness exceeds 4.2 nm. The thickness range in which the magnetoresistance ratio MR remains constant is 3.4 nm or more and 4.2 nm or less. Furthermore, in the graph G3b of the example shown in Figure 8, the magnetoresistance ratio MR does not increase with increasing thickness of the intermediate layer 113b, but remains almost constant, and then suddenly decreases when the thickness exceeds 5.7 nm. The thickness range in which the magnetoresistance ratio MR remains almost constant is 4.9 nm or more and 5.7 nm or less. Thus, a thickness range of 0.8 nm, i.e., approximately 1 nm, can be secured as the thickness range in which the magnetoresistance ratio MR remains almost constant.

[0066] In the graph G1b of the comparative example, the magnetoresistance ratio MR is not substantially constant, but in the graphs G2b and G3b of the examples, there is a thickness range in which the magnetoresistance ratio MR is substantially constant. Furthermore, as shown in the graph G1b of the comparative example and the graphs G2b and G3b of the examples, even when the thickness of the intermediate layer 113b of the examples is several times thicker than the thickness of the intermediate layer 113b of the comparative example, the magnetoresistance ratio MR remains stable at around 190%.

[0067] In the graph G2c of the embodiment shown in Figure 9, the thermal stability index Δ does not increase as the thickness of the intermediate layer 113b increases, but remains almost constant. The thermal stability index Δ remains constant in the thickness range of 3.4 nm or more and 4.2 nm or less. Furthermore, in the graph G3c of the embodiment shown in Figure 9, the thermal stability index Δ does not increase as the thickness of the intermediate layer 113b increases, but remains almost constant. The thermal stability index Δ remains almost constant in the thickness range of 4.9 nm or more and 5.7 nm or less. In this way, a thickness range of 0.8 nm, i.e., approximately 1 nm, can be secured as the thickness range in which the thermal stability index Δ remains almost constant.

[0068] In the graph G1c of the comparative example, the thermal stability index Δ is not substantially constant, but in the graphs G2c and G3c of the examples, there is a thickness range in which the thermal stability index Δ is substantially constant. Furthermore, as shown in the graph G1c of the comparative example and the graphs G2c and G3c of the examples, even when the thickness of the intermediate layer 113b of the example is several times thicker than the thickness of the intermediate layer 113b of the comparative example, the thermal stability index Δ remains stable at around 70, which is greater than the thermal stability index Δ of the comparative example.

[0069] As described above, the thickness of the intermediate layer 113b of the magnetoresistive element 110 of the example can be made thicker than that of the magnetoresistive element 110A of the comparative example, thereby increasing the interfacial magnetic anisotropy, improving the retention characteristics (Δ), and further suppressing a decrease in the magnetoresistive ratio (MR). In particular, the magnetoresistive element 110 of the example is superior to the magnetoresistive element 110A of the comparative example in terms of the thermal stability of stored information. Furthermore, by using a configuration of the intermediate layer 113b including the first oxide layer 1131, the metal layer 1132, and the second oxide layer 1133, it is possible to provide a magnetoresistive element 110 having a wide thickness margin (film thickness margin) for the intermediate layer 113b.

[0070] In other words, as in the embodiment, by stacking and inserting the first oxide layer 1131, metal layer 1132, and second oxide layer 1133, each made of the non-magnetic layer elements, in the order listed, between the first magnetic layer 113a and the second magnetic layer 113c, it is possible to suppress the increase in resistance caused by the intermediate layer 113b (parasitic resistance in the intermediate layer 113b), achieve a high TMR ratio (MR), and achieve high retention characteristics (Δ). This allows for a relatively wide margin in the thickness of the intermediate layer 113b, making it possible to design a stable mass-production process.

[0071] <1-4-2. Thickness Range of TaOx Layer> The thickness range of the TaOx layer (first oxide layer 1131) according to the example of this embodiment will be described with reference to FIGS.

[0072] FIG. 10 shows the resistance RA (Ω·μm) of the magnetoresistive element 110 according to the example. ２11 is a graph showing the relationship between the magnetoresistance ratio MR (%) and the thickness (nm) of the TaOx layer of the magnetoresistive element 110 according to the example. Here, the behavior will be explained by fixing the thickness of the CoFeB layer (metal layer 1132) to 2.2 nm and the thickness of the MgO layer (second oxide layer 1133) to 0.54 nm.

[0073] As shown in Fig. 10, when the thickness of the TaOx layer becomes thinner than 1 nm, the resistance RA increases, and the magnetoresistance ratio MR decreases, as shown in Fig. 11. This is because, as the thickness of the TaOx layer becomes thinner in TaOx / CoFeB / MgO, the influence of the MgO layer becomes greater, and the parasitic resistance increases.

[0074] Furthermore, when the thickness of the TaOx layer exceeds 2.6 nm as shown in Fig. 10, there is no significant change in the resistance RA, but the magnetoresistance ratio MR drops sharply as shown in Fig. 11. This is because when the thickness of the TaOx layer exceeds 2.6 nm, the total thickness of the intermediate layer 113b (the thickness of TaOx / CoFeB / MgO) increases, which breaks the magnetic coupling between the first magnetic layer 113a and the second magnetic layer 113c, resulting in a drop in the magnetoresistance ratio MR and deterioration of the write characteristics.

[0075] For these reasons, it is preferable that the thickness of the TaOx layer (first oxide layer 1131) be 1.0 nm or more and 2.6 nm or less, in which case an increase in the resistance RA and a decrease in the magnetoresistance ratio MR of the magnetoresistance element 110 can be suppressed.

[0076] <1-4-3. Thickness Range of CoFeB Layer> The thickness range of the CoFeB layer (metal layer 1132) according to the example of this embodiment will be described with reference to FIGS.

[0077] FIG. 12 shows the resistance RA (Ω·μm) of the magnetoresistive element 110 according to the example. ２13 is a graph showing the relationship between the magnetoresistance ratio MR (%) and the thickness (nm) of the CoFeB layer of the magnetoresistive element 110 according to the example. Here, the behavior will be explained by fixing the thickness of the TaOx layer (first oxide layer 1131) to 2.55 nm and the thickness of the MgO layer (second oxide layer 1133) to 0.54 nm.

[0078] As shown in Fig. 12, when the thickness of the CoFeB layer is thinner than 0.5 nm, the magnetoresistance ratio MR decreases as the resistance RA increases, as shown in Fig. 13. This is because the insulating properties of the TaOx / CoFeB / MgO intermediate layer 113b gradually increase as the CoFeB thickness decreases. Furthermore, when the thickness of the CoFeB layer exceeds 3.0 nm, the CoFeB layer exhibits in-plane magnetic anisotropy, weakening the magnetic coupling between the first magnetic layer 113a and the second magnetic layer 113c and decreasing the magnetoresistance ratio MR.

[0079] For these reasons, it is preferable that the thickness of the CoFeB layer (metal layer 1132) be 0.5 nm or more and 3.0 nm or less, in which case an increase in the resistance RA and a decrease in the magnetoresistance ratio MR of the magnetoresistance element 110 can be suppressed.

[0080] <1-4-4. Thickness Range of MgO Layer> The thickness range of the MgO layer (second oxide layer 1133) according to the examples of this embodiment will be described with reference to FIGS. 14 and 15. FIG.

[0081] FIG. 14 shows the resistance RA (Ω·μm) of the magnetoresistive element 110 according to the example. ２ 15 is a graph showing the relationship between the magnetoresistance ratio MR (%) and the thickness (nm) of the MgO layer of the magnetoresistive element 110 according to the example. Here, the behavior will be explained by fixing the thickness of the TaOx layer (first oxide layer 1131) to 2.55 nm and the thickness of the CoFeB layer (metal layer 1132) to 2.2 nm.

[0082] As shown in Fig. 14, when the thickness of the MgO layer is thicker than 0.9 nm, the resistance RA increases, and as the resistance RA increases, the magnetoresistance ratio MR decreases, as shown in Fig. 15. Furthermore, when the thickness of the MgO layer is thinner than 0.18 nm, the perpendicular magnetic anisotropy of the second magnetic layer 113c weakens, and the magnetoresistance ratio MR decreases.

[0083] For these reasons, it is preferable that the thickness of the MgO layer (second oxide layer 1133) be 0.18 nm or more and 0.9 nm or less, in which case an increase in the resistance RA and a decrease in the magnetoresistance ratio MR of the magnetoresistance element 110 can be suppressed.

[0084] 1-5. Specific Examples of Intermediate Layer Specific examples of the intermediate layer 113b according to this embodiment will be described with reference to Fig. 4. Examples of the configuration of the intermediate layer 113b of the magnetoresistive element 110 shown in Fig. 4 are listed below. In the example configuration shown below, either the first oxide layer 1131 or the second oxide layer 1133 is made of MgO, and CoFeB is selected as the metal layer 1132.

[0085] (Specific Example 1: First Oxide Layer / Metal Layer / Second Oxide Layer) 1) TaOx / CoFeB / MgO (see FIG. 5) 2) MgO / CoFeB / TaOx 3) MoOx / CoFeB / MgO 4) MgO / CoFeB / MoOx 5) WOx / CoFeB / MgO 6) MgO / CoFeB / WOx 7) TiOx / CoFeB / MgO 8) MgO / CoFeB / TiOx 9) ZrOx / CoFeB / MgO 10) MgO / CoFeB / ZrOx 11) HfOx / CoFeB / MgO 12) MgO / CoFeB / HfOx 13) AlOx / CoFeB / MgO 14) MgO / CoFeB / AlOx

[0086] As materials for forming the first oxide layer 1131 or the second oxide layer 1133, the above-mentioned eight types of materials, namely TaOx, MoOx, WOx, TiOx, ZrOx, HfOx, AlOx, and MgO, are suitable, and as configuration examples for the intermediate layer 113b of the magnetoresistive element 110, when the metal layer 1132 is made of CoFeB, 64 different structures can be proposed.

[0087] (Specific Example 2: Metal Layer) When a material other than the above-mentioned CoFeB is used as the material for the metal layer 1132, the metal layer 1132 preferably contains B, and may be configured to contain at least one element selected from Co and Fe. Furthermore, in addition to B, Co, or Fe, the metal layer 1132 may contain Mo, Ti, W, etc. As an example of such a material, the following materials can be selected.

[0088] 1) CoB, CoMoB, CoTiB, CoWB 2) FeB, FeMoB, FeTiB, FeWB 3) CoFeMoB, CoFeTiB, CoFeWB

[0089] Considering the combination of the metal layer 1132 of this specific example 2 with the first oxide layer 1131 and second oxide layer 1133 described in the above-mentioned specific example 1, 8 x 12 x 8 = 768 different structures of the intermediate layer 113b can be proposed.

[0090] 1-6. Specific Examples of Insertion Positions of Magnetoresistive Element into Chip> A specific example of an insertion position of the magnetoresistive element 110 according to this embodiment into the chip 500 will be described with reference to Fig. 16. Fig. 16 is a cross-sectional view showing a specific example of an insertion position of the magnetoresistive element 110 according to this embodiment into the chip 500.

[0091] 16 , the chip 500 has a semiconductor layer 510 and multiple wiring layers 520, 530, 540, and 550. The semiconductor layer 510 and the wiring layers 520, 530, 540, and 550 constitute a part of the chip 500. The chip 500 includes a logic unit 500a and a memory unit 500b. The memory unit 500b functions as, for example, an MRAM unit. The logic unit 500a and the memory unit 500b are mounted together on, for example, one chip 500.

[0092] The semiconductor layer 510 is, for example, a silicon substrate. The wiring layer 520 is, for example, a dielectric layer including various elements 521 such as transistors and multiple wirings. The wiring layer 530 is, for example, a dielectric layer including multiple wirings such as vias 531 and multiple magnetoresistive elements 110. In other words, each magnetoresistive element 110 is provided in the wiring layer 530, and this wiring layer 530 functions as an MRAM layer. The wiring layer 540 is, for example, a dielectric layer including multiple wirings such as vias 541. The wiring layer 550 is, for example, a dielectric layer including multiple wirings such as vias 551 and a metal layer 552. Note that each magnetoresistive element 110 may be provided in a layer other than the wiring layer 530, and the stacked structure of FIG. 16 is merely an example.

[0093] <2. Second Embodiment> <2-1. Configuration Example of Magnetoresistive Element> A configuration example of a magnetoresistive element 110B according to this embodiment will be described with reference to Fig. 17. Fig. 17 is a diagram showing a configuration example of a magnetoresistive element 110B according to this embodiment. This embodiment is basically the same as the first embodiment, but differences therebetween will be described.

[0094] 17 , in the magnetoresistive element 110B according to this embodiment, the cap layer 114 has a first oxide layer 114a, a metal layer 114b, and a second oxide layer 114c. The first oxide layer 114a corresponds to the first oxide layer 1131 according to the first embodiment, the metal layer 114b corresponds to the metal layer 1132 according to the first embodiment, and the second oxide layer 114c corresponds to the second oxide layer 1133 according to the first embodiment. The memory layer 113 may be composed of one layer or multiple layers, and may be composed in the same manner as the first magnetic layer 113a or the second magnetic layer 113c, for example.

[0095] In this way, by forming the cap layer 114 by stacking the first oxide layer 114a, the metal layer 114b, and the second oxide layer 114c in this order, even if the thickness of the cap layer 114 is made relatively thick, it is possible to suppress an increase in resistance caused by the cap layer 114 (parasitic resistance of the cap layer 114), and to obtain a magnetoresistive element 110B with high magnetic anisotropy, thereby realizing a high TMR ratio (MR) and high retention characteristics (Δ). Note that the materials for each layer may be the same as those in the first embodiment, for example.

[0096] According to this embodiment, it is possible to obtain the same effects as those of the first embodiment. That is, by configuring the cap layer 114 with the first oxide layer 114 a, the metal layer 114 b, and the second oxide layer 114 c, it is possible to improve the retention characteristics and suppress the decrease in the TMR ratio.

[0097] 3. Actions and Effects of Each Embodiment As described above, according to each embodiment, the magnetoresistive element 110 (110B) includes the reference layer 111, the barrier layer 112 stacked on the reference layer 111, the memory layer 113 stacked on the barrier layer 112, and the cap layer 114 stacked on the memory layer 113. The memory layer 113 or the cap layer 114 has a first oxide layer 1131 (114a), a metal layer 1132 (114b) stacked on the first oxide layer 1131 (114a), and a second oxide layer 1133 (114c) stacked on the metal layer 1132 (114b) (see FIGS. 4 and 17 ). As a result, even if the thickness of the memory layer 113 or the cap layer 114 is increased, an increase in resistance caused by the memory layer 113 or the cap layer 114 can be suppressed, and a high retention characteristic (Δ) and a high TMR ratio (MR) can be obtained. Therefore, it is possible to improve the retention characteristics and suppress the decrease in the TMR ratio.

[0098] Furthermore, the memory layer 113 may have a first magnetic layer 113a stacked on the barrier layer 112, an intermediate layer 113b stacked on the first magnetic layer 113a, and a second magnetic layer 113c stacked on the intermediate layer 113b, and the intermediate layer 113b may have a first oxide layer 1131, a metal layer 1132, and a second oxide layer 1133 (see FIG. 4 ). This makes it possible to suppress an increase in resistance caused by the memory layer 113 even if the thickness of the memory layer 113 is increased, and to obtain a high retention characteristic (Δ) and a high TMR ratio (MR), thereby realizing an improvement in retention characteristic and suppression of a decrease in the TMR ratio.

[0099] Alternatively, the metal layer 1132 (114b) may be adjacent to the first oxide layer 1131 (114a), and the second oxide layer 1133 (114c) may be adjacent to the metal layer 1132 (114b) (see FIGS. 4 and 17). This ensures improved retention characteristics and suppression of a decrease in the TMR ratio.

[0100] The first oxide layer 1131 (114a) and the second oxide layer 1133 (114c) may be formed of an oxide containing at least one non-magnetic element selected from the group consisting of Mg, Ta, Mo, W, Ti, Zr, Hf, and Al (see FIG. 4, etc.). This ensures improved retention characteristics and suppression of a decrease in the TMR ratio.

[0101] The metal layer 1132 (114b) may also contain at least one of Co and Fe (see FIG. 4, etc.), which can reliably improve the retention characteristics and prevent a decrease in the TMR ratio.

[0102] Furthermore, the metal layer 1132 (114b) may further contain B (see FIG. 4, etc.), which can reliably improve the retention characteristics and prevent the decrease in the TMR ratio.

[0103] The metal layer 1132 (114b) may further contain at least one element selected from the group consisting of Mo, Ti, and W (see FIG. 4, etc.), which can reliably improve the retention characteristics and prevent a decrease in the TMR ratio.

[0104] The first oxide layer 1131 (114a) and the second oxide layer 1133 (114c) may be formed of oxides containing different non-magnetic elements (see FIG. 5, etc.), which can reliably improve the retention characteristics and prevent the decrease in the TMR ratio.

[0105] Alternatively, the first oxide layer 1131 (114a) may be made of TaOx, and the second oxide layer 1133 (114c) may be made of MgO (see FIG. 5, etc.), which can reliably improve retention characteristics and prevent a decrease in the TMR ratio.

[0106] The metal layer 1132 (114b) may be made of CoFeB (see FIG. 5, etc.), which can reliably improve the retention characteristics and prevent the TMR ratio from decreasing.

[0107] The thickness of the first oxide layer 1131 (114a) may be 1.0 nm or more and 2.6 nm or less (see FIGS. 10 and 11), which can suppress an increase in the resistance RA and a decrease in the magnetoresistance ratio MR of the magnetoresistance element 110 (110B).

[0108] The first oxide layer 1131 (114a) may have a thickness of 1.0 nm to 2.6 nm and may be made of TaOx (see FIGS. 10 and 11), which can reliably suppress an increase in the resistance RA and a decrease in the magnetoresistance ratio MR of the magnetoresistance element 110 (110B).

[0109] The thickness of the metal layer 1132 (114b) may be 0.5 nm or more and 3.0 nm or less (see FIGS. 12 and 13), which can suppress an increase in the resistance RA and a decrease in the magnetoresistance ratio MR of the magnetoresistance element 110 (110B).

[0110] The metal layer 1132 (114b) may have a thickness of 0.5 nm to 3.0 nm and may be made of CoFeB (see FIGS. 12 and 13), which can reliably suppress an increase in the resistance RA and a decrease in the magnetoresistance ratio MR of the magnetoresistance element 110 (110B).

[0111] The thickness of the second oxide layer 1133 (114c) may be 0.18 nm or more and 0.9 nm or less (see FIGS. 14 and 15), which can suppress an increase in the resistance RA and a decrease in the magnetoresistance ratio MR of the magnetoresistance element 110 (110B).

[0112] The second oxide layer 1133 (114c) may have a thickness of 0.18 nm to 0.9 nm and may be made of MgO (see FIGS. 14 and 15), which reliably prevents an increase in the resistance RA and a decrease in the magnetoresistance ratio MR of the magnetoresistance element 110 (110B).

[0113] The thickness of the first oxide layer 1131 (114a) may be thicker than the thickness of the second oxide layer 1133 (114c) (see FIGS. 10, 11, 14, and 15), which can suppress an increase in the resistance RA and a decrease in the magnetoresistance ratio MR of the magnetoresistive element 110 (110B).

[0114] The first oxide layer 1131 (114a) may be thicker than the second oxide layer 1133 (114c) and made of TaOx, and the second oxide layer 1133 (114c) may be made of MgO (see FIGS. 10, 11, 14, and 15). This reliably prevents an increase in the resistance RA and a decrease in the magnetoresistance ratio MR of the magnetoresistive element 110 (110B).

[0115] 4. Other Embodiments The configurations and processes according to the above-described embodiments (including examples and modified examples) may be implemented in various different forms other than the above-described embodiments. For example, the configurations and processes are not limited to the above-described examples and may be implemented in various forms. Furthermore, for example, the configurations, processing procedures, specific names, or information including various data and parameters shown in the above documents and drawings may be changed arbitrarily unless otherwise specified.

[0116] Furthermore, the components and processes according to the above-described embodiments (including examples and modifications) do not necessarily have to be physically configured as shown in the drawings. In other words, the specific form of distribution and integration of the components and processes is not limited to that shown in the drawings, and all or part of them may be functionally or physically distributed or integrated in any unit depending on various loads, usage conditions, etc.

[0117] Furthermore, the configurations and processes of the above-described embodiments (including examples and modified examples) may be combined as appropriate. For example, at least a part of an embodiment may be combined as appropriate with at least a part of another embodiment. Furthermore, the effects of the embodiments are merely examples and are not intended to be limiting, and other effects may also be obtained.

[0118] <5. Application Examples> <5-1. Various Devices> An application example of the storage device 10 according to any of the above-described embodiments will be described with reference to Fig. 18. Fig. 18 is a diagram showing an application example of the storage device 10 according to any of the above-described embodiments.

[0119] The storage device 10 according to any of the above-described embodiments may be applied to various cases where light such as visible light, infrared light, ultraviolet light, and X-rays is sensed, for example, as follows: For example, the storage device 10 may be applied to various devices (electronic devices) such as those described below, or electronic devices mounted on various devices.

[0120] As shown in FIG. 18 , the storage device 10 according to any of the above-described embodiments is used in, for example, "devices for capturing images for viewing, such as digital cameras and portable devices with camera functions," "devices for traffic use, such as in-vehicle sensors for capturing images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and for recognizing the driver's state, surveillance cameras for monitoring moving vehicles and roads, and distance measuring sensors for measuring distances between vehicles," "devices for home appliances such as TVs, refrigerators, and air conditioners for capturing images of user gestures and operating the device in accordance with the gestures," "devices for medical and healthcare use, such as endoscopes and devices for capturing blood vessel images by receiving infrared light," "devices for security use, such as surveillance cameras for crime prevention and cameras for person authentication," "devices for beauty use, such as skin measuring devices for capturing images of the skin and microscopes for capturing images of the scalp," "devices for sports use, such as action cameras and wearable cameras for sports use," and "devices for agriculture, such as cameras for monitoring the condition of fields and crops."

[0121] The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be realized as an electronic device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, a construction machine, or an agricultural machine (tractor). Furthermore, for example, the technology according to the present disclosure may be realized as an electronic device mounted on an endoscopic surgery system, a microsurgery system, or the like.

[0122] <5-2. Imaging Device> An imaging device 300 according to an application example will be described with reference to Fig. 19. Fig. 19 is a diagram showing an example of the configuration of the imaging device 300 according to an application example. This imaging device 300 is an example of an electronic device to which the storage device 10 according to any of the above-described embodiments is applied. Examples of the imaging device 300 include electronic devices such as digital still cameras, video cameras, smartphones and mobile phones with imaging functions.

[0123] 19, the imaging device 300 includes an optical system 301, a shutter device 302, an imaging element (solid-state imaging device) 303, a control circuit (drive circuit) 304, a signal processing circuit 305, a monitor 306, and a memory 307. The imaging device 300 is capable of capturing still images and moving images.

[0124] The optical system 301 includes one or more lenses. The optical system 301 guides light from a subject (incident light) to the image sensor 303, and forms an image on the light receiving surface of the image sensor 303.

[0125] The shutter device 302 is disposed between the optical system 301 and the image sensor 303. The shutter device 302 controls the light irradiation period and the light blocking period for the image sensor 303 under the control of the control circuit 304.

[0126] The image sensor 303 accumulates signal charges for a certain period of time in response to light that is focused on the light receiving surface via the optical system 301 and the shutter device 302. The signal charges accumulated in the image sensor 303 are transferred in accordance with a drive signal (timing signal) supplied from the control circuit 304. The image sensor 303 may be, for example, a solid-state image sensor.

[0127] The control circuit 304 outputs a drive signal that controls the transfer operation of the image sensor 303 and the shutter operation of the shutter device 302 , thereby driving the image sensor 303 and the shutter device 302 .

[0128] The signal processing circuit 305 performs various signal processing on the signal charges output from the image sensor 303. The image (image data) obtained by the signal processing performed by the signal processing circuit 305 is supplied to a monitor 306 and also to a memory 307.

[0129] The monitor 306 displays moving or still images captured by the image sensor 303 based on the image data supplied from the signal processing circuit 305. As the monitor 306, for example, a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel is used.

[0130] The memory 307 stores image data supplied from the signal processing circuit 305, i.e., image data of moving images or still images captured by the image sensor 303. As the memory 307, for example, the storage device 10 according to any one of the above-described embodiments is used.

[0131] Even in the imaging device 300 configured in this manner, by applying the memory device 10 according to any of the above-mentioned embodiments as the memory 307, it is possible to improve retention characteristics and suppress the decrease in the TMR ratio.

[0132] <5-3. Distance Measuring Device> A distance measuring device 400 according to an application example will be described with reference to Fig. 20. Fig. 20 is a diagram showing an example of the configuration of the distance measuring device 400 according to an application example. This distance measuring device 400 is an example of an electronic device to which the storage device 10 according to any of the above-described embodiments is applied.

[0133] 20, distance measuring device (distance image sensor) 400 includes a light source unit 401, an optical system 402, an image sensor (solid-state image sensor) 403, a control circuit (drive circuit) 404, a signal processing circuit 405, a monitor 406, and a memory 407. Distance measuring device 400 projects light from light source unit 401 toward an object and receives light (modulated light or pulsed light) reflected from the surface of the object, thereby obtaining a distance image according to the distance to the object.

[0134] The light source unit 401 projects light toward the subject. For example, a vertical cavity surface emitting laser (VCSEL) array that emits laser light as a surface light source, or a laser diode array in which laser diodes are arranged in a line, is used as the light source unit 401. The laser diode array is supported by a predetermined drive unit (not shown) and scanned in a direction perpendicular to the direction in which the laser diodes are arranged.

[0135] The optical system 402 includes one or more lenses. The optical system 402 guides light from a subject (incident light) to the image sensor 403, and forms an image on the light receiving surface (sensor portion) of the image sensor 403.

[0136] The image sensor 403 accumulates signal charges in response to light that is imaged on the light receiving surface via the optical system 402. A distance signal indicating a distance determined from a light receiving signal (APD OUT) output from the image sensor 403 is supplied to a signal processing circuit 405. As the image sensor 403, for example, a solid-state image sensor such as an image sensor is used.

[0137] The control circuit 404 outputs a drive signal (control signal) that controls the operation of the light source unit 401, the image sensor 403, and the like, thereby driving the light source unit 401, the image sensor 403, and the like.

[0138] The signal processing circuit 405 performs various signal processing on the distance signal supplied from the image sensor 403. For example, the signal processing circuit 405 performs image processing (e.g., histogram processing, peak detection processing, etc.) to construct a distance image based on the distance signal. The image (image data) obtained by the signal processing performed by the signal processing circuit 405 is supplied to a monitor 406 and also to a memory 407.

[0139] The monitor 406 displays the distance image captured by the image sensor 403 based on the image data supplied from the signal processing circuit 405. The monitor 406 may be, for example, a panel display device such as a liquid crystal panel or an organic EL panel.

[0140] The memory 407 stores image data supplied from the signal processing circuit 405, i.e., image data of the distance image captured by the image sensor 403. As the memory 407, for example, the storage device 10 according to any one of the above-described embodiments is used.

[0141] Even in the distance measuring device 400 configured in this manner, by applying the memory device 10 according to any of the above-mentioned embodiments as the memory 407, it is possible to improve the retention characteristics and suppress the decrease in the TMR ratio.

[0142] As described above, the storage device 10 according to any of the above-described embodiments can be implemented in various electronic devices. For example, the storage device 10 according to any of the above-described embodiments may be installed in various electronic devices, such as an HDD (hard disk drive), a notebook PC (personal computer), a mobile device (e.g., a smartphone or tablet PC), a PDA (personal digital assistant), a wearable device, a game device, or a music device, in addition to the imaging device 300 or the distance measuring device 400. For example, the storage device 10 may be used as various types of memory, such as storage.

[0143] <6. Supplementary Notes> The present technology may also have the following configurations. (1) A magnetoresistive element including: a reference layer; a barrier layer stacked on the reference layer; a memory layer stacked on the barrier layer; and a cap layer stacked on the memory layer, wherein the memory layer or the cap layer has: a first oxide layer, a metal layer stacked on the first oxide layer, and a second oxide layer stacked on the metal layer. (2) The magnetoresistive element according to (1), wherein the memory layer has: a first magnetic layer stacked on the barrier layer; an intermediate layer stacked on the first magnetic layer; and a second magnetic layer stacked on the intermediate layer, wherein the intermediate layer has: the first oxide layer, the metal layer, and the second oxide layer. (3) The magnetoresistive element according to (1) or (2), wherein the metal layer is adjacent to the first oxide layer, and the second oxide layer is adjacent to the metal layer. (4) The magnetoresistive element according to any one of (1) to (3), wherein the first oxide layer and the second oxide layer are formed of an oxide containing at least one nonmagnetic element selected from the group consisting of Mg, Ta, Mo, W, Ti, Zr, Hf, and Al. (5) The magnetoresistive element according to any one of (1) to (4), wherein the metal layer contains at least one element selected from the group consisting of Co and Fe. (6) The magnetoresistive element according to (5), wherein the metal layer further contains B. (7) The magnetoresistive element according to (5) or (6), wherein the metal layer further contains at least one element selected from the group consisting of Mo, Ti, and W. (8) The magnetoresistive element according to any one of (1) to (7), wherein the first oxide layer and the second oxide layer are formed of oxides containing different nonmagnetic elements. (9) The magnetoresistive element according to (8), wherein the first oxide layer is made of TaOx, and the second oxide layer is made of MgO. (10) The magnetoresistive element according to (9), wherein the metal layer is made of CoFeB. (11) The magnetoresistive element according to any one of (1) to (10), wherein the thickness of the first oxide layer is 1.0 nm or more and 2.6 nm or less.(12) The magnetoresistive element according to (11), wherein the first oxide layer is formed of TaOx. (13) The magnetoresistive element according to any one of (1) to (12), wherein the thickness of the metal layer is 0.5 nm or more and 3.0 nm or less. (14) The magnetoresistive element according to (13), wherein the metal layer is formed of CoFeB. (15) The magnetoresistive element according to any one of (1) to (14), wherein the thickness of the second oxide layer is 0.18 nm or more and 0.9 nm or less. (16) The magnetoresistive element according to (15), wherein the second oxide layer is formed of MgO. (17) The magnetoresistive element according to any one of (1) to (16), wherein the thickness of the first oxide layer is greater than the thickness of the second oxide layer. (18) The magnetoresistive element according to (17), wherein the first oxide layer is made of TaOx, and the second oxide layer is made of MgO. (19) A storage device comprising: a magnetoresistive element comprising: a reference layer, a barrier layer stacked on the reference layer, a memory layer stacked on the barrier layer, and a cap layer stacked on the memory layer, and the memory layer or the cap layer has: a first oxide layer, a metal layer stacked on the first oxide layer, and a second oxide layer stacked on the metal layer. (20) An electronic device comprising a memory device having a magnetoresistive element, wherein the magnetoresistive element comprises: a reference layer, a barrier layer stacked on the reference layer, a memory layer stacked on the barrier layer, and a cap layer stacked on the memory layer, and the memory layer or the cap layer has: a first oxide layer, a metal layer stacked on the first oxide layer, and a second oxide layer stacked on the metal layer. (21) A memory device comprising the magnetoresistive element according to any one of (1) to (18). (22) An electronic device comprising the memory device according to (21).

[0144] 10 Memory device 11 Memory cell array 20 Peripheral circuit 21 I / O 22 Control circuit 23 Voltage generation circuit 24 Write circuit 25 Read circuit 26 Bit line address decoder 27 Bit line control circuit 28 Word line address decoder 29 Word line control circuit 30 Sense amplifier 100 Memory cell 101 Wiring 102 Wiring 103 Contact layer 104 Contact layer 110 Magnetoresistance element 111 Reference layer 112 Barrier layer 113 Storage layer 113a First magnetic layer 113b Intermediate layer 113c Second magnetic layer 1131 First oxide layer 1132 Metal layer 1133 Second oxide layer 114 Cap layer 114a First oxide layer 114b Metal layer 114c Second oxide layer 120 Selection element 300 Imaging device 307 Memory 400 Range finder 407 Memory SL Source line WL Word line

Claims

1. A magnetoresistive element comprising: a reference layer; a barrier layer stacked on the reference layer; a memory layer stacked on the barrier layer; and a cap layer stacked on the memory layer, wherein the memory layer or the cap layer has a first oxide layer, a metal layer stacked on the first oxide layer, and a second oxide layer stacked on the metal layer.

2. A magnetoresistive element as described in claim 1, wherein the memory layer has a first magnetic layer stacked on the barrier layer, an intermediate layer stacked on the first magnetic layer, and a second magnetic layer stacked on the intermediate layer, and the intermediate layer has the first oxide layer, the metal layer, and the second oxide layer.

3. The magnetoresistive element of claim 1, wherein the metal layer is adjacent to the first oxide layer, and the second oxide layer is adjacent to the metal layer.

4. The magnetoresistance element according to claim 1, wherein the first oxide layer and the second oxide layer are formed from an oxide containing at least one nonmagnetic element selected from the group consisting of Mg, Ta, Mo, W, Ti, Zr, Hf and Al.

5. The magnetoresistance element according to claim 1, wherein the metal layer contains at least one element selected from the group consisting of Co and Fe.

6. The magnetoresistive element according to claim 5, wherein the metal layer further contains B.

7. The magnetoresistance element according to claim 5, wherein the metal layer further contains at least one element selected from the group consisting of Mo, Ti and W.

8. The magnetoresistance element according to claim 1, wherein the first oxide layer and the second oxide layer are formed of oxides containing different nonmagnetic elements.

9. The magnetoresistance element according to claim 8, wherein the first oxide layer is made of TaOx, and the second oxide layer is made of MgO.

10. The magnetoresistance element according to claim 9, wherein the metal layer is formed of CoFeB.

11. The magnetoresistive element according to claim 1, wherein the thickness of the first oxide layer is not less than 1.0 nm and not more than 2.6 nm.

12. The magnetoresistance element according to claim 11, wherein the first oxide layer is made of TaOx.

13. The magnetoresistance element according to claim 1, wherein the thickness of the metal layer is not less than 0.5 nm and not more than 3.0 nm.

14. The magnetoresistive element according to claim 13, wherein the metal layer is formed of CoFeB.

15. The magnetoresistance element according to claim 1, wherein the thickness of the second oxide layer is not less than 0.18 nm and not more than 0.9 nm.

16. The magnetoresistance element according to claim 15, wherein the second oxide layer is made of MgO.

17. The magnetoresistive element of claim 1, wherein the thickness of said first oxide layer is greater than the thickness of said second oxide layer.

18. The magnetoresistance element according to claim 17, wherein the first oxide layer is made of TaOx, and the second oxide layer is made of MgO.

19. A memory device comprising a magnetoresistive element, the magnetoresistive element comprising: a reference layer; a barrier layer stacked on the reference layer; a memory layer stacked on the barrier layer; and a cap layer stacked on the memory layer, the memory layer or the cap layer having a first oxide layer, a metal layer stacked on the first oxide layer, and a second oxide layer stacked on the metal layer.

20. An electronic device comprising: a memory device having a magnetoresistive element, the magnetoresistive element comprising: a reference layer; a barrier layer stacked on the reference layer; a memory layer stacked on the barrier layer; and a cap layer stacked on the memory layer, the memory layer or the cap layer having: a first oxide layer; a metal layer stacked on the first oxide layer; and a second oxide layer stacked on the metal layer.

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