Two-stage cascade decision device, decision feedback equalizer and wired receiver

Abstract

Disclosed in the present application are a two-stage cascade decision device, a decision feedback equalizer and a wired receiver, which improve the speed of a decision device. A first-stage circuit of the two-stage cascade decision device is a strong-arm decision device. A second-stage circuit comprises four PMOS transistors M9, M10, M18, M19 and three NMOS transistors M17, M20, M21, wherein source electrodes of M9, M10, M18 and M19 are all connected to a power supply; gate electrodes of M19 and M18 are connected to a first output end MN and a second output end MP of the strong-arm decision device, respectively; gate electrodes of M17, M9 and M10 all receive clock signals; drain electrodes of M9, M18 and M20 and a gate electrode of M21 are all connected to a first output end ON of the second-stage circuit; drain electrodes of M10, M19 and M21 and a gate electrode of M20 are all connected to a second output end OP of the second-stage circuit; source electrodes of M20 and M21 and a drain electrode of M17 are connected together; and a source electrode of M17 is grounded.

Description

Two-stage cascade decision maker, decision feedback equalizer and wired receiver

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on November 1, 2023, with application number 2023114410621 and application name “A two-stage cascaded decider, decision feedback equalizer and wired receiver”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the technical field of integrated circuits, and more particularly to a two-stage cascaded decision maker, a decision feedback equalizer and a wired receiver. Background Art

[0003] Decision makers, also known as comparators, are widely used in mixed-signal circuits and systems, such as analog-to-digital converters, adaptive configuration loops, memories, and wired receivers. The speed of these decision makers has a crucial impact on the performance of the entire mixed-signal circuit or system. Maximizing decision maker speed is a constant goal in this field.

[0004] Summary of the Invention

[0005] In view of this, the present invention provides a two-stage cascaded decider, a decision feedback equalizer and a wired receiver to increase the rate of the decider.

[0006] A two-stage cascaded decision maker, wherein:

[0007] The first stage circuit of the two-stage cascade decision maker is a strong-arm decision maker;

[0008] The second stage circuit of the two-stage cascade decision device includes: a PMOS tube M9, a PMOS tube M10, an NMOS tube M17, a PMOS tube M18, a PMOS tube M19, an NMOS tube M20 and an NMOS tube M21;

[0009] Wherein, the source of the PMOS transistor M9, the source of the PMOS transistor M10, the source of the PMOS transistor M18 and the source of the PMOS transistor M19 are all connected to a power supply;

[0010] The gate of the PMOS transistor M19 is connected to the first output terminal MN of the strong-arm decision maker; the gate of the PMOS transistor M18 is connected to the second output terminal MP of the strong-arm decision maker;

[0011] The gate of the NMOS transistor M17, the gate of the PMOS transistor M9 and the gate of the PMOS transistor M10 all receive a clock signal CLK;

[0012] The drain of the PMOS transistor M9, the drain of the PMOS transistor M18, the drain of the NMOS transistor M20, and the gate of the NMOS transistor M21 are all connected to the first output terminal ON of the second-stage circuit;

[0013] The drain of the PMOS transistor M10, the drain of the PMOS transistor M19, the drain of the NMOS transistor M21, and the gate of the NMOS transistor M20 are all connected to the second output terminal OP of the second-stage circuit;

[0014] The source of the NMOS transistor M20, the source of the NMOS transistor M21, and the drain of the NMOS transistor M17 are connected together;

[0015] The source of the NMOS transistor M17 is grounded.

[0016] Optionally, the strong-arm decision maker includes: NMOS tube M1, NMOS tube M2, NMOS tube M3, NMOS tube M4, PMOS tube M5, PMOS tube M6, PMOS tube M7, PMOS tube M8, PMOS tube M11, NMOS tube M12, PMOS tube M13, NMOS tube M14, NMOS tube M15 and NMOS tube M16;

[0017] The source of the PMOS transistor M5, the source of the PMOS transistor M13, the source of the PMOS transistor M11, the source of the PMOS transistor M7, the source of the PMOS transistor M6, and the source of the PMOS transistor M8 are all connected to the power supply;

[0018] The gate of the PMOS transistor M5, the gate of the PMOS transistor M6, the gate of the PMOS transistor M7, the gate of the PMOS transistor M8, the gate of the NMOS transistor M15, and the gate of the NMOS transistor M16 all receive the clock signal CLK;

[0019] The drain of the PMOS transistor M5, the drain of the PMOS transistor M13, the drain of the NMOS transistor M14, the gate of the PMOS transistor M11 and the gate of the NMOS transistor M12 are all connected to the first output terminal MN of the strong-arm decision device;

[0020] The gate of the PMOS transistor M13, the gate of the NMOS transistor M14, the drain of the PMOS transistor M11, and the drain of the PMOS transistor M7 are all connected to the second output terminal MP of the strong-arm decision device;

[0021] The drain of the PMOS transistor M6, the source of the NMOS transistor M14, the drain of the NMOS transistor M1, and the drain of the NMOS transistor M4 are connected to a point N;

[0022] The source of the NMOS transistor M12, the drain of the PMOS transistor M8, the drain of the NMOS transistor M2, and the drain of the NMOS transistor M3 are connected to a point P;

[0023] The gate of the NMOS transistor M3 and the gate of the NMOS transistor M4 are connected to the first pair of differential input terminals of the strong-arm decision device, for receiving a reference voltage Vref;

[0024] The gate of the NMOS transistor M1 and the gate of the NMOS transistor M2 are connected to the second pair of differential input terminals of the strong-arm decision maker for receiving differential input signals; the second pair of differential input terminals includes a first terminal VIP and a second terminal VIN, the gate of the NMOS transistor M1 is connected to the first terminal VIP; the gate of the NMOS transistor M2 is connected to the second terminal VIN;

[0025] The source of the NMOS tube M1 and the source of the NMOS tube M3 are connected to the drain of the NMOS tube M15;

[0026] The source of the NMOS transistor M4 and the source of the NMOS transistor M2 are connected to the drain of the NMOS transistor M16;

[0027] The source of the NMOS transistor M15 and the source of the NMOS transistor M16 are both grounded.

[0028] Optionally, when the rising edge of the clock signal CLK arrives, the voltages of the first output terminal ON and the second output terminal OP of the second stage circuit are both pulled down to 0.5 times VDD; VDD is the voltage of the power supply.

[0029] Optionally, the body bias voltages of the PMOS transistor M5, PMOS transistor M6, PMOS transistor M7, PMOS transistor M8, PMOS transistor M9, PMOS transistor M10, NMOS transistor M17, NMOS transistor M20, NMOS transistor M21, NMOS transistor M1, NMOS transistor M2, NMOS transistor M3, and NMOS transistor M4 are all 0V;

[0030] The body bias voltages of the PMOS transistors M11, M13, M18, and M19 are all -2V;

[0031] The body bias voltages of the NMOS transistors M15, M16, M12 and M14 are all +2V.

[0032] Optionally, the strong-arm decision maker includes: NMOS transistor Q1, NMOS transistor Q2, NMOS transistor Q3, NMOS transistor Q4, PMOS transistor Q5, PMOS transistor Q6, PMOS transistor Q7, PMOS transistor Q8 and NMOS transistor Q9;

[0033] Wherein, the source of the PMOS transistor Q5, the source of the PMOS transistor Q6, the source of the PMOS transistor Q7 and the source of the PMOS transistor Q8 are all connected to the power supply;

[0034] The gate of the PMOS transistor Q7, the gate of the PMOS transistor Q8 and the gate of the NMOS transistor Q9 all receive the clock signal CLK;

[0035] The drain of the PMOS transistor Q7, the drain of the PMOS transistor Q5, the drain of the NMOS transistor Q3, the gate of the PMOS transistor Q6 and the gate of the NMOS transistor Q4 are all connected to the first output terminal MN of the strong-arm decision device;

[0036] The gate of the PMOS transistor Q5, the gate of the NMOS transistor Q3, the drain of the PMOS transistor Q6, the drain of the NMOS transistor Q4 and the drain of the PMOS transistor Q8 are all connected to the second output terminal MP of the strong-arm decision device;

[0037] The gate of the NMOS transistor Q1 and the gate of the NMOS transistor Q2 are connected to a pair of differential input terminals of the strong-arm decision maker; the differential input terminals include a first terminal VIP and a second terminal VIN, the gate of the NMOS transistor Q2 is connected to the first terminal VIP; the gate of the NMOS transistor Q1 is connected to the second terminal VIN;

[0038] The source of the NMOS transistor Q3 is connected to the drain of the NMOS transistor Q1; the source of the NMOS transistor Q4 is connected to the drain of the NMOS transistor Q2;

[0039] The source of the NMOS transistor Q1, the source of the NMOS transistor Q2, and the drain of the NMOS transistor Q9 are connected together;

[0040] The source of the NMOS transistor Q9 is grounded.

[0041] A decision feedback equalizer includes: any one of the two-stage cascade decision devices disclosed above.

[0042] A wired receiver includes: any one of the decision feedback equalizers disclosed above.

[0043] It can be seen from the above technical solution that the present invention adds a circuit after the strong-arm decider to form a two-stage cascade decider. The second-stage circuit isolates the large load for the first-stage circuit, and the first-stage circuit provides an input signal with a larger swing for the second-stage circuit. The total gain of the two-stage cascade decider is the product of the gains of the first-stage circuit and the second-stage circuit. The full-swing output can be achieved within a shorter decision delay, thereby improving the decision speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0045] FIG1 is a circuit diagram of a two-stage cascade decision maker disclosed in an embodiment of the present invention;

[0046] FIG2 is a circuit diagram of a strong-arm decision maker disclosed in an embodiment of the present invention;

[0047] FIG3 is a comparison diagram of simulation waveforms of a two-stage cascaded decision device and a strong-arm decision device disclosed in an embodiment of the present invention;

[0048] FIG4 is a schematic diagram of the current path of the two-stage cascade decision device shown in FIG1 in the pre-amplification stage;

[0049] FIG5 is a schematic diagram of the current path of the two-stage cascade decision device shown in FIG1 during the re-amplification stage;

[0050] FIG6 is a schematic diagram of the current path of the two-stage cascade decision device shown in FIG1 during the regeneration stage;

[0051] FIG7 is a graph showing the relationship between the decision delay and the body bias voltage;

[0052] Figure 8a shows the decision circuit with load capacitance C L =20fF, as the input signal amplitude drops from 20mV to 5mV, the decision device output signal waveform;

[0053] FIG8b is a waveform diagram of the output signal of the decision maker when the input signal swing Vin=10mV and the load capacitance increases from 10fF to 20fF;

[0054] FIG9a is a graph showing the change in decision delay of the decision device with the swing of the input signal;

[0055] FIG9 b is a graph showing the change in the decision delay of the decision device with the capacitance of the load capacitor. DETAILED DESCRIPTION

[0056] For the purpose of reference and clarity, the technical terms, abbreviations or acronyms used below are summarized as follows:

[0057] Strong arm judge: Strong ARM comparator;

[0058] MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor, Metal Oxide Semiconductor Field Effect Transistor, referred to as MOS tube;

[0059] NMOS tube: N-type MOSFET;

[0060] PMOS tube: P-type MOSFET;

[0061] FDSOI: Fully Depleted Silicon on Insulator, fully depleted silicon on insulator;

[0062] PWELL: P well;

[0063] NWELL: N-well;

[0064] CMOS: Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor;

[0065] DFE: Decision Feedback Equalization, decision feedback equalizer.

[0066] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0067] 1 , an embodiment of the present invention discloses a two-stage cascade decision maker. The circuit structures of the first and second stage circuits are described in detail below:

[0068] 1) First-stage circuit

[0069] The first stage circuit of the two-stage cascade decision maker is a strong-arm decision maker, which has the advantages of simple circuit structure, no static power consumption, and the ability to generate rail-to-rail output swing.

[0070] Still referring to FIG1 , the strong-arm decision maker may include: an NMOS transistor M1, an NMOS transistor M2, an NMOS transistor M3, an NMOS transistor M4, a PMOS transistor M5, a PMOS transistor M6, a PMOS transistor M7, a PMOS transistor M8, a PMOS transistor M11, an NMOS transistor M12, a PMOS transistor M13, an NMOS transistor M14, an NMOS transistor M15, and an NMOS transistor M16;

[0071] Among them, the source of M5, the source of M13, the source of M11, the source of M7, the source of M6 and the source of M8 all receive the power supply voltage VDD;

[0072] The gates of M5, M6, M7, M8, M15 and M16 are all connected to the clock signal input terminal of the strong arm decision maker, namely the CLK terminal;

[0073] The drain of M5, the drain of M13, the drain of M14, the gate of M11 and the gate of M12 are all connected to the first output terminal MN of the strong-arm decision maker;

[0074] The gate of M13, the gate of M14, the drain of M11 and the drain of M7 are all connected to the second output terminal MP of the strong-arm decision maker;

[0075] The drain of M6, the source of M14, the drain of M1 and the drain of M4 are connected to a point N;

[0076] The source of M12, the drain of M8, the drain of M2 and the drain of M3 are connected to a point P;

[0077] The gate of M3 and the gate of M4 are connected to the first pair of differential input terminals of the strong-arm decision maker, for receiving a reference voltage Vref;

[0078] The gate of M1 and the gate of M2 are connected to the second pair of differential input terminals of the strong-arm decision maker for receiving differential input signals; the second pair of differential input terminals includes a VIP terminal and a VIN terminal, the gate of M1 is connected to the VIP terminal; the gate of M2 is connected to the VIN terminal;

[0079] The source of M1 and the source of M3 are connected to the drain of M15;

[0080] The source of M4 and the source of M2 are connected to the drain of M16;

[0081] The source of M15 and the source of M16 are both grounded.

[0082] Alternatively, the strong-arm decision maker may also adopt the circuit structure shown in FIG2 , including: NMOS transistor Q1 , NMOS transistor Q2 , NMOS transistor Q3 , NMOS transistor Q4 , PMOS transistor M5 , PMOS transistor M6 , PMOS transistor M7 , PMOS transistor M8 and NMOS transistor M9 ;

[0083] Among them, the source of Q5, the source of Q6, the source of Q7 and the source of Q8 are all connected to the power supply voltage;

[0084] The gates of Q7, Q8 and Q9 are all connected to the CLK terminal;

[0085] The drain of Q7, the drain of Q5, the drain of Q3, the gate of Q6 and the gate of Q4 are all connected to the first output terminal MN of the strong-arm decision maker;

[0086] The gate of Q5, the gate of Q3, the drain of Q6, the drain of Q4 and the drain of Q8 are all connected to the second output terminal MP of the strong-arm decision maker;

[0087] The gates of Q1 and Q2 are connected to a pair of differential input terminals of the strong-arm decision maker; the differential input terminals include an INP terminal and an INN terminal, the gate of Q2 is connected to the INP terminal; the gate of Q1 is connected to the INN terminal;

[0088] The source of Q3 is connected to the drain of Q1; the source of Q4 is connected to the drain of Q2;

[0089] The source of Q1, the source of Q2, and the drain of Q9 are connected together;

[0090] The source of Q9 is grounded.

[0091] The strong-arm determinators shown in Figures 1 and 2 are both capable of converting the smaller voltage difference between the VIP and VIN terminals into a larger voltage difference between the MP and MN terminals. The main difference between the strong-arm determinators shown in Figures 1 and 2 is that the strong-arm determinator shown in Figure 1 is constructed based on a dual-path differential signaling scheme. It compares the differential input signal with the reference voltage Vref and outputs a binary signal of 0 or 1 based on the comparison result. The strong-arm determinator shown in Figure 2 is constructed based on a single-path differential signaling scheme. It compares the voltages of two ground-relative signals and outputs a binary signal of 0 or 1 based on the comparison result. In specific applications, the choice of which strong-arm determinator to use can be determined based on actual needs.

[0092] 2) Second stage circuit

[0093] The second stage circuit of the two-stage cascade decision device includes: a PMOS transistor M9, a PMOS transistor M10, an NMOS transistor M17, a PMOS transistor M18, a PMOS transistor M19, an NMOS transistor M20 and an NMOS transistor M21;

[0094] Among them, the source of M9, the source of M10, the source of M18 and the source of M19 are all connected to the power supply voltage VDD;

[0095] The gate of M19 is connected to the first output terminal MN of the strong arm judge; the gate of M18 is connected to the second output terminal MP of the strong arm judge;

[0096] The gates of M17, M9 and M10 are all connected to the CLK terminal;

[0097] The drain of M9, the drain of M18, the drain of M20 and the gate of M21 are all connected to the first output terminal ON of the second stage circuit;

[0098] The drain of M10, the drain of M19, the drain of M21, and the gate of M20 are all connected to the second output terminal OP of the second stage circuit; the ON terminal and the OP terminal form a pair of differential output terminals, and the voltage difference between the ON terminal and the OP terminal is the output voltage VOUT of the two-stage cascade decision device;

[0099] The source of M20, the source of M21, and the drain of M17 are connected together;

[0100] The source of M17 is grounded.

[0101] The following description is based on the two-stage cascade decision device shown in Figure 1 as an example. The second pair of differential input terminals (VIP and VIN terminals) of the two-stage cascade decision device receives the differential input signal, i.e., the signal to be compared, and the first pair of differential input terminals receives the reference voltage Vref. After the CLK terminal, the first pair of differential input terminals, and the second pair of differential input terminals are all input with signals, the working process of the two-stage cascade decision device is divided into four stages: pre-charge, pre-amplification, re-amplification, and regeneration, which correspond to stages ①, ②, ③, and ④ in Figure 3, respectively. The MPTSS, MNTSS, OPTSS, and ONTSS curves in Figure 3 represent the curves of the MP, MN, OP, and ON node voltages in the two-stage cascade decision device over time, respectively. The t in Figure 3 A1_TSS , t A2_TSS , t latch_TSS They respectively represent the pre-amplification delay (i.e., the duration of the pre-amplification stage), the re-amplification delay (i.e., the duration of the re-amplification stage), and the regeneration delay (i.e., the duration of the regeneration stage) of the two-stage cascaded decision device; the CLK curve in FIG3 represents the curve of the CLK terminal voltage changing with time; the OPSAS and ONSAS curves in FIG3 respectively represent the curves of the OP and ON node voltages changing with time when the strong-arm decision device shown in FIG1 is applied alone (i.e., without connecting the second-stage circuit, the strong-arm decision device applied alone will be referred to as SAS hereinafter), t A_SAS , t lathc_SAS These are the amplification delay and regeneration delay of the SAS (the SAS has three stages: pre-charging, amplification, and regeneration. This is prior art and will not be described in detail in this article). The following details the operating principles of the four stages of the two-stage cascaded decision maker (the following analysis is based on the example of equal threshold voltages for all NMOS transistors and all PMOS transistors. In reality, due to factors such as process technology, it is impossible to achieve equal threshold voltages for all NMOS transistors / all PMOS transistors, but this does not affect the following principle derivation):

[0102] 1) Pre-charge stage

[0103] When the CLK terminal is low, the two-stage cascaded decision maker enters the pre-charge stage. In the pre-charge stage, the gate-source voltage of M15 to M17 is 0, which is less than the NMOS threshold voltage V THN , so M15~M17 are turned off; the gate-source voltage of M5~M10 is -VDD, and its absolute value is greater than the absolute value of the PMOS tube threshold voltage |V THP |, so M5~M10 are turned on; the power supply charges the six nodes N, P, MN, MP, ON, and OP to the power supply voltage VDD through M5~M10 (these six nodes all have load capacitance, and charging a node means charging the load capacitance of the node).

[0104] 2) Pre-amplification stage

[0105] When the clock signal CLK rises (CLK is high, corresponding to VDD), M5~M10 are turned off, and the two-stage cascade decision maker enters the pre-amplification stage, while M15~M17 are turned on. The input of the comparison signal and the reference voltage Vref causes M1~M4 to turn on; after M17 is turned on, the gate-source voltage of M20~M21 is greater than V THN , so M20~M21 is turned on; M11~M14 remains in the off state. At this time, the four nodes N, P, ON, and OP begin to discharge to ground, and the two nodes MP and MN still maintain the power supply voltage VDD; assuming Vref is equal to 0V, since the larger the gate voltage of the NMOS tube, the stronger its discharge ability, so in the process of the N and P nodes discharging to ground, the discharge speed of the N node relative to the P node is determined by the voltage of the VIP terminal relative to the VIN terminal.

[0106] If the N node discharges faster than the P node (Figure 3 takes the N node discharge speed as an example), the N node voltage drops to VDD-V before the P node voltage. THN ; When the voltage at the N node drops to VDD-V THN When M14 is turned on (because the gate-source voltage of M14 is equal to the difference between the MP node voltage and the N node voltage, and the MP node voltage is equal to the power supply voltage VDD, when the N node voltage drops to VDD-V THN When the gate-source voltage of M14 is equal to VDD-(VDD-V THN )=V THN , so M14 will be turned on), at this time the MN node begins to discharge to the ground; then, when the P node voltage also drops to VDD-V THNWhen , M12 also turns on, and node MP begins to discharge to ground. Because node MN begins discharging earlier and faster than node MP, the voltage at node MN is lower than that at node MP. This converts the smaller voltage difference between VIP and VIN into a larger voltage difference between MN and MP. The principle behind the faster discharge of node P than node N is similarly explained and will not be elaborated on here.

[0107] At the same time, during the discharge of ON and OP nodes to the ground, since the gate voltages of M20 to M21 are equal, the discharge speeds of ON and OP nodes are consistent. When the voltages of ON and OP nodes drop to a certain value V Q When (V Q As shown in Figure 3, M20-M21 enter and maintain the critical off state. In the pre-amplification stage, the final current path of the two-stage cascaded decision device is shown in black lines in Figure 4, and the gray lines in Figure 4 indicate open circuits.

[0108] It should be noted that the pre-amplification delay t A1_TSS is the load capacitance C of the MN and MP nodes M The discharge delay is expressed as: t A1_TSS =2C M ×|V THP | / I tail1 (1)

[0109] Among them, I tail1 is the tail current, that is, the current flowing through M15 / M16, V THP is the threshold voltage of the PMOS tube. It can be seen from the formula that the pre-amplification delay is proportional to the load capacitance. The size of the load capacitance is determined by the application scenario of the decider. For example, when the decider is used in a four-way time-interleaved DFE, the load capacitance mainly includes the parasitics of the long connection in the feedback loop, the parasitic capacitance of the MOS tube at the output node of the decider, and the capacitance of the tap input tube. Compared with SAS, the embodiment of the present invention uses the second-stage circuit to isolate the large load for the strong-arm decider, so that the load of the first-stage circuit is only the gate capacitance of the input tube of the second-stage circuit and the parasitics of the short metal connection between the two-stage circuit, thereby greatly reducing the load of the first-stage circuit and further reducing its pre-amplification delay.

[0110] Formula 1 is a well-known formula. For details, please refer to the following literature: S. Babayan-Mashhadi at al., "Analysis and design of a low-voltage low-power double-tail comparator," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 2, pp. 343-352, Feb. 2014.

[0111] 3) Re-amplification stage

[0112] If the N node discharges faster than the P node, the voltage of the MN node drops to VDD-V before the MP node during the discharge process of the MN and MP nodes. THP ; When the voltage at the MN node drops to VDD-V THP When , M11 and M19 will be turned on, M19 will charge the OP node, and the two-stage cascaded decision device will enter the re-amplification stage.

[0113] When the MP node also drops to VDD-V THP When M13 and M18 are turned on, the power supply charges the ON node through M18. The charging current difference between the ON node and the OP node is determined by the output voltage difference of the first-stage circuit. At this time, the second-stage circuit converts the voltage difference between the MN and MP nodes into a larger voltage difference between the ON and OP nodes. Therefore, the total gain of the two-stage cascade decision device is the product of the gains of the first-stage circuit and the second-stage circuit. Compared with SAS, this helps to obtain a larger output signal swing in the same time.

[0114] At the same time, after M11 turns on, the power supply charges the MP node through M11, causing the MP node voltage to drop and then rise, ultimately turning off M13 and M18. The MN node only has a discharge path, causing the MN node voltage to drop rapidly. Turning off M12 now leaves the MP node only a charge path, causing the MP node voltage to rise rapidly. The voltage difference between the MN and MP nodes increases exponentially (i.e., the input signal of the second-stage circuit increases exponentially), which helps reduce the re-amplification delay.

[0115] During the re-amplification phase, the final current path of the two-stage cascaded decision block is shown in black in Figure 5, while the gray line in Figure 5 indicates an open circuit. Ultimately, the MP node is pulled up, the MN node is pulled down, and the small differential input signal between the VIN and VIP terminals is amplified into a larger voltage difference between the ON and OP nodes.

[0116] 4) Regeneration stage

[0117] Since M19 is turned on before M18 to charge the OP node in the re-amplification stage, and the charging current of the OP node is greater than that of the ON node, M20 is turned on. At this time, the two-stage cascade decision maker enters the regeneration stage. M20 quickly pulls the ON node voltage down to ground, M21 is turned off, and the power supply quickly charges the OP node to the power supply voltage VDD through M19, completing the regeneration process. At this time, the current path in the two-stage cascade decision maker is shown as the black line in Figure 6, and the gray line in Figure 6 indicates a circuit break.

[0118] It should be noted that in the pre-amplification stage, M18-M19 remain off, so the output nodes ON and OP are pulled down to the voltage V at the same speed. Q , by designing the size of each MOSFET, V Q = VDD / 2, the second-stage circuit is in a critical regeneration state. The second-stage circuit output differential voltage is charged from VDD / 2 to VDD, or discharged from VDD / 2 to ground. This prevents the second-stage circuit output differential voltage from discharging from VDD to ground, or charging from ground to VDD, which helps reduce regeneration delay. Furthermore, as shown in Figure 3, if the differential output swing reaches VDD / 2 as the decision completion criterion, the decision delay of this two-stage cascaded decision maker is significantly shorter than that of the SAS.

[0119] In summary, the decision delay of a two-stage cascaded decision maker consists of three parts: pre-amplification delay, re-amplification delay, and regeneration delay. The key points of reducing decision delay in a two-stage cascaded decision maker include: first, the second-stage circuit isolates the large load from the first-stage circuit, effectively reducing the first-stage circuit's pre-amplification delay; the first-stage circuit provides the second-stage circuit with a larger input voltage swing, which helps reduce re-amplification delay; second, the total gain of the decision maker is the product of the two-stage gains, which helps achieve full-swing output in a shorter time; and third, during the pre-amplification phase, the second-stage circuit's output node simultaneously discharges to VDD / 2, which helps the second-stage circuit quickly enter the regeneration phase and reduces regeneration delay.

[0120] FDSOI devices with ultra-thin buried oxide layers are known to exhibit body biasing. Body biasing is a technique that allows the threshold voltage of P-type and N-type MOS transistors to be altered by applying a voltage to the body. There are two body bias modes: forward body bias (FBB), which applies a positive voltage to the N-type MOS transistor body or a negative voltage to the P-type MOS transistor body to lower the MOS transistor threshold voltage, achieving higher drive capability and faster switching speed; and reverse body bias (RBB), which applies a negative voltage to the N-type MOS transistor body or a positive voltage to the P-type MOS transistor body to increase the MOS transistor threshold voltage and reduce leakage current. Due to the unique structure of FDSOI devices, the body bias range is not limited by latch-up effects, extending to -2V to +2V, with a control accuracy of 70mV / V.

[0121] For the two-stage cascade decision maker shown in FIG1 , in order to verify the influence of the body bias effect on the decision delay of the two-stage cascade decision maker, simulation verification can be performed based on the control variable method. The simulation results are shown in FIG7 , which is a corresponding relationship diagram between the decision delay and the body bias voltage.

[0122] Optionally, for the two-stage cascaded decision maker shown in Figure 1, in order to adapt to ultra-high-speed application scenarios, the embodiment of the present invention selects a flip-well device to increase the operating rate. In the charging stage, that is, the reset stage, M5 to M10 charges the circuit nodes to the power supply voltage and removes the previous state of the intermediate nodes. Applying body bias to M5 to M10 has almost no effect on the delay performance. As shown in Figure 7, the delay change is less than 0.32ps during the process of the body bias voltage of M5 to M10 changing from -2V to +2V. Considering that the body bias operation is limited by the parasitic diode between PWELL and NWELL, the body bias voltage of M5 to M10 is set to 0V.

[0123] In the pre-amplification stage, M1 to M4 are turned on, and before M12 or M14 is turned on, the differential current is applied to the parasitic capacitance C at the node P and the node N. P and C N Discharge, differential current and input differential voltage VIP and VIN voltage difference ΔV in Proportional to the voltage difference ΔV in is converted into the voltage difference between node P and node N |V P -V N |, the voltage gain at this time is:

[0124] Among them, I CM is the common mode current flowing through M1 to M4, V THN is the threshold voltage of NMOS tube, and the equivalent transconductance g of M1~M4 m1～4 =2I CM / (V GS -V THN ) 1～4 , where (V GS -V THN ) 1～4 is the equivalent overdrive voltage of M1 to M4, so increase V THN A larger voltage gain can be obtained. In addition to the rate, the influence of the equivalent input noise of the decision device should also be considered. Most of the equivalent input noise comes from the kT / C noise of M1 to M4 and M6 and M8. In the pre-amplification stage, the circuit is equivalent to an integrator, and the input reference noise is:

[0125] Where γ is the noise factor, k is the Boltzmann constant, T is the temperature, (V GS -VTHN ) 1～4 is the equivalent overdrive voltage of M1~M4, C P,N is the capacitance of the P and N nodes. Equation 3 shows that input-referred noise is inversely proportional to the input MOS transistor threshold voltage. Considering both gain and input-referred noise, the simulation results in Figure 7 show that a -2V backgate bias of M1-M4 minimizes decision delay. However, considering that the body bias is limited by the parasitic diode between PWELL and NWELL, the body bias voltage of M1-M4 is set to 0V.

[0126] Formula 3 and Formula 4 are both well-known formulas. For details, please refer to the following literature: B. Razavi, "The SrongARM latch," in IEEE Solid-State Circuits Magazine, vol. 7, no. 2, pp. 2-17, June 2015.

[0127] The threshold voltage of M15-M16 directly affects the switching rate of the decision maker. A smaller threshold voltage helps M15-M16 turn on quickly. Based on the above analysis and the trend of the simulation curve in Figure 7, the body bias of M15 and M16 is set to +2V to reduce the threshold voltage of M15-M16.

[0128] Formula (1) shows that the pre-amplification delay is proportional to the PMOS threshold voltage, and the gate input voltage difference between M18 and M19 in the re-amplification stage is proportional to the PMOS threshold voltage. Proportional to the PMOS threshold voltage. The pre-amplification delay and the initial voltage during the re-amplification phase decrease as the PMOS threshold voltage decreases. The simulation results shown in Figure 7 show that as the body bias voltage of M11 and M13 decreases, the total delay of the two-stage cascaded decision circuit decreases, even if the initial voltage during the re-amplification phase decreases. Therefore, setting the body bias of M11 and M13 to -2V reduces the PMOS threshold voltage, while setting the body bias of M12 and M14 to +2V achieves a more balanced inverter structure.

[0129] In the re-amplification phase, M18 and M19 are turned on, charging the gates of the cross-coupled pair M20 and M21 to trigger the decision device to enter the regeneration phase. The magnitude of the conduction current is proportional to the transconductance of M18 and M19. When the device size remains unchanged, that is, W / L remains unchanged, the transconductance is equal to where μ p is the carrier mobility, C ox Gate oxide capacitance, W is the width of MOSFET, L is the length of MOSFET, V GS is the gate-source voltage of the MOSFET, V THP is the threshold voltage of the PMOS tube, the charging current is related to V THPInversely proportional. Based on the above analysis and the trend of the simulation curve in Figure 7, it is recommended to set the body bias voltage of M18 and M19 to -2V. This transconductance formula is well known. For details, please refer to the following literature: "Design of Analog CMOS Integrated Circuits" by Behzad Razavi.

[0130] When the body bias of M17, M20 and M21 changes from +2V to -2V, the threshold voltage drops by about 280mV, making V Q The value is reduced by about 220mV. Charging the relatively low voltage to the power supply requires more regeneration delay. However, due to the short channel effect, as V Q As the current through M18 or M19 decreases, the current flowing through M18 or M19 increases. The simulation results shown in Figure 7 show that the decision delay changes by less than 0.3 ps when the body bias changes from -2 V to +2 V. The body bias of M17, M20, and M21 has little effect on the decision delay. Considering the parasitic diodes between PWELL and NWELL, the body bias of M17, M20, and M21 is set to 0 V.

[0131] In summary, for the two-stage cascade decision maker shown in Figure 1, during circuit design, the MOS transistors in the embodiments of the present invention all utilize FDSOI devices. These FDSOI devices can, for example, be flip-well devices, but are not limited thereto. Based on the impact of the body bias effect on the decision delay of the two-stage cascade decision maker, appropriate body bias voltages are selected for each MOS transistor: the body bias voltage of M5-M10, M17, M20-M21, and M1-M4 is 0V; the body bias voltage of M11, M13, M18, and M19 is -2V; and the body bias voltage of M15-M16, M12, and M14 is +2V.

[0132] Hereinafter, the strong-arm arbiter, when used alone, is referred to as SAS, and the two-stage cascaded arbiter shown in Figure 1 is referred to as TSS. To verify the effectiveness of TSS and body biasing, comparative simulations were conducted in embodiments of the present invention. The simulation results are shown in Figures 8a-8b and 9a-9b. In Figures 8a-8b and 9a-9b, TSS (with / i BB) represents TSS with body bias optimization, and TSS (with / o BB) represents TSS without body bias optimization. All MOS transistor body terminals are grounded.

[0133] The transient simulation results shown in Figures 9a and 9b show that the advantage of fast TSS rate is more obvious when the input signal swing is small or the load capacitance is large. Figure 8a shows that when the load capacitance is constant (for example, C L=20fF). When the input signal amplitude drops from 20mV to 5mV, the SAS cannot detect the weak signal as a correct digital output, resulting in a judgment error. However, the two TSSs still output the correct judgment result and the output signal is full-swing. Figure 8b shows that when the input signal swing is constant (for example, Vin = 10mV), as the load capacitance increases from 10fF to 20fF, the two TSSs achieve full-swing output, while the SAS only achieves an output swing of approximately 80% of VDD.

[0134] As shown in Figures 9a and 9b, simulation results show that the TSS with body bias has a shorter decision delay than the other two decision devices when the input swing Vin varies from 5mV to 100mV and the load capacitance varies from 5fF to 30fF. As the input swing decreases or the load capacitance increases, the delay difference between the TSS and SAS increases, while the decision delay difference remains essentially unchanged with or without body bias. As shown in Figure 8a, with an input swing of 100mV, the decision delays of the TSS with body bias, the TSS without body bias, and the SAS are 13.87ps, 17.47ps, and 22.08ps, respectively. The TSS without body bias has a 20.9% shorter decision delay than the SAS, and the TSS with body bias has a 20.6% shorter decision delay than the TSS without body bias. As shown in Figure 8b, with a load capacitance of 5fF, the decision delays for TSS with body bias, TSS without body bias, and SAS are 16.06ps, 20.55ps, and 24.08ps, respectively. The TSS without body bias has a 14.7% shorter decision delay than the SAS, and the TSS with body bias has a 30% shorter decision delay than the TSS without body bias.

[0135] The power consumption of TSS with body bias, TSS without body bias, and SAS is 1.28mW, 1.02mW, and 0.83mW, respectively. Although the power consumption of TSS with body bias is about 1.5 times that of SAS, the power consumption of the decision maker is relatively small in the total power consumption of the receiver, so the additional power consumption cost is relatively small in the total power consumption of the receiver.

[0136] In addition, an embodiment of the present invention further discloses a DFE, comprising: any one of the two-stage cascaded decision devices disclosed above.

[0137] Specifically, with the continuous increase in data rates, wired transceiver design faces increasing challenges, especially when ensuring low power consumption and high equalization performance. To ensure received signal quality and meet low bit error rate requirements, DFE is widely used at the wired receiver end. However, the power consumption and area costs of the DFE, as well as the timing constraints of the feedback loop, are two major trade-offs that must be considered. The low power design requirement necessitates the use of a direct feedback architecture for DFE in wired receivers. The greatest design challenge for direct feedback DFEs is the timing constraints of the feedback loop, which requires signal decision, feedback, and signal establishment to be completed within a single signal cycle. As data rates increase and signal cycles continue to shorten, the timing constraints of direct feedback DFEs have become a bottleneck limiting the speed of wired receivers. The decision delay of the strong-arm arbiter is too long, making it impossible to meet the tight timing constraints of direct feedback DFEs in high-speed / ultra-high-speed data transmission scenarios. However, the two-stage cascaded arbiter disclosed in the embodiments of the present invention offers a short decision delay, effectively meeting the tight timing constraints of direct feedback DFEs in high-speed / ultra-high-speed data transmission scenarios.

[0138] In addition, an embodiment of the present invention further discloses a wired receiver, including: any one of the DFEs disclosed above.

[0139] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other and will not be repeated here.

[0140] The terms "first," "second," and the like in the specification and claims of the present invention and the accompanying drawings are used to distinguish between similar objects and are not necessarily used to describe a specific order or precedence. Furthermore, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, product, or apparatus comprising a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, product, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a" does not preclude the presence of additional identical elements in the process, method, product, or apparatus comprising the element.

[0141] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the embodiments of the present invention. Therefore, the embodiments of the present invention are not limited to the embodiments shown herein, but are intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A two-stage cascade decision device, characterized in that: The first stage circuit of the two-stage cascade decision device is a strong-arm decision device; The second stage circuit of the two-stage cascade decision device includes: a PMOS tube M9, a PMOS tube M10, an NMOS tube M17, a PMOS tube M18, a PMOS tube M19, an NMOS tube M20 and an NMOS tube M21; Wherein, the source of the PMOS tube M9, the source of the PMOS tube M10, the source of the PMOS tube M18 and the source of the PMOS tube M19 are all connected to a power source; The gate of the PMOS tube M19 is connected to the first output terminal (MN) of the strong arm decision device; the gate of the PMOS tube M18 is connected to the second output terminal (MP) of the strong arm decision device; The gate of the NMOS tube M17, the gate of the PMOS tube M9 and the gate of the PMOS tube M10 all receive a clock signal (CLK); The drain of the PMOS tube M9, the drain of the PMOS tube M18, the drain of the NMOS tube M20 and the gate of the NMOS tube M21 are all connected to the first output terminal (ON) of the second stage circuit; The drain of the PMOS tube M10, the drain of the PMOS tube M19, the drain of the NMOS tube M21 and the gate of the NMOS tube M20 are all connected to the second output end (OP) of the second stage circuit; The source of the NMOS tube M20, the source of the NMOS tube M21 and the drain of the NMOS tube M17 are connected together; The source of the NMOS tube M17 is grounded.

2. The two-stage cascade decision device according to claim 1, characterized in that: The strong arm decision device includes: NMOS tube M1, NMOS tube M2, NMOS tube M3, NMOS tube M4, PMOS tube M5, PMOS tube M6, PMOS tube M7, PMOS tube M8, PMOS tube M11, NMOS tube M12, PMOS tube M13, NMOS tube M14, NMOS tube M15 and NMOS tube M16; Wherein, the source of the PMOS tube M5, the source of the PMOS tube M13, the source of the PMOS tube M11, the source of the PMOS tube M7, the source of the PMOS tube M6 and the source of the PMOS tube M8 are all connected to the power supply; The gate of the PMOS tube M5, the gate of the PMOS tube M6, the gate of the PMOS tube M7, the gate of the PMOS tube M8, the gate of the NMOS tube M15 and the gate of the NMOS tube M16 all receive the clock signal (CLK); The drain of the PMOS tube M5, the drain of the PMOS tube M13, the drain of the NMOS tube M14, the gate of the PMOS tube M11 and the gate of the NMOS tube M12 are all connected to the first output terminal (MN) of the strong arm decision device; The gate of the PMOS tube M13, the gate of the NMOS tube M14, the drain of the PMOS tube M11 and the drain of the PMOS tube M7 are all connected to the second output terminal (MP) of the strong arm decision device; The drain of the PMOS tube M6, the source of the NMOS tube M14, the drain of the NMOS tube M1 and the drain of the NMOS tube M4 are connected to one point (N); The source of the NMOS tube M12, the drain of the PMOS tube M8, the drain of the NMOS tube M2 and the drain of the NMOS tube M3 are connected to one point (P); The gate of the NMOS tube M3 and the gate of the NMOS tube M4 are connected to the first pair of differential input terminals of the strong arm decision device, and are used to receive a reference voltage (Vref); The gate of the NMOS tube M1 and the gate of the NMOS tube M2 are connected to the second pair of differential input terminals of the strong arm decision device, for receiving differential input signals; the second pair of differential input terminals includes a first terminal (VIP) and a second terminal (VIN), the gate of the NMOS tube M1 is connected to the first terminal (VIP); the gate of the NMOS tube M2 is connected to the second terminal (VIN); The source of the NMOS tube M1 and the source of the NMOS tube M3 are connected to the drain of the NMOS tube M15; The source of the NMOS tube M4 and the source of the NMOS tube M2 are connected to the drain of the NMOS tube M16; The source of the NMOS transistor M15 and the source of the NMOS transistor M16 are both grounded.

3. The two-stage cascade decision device according to claim 2, characterized in that: When the rising edge of the clock signal (CLK) arrives, the voltages of the first output terminal (ON) and the second output terminal (OP) of the second stage circuit are both pulled down to 0.5 times of VDD; VDD is the voltage of the power supply.

4. The two-stage cascade decision device according to claim 3, characterized in that: The body bias voltages of the PMOS tube M5, PMOS tube M6, PMOS tube M7, PMOS tube M8, PMOS tube M9, PMOS tube M10, NMOS tube M17, NMOS tube M20, NMOS tube M21, NMOS tube M1, NMOS tube M2, NMOS tube M3 and NMOS tube M4 are all 0V; The body bias voltages of the PMOS tube M11, the PMOS tube M13, the PMOS tube M18 and the PMOS tube M19 are all -2V; The body bias voltages of the NMOS transistor M15, the NMOS transistor M16, the NMOS transistor M12 and the NMOS transistor M14 are all +2V.

5. The two-stage cascade decision device according to claim 1, characterized in that: The strong arm decision device comprises: NMOS tube Q1, NMOS tube Q2, NMOS tube Q3, NMOS tube Q4, PMOS tube Q5, PMOS tube Q6, PMOS tube Q7, PMOS tube Q8 and NMOS tube Q9; Wherein, the source of the PMOS tube Q5, the source of the PMOS tube Q6, the source of the PMOS tube Q7 and the source of the PMOS tube Q8 are all connected to the power supply; The gate of the PMOS tube Q7, the gate of the PMOS tube Q8 and the gate of the NMOS tube Q9 all receive the clock signal (CLK); The drain of the PMOS tube Q7, the drain of the PMOS tube Q5, the drain of the NMOS tube Q3, the gate of the PMOS tube Q6 and the gate of the NMOS tube Q4 are all connected to the first output terminal (MN) of the strong arm decision device; The gate of the PMOS tube Q5, the gate of the NMOS tube Q3, the drain of the PMOS tube Q6, the drain of the NMOS tube Q4 and the drain of the PMOS tube Q8 are all connected to the second output terminal (MP) of the strong arm decision device; The gate of the NMOS tube Q1 and the gate of the NMOS tube Q2 are connected to a pair of differential input terminals of the strong arm decision device; the differential input terminals include a first terminal (VIP) and a second terminal (VIN), the gate of the NMOS tube Q2 is connected to the first terminal (VIP); the gate of the NMOS tube Q1 is connected to the second terminal (VIN); The source of the NMOS tube Q3 is connected to the drain of the NMOS tube Q1; the source of the NMOS tube Q4 is connected to the drain of the NMOS tube Q2; The source of the NMOS tube Q1, the source of the NMOS tube Q2 and the drain of the NMOS tube Q9 are connected together; The source of the NMOS tube Q9 is grounded.

6. A decision feedback equalizer, characterized in that: include: A two-stage cascaded decision device as claimed in any one of claims 1 to 5.

7. A wired receiver, characterized in that: include: A decision feedback equalizer as claimed in claim 6.

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