Horizontal hall device and preparation method therefor

Abstract

A horizontal Hall device and a preparation method therefor. The horizontal Hall device comprises: a substrate layer and a BOX layer on the substrate layer; an epitaxial layer is provided on the BOX layer; a well layer is provided on the epitaxial layer; an STI layer is provided on the well layer; sensing electrode pairs and bias electrode pairs are provided on the STI layer; grounding electrodes are provided on the epitaxial layer; and a current blocking layer is provided between every adjacent sensing electrode and bias electrode. The preparation method for the horizontal Hall device comprises: preparing a substrate provided with the BOX layer and the epitaxial layer; performing deep-trench etching on the epitaxial layer, the bottom of the deep trenches being in direct contact with the BOX layer, and filling the deep trenches to form the current blocking layers; performing photolithography and doping on the upper part of the epitaxial layer to form the well layer; performing shallow trench etching on the well layer area to form a shallow trench located on the well layer, and depositing silicon dioxide to form the STI layer; and doping a sensing electrode pair area and a bias electrode pair area to form a heavily doped contact area, and doping the epitaxial layer to form a heavily doped contact layer.

Description

A horizontal Hall effect device and its preparation method Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a horizontal Hall device applied to a Hall sensor and a preparation method thereof. Background Art

[0002] Currently, CMOS Hall sensors, a type of magnetic sensor, are widely used in automotive electronics, medical electronics, consumer electronics, and other fields due to their process compatibility, low cost, and high integration. A Hall sensor primarily consists of a Hall element and corresponding signal conditioning circuitry. Specifically, for three-dimensional magnetic field detection, a Hall sensor includes a horizontal Hall element for detecting magnetic fields perpendicular to the chip surface and a vertical Hall element for detecting magnetic fields parallel to the chip surface. The Hall element converts magnetic field signals into electrical signals. Signal conversion efficiency and quality determine the overall performance of a Hall sensor, making high-performance Hall elements crucial.

[0003] For traditional Hall effect devices, improving performance primarily faces the following challenges. First, some current, after entering the device, flows out along the device edge through the sensing electrode, creating a "short-circuit effect." This current flows along the device edge and does not contribute to the Hall voltage signal, resulting in reduced device sensitivity. Compared to traditional structures, the horizontal Hall effect device in patent application CN208297701U incorporates a P+ injection layer on the N-well. While this PN junction structure suppresses the "short-circuit effect," some current still flows along a relatively short current path to the sensing electrode, reducing sensitivity. Second, the structure of traditional Hall effect devices means that their sensitivity is constrained by electrode size. While smaller electrode size can improve sensitivity, it also introduces process challenges and increases initial offset. Therefore, achieving both high sensitivity and low offset is difficult due to electrode size limitations. Third, due to surface parasitic effects such as defects at the interface and impurity particles, Hall effect devices exhibit 1 / f noise, which affects the device's signal-to-noise ratio. Furthermore, in CMOS integrated Hall devices, the Hall device and external circuitry are integrated on a single wafer, resulting in significant crosstalk between the devices. While junction isolation can be used to reduce crosstalk, this also introduces nonlinear resistance, leading to increased residual offset. Furthermore, the large junction isolation area increases chip cost. Application Publication No. CN102790072A utilizes junction isolation technology in an integrated Hall device. This technology isolates the substrate from crosstalk with other devices by forming an isolation ring in the P-type doped region surrounding the N-well. However, the introduction of a PN junction structure increases nonlinear resistance, leading to increased residual offset. This also increases the chip area occupied by the Hall device, raising costs.

[0004] Summary of the Invention

[0005] To address the shortcomings of the existing technology, the present invention proposes a horizontal Hall effect device and fabrication method. This device utilizes a deep trench isolation (DTI) and structured structure (STI) to regulate the current path, avoid short-circuiting, reduce surface noise, and enhance Hall effect device sensitivity. This allows Hall effect device sensitivity to be independent of electrode size, while increasing electrode size to reduce offset while maintaining or even improving sensitivity. A fully isolated structure completely isolates the sensor from other devices, preventing crosstalk from other components.

[0006] To achieve the above objectives, the present invention provides a horizontal Hall effect device, comprising:

[0007] A first conductive type substrate layer is provided, a BOX layer is provided on the first conductive type substrate layer, a first conductive type epitaxial layer is provided on the BOX layer, a second conductive type well layer is provided on the first conductive type epitaxial layer, an STI (Shallow Trench Isolation) layer is provided on the second conductive type well layer, a second conductive type sensing electrode pair and a second conductive type bias electrode pair are provided on the STI layer, the second conductive type sensing electrode pair and the second conductive type bias electrode pair extend deep into the second conductive type well layer, a ground electrode is connected to the first conductive type epitaxial layer, and the current blocking layer is provided between adjacent second conductive type sensing electrodes and second conductive type bias electrodes, and the current blocking layer starts from the STI layer, passes through the second conductive type well layer and the first conductive type epitaxial layer, and then reaches the BOX layer.

[0008] To achieve the above object, the present invention also provides a method for preparing a horizontal Hall device, comprising the following steps:

[0009] A substrate having a BOX layer and an epitaxial layer is prepared; the epitaxial layer is a first conductivity type epitaxial layer, and the substrate is a first conductivity type substrate.

[0010] The first conductive type epitaxial layer is subjected to deep trench etching to form a deep trench located on the BOX layer, wherein the bottom of the deep trench is in direct contact with the BOX layer, and the deep trench is filled by depositing silicon dioxide to form a current blocking layer.

[0011] A doping window exposed by photoresist is formed by photolithography and the current blocking layer is covered with photoresist, and a second conductive type well layer is formed by doping on the upper portion of the first conductive type epitaxial layer.

[0012] Shallow trench etching is performed on the second conductive type well layer region outside the current blocking layer, the sensing electrode pair region, and the bias electrode pair region to form a shallow trench on the second conductive type well layer, and an STI layer is formed by depositing silicon dioxide.

[0013] The sensing electrode pair region and the bias electrode pair region are doped to form a heavily doped second conductivity type contact layer, and the first conductivity type epitaxial layer is doped to form a heavily doped first conductivity type contact layer.

[0014] Compared with the prior art, the present invention has the following advantages:

[0015] (1) The present invention adopts a current blocking layer, especially a DTI structure, to improve the sensitivity of the device and suppress the "short-circuit effect". Because the current tends to flow along the short current path, that is, the low-resistance direction, for traditional Hall devices, part of the current will flow out of the device along the edge of the device through the sensing electrode after entering the device, that is, a "short-circuit effect" occurs. This part of the current that causes the "short-circuit effect" will not generate an effective Hall voltage after being affected by the magnetic field force in the working state of the Hall device, thereby causing the sensitivity of the device to the induced magnetic field to decrease. The Hall device of the present invention changes the distribution of the internal resistance of the device by introducing a current blocking layer (DTI structure), so that the current path in the original low-resistance direction becomes a high-resistance path, and the current no longer flows along the short current path, suppressing the occurrence of the "short-circuit effect". In addition, this part of the current will generate a Hall voltage perpendicular to the current flow direction after being affected by the magnetic field force, thereby improving the sensitivity of the device and solving the "short-circuit effect" that restricts the improvement of the sensitivity of the Hall device.

[0016] (2) The present invention eliminates the constraint of electrode size on the sensitivity of the Hall device, and can achieve the goal of increasing the electrode size to reduce the offset while no longer affecting the sensitivity of the device. For traditional Hall devices, the sensitivity is proportional to the geometric factor, and the geometric factor is inversely proportional to the electrode size, so a smaller electrode size can achieve a greater sensitivity. However, due to factors such as process accuracy and process fluctuations, the smaller the electrode size, the more difficult it is to ensure a symmetrical distribution between electrodes, and the asymmetry between electrodes will cause the initial offset of the device to increase, thereby affecting the resolution of the Hall sensor. Therefore, the traditional structure is limited by the adjustment of the electrode size, and it is difficult to achieve both high sensitivity and low offset. For a horizontal Hall device proposed in the present invention, a DTI structure is used to regulate the current path, so that the sensitivity of the Hall device is no longer constrained by the geometric factor in traditional theory, but is adjusted by the length of the DTI structure, avoiding the influence of the electrode size on the device sensitivity. Therefore, the electrode size can be increased to reduce the offset while ensuring that the device sensitivity is not affected.

[0017] (3) Improved device sensitivity. For horizontal Hall devices, a shallower active area N-well can lead to higher sensitivity. In the horizontal Hall device proposed in this invention, the introduction of a surface-controlled depth STI structure effectively reduces the depth of the active area N-well, thereby improving device sensitivity. Furthermore, due to the solution to the "short-circuit effect," the device sensitivity is also greatly improved.

[0018] (4) Full isolation structure. Different from the PN junction isolation structure used in traditional Hall devices, the horizontal Hall device proposed in the present invention realizes a full isolation structure through the combination of DTI structure and BOX layer. On the one hand, the junction field effect introduced by the PN junction at the edge of the Hall device in the traditional structure will cause the symmetry of the Hall device to decrease, thereby increasing the offset. The horizontal Hall device proposed in the present invention adopts a trench isolation structure, and there is almost no junction field effect at the edge of the device, which reduces the initial offset of the Hall device. On the other hand, the horizontal Hall device proposed in the present invention is completely isolated from other areas, isolating the substrate noise and crosstalk from other devices, so that the Hall device and the external circuit can work normally after integration without being affected by signal crosstalk from other devices, thereby improving the working stability of the Hall device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are used to provide a further understanding of the present invention and are used to explain the present invention together with the embodiments of the present invention, but do not constitute a limitation of the present invention:

[0020] FIG1 is a three-dimensional structural diagram of a horizontal Hall device of the present invention;

[0021] FIG2 is a cross-sectional view of a horizontal Hall device A1-A1' of the present invention in FIG1;

[0022] FIG3 is a cross-sectional view of a horizontal Hall device B1-B1' of the present invention in FIG1;

[0023] FIG4 is a schematic diagram of current density distribution obtained by looking down at the horizontal Hall device of the structure of the present invention and the conventional structure in FIG1 ;

[0024] FIG5 is a Hall voltage output curve of a horizontal Hall device having a structure of the present invention and a conventional structure;

[0025] FIG6 is a Hall voltage output curve of a horizontal Hall device of the present invention;

[0026] FIG7 is a flow chart of the preparation of a horizontal Hall device according to the present invention;

[0027] In the figure, there is a first conductive type substrate 1, a BOX layer 2, a first conductive type epitaxial layer 3, a DTI isolation structure 4, a current blocking layer 5, a second conductive type well layer 6, an STI layer 7, a heavily doped second conductive type contact layer 8, a heavily doped first conductive type contact layer 9, a pair of sensing electrodes 91 and 92, a pair of bias electrodes 93 and 94, and a ground electrode 100. DETAILED DESCRIPTION

[0028] Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0029] It should be understood that the various steps described in the method embodiments of the present invention may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present invention is not limited in this respect.

[0030] As used herein, the term "including" and its variations are open-ended, i.e., "including but not limited to." The term "based on" means "based, at least in part, on." The term "one embodiment" means "at least one embodiment," the term "another embodiment" means "at least one additional embodiment," and the term "some embodiments" means "at least some embodiments." Other terms are defined in the following description.

[0031] It should be noted that the modifications of "one" and "plurality" mentioned in the present invention are illustrative rather than restrictive. Those skilled in the art will understand that unless the context clearly indicates otherwise, they should be understood as "one or more." "Plurality" should be understood as two or more.

[0032] Example 1

[0033] A horizontal Hall device includes: a first conductive type substrate layer 1, a BOX layer 2 provided on the first conductive type substrate layer 1, a first conductive type epitaxial layer 3 provided on the BOX layer 2, a second conductive type well layer 6 provided on the first conductive type epitaxial layer 3, an STI layer 7 provided on the second conductive type well layer 6, a second conductive type sensing electrode pair 91, 92 and a second conductive type bias electrode pair 93, 94 provided on the STI layer 7, the second conductive type sensing electrode pair 91, 92 and the second conductive type bias electrode pair 93, 94 extending deep into the second conductive type well layer 6, a ground electrode 100 connected to the first conductive type epitaxial layer 3, and is characterized in that a current blocking layer 5 is provided between adjacent second conductive type sensing electrodes and second conductive type bias electrodes, and the current blocking layer 5 starts from the STI layer 7 and passes through the second conductive type well layer 6 and the first conductive type epitaxial layer 3 before reaching the BOX layer 2. In this embodiment,

[0034] The current blocking layer 5 extends outward to the edges of the first conductive type epitaxial layer 3 , the second conductive type well layer 6 , and the STI layer 7 ;

[0035] An isolation structure 4 is provided on the BOX layer 2 and is located outside the first conductivity type epitaxial layer 3, the second conductivity type well layer 6, the STI layer 7 and the current blocking layer 5 and surrounds the first conductivity type epitaxial layer 3, the second conductivity type well layer 6, the STI layer 7 and the current blocking layer 5;

[0036] The isolation structure 4 is a DTI deep trench isolation structure; the current blocking layer 5 is a DTI deep trench isolation region.

[0037] In this embodiment, the first conductivity type is p-type and the second conductivity type is n-type, or, in this embodiment, the first conductivity type is n-type and the second conductivity type is p-type.

[0038] Example 2

[0039] A method for preparing a horizontal Hall device, comprising:

[0040] A substrate having a BOX layer and an epitaxial layer is prepared; the epitaxial layer is a first conductivity type epitaxial layer, and the substrate is a first conductivity type substrate.

[0041] The first conductive type epitaxial layer is deep-grooved to form a deep groove on the BOX layer, with the bottom of the deep groove in direct contact with the BOX layer, and the deep groove is filled with silicon dioxide to form a current blocking layer 5.

[0042] A doping window exposed by photoresist is formed by photolithography and the flow blocking layer 5 is covered with photoresist, and a second conductive type well layer 6 is formed by doping on the upper portion of the first conductive type epitaxial layer.

[0043] Shallow trench etching is performed on the second conductive type well layer 6 outside the current blocking layer 5, the sensing electrode pair region, and the bias electrode pair region to form a shallow trench on the second conductive type well layer, and an STI layer 7 is formed by depositing silicon dioxide.

[0044] The sensing electrode pair region and the bias electrode pair region are doped to form a heavily doped second conductivity type contact layer 8 , and the first conductivity type epitaxial layer is doped to form a heavily doped first conductivity type contact layer 9 .

[0045] In this embodiment, when deep trench etching is performed on the first conductive type epitaxial layer, the first conductive type epitaxial layer is etched to form a square deep trench located on the BOX layer, and the square deep trench is filled with silicon dioxide by depositing. An isolation structure 4 is formed. The isolation structure 4 can surround the flow blocking layer 5, the heavily doped second conductive type contact layer 8, the STI layer 7 and the second conductive type well layer 6 and the first conductive type epitaxial layer thereunder, and the first conductive type epitaxial layer located in the corner area of ​​the isolation structure 4 is exposed on the surface of the isolation structure 4.

[0046] Embodiment 1 of the present invention will be described in more detail below with reference to the accompanying drawings.

[0047] 1 , a BOX layer 2 is provided on a first conductive type substrate layer 1, and a first conductive type epitaxial layer 3 is provided on the BOX layer 2. Referring to FIG. 2 and FIG. 3 , deep trench etching is performed on the first conductive type epitaxial layer to form a square deep trench and four strip-shaped deep trenches on the BOX layer 2. Silicon dioxide is deposited in the square deep trench and the four strip-shaped deep trenches to form an isolation structure 4 and a current blocking layer 5, respectively. The so-called current blocking layer 5 may be a DTI structure, i.e., a deep trench isolation (DTI). Isolation) is used to achieve complete current blocking and complete isolation of the device by increasing the resistance therebetween to hinder or even block the electron flow path. A regular octagonal window is provided in the first conductive type epitaxial layer 3. The four spaced sides of the regular octagonal window coincide with the four sides of the isolation structure 4 respectively. Four current blocking layers 5 are respectively located on the other four spaced sides of the octagonal window. The area within the octagonal window outside the current blocking layer 5 is doped to form a second conductive type well layer 6. The second conductive type well layer 6 is etched to remove the surface second conductive type well layer in the area outside the area where the sensing electrode pair and the bias electrode pair are to be formed. A second conductive type well layer 6 is formed, and silicon dioxide is deposited thereon to form an STI layer 7. The second conductive type well layer where the sensing electrode pair and the bias electrode pair are to be formed is then doped to form a heavily doped second conductive type contact layer 8. The first conductive type epitaxial layer located at the corner of the isolation structure 4 is doped to form a heavily doped first conductive type contact layer 9. Finally, a dielectric layer is covered, and holes are drilled and metal is deposited thereon to form sensing electrode pairs 91 and 92 and bias electrode pairs 93 and 94 respectively connected to each second conductive type contact layer 8, and a ground electrode 100 connected to each heavily doped first conductive type contact layer 9.

[0048] Referring to Figure 1 , the isolation structure 4 is square, with a current blocking layer 5 disposed within the cavity, located on the diagonal of the square and having 90° symmetry. Both the current blocking layer 5 and the second conductive type contact layer 8 have rectangular cross-sections. The current blocking layer 5 is no longer than 30 μm and no wider than 1.5 μm. The second conductive type contact layer 8 is no longer than one-tenth the side length of the STI layer in which it resides and no wider than 1.5 μm. The distance between the second conductive type contact layer 8 and the side of the adjacent octagonal N-well layer is greater than 0.5 μm. Referring to Figures 2 or 3 , the maximum depth of the STI layer 7 is less than 5 μm.

[0049] The second conductive type sensing electrode pairs 91 and 92 are symmetrically distributed, and the second conductive type bias electrode pairs 93 and 94 are symmetrically distributed. In the working state, the second conductive type bias electrode pairs 93 and 94 are used to input and output bias electrical signals, and the second conductive type sensing electrode pairs 91 and 92 are used to output sensing electrical signals.

[0050] Figure 4 is a schematic diagram of the current density distribution obtained by looking down at a horizontal Hall device with the structure of the present invention and a traditional structure in Figure 1. As shown in Figure 4(b), in a horizontal Hall device with a traditional structure, the current tends to flow in the direction of low resistance, and a portion of the current will flow directly along the shortest path on the surface of the device to the adjacent electrode, resulting in a decrease in sensitivity, that is, a "short-circuit effect". As shown in Figure 4(a), a horizontal Hall device proposed by the present invention has a current blocking layer 5 with controllable length inside the cavity, which changes the distribution of resistance inside the device, so that the current path in the original low-resistance direction becomes a high-resistance path. Part of the current no longer flows along the path where the "short-circuit effect" occurs, and this part of the current will generate a Hall voltage perpendicular to the direction of current flow after being acted upon by the magnetic field force. As shown in Figure 5, the Hall voltage of the structure of the present invention is increased by up to 92% compared to the traditional structure, thereby improving the sensitivity of the device and solving the "short-circuit effect" that restricts the improvement of the sensitivity of the Hall device.

[0051] FIG5 is a Hall voltage output curve of a horizontal Hall device of the present invention and the conventional structure in FIG1. ​​As shown in the figure, at different electrode sizes L c Under these conditions, the structure of the present invention achieves a maximum Hall voltage improvement of 92% compared to the conventional structure. When the electrode size is varied, the Hall voltage of the structure of the present invention remains virtually unchanged, while the conventional structure experiences significant changes. This suggests that by regulating the current path, the structure of the present invention frees the sensitivity of the Hall device from the constraints of the geometric factors in conventional theory, thus avoiding the influence of electrode size on device sensitivity. The electrode size can be increased to reduce misalignment without affecting device sensitivity.

[0052] FIG6 is a Hall voltage output curve of a horizontal Hall device of the present invention. As shown in the figure, as the length L of the current blocking layer 5 increases, D As the length of the current blocking layer 5 increases, the Hall voltage of the horizontal Hall device of the present invention increases accordingly, indicating that the sensitivity of the Hall device of the present invention is regulated by the length of the current blocking layer 5.

[0053] FIG7 is a flow chart of the preparation of a horizontal Hall device according to the present invention. The preparation method of a horizontal Hall device according to the present invention will be described in detail below with reference to FIG7 .

[0054] As shown in Figure 7(a), a P-type substrate with a BOX layer and a P-type epitaxial layer is obtained by wafer bonding technology.

[0055] As shown in FIG7( b ), deep trenches are formed on the P-type epitaxial layer by dry etching to form deep trenches with a specific shape on the BOX layer, and the bottom of the deep trenches is in direct contact with the BOX layer.

[0056] As shown in Figure 7(c), silicon dioxide is deposited in the deep trenches by chemical vapor deposition to fill the deep trenches and form a DTI structure;

[0057] As shown in FIG7( d ), a shallow N-well layer is formed in the P-type epitaxial layer 3 by high-energy N-type ion implantation;

[0058] As shown in Figure 7(e), the shallow N-well layer is shallowly grooved by dry etching.

[0059] As shown in Figure 7(f), silicon dioxide is deposited in the shallow trench by chemical vapor deposition to fill the shallow trench and form an STI layer.

[0060] As shown in Figure 7(g), an N+ contact layer is formed on the shallow N well layer by high-energy N-type ion implantation.

[0061] As shown in Figure 7(h), a P+ contact layer is formed on the P-type epitaxial layer by high-energy P-type ion implantation.

[0062] As shown in Figure 7(i), a dielectric layer is deposited on the P-type epitaxial layer.

[0063] As shown in Figure 7(j), holes are drilled in the dielectric layer above the N+ contact layer and the P+ contact layer.

[0064] As shown in Figure 7(k), a metal layer is deposited on the dielectric layer.

[0065] As shown in FIG7(i), the metal layer is photolithographically and etched to form metal electrodes on the N+ contact layer and the P+ contact layer.

[0066] Finally, it should be noted that: although the present invention has been described in detail with reference to the embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. However, any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A horizontal Hall device, characterized in that: include: A first conductive type substrate layer (1), a BOX layer (2) is provided on the first conductive type substrate layer (1), a first conductive type epitaxial layer (3) is provided on the BOX layer (2), a second conductive type well layer (6) is provided on the first conductive type epitaxial layer (3), an STI layer (7) is provided on the second conductive type well layer (6), a second conductive type sensing electrode pair (91, 92) and a second conductive type bias electrode pair (93, 94) are provided on the STI layer (7), and the second conductive type sensing electrode pair ( The invention relates to a first conductive type sensing electrode (91, 92) and a second conductive type bias electrode pair (93, 94) extending deep into the second conductive type well layer (6), and a grounding electrode (100) is connected to the first conductive type epitaxial layer (3). The invention is characterized in that a current blocking layer (5) is provided between adjacent second conductive type sensing electrodes and second conductive type bias electrodes, and the current blocking layer (5) starts from the STI layer (7) and passes through the second conductive type well layer (6) and the first conductive type epitaxial layer (3) before touching the BOX layer (2).

2. The horizontal Hall device according to claim 1, characterized in that: The current blocking layer (5) extends outward to the edges of the first conductive type epitaxial layer (3), the second conductive type well layer (6), and the STI layer (7).

3. The horizontal Hall device according to claim 1 or 2, characterized in that: An isolation structure (4) is provided on the BOX layer (2), and the isolation structure (4) is located outside the first conductive type epitaxial layer (3), the second conductive type well layer (6), the STI layer (7) and the current blocking layer (5), and surrounds the first conductive type epitaxial layer (3), the second conductive type well layer (6), the STI layer (7) and the current blocking layer (5).

4. The horizontal Hall device according to claim 3, characterized in that: The isolation structure (4) is a DTI deep trench isolation structure.

5. The horizontal Hall device according to claim 1 or 2, characterized in that: The current blocking layer (5) is a DTI deep trench isolation region.

6. The horizontal Hall device according to claim 1, characterized in that: The first conductivity type is p-type, and the second conductivity type is n-type.

7. The horizontal Hall device according to claim 1, characterized in that: The first conductivity type is n-type, and the second conductivity type is p-type.

8. The horizontal Hall device according to claim 1, characterized in that: The sensing electrode connection lines in the second conductive type sensing electrode pair are perpendicular to the bias electrode connection lines in the second conductive type bias electrode pair.

9. A method for preparing a horizontal Hall device, comprising: preparing a substrate having a BOX layer and an epitaxial layer; The epitaxial layer is a first conductivity type epitaxial layer, and the substrate is a first conductive type substrate, The first conductive type epitaxial layer is subjected to deep trench etching to form a deep trench located on the BOX layer, wherein the bottom of the deep trench is in direct contact with the BOX layer, and the deep trench is filled with silicon dioxide to form a current blocking layer (5). A doping window exposed by a photoresist is formed by photolithography and a flow blocking layer (5) is covered with the photoresist, and a second conductive type well layer (6) is formed by doping on the upper part of the first conductive type epitaxial layer. shallowly etching the second conductive type well layer (6) region outside the current blocking layer (5), the sensing electrode pair region and the bias electrode pair region to form a shallow groove on the second conductive type well layer, and forming an STI layer (7) by depositing silicon dioxide, The sensing electrode pair region and the bias electrode pair region are doped to form a heavily doped second conductivity type contact layer (8), and the first conductivity type epitaxial layer (3) is doped to form a heavily doped first conductivity type contact layer (9).

10. The method for preparing a horizontal Hall device according to claim 9, characterized in that: When deep trench etching is performed on the first conductive type epitaxial layer, the first conductive type epitaxial layer is etched to form a square deep trench located on the BOX layer, and the square deep trench is filled with silicon dioxide by deposition to form an isolation structure (4), wherein the isolation structure (4) can surround the current blocking layer (5), the heavily doped second conductive type contact layer (8), the STI layer (7) and the second conductive type well layer (6) thereunder, the first conductive type epitaxial layer (3) and the heavily doped first conductive type contact layer (9), and the first conductive type epitaxial layer located in the corner region of the isolation structure (4) is exposed on the surface of the isolation structure (4).

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