Wafer-level ultrathin quad flat no-lead chip packaging method and chip packaging structure

Abstract

Disclosed in the present invention are a wafer-level ultrathin quad flat no-lead chip packaging method and a chip packaging structure. The method comprises the following steps: S1, enabling the front surfaces of chips to be flip chip bonded to a carrier wafer, and providing a plastic packaging layer on the back surface of each chip to form a reconstructed wafer; S2, after providing a support wafer on the surface of the plastic packaging layer of the reconstructed wafer, debonding the carrier wafer; S3, inverting the reconstructed wafer, and respectively forming at least one re-passivation layer, at least one re-wiring metal layer, an insulating layer, and rectangular metal columns on the front surface of each chip, wherein the top insulating layer covers the top re-wiring metal layer, and the upper surface of each rectangular metal column is higher than the upper surface of the insulating layer on the top layer; and S4, dicing the reconstructed wafer along scribe lines to form a quad flat no-lead chip packaging structure, wherein partially exposed rectangular metal columns are provided on the side wall of the chip packaging structure. The present invention implements optimization of the thickness of the whole chip packaging structure, and the chip packaging structure has a small packaging size, high transmission speed, a short production period, and low process costs.

Description

A wafer-level ultra-thin four-sided pinless chip packaging method and chip packaging structure Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and more particularly to a wafer-level ultra-thin four-sided pinless chip packaging method and a chip packaging structure. Background Art

[0002] With technological advancements and the increasing market demand for smaller, higher-performance electronic products, chip packaging miniaturization has become an inevitable trend. Miniaturized chip packaging enables higher integration, reduces the size and weight of electronic products, and improves product portability and usability. Miniaturized packaging also provides better heat dissipation, helping the chip dissipate heat more efficiently in a compact space, reducing temperatures and improving stability and reliability. Furthermore, miniaturized chip packaging facilitates high integration, integrating more functions and components into a small chip. This reduces circuit board complexity, improves system performance, and lowers product costs.

[0003] WLCSP is an emerging packaging technology that combines wafer-level and chip-scale packaging. It packages the chip directly while it's still on the wafer, and then dices the wafer into individual chips. Compared to traditional packaging, wafer-level packaging offers advantages such as smaller size, higher transmission speeds, higher connection density, shorter production cycles, higher efficiency, and lower process costs.

[0004] The current WLCSP package mainly consists of a five-layer structure: a backside protective layer (silicon wafer or adhesive layer), chip thickness, a redistribution metal layer, an under-bump metal layer, and a ball implant. The backside protective layer is optional, so the minimum package thickness of the product can reach 200um, including a chip thickness of 100um, a redistribution metal layer of 20um, an under-bump metal layer of 5um, and a ball implant of 75um.

[0005] In recent years, with the continuous upgrading of electronic products, emerging markets such as smartphones, 5G, and AI have put forward higher requirements for packaging technology. As an emerging technology, WLCSP packaging is also constantly being optimized and improved to meet the development needs of increasingly thin, short, and low-cost electronic products.

[0006] Therefore, how to optimize the process and structure of existing WLCSP packaging has always been a difficult problem that needs to be overcome.

[0007] Summary of the Invention

[0008] In order to solve the above problems, the present invention provides a wafer-level ultra-thin four-sided pinless chip packaging method and chip packaging structure, which can achieve the minimum packaging size and packaging thickness, and the minimum packaging structure can reach 128um thickness.

[0009] According to one aspect of the present invention, a wafer-level ultra-thin four-sided leadless chip packaging method is provided, the method comprising the following steps:

[0010] S1. Provide a carrier wafer, cut the same or different incoming wafers into single chips, and flip-chip the front side of the chips onto the carrier wafer; and set a plastic sealing layer on the back side of the chips to form a reconstructed wafer;

[0011] The spacing between individual chips on the reconstructed wafer, which comes from the same or different incoming wafers, can be adjusted according to the actual design. This is relatively larger than the chip spacing on the incoming wafer and has more design space. Therefore, the reconstructed wafer facilitates the construction of chip packaging products with larger unit area and more input and output (I / O).

[0012] S2. After placing a support wafer on the plastic sealing layer surface of the reconstructed wafer, debonding the carrier wafer;

[0013] S3. Invert and reconstruct the wafer to form at least one re-passivation layer, at least one rewiring metal layer, an insulating layer and rectangular metal pillars connected to the chip pressure area on the front side of each chip to achieve chip interconnection; the top insulating layer covers the top rewiring metal layer.

[0014] The upper surface of the rectangular metal pillar is higher than the upper surface of the top insulating layer; the rectangular metal pillar is set higher than the top insulating layer to facilitate the subsequent soldering of the chip to the substrate. The thickness of the insulating layer ranges from 0-40um. The chip needs to be packaged together with the PCB, substrate, frame and other structures. If the rectangular metal pillar is lower than the insulating layer, there is a risk of cracking in the RDL. The insulating layer will be closely connected to the packaging structure such as the PCB, and there is a risk of poor soldering. Therefore, the upper surface of the rectangular metal pillar needs to be higher than the upper surface of the top insulating layer to increase the soldering area and improve soldering performance. This is beneficial to the transmission efficiency of the chip and the rest of the packaging structure and will reduce the occurrence of voids.

[0015] The size of the top rewiring metal layer connected to the rectangular metal pillars is larger than the size of the corresponding single chip; the rectangular metal pillars are symmetrically or asymmetrically distributed around the edges of the top rewiring metal layer, and the rectangular metal pillars partially or completely cover the dicing streets of the reconstructed wafer; the rectangular metal pillars partially or completely cover the top insulating layer located above the dicing streets;

[0016] The rectangular metal column includes an under-bump metallization layer, and tin is plated on the under-bump metallization layer to form a tinned layer, wherein the thickness of the tinned layer is 8-20 μm;

[0017] S4. Cut and reconstruct the wafer along the cutting lines to form a single chip packaging structure with no pins on four sides, wherein the sidewalls of the chip packaging structure have partially exposed rectangular metal columns.

[0018] In some embodiments, in step S1 , a temporary bonding film is first applied to the carrier wafer, and then the chips are flip-chip mounted one by one on the carrier wafer.

[0019] In some embodiments, in step S1 , the plastic encapsulation layer is formed by injection molding a plastic encapsulation material or by laminating an ABF film.

[0020] In some embodiments, in step S3, the concentration of the leveler in the electroplating solution during the tin plating process is 30%-80%. By adjusting the concentration of the leveler in the electroplating solution, the rectangular metal pillars are made flatter.

[0021] In some embodiments, in step S3, a photoresist is coated on the chip of the reconstructed wafer, and a photolithography or laser process is performed using a mask to open a pattern opening to form a repassivation layer;

[0022] Apply a photoresist layer again, use a mask to perform photolithography or laser processing to open a metal layer pattern opening; electroplating is performed in the metal layer pattern opening to form a rewiring metal layer;

[0023] Alternatively, the same method is used to add multiple layers of repassivation layers and rewiring metal layers to realize a multi-layer rewiring metal layer interconnection structure.

[0024] In some embodiments, in step S4, before cutting, positioning protrusions are provided at the edge of the chip. The positioning protrusions can be of any shape, and the provision of the positioning protrusions not only facilitates the subsequent welding of the chip to the substrate, but also helps to distinguish the boundaries of the chip during dicing.

[0025] In some embodiments, the sidewalls of the chip package structure are stepped, making it easier for the sidewalls of the single chip package structure to sinter. The height of the sinter sinter can be used to intuitively determine the soldering effect between the product and the PCB, thereby ensuring the package quality, reducing soldering defects, and improving the reliability and stability of the product.

[0026] On the other hand, the present invention also discloses a chip packaging structure prepared by the above method, which includes a supporting wafer, a plastic packaging layer, a chip, a re-passivation layer, a rewiring metal layer and a rectangular metal column arranged from bottom to top, and the size of the rewiring metal layer is larger than the size of the chip; the rectangular metal columns are symmetrically or asymmetrically distributed on the four edges of the rewiring metal layer, and the rectangular metal columns partially or completely cover the cutting path of the supporting wafer.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] The present invention adopts a wafer-level ultra-thin four-sided leadless chip packaging method, which optimizes the thickness of the entire chip packaging structure by optimizing the structure and distribution position of rectangular metal columns;

[0029] The rectangular metal pillar structure is achieved by electroplating an appropriate thickness of tin (8um-20um) under the bump metal layer, allowing the entire package to reach a thickness of 128um. This optimizes the package height by 36% compared to traditional WLCSP packages. The optimum tin plating thickness is 8um-20um. A thickness below 8um results in poor solderability, while a thickness above 20um will not produce optimal soldering results. Therefore, for cost and solderability considerations, the optimal tin plating thickness is 8-20um. This ensures stable contact between the probe and the chip's metal pressure zone during wafer-level testing, and ensures higher soldering strength when the chip package structure is subsequently soldered to the substrate, while preventing quality issues such as voids.

[0030] The distribution of the rectangular metal pillars is also different from the distribution of the balls in the traditional WLCSP package. The balls in the traditional WLCSP package are located in the middle of the chip and are arranged in an array. When the chip is installed on the substrate, the bonding between the two cannot be directly observed, which creates a technical barrier for technicians to judge the reliability of the chip package. In addition, there is a problem that the height of the metal balls is inconsistent, which affects the bonding strength between the chip and the substrate. To solve this technical problem, the distribution of the rectangular metal pillars in the present invention refers to the structural design of the QFN class, and the rectangular metal pillars are symmetrically distributed around the chip (including the cutting path) to facilitate packaging. According to actual needs, the rectangular metal pillars can also be asymmetrically distributed around the chip. There are partially exposed rectangular metal pillars on the side walls of the chip packaging structure, and the soldering effect between the product and the PCB can be intuitively judged by the height of the tin creeping on the side, thereby ensuring its packaging quality, reducing soldering defects, and improving the reliability and stability of the product.

[0031] The present invention can improve the interconnection density between chips and solve high-density heterogeneous integration based on the rewiring metal layer on the chip, realizing the development trend of electronic packaging such as small chip size, light and thin, high pin count and high speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] FIG1 is a schematic structural diagram of a chip flip-chip mounted on a carrier wafer in step S1 of the present invention;

[0033] FIG2 is a schematic structural diagram of the reconstructed wafer in step S1 of the present invention;

[0034] 3 is a schematic structural diagram of a support wafer disposed on the surface of the plastic sealing layer in step S2 of the present invention;

[0035] FIG4 is a schematic structural diagram of a reconstructed wafer after debonding the carrier wafer in step S2 of the present invention;

[0036] FIG5 is a schematic structural diagram of a chip packaging structure having only one repassivation layer and a rewiring metal layer in step S3 of the present invention;

[0037] FIG6 is a schematic structural diagram of a single chip packaging structure without pins on four sides in step S4 of the present invention;

[0038] 7 is a schematic diagram of a chip packaging structure of the present invention having a stepped sidewall structure;

[0039] FIG8 is a schematic diagram of a structure in which rectangular metal pillars are symmetrically distributed on a redistribution metal layer. DETAILED DESCRIPTION

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0041] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0042] The present invention discloses a wafer-level ultra-thin four-sided leadless chip packaging method, which comprises the following steps:

[0043] S1. As shown in FIG1 , a carrier wafer 3 is provided, and a temporary bonding film 2 (TBF film) is attached to the carrier wafer 3;

[0044] The incoming wafer is ground to a suitable thickness and then cut into individual chips 1, and the front sides of the chips 1 are flipped one by one on the carrier wafer 3. The incoming wafers can be the same or different and cut into individual chips, providing more solutions for diversified chip design.

[0045] A plastic packaging layer 4 is provided on the back of the chip 1 to form a reconstructed wafer, as shown in FIG2 .

[0046] The spacing between individual chips on the reconstructed wafer, which comes from the same or different incoming wafers, can be adjusted according to the actual design. This is relatively larger than the chip spacing on the incoming wafer and has more design space. Therefore, the reconstructed wafer facilitates the construction of chip packaging products with larger unit area and more input and output (I / O).

[0047] S2. After arranging the support wafer 5 on the surface of the plastic sealing layer 4 of the reconstructed wafer, the carrier wafer 3 is debonded. The support wafer 5 is used to provide mechanical support for the entire structure. The structural diagrams of this step are shown in Figures 3 and 4.

[0048] The carrier wafer 3 and the temporary bonding film 2 are debonded and peeled off from the reconstructed wafer by laser / thermal debonding.

[0049] S3. Invert and reconstruct the wafer, and form at least one re-passivation layer 6, at least one rewiring metal layer 7, an insulating layer and a rectangular metal column 8 connected to the chip 1 pressure area 101 on the front side of the single chip 1; realize the interconnection of the chips; the top insulating layer covers the top rewiring metal layer 7.

[0050] The upper surface of the rectangular metal pillar is higher than the upper surface of the top insulating layer; the rectangular metal pillar is higher than the top insulating layer, which is convenient for soldering the chip to the substrate later. The size of the top rewiring metal layer 7 connected to the rectangular metal pillar 8 is larger than the size of the corresponding single chip 1; the rectangular metal pillars 8 are symmetrically or asymmetrically distributed on the four edges of the top rewiring metal layer 7, and the rectangular metal pillars 8 partially or completely cover the cutting path of the reconstructed wafer. The rectangular metal pillar partially or completely covers the top insulating layer above the cutting path. In this embodiment, the rectangular metal pillar 8 partially covers the cutting path of the reconstructed wafer. The application scenario in which the rectangular metal pillar 8 completely covers the cutting path of the reconstructed wafer generally refers to the need for soldering the side walls of the pins of certain QFN products, so the side walls of the rectangular metal pillar 8 (Pillar BUMP) are exposed flush with the side walls of the chip after dicing for soldering.

[0051] The rectangular metal pillar 8 includes an under-bump metallurgy layer, and the under-bump metallurgy layer is plated with tin to form a tin-plated layer. The thickness of the tin-plated layer is 8-20 μm.

[0052] The structure shown in Figure 5 is a chip package structure comprising only a repassivation layer 6, a rewiring metal layer 7, and an insulating layer 9. In this embodiment, rectangular metal pillars 8 are symmetrically distributed around the edges of the rewiring metal layer 7, as shown in Figure 8. Depending on practical needs, the rectangular metal pillars 8 can also be asymmetrically distributed around the edges of the rewiring metal layer 7, which is not described in detail in this disclosure.

[0053] S4. The wafer is reconstructed by cutting along the dicing lanes to form a single chip package structure with no pins on all four sides. The sidewalls of the chip package structure have partially exposed rectangular metal pillars 8. This makes the sidewalls of the single chip package structure easier to solder. The single chip package structure after cutting is shown in Figure 6.

[0054] Before cutting, positioning protrusions are set at the edge of the chip. The positioning protrusions can be of any shape. The setting of the positioning protrusions is not only conducive to the subsequent welding of the chip and the substrate, but also helps to distinguish the boundaries of the chip during dicing.

[0055] In step S1, the plastic encapsulation layer 4 can be formed by injection molding using a plastic encapsulation compound. The plastic encapsulation compound flows between the chip 1 and the temporary bonding film 2 and forms a protective film after solidification, thereby protecting the surface of the chip 1. The plastic encapsulation layer 4 can also be formed by laminating an ABF film. If an ABF film is used, the injection molding is performed by lamination. The ABF film has a certain fluidity under the lamination and process temperature conditions and can fill the gap between the chips 1.

[0056] In step S2, the support wafer 5 is ground to a specified thickness, and adhesive is applied to the support wafer 5 to provide protection. A laser printer can also be used to print on the adhesive surface of the chip 1 according to customer requirements, such as a logo, chip 1 model, and other information.

[0057] In step S3, a photoresist is coated on the chip 1 of the reconstructed wafer, and a photolithography or laser process is performed using a mask to open a pattern opening to form a repassivation layer 6;

[0058] Apply a photoresist layer again, use a mask to perform photolithography or laser processing to open a metal layer pattern opening; electroplating is performed in the metal layer pattern opening to form a rewiring metal layer 7;

[0059] Alternatively, the same method is used to add multiple layers of re-passivation layer 6 and re-wiring metal layer 7 to realize a multi-layer re-wiring metal layer 7 interconnection structure.

[0060] The present invention adopts a wafer-level ultra-thin four-sided leadless chip packaging method, which optimizes the thickness of the entire chip packaging structure by optimizing the structure and distribution position of the rectangular metal pillars 8;

[0061] The rectangular metal pillars 8 are constructed by electroplating an appropriate amount of tin (8-20 μm) on the metal layer under the bump, allowing the overall package thickness to reach 128 μm. This improves the package height by 36% compared to traditional WLCSP packages. The optimal tin plating thickness is 8-20 μm. A thickness below 8 μm results in poor solderability, while a thickness above 20 μm will not provide optimal soldering results. Therefore, for cost and solderability considerations, the optimal tin plating thickness is 8-20 μm.

[0062] The distribution of the rectangular metal pillars 8 is also different from the distribution of the balls in the traditional WLCSP package. The balls in the traditional WLCSP package are located in the middle of the chip 1 and are arranged in an array. When the chip 1 is installed on the substrate, the bonding between the two cannot be directly observed, which creates a technical obstacle for technicians to judge the reliability of the chip 1 package. In addition, there is a problem that the height of the metal balls is inconsistent, which affects the bonding strength between the chip 1 and the substrate. To solve this technical problem, the distribution of the rectangular metal pillars 8 in the present invention refers to the structural design of the QFN class, and the rectangular metal pillars 8 are symmetrically distributed around the chip 1 (including the cutting path) to facilitate packaging. The side walls of the chip packaging structure have partially exposed rectangular metal pillars 8, and the soldering effect between the product and the PCB can be intuitively judged by the height of the tin creeping on the side, thereby ensuring its packaging quality, reducing soldering defects, and improving the reliability and stability of the product.

[0063] The present invention employs a step-cutting technique during cutting, forming a stepped structure on the sidewalls of the chip package structure, as shown in Figure 7. This facilitates side tin creep, allowing the soldering effect between the chip and the PCB to be intuitively determined by the height of the side tin creep, ensuring package quality, reducing soldering defects, and improving product reliability and stability.

[0064] The chip packaging structure prepared according to the above method has the following advantages:

[0065] The package is small. Because it lacks wires, bonding, or plastic processes, the package doesn't need to extend beyond the chip. Combined with the rectangular metal pillar design, the chip package structure's dimensions are nearly equal to the chip itself. High transmission speeds, thanks to shorter connecting lines, enable superior performance under high-performance requirements, such as high frequencies. The production cycle is short, significantly reducing the number of intermediate steps in the entire process from chip manufacturing to packaging and final product, resulting in high production efficiency and significantly shortened cycle times. The process is low-cost, with packaging and testing completed at the silicon wafer level, minimizing costs through mass production.

[0066] The present invention can improve the interconnection density between chips 1 and solve high-density heterogeneous integration based on the redistribution metal layer 7 on the chip 1, and realize the development trend of electronic packaging such as small chip size, light weight, high pin count and high speed.

[0067] The above are only some embodiments of the present invention. It should be pointed out that for ordinary technicians in this field, other variations and improvements can be made without departing from the creative concept of the present invention, and these all fall within the scope of protection of the present invention.

Claims

1. A wafer-level ultra-thin four-sided leadless chip packaging method, characterized in that: The steps include: S1. Provide a carrier wafer, cut the same or different incoming wafers into single chips, and flip the front side of the chip onto the carrier wafer; and set a plastic sealing layer on the back side of the chip to form a reconstructed wafer; S2, after arranging a support wafer on the surface of the plastic sealing layer of the reconstructed wafer, debonding the carrier wafer; S3, inverting the reconstructed wafer, and forming at least one repassivation layer, at least one rewiring metal layer, an insulating layer and a rectangular metal column connected to the chip pressing area on the front side of a single chip, respectively, to realize the interconnection of the chips; the top insulating layer covers the top rewiring metal layer; The upper surface of the rectangular metal column is higher than the upper surface of the top insulating layer; The size of the top rewiring metal layer connected to the rectangular metal pillars is larger than the size of the corresponding single chip; The rectangular metal pillars are symmetrically or asymmetrically distributed around the edges of the top rewiring metal layer, and the rectangular metal pillars partially or completely cover the cutting paths of the reconstructed wafer; the rectangular metal pillars partially or completely cover the top insulating layer above the cutting paths; The rectangular metal column includes an under-bump metal layer, and tin is plated on the under-bump metal layer to form a tinned layer, the thickness of the tinned layer is 8-20 um; the concentration of the leveler in the electroplating solution during the tinning process is 30%-80%; S4, cutting and reconstructing the wafer along the cutting path to form a single chip packaging structure without pins on four sides, wherein the side wall of the chip packaging structure has a partially exposed rectangular metal column; Achieve the smallest package size and package thickness, with a minimum package structure thickness of 128um.

2. A wafer-level ultra-thin four-sided leadless chip packaging method according to claim 1, characterized in that: In step S1, a temporary bonding film is firstly applied to the carrier wafer, and then the chips are flipped onto the carrier wafer one by one.

3. A wafer-level ultra-thin four-sided leadless chip packaging method according to claim 2, characterized in that: In step S1 , the plastic sealing layer is formed by using a plastic sealing material through an injection molding process or by using an ABF film through lamination.

4. A wafer-level ultra-thin four-sided leadless chip packaging method according to claim 3, characterized in that: In step S4, positioning protrusions are provided at the edges of the chips before cutting.

5. The wafer-level ultra-thin four-sided leadless chip packaging method according to claim 1, characterized in that: In step S3, a photoresist is coated on the chip of the reconstructed wafer, and a mask is used for photolithography or laser processing to open a pattern opening to form a repassivation layer; Apply a photoresist layer again, and use a mask to perform photolithography or laser processing to open the metal layer pattern opening; Electroplating in the metal layer pattern opening to form a rewiring metal layer; Alternatively, the same method is used to add multiple layers of repassivation layers and rewiring metal layers to realize a multi-layer rewiring metal layer interconnection structure.

6. The wafer-level ultra-thin four-side leadless chip packaging method according to claim 1, characterized in that: The side wall of the chip packaging structure is a stepped structure.

7. A chip packaging structure, prepared by the method according to any one of claims 1 to 6, characterized in that: The chip packaging structure includes a supporting wafer, a plastic sealing layer, a chip, a re-passivation layer, a re-wiring metal layer and a rectangular metal column arranged from bottom to top, wherein the size of the re-wiring metal layer is larger than the size of the chip; the rectangular metal columns are symmetrically or asymmetrically distributed around the edges of the re-wiring metal layer, and the rectangular metal columns partially or completely cover the cutting path of the supporting wafer.

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