Power semiconductor device, vehicle-mounted charger and vehicle

Abstract

A vehicle, having a vehicle-mounted charger. The vehicle-mounted charger has a power semiconductor device, the power semiconductor device comprising a substrate, a first signal pin, and a plurality of power pins. The first signal pin and the power pins are both electrically connected to the substrate, the plurality of power pins being arranged on the same side surface of the substrate, and the first signal pin and the power pins being arranged on different side surfaces of the substrate.

Description

Power semiconductor devices, on-board chargers, vehicles

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202323125650.2, filed on November 17, 2023, entitled “Power semiconductor device, on-board charger, vehicle,” and the entire contents of that application are incorporated herein for all purposes. Technical Field

[0003] The present application relates to the field of semiconductor technology, and more specifically to a power semiconductor device, an on-board charger, and a vehicle. Background Art

[0004] Power semiconductor devices, also known as power electronic devices or power electronics, are fundamental components in the power electronics field. They enable electrical energy conversion and circuit control, primarily performing functions such as power conversion, power amplification, power switching, line protection, inversion (DC to AC), and rectification (AC to DC). They can be categorized as semi-controlled, fully controlled, and uncontrolled. Thyristors are semi-controlled devices, possessing the highest voltage and current capacity of all devices. Power diodes are uncontrolled devices, characterized by a simple structure and principle and reliable operation. Furthermore, they can be categorized as voltage-driven and current-driven devices. GTOs and GTRs are current-driven devices, while IGBTs and power MOSFETs are voltage-driven devices.

[0005] In related technologies, the power pins in power semiconductor devices are distributed on different sides of the substrate. The power pins are distributed on the same side as the signal pins or part of the signal pins, causing the power lines and signal lines to cross or be close to each other, resulting in mutual interference between the power lines and signal lines.

[0006] Summary of the Invention

[0007] The present application is proposed to address at least one of the above-mentioned problems. According to one aspect of the present application, a power semiconductor device is provided, comprising: a substrate, a first signal pin, and a plurality of power pins; the first signal pin and the power pin are both electrically connected to the substrate; wherein the plurality of power pins are disposed on the same side of the substrate, and the first signal pin and the power pin are disposed on different sides of the substrate.

[0008] In one embodiment of the present application, the plurality of power pins are arranged on a first side surface of the substrate, the first signal pin is arranged on a second side surface of the substrate, and the first side surface and the second side surface are arranged adjacent to or opposite to each other.

[0009] In one embodiment of the present application, there are multiple first signal pins, and the multiple first signal pins are arranged on at least two side surfaces of the substrate.

[0010] In one embodiment of the present application, a plurality of the power pins are arranged on the first side of the substrate; some of the first signal pins are arranged on the second side of the substrate, and the remaining first signal pins are arranged on the third side of the substrate; wherein the second side and the third side are both arranged adjacent to the first side, or the second side is arranged adjacent to the first side and the third side is arranged opposite to the first side.

[0011] In one embodiment of the present application, a plurality of the power pins are arranged on the first side of the substrate; a first part of the first signal pins are arranged on the second side of the substrate, a second part of the first signal pins are arranged on the third side of the substrate, and the remaining first signal pins are arranged on the fourth side of the substrate; wherein the second side and the third side are both arranged adjacent to the first side, and the fourth side is arranged opposite to the first side.

[0012] In one embodiment of the present application, the power semiconductor device further includes a temperature sensor, and the temperature sensor is disposed on the substrate.

[0013] In one embodiment of the present application, the temperature sensor includes a first thermistor and / or a second thermistor, wherein both ends of the first thermistor are electrically connected to the second signal pin, one end of the second thermistor is electrically connected to the third signal pin, and the other end is electrically connected to one of the power pins.

[0014] In one embodiment of the present application, the second signal pin and the power pin are arranged on different sides of the substrate.

[0015] In one embodiment of the present application, the second signal pin and the first signal pin are arranged on different sides of the substrate; or, the second signal pin and at least part of the first signal pin are arranged on the same side of the substrate.

[0016] In one embodiment of the present application, the third signal pin and the power pin are arranged on the same side of the substrate.

[0017] In one embodiment of the present application, the plurality of power pins and the third signal pin are arranged on the first side of the substrate, the first signal pin and the second signal pin are arranged on the second side of the substrate, and the first side and the second side are arranged adjacent to or opposite to each other.

[0018] In one embodiment of the present application, the plurality of power pins and the third signal pin are arranged on the same side of the substrate; the number of the first signal pins is multiple, and the plurality of first signal pins are arranged on at least two sides of the substrate, and the second signal pin is arranged on at least one side where the first signal pin is arranged.

[0019] In one embodiment of the present application, a plurality of the power pins and the third signal pin are arranged on the first side of the substrate; some of the first signal pins are arranged on the second side of the substrate, and the remaining first signal pins are arranged on the third side of the substrate; the third signal pin is arranged on the second side or the third side; wherein, the second side and the third side are both arranged adjacent to the first side, or, the second side is arranged adjacent to the first side and the third side is arranged opposite to the first side.

[0020] In one embodiment of the present application, a plurality of the power pins and the third signal pins are arranged on the first side of the substrate, a first part of the first signal pins are arranged on the second side of the substrate, a second part of the first signal pins are arranged on the third side of the substrate, and the remaining first signal pins are arranged on the fourth side of the substrate; the second signal pin is arranged on the fourth side; wherein the second side and the third side are both arranged adjacent to the first side, and the fourth side is arranged opposite to the first side.

[0021] In one embodiment of the present application, the power semiconductor device includes any one of the following: a diode, a thyristor, a metal-oxide semiconductor field-effect transistor, an insulated gate bipolar transistor, silicon carbide, or gallium nitride.

[0022] In one embodiment of the present application, the power pin and the first signal pin each include at least one of the following: an SOP surface mount pin, a DIP plug-in pin, a PLCC plug-in pin, or an SOJ surface mount pin.

[0023] In one embodiment of the present application, the power semiconductor device further includes an outer shell and a wafer, wherein the wafer is disposed on the substrate; the outer shell encapsulates the wafer and the substrate.

[0024] According to another aspect of the present application, there is provided an on-board charger comprising any one of the power semiconductor devices described above.

[0025] According to another aspect of the present application, a vehicle is provided, comprising the above-mentioned on-board charger.

[0026] According to the power semiconductor device, on-board charger, and vehicle of the embodiments of the present application, by arranging multiple power pins on the same side of the substrate and the first signal pin and the power pin on different sides of the substrate, the power lines and the first type of signal lines can be separated, thereby avoiding cross wiring and preventing mutual interference between the power lines and the first type of signal lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other purposes, features, and advantages of the present application will become more apparent through a more detailed description of the embodiments of the present application in conjunction with the accompanying drawings. The accompanying drawings are intended to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the drawings, the same reference numerals generally represent the same components or steps.

[0028] FIG1 shows a circuit diagram of a half-bridge circuit provided in an embodiment of the present application.

[0029] FIG2 shows a schematic diagram of packaging of a power semiconductor device according to an embodiment of the present application.

[0030] FIG3 shows a schematic diagram of packaging of another power semiconductor device provided according to an embodiment of the present application.

[0031] FIG4 shows a schematic diagram of packaging of another power semiconductor device provided according to an embodiment of the present application.

[0032] FIG5 shows a schematic diagram of packaging of another power semiconductor device provided according to an embodiment of the present application.

[0033] FIG6 shows a circuit diagram of a power semiconductor device with a thermistor according to an embodiment of the present application.

[0034] FIG7 shows a schematic diagram of packaging of another power semiconductor device provided according to an embodiment of the present application.

[0035] FIG8 shows a schematic diagram of packaging of another power semiconductor device provided according to an embodiment of the present application.

[0036] FIG9 shows a schematic diagram of packaging of another power semiconductor device provided according to an embodiment of the present application.

[0037] FIG10 shows a circuit diagram of another power semiconductor device with a thermistor according to an embodiment of the present application.

[0038] FIG11 shows a schematic diagram of packaging of another power semiconductor device provided according to an embodiment of the present application.

[0039] FIG12 shows a circuit diagram of another power semiconductor device with a thermistor according to an embodiment of the present application.

[0040] FIG13 shows a schematic diagram of packaging of another power semiconductor device provided according to an embodiment of the present application.

[0041] FIG14 shows a schematic diagram of packaging of another power semiconductor device provided according to an embodiment of the present application.

[0042] FIG15 shows a schematic diagram of packaging of another power semiconductor device provided according to an embodiment of the present application.

[0043] FIG16 shows a schematic diagram of packaging of another power semiconductor device provided according to an embodiment of the present application.

[0044] FIG17 shows a schematic diagram of packaging of another power semiconductor device provided according to an embodiment of the present application.

[0045] FIG18 is a schematic diagram showing a top heat dissipation pin in the form of an SOP patch according to an embodiment of the present application.

[0046] FIG19 is a schematic diagram showing a top heat dissipation pin in a DIP plug-in form according to an embodiment of the present application.

[0047] FIG20 is a schematic diagram showing a top heat dissipation pin in the form of a PLCC patch according to an embodiment of the present application.

[0048] FIG21 is a schematic diagram showing a top heat dissipation pin in the form of an SOJ patch according to an embodiment of the present application. DETAILED DESCRIPTION

[0049] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, some technical features well known in the art are not described in order to avoid confusion with the present application.

[0050] It should be understood that the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the disclosure thorough and complete and to fully convey the scope of the present application to those skilled in the art. In the drawings, the dimensions and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals throughout represent like elements.

[0051] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.

[0052] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0053] In order to fully understand the present application, a detailed structure will be provided in the following description to illustrate the technical solution proposed in the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementation methods.

[0054] In order to make the application of power semiconductor devices more flexible, the packaging of the power semiconductor devices provided in the embodiments of the present application is relatively flexible, which facilitates wiring during actual application and layout on the circuit board.

[0055] The embodiments of the present application do not specifically limit the specific application scenarios of power semiconductor devices. For example, they can be applied to power supply systems, where the power supply system can be a photovoltaic power generation system, a wind power system, or an energy storage system. In addition, they can also be applied to charging piles for electric vehicles or chargers or motor drivers for electric vehicles, such as the charging circuit inside a charging pile. Generally, the charging circuit includes a power converter, which may include a DC / DC conversion circuit and an AC / DC conversion circuit (rectifier circuit). These conversion circuits generally include power semiconductor devices. In addition, they can also be applied to power supplies for data centers or artificial intelligence (AI).

[0056] In addition, the embodiments of the present application do not specifically limit the number of power tubes included in the power semiconductor device. For example, it may include one power tube, two power tubes, or a greater number of power tubes. The number of power tubes in the power semiconductor device can be set according to the actual application scenario. For example, the power semiconductor device may include a power tube corresponding to a half-bridge circuit, or a power tube corresponding to a full-bridge circuit. A half-bridge circuit corresponds to at least two power tubes, and a full-bridge circuit corresponds to at least four power tubes.

[0057] In order to facilitate those skilled in the art to better understand the technical solutions provided in the embodiments of the present application, the power semiconductor devices corresponding to the half-bridge circuit are introduced below as an example.

[0058] Refer to Figure 1, which is a circuit diagram of a half-bridge circuit provided in an embodiment of the present application.

[0059] This embodiment is described using a half-bridge circuit including two power transistors as an example, that is, the two power transistors are packaged together as a whole to form a power semiconductor device. It should be understood that the half-bridge circuit can also include two diodes or a diode and a MOS transistor.

[0060] FIG1 takes the example of two power transistors being MOS transistors, wherein the first MOS transistor is MOS1 and the second MOS transistor is MOS2.

[0061] The drain of MOS1 is connected to the first power pin P1 , the source S1 of MOS1 is connected to the drain of MOS2 , and at the same time, S1 is connected to the second power pin P2 , and the source S2 of MOS2 is connected to the third power pin P3 .

[0062] The gate G1 of MOS1 and the source S1 of MOS1 are used to connect to external control signals, that is, the switching state of MOS1 depends on the level of the external signal connected to G1 and S1. Similarly, the switching state of MOS2 depends on the level of the external signal connected to G2 and S2.

[0063] For the package of the power semiconductor device corresponding to the half-bridge circuit, the corresponding pins include: P1, P2, P3, G1, G2, S1 and S2.

[0064] Among them, P1, P2 and P3 are power pins; G1, G2, S1 and S2 are first signal pins.

[0065] Refer to FIG2 , which is a schematic diagram of a power semiconductor device corresponding to FIG1 provided in an embodiment of the present application.

[0066] The power semiconductor device provided in the embodiment of the present application includes: a substrate, a wafer, an outer shell, a first signal pin and a plurality of power pins.

[0067] The wafer is set on a substrate; wherein, the substrate can be implemented in the form of direct bonding copper (DBC); the embodiment of the present application does not specifically limit the specific implementation form of the substrate. The embodiment of the present application is only for the convenience of description and to facilitate technical personnel in this field to understand the implementation plan, and the DBC substrate is introduced as an example.

[0068] Since the embodiment of the present application is described using a power semiconductor device corresponding to a half-bridge circuit as an example, it includes two power transistors, each of which corresponds to at least one wafer. For example, the power semiconductor device provided in this embodiment includes two wafers, such as wafer A and wafer B as shown in Figure 2. Wafer A corresponds to MOS1 in Figure 1, and wafer B corresponds to MOS2 in Figure 1. Each power transistor includes corresponding power pins and signal pins.

[0069] It should be understood that each power tube can correspond to at least one die. In the embodiments of this application, only one power tube corresponding to one die is used as an example. In addition, each power tube can correspond to multiple die, and multiple die can be connected in series or in parallel. This is not specifically limited in the embodiments of this application.

[0070] Since both wafer A and wafer B are conductors, and the substrate can be made of copper, which is also a conductor, wafer A and wafer B can be directly soldered on the DBC substrate.

[0071] In order to avoid short circuit between wafer A and wafer B, wafer A and wafer B need to be insulated and isolated by insulating tape.

[0072] The power pins and first signal pins are both electrically connected to the substrate. This embodiment corresponds to two power transistors, each corresponding to three power pins. That is, power pins P1, P2, and P3 can all be soldered to the DBC substrate. First signal pins S1, S2, G1, and G2 can also be directly soldered to the DBC substrate.

[0073] As can be seen from FIG. 2 , P1 , P2 , and P3 are arranged on the same side of the DBC substrate, and S1 , S2 , G1 , and G2 are arranged on the other side of the DBC substrate.

[0074] In traditional power semiconductor devices, power pins are distributed on different sides of the substrate. The power pins are distributed on the same side as the first signal pins or part of the first signal pins. As a result, in actual applications, the power lines and the first-class signal lines cross or are close to each other, resulting in mutual interference between the power lines and the first-class signal lines.

[0075] The power semiconductor device provided in the embodiment of the present application sets multiple power pins on the same side of the substrate, and the first signal pin and the power pin are set on different sides of the substrate, so that the power lines and the first type of signal lines can be separated, avoiding cross wiring, and there is no mutual interference between the power lines and the first type of signal lines.

[0076] Generally, a power semiconductor device further includes an outer shell, which is used to encapsulate the wafer and substrate. The outer shell can be made of plastic, also known as a plastic package 10.

[0077] In some embodiments of the present application, multiple power pins are arranged on the first side of the substrate, and the first signal pin is arranged on the second side of the substrate. The first side and the second side are arranged adjacent to or opposite to each other.

[0078] As shown in Figure 2, the power semiconductor device includes power pins (P1, P2 and P3) and first signal pins (S1, S2, G1 and G2), wherein P1, P2 and P3 are arranged on the first side of the substrate, S1, S2, G1 and G2 are arranged on the second side of the substrate, and the first side and the second side are arranged adjacent to each other.

[0079] As shown in Figure 3, the power semiconductor device includes power pins (P1, P2 and P3) and first signal pins (S1, S2, G1 and G2), wherein P1, P2 and P3 are arranged on the first side of the substrate, and S1, S2, G1 and G2 are arranged on the second side of the substrate, and the first side and the second side are arranged opposite to each other.

[0080] In some embodiments of the present application, there may be multiple first signal pins, and the multiple first signal pins may be arranged on at least two side surfaces of the substrate.

[0081] Exemplarily, multiple power pins are arranged on the first side of the substrate; some first signal pins are arranged on the second side of the substrate, and the remaining first signal pins are arranged on the third side of the substrate; wherein the second side and the third side are both arranged adjacent to the first side.

[0082] As shown in Figure 4, the power semiconductor device includes power pins (P1, P2 and P3) and first signal pins (S1, S2, G1 and G2), wherein P1, P2 and P3 are arranged on the first side of the substrate, S1 and G1 are arranged on the second side of the substrate, and S2 and G2 are arranged on the third side of the substrate, and the second side and the third side are both arranged adjacent to the first side.

[0083] Exemplarily, multiple power pins are arranged on the first side of the substrate; some first signal pins are arranged on the second side of the substrate, and the remaining first signal pins are arranged on the third side of the substrate; wherein the second side is arranged adjacent to the first side and the third side is arranged opposite to the first side.

[0084] As shown in Figure 5, the power semiconductor device includes power pins (P1, P2 and P3) and first signal pins (S1, S2, G1 and G2), wherein P1, P2 and P3 are arranged on the first side of the substrate, S1 and G1 are arranged on the second side of the substrate, and S2 and G2 are arranged on the third side of the substrate, the second side is arranged adjacent to the first side and the third side is arranged opposite to the first side.

[0085] Of course, this application does not exclude the following situations: multiple power pins are arranged on the first side of the substrate; the first part of the first signal pins are arranged on the second side of the substrate, the second part of the first signal pins are arranged on the third side of the substrate, and the remaining first signal pins are arranged on the fourth side of the substrate; wherein the second side and the third side are both arranged adjacent to the first side, and the fourth side is arranged opposite to the first side.

[0086] Since power semiconductor devices generate heat during operation, it is necessary to detect the temperature of the power semiconductor devices for their safety. The power semiconductor devices provided in the embodiments of the present application can be provided with a temperature sensor inside the device package, such as a thermistor, to implement temperature detection. When the temperature of the power semiconductor device rises too high, the power semiconductor device can be protected in a timely manner.

[0087] In some embodiments of the present application, the power semiconductor device further includes a temperature sensor, which is disposed on the substrate.

[0088] Exemplarily, the power semiconductor device includes a thermistor, which is disposed on a substrate, and two ends of the thermistor are electrically connected to the second signal pins respectively.

[0089] As shown in FIG6 , compared with FIG1 , a thermistor RT1 is provided inside the power semiconductor device. Two ends of the thermistor RT1 are electrically connected to second signal pins T1 and T2 respectively. Corresponding temperature data can be obtained by measuring the signals of the second signal pins T1 and T2.

[0090] In some examples, the second signal pin and the power pin are disposed on different sides of the substrate.

[0091] Exemplarily, the second signal pin and the first signal pin are arranged on different sides of the substrate. The first signal pin can be arranged on the same side or different sides of the substrate. Please refer to the arrangement of the first signal pin above and will not be repeated here.

[0092] As shown in Figure 7, the power semiconductor device includes power pins (P1, P2 and P3), first signal pins (S1, S2, G1 and G2) and second signal pins (T1 and T2), wherein P1, P2 and P3 are arranged on the first side of the substrate, S1, S2, G1 and G2 are arranged on the second side of the substrate, T1 and T2 are arranged on the third side of the substrate, and the second side and the third side are arranged adjacent to each other.

[0093] Of course, this application does not exclude the situation in which the second side surface and the third side surface in FIG. 7 are arranged opposite to each other.

[0094] As shown in Figure 8, the power semiconductor device includes power pins (P1, P2 and P3), first signal pins (S1, S2, G1 and G2) and second signal pins (T1 and T2), wherein P1, P2 and P3 are arranged on the first side of the substrate, S1 and G1 are arranged on the second side of the substrate, S2 and G2 are arranged on the third side of the substrate, T1 and T2 are arranged on the fourth side of the substrate, the second side and the third side are arranged opposite to each other, and the fourth side and the first side are arranged opposite to each other.

[0095] Of course, the present application does not exclude the situation in FIG. 8 where the second side surface and the third side surface are adjacently arranged, and the fourth side surface and the first side surface are adjacently arranged.

[0096] Exemplarily, the second signal pins and at least part of the first signal pins are disposed on the same side of the substrate.

[0097] As shown in Figure 9, the power semiconductor device includes power pins (P1, P2 and P3), first signal pins (S1, S2, G1 and G2) and second signal pins (T1 and T2), wherein P1, P2 and P3 are arranged on the first side of the substrate, S1, G1, T1 and T2 are arranged on the second side of the substrate, S2 and G2 are arranged on the third side of the substrate, and the second side and the third side are arranged adjacent to each other.

[0098] Of course, the present application does not exclude the situation in which the second side surface and the third side surface in FIG. 9 are arranged opposite to each other, and the present application also does not exclude the situation in which T1 and T2 can be arranged on the same side surface as all the first signal pins.

[0099] Exemplarily, the power semiconductor device includes a thermistor, which is disposed on the substrate. One end of the thermistor is electrically connected to the third signal pin, and the other end of the thermistor is electrically connected to one of the power pins.

[0100] As shown in FIG10 , compared with FIG1 , a thermistor RT2 is provided inside the power semiconductor device. One end of the thermistor RT2 is electrically connected to the third signal pin T3, and the other end is electrically connected to the power pin P3. Corresponding temperature data can be obtained by measuring the signal of the third signal pin T3.

[0101] In some examples, the third signal pin and the power pin are disposed on the same side of the substrate. The first signal pin may be disposed on the same side or different sides of the substrate, and the configuration of the first signal pin may be referred to above and will not be repeated here.

[0102] As shown in Figure 11, the power semiconductor device includes power pins (P1, P2 and P3), first signal pins (S1, S2, G1 and G2) and a third signal pin T3, wherein P1, P2, P3 and T3 are arranged on the first side of the substrate, S1, S2, G1 and G2 are arranged on the second side of the substrate, and the first side and the second side are arranged opposite to each other.

[0103] Of course, the present application does not exclude other configurations of the first signal pins S1 , S2 , G1 and G2 in FIG. 11 .

[0104] Exemplarily, the power semiconductor device includes two thermistors, namely a first thermistor and a second thermistor, wherein both ends of the first thermistor are electrically connected to the second signal pins, one end of the second thermistor is electrically connected to the third signal pin, and the other end is electrically connected to one of the power pins.

[0105] Alternatively, the power semiconductor device may further include a larger number of thermistors, which will not be further elaborated here.

[0106] As shown in FIG12 , compared with FIG1 , a thermistor RT1 and a thermistor RT2 are provided inside the power semiconductor device. The two ends of the thermistor RT1 are electrically connected to the second signal pins T1 and T2, respectively. One end of the thermistor RT2 is electrically connected to the third signal pin T3, and the other end is electrically connected to the power pin P3. Corresponding temperature data can be obtained by measuring the signals of the second signal pins T1, T2 and the third signal pin T3.

[0107] In some embodiments of the present application, multiple power pins and a third signal pin are arranged on the first side of the substrate, and the first signal pin and the second signal pin are arranged on the second side of the substrate. The first side and the second side are arranged adjacent to or opposite to each other.

[0108] As shown in Figure 13, the power semiconductor device includes power pins (P1, P2 and P3), first signal pins (S1, S2, two G1s and two G2s), second signal pins (T1 and T2) and third signal pin T3, wherein P1, P2, P3 and T3 are arranged on the first side of the substrate, S1, S2, two G1s, two G2s, T1 and T2 are arranged on the second side of the substrate, and the first side and the second side are arranged opposite to each other.

[0109] As shown in Figure 14, the power semiconductor device includes power pins (P1, P2 and P3), first signal pins (S1, S2, two G1s and two G2s), second signal pins (T1 and T2) and third signal pin T3, wherein P1, P2, P3 and T3 are arranged on the first side of the substrate, S1, S2, two G1s, two G2s, T1 and T2 are arranged on the second side of the substrate, and the first side and the second side are arranged adjacent to each other.

[0110] In some embodiments of the present application, multiple power pins and third signal pins are arranged on the same side of the substrate; the number of first signal pins is multiple, and the multiple first signal pins are arranged on at least two sides of the substrate, and the second signal pin is arranged on at least one side where the first signal pin is arranged.

[0111] Exemplarily, multiple power pins and a third signal pin are arranged on the first side of the substrate; some of the first signal pins are arranged on the second side of the substrate, and the remaining first signal pins are arranged on the third side of the substrate; the third signal pin is arranged on the second side or the third side; wherein the second side and the third side are both arranged adjacent to the first side.

[0112] As shown in Figure 15, the power semiconductor device includes power pins (P1, P2 and P3), first signal pins (S1, S2, two G1s and two G2s), second signal pins (T1 and T2) and third signal pin T3, wherein P1, P2, P3 and T3 are arranged on the first side of the substrate, S1 and two G1s are arranged on the second side of the substrate, S2 and two G2s are arranged on the third side of the substrate, T1 and T2 are arranged on the second side of the substrate, and the second side and the third side are both arranged adjacent to the first side.

[0113] Exemplarily, multiple power pins and a third signal pin are arranged on the first side of the substrate; some of the first signal pins are arranged on the second side of the substrate, and the remaining first signal pins are arranged on the third side of the substrate; the third signal pin is arranged on the second side or the third side; wherein the second side is arranged adjacent to the first side and the third side is arranged opposite to the first side.

[0114] As shown in Figure 16, the power semiconductor device includes power pins (P1, P2 and P3), first signal pins (S1, S2, two G1s and two G2s), second signal pins (T1 and T2) and third signal pin T3, wherein P1, P2, P3 and T3 are arranged on the first side of the substrate, S1 and two G1s are arranged on the second side of the substrate, S2 and two G2s are arranged on the third side of the substrate, T1 and T2 are arranged on the third side of the substrate, the second side is arranged adjacent to the first side and the third side is arranged opposite to the first side.

[0115] Exemplarily, multiple power pins and a third signal pin are arranged on the first side of the substrate, a first part of the first signal pins are arranged on the second side of the substrate, a second part of the first signal pins are arranged on the third side of the substrate, and the remaining first signal pins are arranged on the fourth side of the substrate; the second signal pin is arranged on the fourth side; wherein the second side and the third side are both arranged adjacent to the first side, and the fourth side is arranged opposite to the first side.

[0116] As shown in Figure 17, the power semiconductor device includes power pins (P1, P2 and P3), first signal pins (two S1, two S2, two G1 and two G2), second signal pins (T1 and T2) and third signal pin T3, wherein P1, P2, P3 and T3 are arranged on the first side of the substrate, one S1 and one G1 are arranged on the second side of the substrate, one S2 and one G2 are arranged on the third side of the substrate, the other S1, S2, G1 and G2 are arranged on the fourth side of the substrate, T1 and T2 are arranged on the fourth side of the substrate, the second side and the third side are both arranged adjacent to the first side, and the fourth side is arranged opposite to the first side.

[0117] In some embodiments of the present application, the power pin and the first signal pin each include at least one of the following: an SOP surface mount pin, a DIP plug-in pin, a PLCC plug-in pin, or an SOJ surface mount pin.

[0118] SOP (Small Outline Package) pinout: SOP stands for Small Outline Package. Its pins are located on both sides of the package, arranged horizontally or vertically. This package format offers advantages such as small size, excellent electrical performance, and high production efficiency, making it widely used in modern electronic devices. SOP packaging is suitable for a variety of electronic components, such as integrated circuits, diodes, transistors, resistors, and capacitors.

[0119] DIP (Double In-line Package): DIP stands for Double In-line Package. Its pins extend from both sides of the package, and the package materials are either plastic or ceramic. DIP is the most popular plug-in package, used in standard logic ICs, memory LSIs, microcomputer circuits, and more.

[0120] PLCC (Plastic Leaded Chip Carrier) is a plastic-encapsulated J-lead chip package. It has a square, 32-pin package with pins around all four sides, making it much smaller than a DIP package. This package is primarily used for integrated circuits.

[0121] SOJ SMD pin: SOJ is the abbreviation of Small Outline J-Lead Package. It is a derivative of SOP with J-shaped pins and is suitable for use in high-frequency products.

[0122] It should be noted that the second signal pin and the third signal pin may also include at least one of an SOP surface mount pin, a DIP plug-in pin, a PLCC plug-in pin, and an SOJ surface mount pin.

[0123] In one possible implementation, to make the packaging of power semiconductor devices more flexible, power pins and signal pins may have different pin formats. That is, the format of at least some power pins may be different from the format of at least some signal pins. All power pins and all signal pins may have different formats, some power pins and all signal pins may have the same format, or some power pins and some signal pins may have the same format while others may have different formats.

[0124] Various pins can be directly soldered to the copper substrate. The gate and source electrodes of the MOS transistors are soldered to the corresponding pin areas on the copper substrate via bonding wires 20 from the wafer. The thermistor is also directly soldered to the copper substrate. To reduce the overall package size of the power semiconductor device, signal pins can also be in the form of SOJI. The entire power semiconductor device is finally plastic-encapsulated as a single unit to ensure smoothness.

[0125] Since power semiconductor devices generate heat during operation, they need to be dissipated. Power semiconductor devices are typically attached to a heat sink to dissipate the heat. The heat sink is typically cooled by air or water. The heat sink typically needs to be insulated from the interior of the power semiconductor device.

[0126] The power semiconductor device provided in the embodiment of the present application may further include: an insulating layer and a heat dissipation surface; the first surface of the insulating layer is bonded to the first surface of the substrate, the wafer is soldered to the second surface of the substrate, and the first surface and the second surface are arranged opposite to each other.

[0127] The heat dissipation surface is attached to the second surface of the insulating layer, and the first surface is opposite to the second surface.

[0128] The heat dissipation surface of the power semiconductor device provided in the embodiment of the present application can be located at the top or at the bottom, without specific limitation.

[0129] In order to enable those skilled in the art to better understand the technical solutions provided by the embodiments of the present application, several common forms of pins of chip packages are first introduced below with reference to the accompanying drawings.

[0130] See Figure 18, which is a schematic diagram of the top heat dissipation pins provided in an embodiment of the present application in the form of SOP patches.

[0131] Pin J shown in FIG18 is in the form of an SOP patch, and the heat dissipation surface 22 is located on the top of the package.

[0132] Refer to Figure 19, which is a schematic diagram of the top heat dissipation pins provided in an embodiment of the present application in the form of DIP straight plugs.

[0133] The pin J shown in FIG19 is in the form of a DIP plug-in, and the heat dissipation surface 22 is located on the top of the package.

[0134] See Figure 20, which is a schematic diagram of the top heat dissipation pins provided in an embodiment of the present application in the form of PLCC patches.

[0135] Pin J shown in FIG20 is in the form of a PLCC patch, and the heat dissipation surface 22 is located on the top of the package.

[0136] See Figure 21, which is a schematic diagram of the top heat dissipation pins provided in an embodiment of the present application in the form of SOJ patches.

[0137] Pin J shown in FIG21 is in the form of a SOJ patch, and the heat dissipation surface 22 is located on the top of the package.

[0138] In addition, if the power semiconductor device provided in the above embodiments is large enough, in addition to the internal integration of a temperature sensor, other detection circuits, such as a current detection circuit, can also be integrated to implement overcurrent protection. For example, a drive circuit can also be integrated internally. The embodiments of the present application do not specifically limit the other circuits that can be integrated within the power semiconductor device, and can be configured based on the size of the entire chip.

[0139] It should be understood that the embodiments of the present application do not specifically limit the specific implementation form of the power semiconductor device, and may include, for example, any of the following: a diode, a thyristor, a metal-oxide semiconductor field-effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), silicon carbide (SiC), or gallium nitride (GaN). Furthermore, the number of wafers corresponding to the power semiconductor device is not specifically limited. For example, one power semiconductor device may correspond to one wafer, or one power semiconductor device may correspond to multiple wafers, and the multiple wafers may be connected in series or in parallel.

[0140] Based on the power semiconductor device provided in the above embodiment, the embodiment of the present application further provides an on-board charger, and uses the on-board charger as an example to introduce the application scenario of the power semiconductor device.

[0141] The on-board charger may include a power converter, wherein the power converter may include a rectifier circuit and a DC / DC circuit, wherein the rectifier circuit may include the power semiconductor device described in the above embodiment, and the DC / DC circuit may also include the power semiconductor device described in the above embodiment.

[0142] The embodiments of the present application do not specifically limit the implementation form of the rectifier circuit, which can be a half-bridge circuit or a full-bridge circuit. When the rectifier circuit is a half-bridge circuit, the power semiconductor devices corresponding to the half-bridge circuit described in the above embodiments can be used; if it is a full-bridge circuit, the power semiconductor devices corresponding to the half-bridge circuit described in the above embodiments can also be used, except that the full-bridge circuit requires multiple power semiconductor devices corresponding to the half-bridge circuit.

[0143] Based on the on-board charger provided in the above embodiment, an embodiment of the present application further provides a vehicle, which includes the on-board charger.

[0144] In summary, according to the power semiconductor device, on-board charger, and vehicle of the embodiments of the present application, by setting multiple power pins on the same side of the substrate, and setting the first signal pin and the power pin on different sides of the substrate, the power lines and the first type of signal lines can be separated, avoiding cross wiring, and there is no mutual interference between the power lines and the first type of signal lines.

[0145] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely illustrative and are not intended to limit the scope of the present application. Various changes and modifications may be made therein by those skilled in the art without departing from the scope and spirit of the present application. All such changes and modifications are intended to be included within the scope of the present application as required by the appended claims.

[0146] Similarly, it should be understood that in order to streamline the present application and aid in understanding one or more of the various application aspects, in the description of the exemplary embodiments of the present application, the various features of the present application are sometimes grouped together into a single embodiment, figure, or description thereof. However, this approach of the present application should not be interpreted as reflecting the intention that the claimed application requires more features than those explicitly recited in each claim. More precisely, as reflected in the corresponding claims, the point of the application is that the corresponding technical problem can be solved with fewer features than all the features of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into the detailed description, with each claim itself serving as a separate embodiment of the present application.

[0147] Furthermore, those skilled in the art will appreciate that although some embodiments described herein include certain features included in other embodiments but not other features, combinations of features from different embodiments are intended to be within the scope of this application and to form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.

[0148] It should be noted that the above embodiments are illustrative rather than limiting of the present application, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The use of the words first, second, and third, etc., does not denote any order. These words may be interpreted as designations.

Claims

1. A power semiconductor device, characterized in that: The power semiconductor device comprises: a substrate, a first signal pin and a plurality of power pins; The first signal pin and the power pin are both electrically connected to the substrate; Wherein, the plurality of power pins are arranged on the same side of the substrate, and the first signal pin and the power pin are arranged on different sides of the substrate.

2. The power semiconductor device according to claim 1, characterized in that: The plurality of power pins are arranged on a first side surface of the substrate, the first signal pin is arranged on a second side surface of the substrate, and the first side surface and the second side surface are arranged adjacent to or opposite to each other.

3. The power semiconductor device according to claim 1 or 2, characterized in that: There are multiple first signal pins, and the multiple first signal pins are arranged on at least two side surfaces of the substrate.

4. The power semiconductor device according to claim 3, characterized in that: A plurality of the power pins are arranged on the first side of the substrate; Some of the first signal pins are arranged on the second side surface of the substrate, and the rest of the first signal pins are arranged on the third side surface of the substrate; The second side surface and the third side surface are both arranged adjacent to the first side surface, or the second side surface is arranged adjacent to the first side surface and the third side surface is arranged opposite to the first side surface.

5. The power semiconductor device according to claim 3, characterized in that: A plurality of the power pins are arranged on the first side of the substrate; The first signal pins of the first part are arranged on the second side surface of the substrate, the first signal pins of the second part are arranged on the third side surface of the substrate, and the remaining first signal pins are arranged on the fourth side surface of the substrate; The second side surface and the third side surface are both arranged adjacent to the first side surface, and the fourth side surface is arranged opposite to the first side surface.

6. The power semiconductor device according to any one of claims 1 to 5, characterized in that: The power semiconductor device further includes a temperature sensor disposed on the substrate.

7. The power semiconductor device according to claim 6, characterized in that: The temperature sensor includes a first thermistor and / or a second thermistor, wherein two ends of the first thermistor are electrically connected to the second signal pins respectively, one end of the second thermistor is electrically connected to the third signal pin, and the other end is electrically connected to one of the power pins.

8. The power semiconductor device according to claim 7, characterized in that: The second signal pin and the power pin are arranged on different sides of the substrate.

9. The power semiconductor device according to claim 8, characterized in that: The second signal pin and the first signal pin are arranged on different sides of the substrate; or, the second signal pin and at least part of the first signal pin are arranged on the same side of the substrate.

10. The power semiconductor device according to any one of claims 7 to 9, characterized in that: The third signal pin and the power pin are arranged on the same side of the substrate.

11. The power semiconductor device according to any one of claims 7 to 9, characterized in that: The plurality of power pins and the third signal pin are arranged on the first side surface of the substrate; the first signal pin and the second signal pin are arranged on the second side surface of the substrate, and the first side surface and the second side surface are arranged adjacent to or opposite to each other.

12. The power semiconductor device according to any one of claims 7 to 9, characterized in that: The plurality of power pins and the third signal pin are arranged on the same side of the substrate; There are multiple first signal pins, and the multiple first signal pins are arranged on at least two side surfaces of the substrate, and the second signal pins are arranged on at least one side surface where the first signal pins are arranged.

13. The power semiconductor device according to claim 12, characterized in that: The plurality of power pins and the third signal pins are arranged on the first side of the substrate; Some of the first signal pins are arranged on the second side surface of the substrate, and the rest of the first signal pins are arranged on the third side surface of the substrate; The third signal pin is arranged on the second side surface or the third side surface; The second side surface and the third side surface are both arranged adjacent to the first side surface, or the second side surface is arranged adjacent to the first side surface and the third side surface is arranged opposite to the first side surface.

14. The power semiconductor device according to claim 12, characterized in that: The plurality of power pins and the third signal pins are arranged on the first side of the substrate, The first signal pins of the first part are arranged on the second side surface of the substrate, the first signal pins of the second part are arranged on the third side surface of the substrate, and the remaining first signal pins are arranged on the fourth side surface of the substrate; The second signal pin is arranged on the fourth side surface; The second side surface and the third side surface are both arranged adjacent to the first side surface, and the fourth side surface is arranged opposite to the first side surface.

15. The power semiconductor device according to any one of claims 1 to 14, characterized in that: The power semiconductor device includes any one of the following: a diode, a thyristor, a metal-oxide semiconductor field effect transistor, an insulated gate bipolar transistor, silicon carbide or gallium nitride.

16. The power semiconductor device according to any one of claims 1 to 15, characterized in that: The power pin and the first signal pin each include at least one of the following: SOP chip pins, DIP direct plug pins, PLCC direct plug pins, SOJ chip pins.

17. The power semiconductor device according to any one of claims 1 to 16, characterized in that: The power semiconductor device further comprises an outer shell and a wafer, wherein the wafer is arranged on the substrate; the outer shell encapsulates the wafer and the substrate.

18. A vehicle-mounted charger, characterized in that: A power semiconductor device comprising any one of claims 1-17.

19. A vehicle, characterized in that: It includes the on-board charger as claimed in claim 18.

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