Sic mosfet cell structure and manufacturing method therefor

Abstract

The present application discloses a SiC MOSFET cell structure and a manufacturing method therefor. The cell structure comprises: a source electrode metal region (source), a source electrode OHM region, a source electrode ohmic contact region N+, a channel N-type doped region NC, a channel P-type doped region PC, a vertical conductive channel JFET region, a Pwell region, a drift layer N-, a substrate N+, a drain electrode OHM region, a gate electrode region (gate), and a gate-source isolation medium SiO2.

Description

SiC MOSFET cell structure and manufacturing method thereof

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on November 23, 2023, with application number 202311570249.1, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the technical field of electronic components, for example, a SiC MOSFET cell structure and a manufacturing method thereof. Background Art

[0003] Compared to silicon (Si), silicon carbide (SiC) boasts material advantages such as three times the bandgap, ten times the breakdown field strength, and three times the thermal conductivity. Consequently, SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) offer low leakage, high operating junction temperature, high breakdown voltage, high switching speed, low losses, and low heat dissipation requirements. Their switching losses and on-current density are lower than those of Si insulated-gate bipolar transistors (IGBTs) and Si MOSFETs. They hold promising application prospects in renewable energy power generation, new energy vehicles, and high-voltage power transmission and transformation, making them a focus of scientific research and industrialization worldwide.

[0004] The main obstacles currently hindering SiC MOSFET device performance improvements are low channel field-effect mobility, high channel resistance, and poor device conduction performance, preventing the full utilization of SiC's material advantages. Although major research institutions and semiconductor manufacturers worldwide are conducting research on gate dielectric fabrication technologies, it currently appears that field-effect mobility will not see significant improvements for a long time.

[0005] Currently, SiC MOSFET wafer designers generally use self-alignment to generate short channels and reduce channel resistance by increasing channel density. Short channels are currently achieved primarily through polysilicon self-oxidation and dielectric sidewall etching. Polysilicon self-oxidation typically uses thick-film polysilicon masked high-temperature oxidation to achieve stable line width variation and thus a short channel. However, this method struggles to ensure consistent channel length due to issues with the quality of the polysilicon film and the morphology after self-oxidation. The dielectric sidewall method uses dielectric sidewall etching to achieve line width variation, which offers better morphology and symmetry. However, the two etching steps damage the semiconductor surface, making process control more challenging.

[0006] In the two self-aligned processes of related technologies, polysilicon self-oxidation results in poor mask morphology due to thick-film polysilicon growth, and the morphological defects are exacerbated by the change in polysilicon oxidation line width; the dielectric sidewall morphology is good, but the two etchings require precise etching control. Once a large amount of over-etching occurs, the surface semiconductor will be damaged. Both of the above methods form the channel through ion implantation, and the implantation process is prone to injection scattering, which affects the channel injection morphology. The length of the vertical channel of the strip-structured cellular MOSFET (MOS) channel and the junction field-effect transistor (JFET) is 1:1 to the ohmic contact length, but the SiC MOSFET channel resistance is large, and this structure is not conducive to reducing the on-resistance.

[0007] Summary of the Invention

[0008] The present application provides a SiC MOSFET cell structure and a manufacturing method thereof, which precisely controls the channel length and morphology, and realizes a new cell structure to improve the channel density.

[0009] The present application provides a SiC MOSFET cell structure, including: a source metal region source, a source OHM region, a source ohmic contact region N+, a channel N-type doped region NC, a channel P-type doped region PC, a vertical conductive channel JFET region, a Pwell region, a drift layer N-, a substrate N+, a drain OHM region, a gate electrode region gate, and a gate-source isolation dielectric SiO2; when a positive voltage is applied to the gate electrode region gate, the surface of the channel P-type doped region PC enters an inversion state, and the device (cell structure) enters an on state, and the electron flow path is: source metal region source → source OHM region → source ohmic contact region N+ → channel N-type doped region NC → channel P-type doped region PC → vertical conductive channel JFET region → drift layer N- → substrate N+ → drain OHM region; when a zero voltage or a negative voltage is applied to the gate electrode region gate, the device (cell structure) enters a blocking state, the drift layer N- is depleted, and the Pwell region acts as a resistance voltage.

[0010] In one or more embodiments, the Pwell region concentration is 1E18 cm -3 Above, the injection depth is between 0.5um and 2.5um.

[0011] In one or more embodiments, the channel P-type doping region PC has a thickness of less than 0.5 μm and a doping concentration of 1E16 cm -3 to 5E17cm -3 between.

[0012] In one or more embodiments, the channel N-type doping region NC has a doping concentration of 1E16 cm -3Above, thickness is greater than 0.2um.

[0013] In one or more embodiments, the source ohmic contact region N+ has a doping concentration greater than 1E18 cm -3 .

[0014] Accordingly, a method for manufacturing a SiC MOSFET cell structure includes the following steps:

[0015] Step 1: growing a drift layer N- on the source ohmic contact region N+ substrate by epitaxial growth;

[0016] Step 2: P-type ion implantation is used to form the Pwell region. In order to achieve better chip withstand voltage, the Pwell concentration is 1E18cm -3 Above, the injection depth is between 0.5um and 2.5um;

[0017] Step 3: Grow an N-type epitaxial layer on the implanted surface by epitaxial growth, with a doping concentration of 1E15cm -3 to 1E18cm -3 Between, the thickness is between 0.1um and 1.0um;

[0018] Step 4: forming a channel by dry etching, wherein the etching depth is less than the sum of the implantation depth of the Pwell region and the thickness of the N-type epitaxial layer;

[0019] Step 5: Form a channel P-type doped layer PC by P-type epitaxial growth, with a thickness of less than 0.5um and a doping concentration of 1E16cm -3 to 5E17cm -3 between;

[0020] Step 6: forming a channel P-type doped region PC by dry etching;

[0021] Step 7: Form a channel N-type doped layer NC by N-type epitaxial growth with a doping concentration of 1E16cm -3 Above, thickness greater than 0.2um;

[0022] Step 8: Form a channel N-type doped region NC by dry etching. When the formed trench width is less than 2 times the NC growth thickness, the trench will be closed and the surface will be flat.

[0023] Step 9: Form the source ohmic contact region N+ by N-type high-dose ion implantation, with a doping concentration greater than 1E18cm -3 ;

[0024] Step 10: Prepare a gate dielectric layer on the wafer surface, with a dielectric thickness between 20 nm and 100 nm;

[0025] Step 11: preparing a gate polysilicon electrode, wherein the thickness of the polysilicon electrode is between 200 nm and 1000 nm;

[0026] Step 12: preparing a gate-source isolation dielectric, wherein the thickness of the isolation dielectric is between 100 nm and 1500 nm;

[0027] Step 13: Etch the gate-source isolation dielectric and form a source OHM region, form a drain OHM region on the back of the wafer, and form a source metal region (thickened). BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIG1 is a schematic diagram of the cell structure of the present application;

[0029] FIG2 is a schematic diagram of the chip cell layout structure of the present application;

[0030] FIG3 is a schematic diagram of growing a drift layer N- by epitaxial growth on an N+ substrate according to the present invention;

[0031] FIG4 is a schematic diagram of forming a Pwell region by P-type ion implantation in the present application;

[0032] FIG5 is a schematic diagram of growing an N-type epitaxial layer on the implanted surface by epitaxial growth in the present application;

[0033] FIG6 is a schematic diagram of forming a channel by dry etching in the present application;

[0034] FIG7 is a schematic diagram of forming a channel P-type doped layer PC by P-type epitaxial growth in the present application;

[0035] FIG8 is a schematic diagram of forming a channel P-type doped region PC by dry etching in the present application;

[0036] FIG9 is a schematic diagram of forming a channel N-type doped layer NC by N-type epitaxial growth in the present application;

[0037] FIG10 is a schematic diagram of forming a channel N-type doped region NC by dry etching in the present application;

[0038] FIG11 is a schematic diagram of forming an N-type ohmic contact region by N-type high-dose ion implantation in the present application;

[0039] FIG12 is a schematic diagram of preparing a gate dielectric layer on a wafer surface in the present application;

[0040] FIG13 is a schematic diagram of preparing a gate polysilicon electrode according to the present application;

[0041] FIG14 is a schematic diagram of preparing a gate-source isolation dielectric according to the present application;

[0042] FIG15 is a schematic diagram of the SiC MOSFET chip processing completed in this application. DETAILED DESCRIPTION

[0043] As shown in Figures 1 and 2, Figure 2 is a top view of the cell layout, and Figure 1 is a cross-sectional view of the cell structure taken from the arrow shown on the left side of Figure 2. The position marked with the reference numerals in Figure 2 does not mean that the part of the structure is exposed at the top, but only represents that the part of the structure is at this position. A SiC MOSFET cell structure includes: a source metal region (source), a source ohmic (OHM) region, a source ohmic contact region N+ (N+ at the upper position in Figure 1), a channel N-type doped region NC, a channel P-type doped region PC, Vertical conductive channel JFET region, P well (well) region, drift layer N-, substrate N+ (N+ at the lower position in Figure 1), drain OHM region, gate electrode region gate, gate-source isolation dielectric SiO2; when a positive voltage is applied to the gate electrode region gate, the surface of the channel P-type doped region PC enters an inversion state, and the cellular structure enters an open state. The electron flow path is: source metal region source → source OHM region → source ohmic contact region N+ → channel N-type doped region NC → channel P-type doped region PC → JFET region → drift layer N- → substrate N+ → drain OHM region; when 0 voltage or negative voltage is applied to the gate electrode region gate, the cellular structure enters a blocking state, the drift layer N- is depleted, and the Pwell region acts as a resistance voltage.

[0044] Accordingly, a method for manufacturing a SiC MOSFET cell structure includes the following steps:

[0045] Step 1: growing a drift layer N- on a substrate N+ by epitaxial growth, as shown in FIG3 ;

[0046] Step 2: P-type ion implantation is used to form a Pwell region, as shown in Figure 4. In order to achieve better chip withstand voltage, the Pwell concentration is 1E18cm -3 Above, the injection depth is between 0.5um and 2.5um;

[0047] Step 3: grow an N-type epitaxial layer on the implanted surface by epitaxial growth, as shown in Figure 5, with a doping concentration of 1E15cm -3 to 1E18cm -3 Between, the thickness is between 0.1um and 1.0um;

[0048] Step 4: forming a trench (channel) by dry etching, as shown in FIG6 , wherein the etching depth is less than the sum of the implantation depth of the Pwell region and the thickness of the N-type epitaxial layer;

[0049] Step 5: Form a channel P-type doped layer PC by P-type epitaxial growth, as shown in Figure 7, with a thickness of less than 0.5um and a doping concentration of 1E16cm -3 to 5E17cm -3 between;

[0050] Step 6: forming a channel P-type doped region PC by dry etching, as shown in FIG8 ;

[0051] Step 7: Form the channel N-type doped layer NC by N-type epitaxial growth. As shown in Figure 9, the channel width is less than 2 times the NC growth thickness. The channel will be closed and the surface is flat. The doping concentration is 1E16cm -3 Above, thickness greater than 0.2um;

[0052] Step 8: forming a channel N-type doped region NC by dry etching, as shown in FIG10 ;

[0053] Step 9: Form the source ohmic contact region N+ by N-type high-dose ion implantation, as shown in Figure 11, with a doping concentration greater than 1E18 cm -3 ;

[0054] Step 10: Prepare a gate dielectric layer on the wafer surface, as shown in FIG12 , with a dielectric thickness between 20 nm and 100 nm;

[0055] Step 11: preparing a gate polysilicon electrode, as shown in FIG13 , wherein the thickness of the polysilicon electrode is between 200 nm and 1000 nm;

[0056] Step 12: Prepare a gate-source isolation dielectric, as shown in FIG14 , wherein the thickness of the isolation dielectric is between 100 nm and 1500 nm;

[0057] Step 13: Etch the gate-source isolation dielectric and make source OHM area contacts, make the drain OHM area on the back of the wafer, and make a thickened source metal area, as shown in FIG15 .

[0058] Example:

[0059] 1200V SiC MOSFET chip processing:

[0060] S1: Grow the drift layer N- on the N+ substrate by epitaxial growth with a thickness of 10 μm and a doping concentration of 1E16 cm -3 ;

[0061] S2: P-type ion implantation forms the Pwell region with an implantation concentration of 5E18cm -3 , the injection depth is 1.0um;

[0062] S3: Grow an N-type epitaxial layer on the implanted surface by epitaxial growth, with a doping concentration of 1E17cm -3 , thickness 0.3um;

[0063] S4: forming a trench by dry etching with an etching depth of 0.4 μm;

[0064] S5: Form a channel P-type doped layer PC by P-type epitaxial growth, with a thickness of 0.2um and a doping concentration of 1E17cm -3 ;

[0065] S6: forming a channel P-type doped region PC by dry etching, with a PC width equal to 0.2 μm;

[0066] S7: Form the channel N-type doped layer NC by N-type epitaxial growth, with a doping concentration of 1E18cm -3 , thickness 0.2um

[0067] S8: Form the channel N-type doped region NC by dry etching with an etching depth of 0.3 μm.

[0068] S9: N-type ohmic contact region is formed by N-type high-dose ion implantation with a doping concentration of 1E19cm -3 ;

[0069] S10: preparing a 50nm gate dielectric layer on the wafer surface;

[0070] S11: preparing a gate polysilicon electrode with a thickness of 500 nm;

[0071] S12: preparing a gate-source isolation dielectric with a thickness of 800 nm;

[0072] S13: Complete SiC MOSFET chip processing through dielectric etching process, metal stripping process, source electrode thickening metallization, back side metallization and other processes.

[0073] This application uses epitaxial growth combined with semiconductor sidewall etching to achieve channel self-alignment. Compared with other methods, this application does not use ion implantation in the doping process, thus avoiding channel defects caused by ion scattering during the implantation process. Furthermore, semiconductor sidewall etching is used to form the PC and NC regions of the channel, so that the channel length is determined by the thickness of the epitaxial film growth. Since the epitaxial thickness is easy to precisely control, the channel length can also be precisely controlled. At the same time, the P-type doped PC region of the channel does not undergo high-energy ion implantation and is not compensated with the N-type, resulting in lower device reliability and channel defect density.

Claims

1. A SiC MOSFET cell structure, comprising: Source metal region source, source ohmic OHM region, source ohmic contact region N+, channel N-type doping region NC, channel P-type doping region PC, vertical conductive channel junction field effect transistor JFET region, P well region, drift layer N-, substrate N+, drain OHM region, gate electrode region gate, gate-source isolation dielectric SiO2; when a positive voltage is applied to the gate electrode region gate, the surface of the channel P-type doping region PC enters an inversion state, and the cell structure enters an open state, and the path of electron flow is: source metal region source→source OHM region→source ohmic contact region N+→channel N-type doping region NC→channel P-type doping region PC→vertical conductive channel JFET region→drift layer N-→substrate N+→drain OHM region; when a 0 voltage or a negative voltage is applied to the gate electrode region gate, the cell structure enters a blocking state, the drift layer N- is depleted, and the Pwell region acts as a voltage resistance.

2. The SiC MOSFET cell structure according to claim 1, wherein: The concentration in the Pwell region is 1E18cm -3 Above, the injection depth is between 0.5um and 2.5um.

3. The SiC MOSFET cell structure according to claim 1, wherein: The channel P-type doping region PC has a thickness of less than 0.5um and a doping concentration of 1E16cm -3 To 5E17cm -3 between.

4. The SiC MOSFET cell structure according to claim 1, wherein: Channel N-type doping region NC, doping concentration is 1E16cm -3 Above, the thickness is greater than 0.2um.

5. The SiC MOSFET cell structure according to claim 1, wherein: Source ohmic contact region N+, doping concentration greater than 1E18cm -3 .

6. A method for manufacturing a SiC MOSFET cell structure according to claim 1, comprising the following steps: Step 1, growing a drift layer N- on a substrate N+ by epitaxial growth; Step 2, forming a Pwell region by P-type ion implantation; Step 3, growing an N-type epitaxial layer on the implanted surface by epitaxial growth; Step 4: forming a channel by dry etching, wherein the etching depth is less than the sum of the implantation depth of the Pwell region and the thickness of the N-type epitaxial layer growth; Step 5, forming a channel P-type doped layer PC by P-type epitaxial growth; Step 6: forming a channel P-type doping region PC by dry etching; Step 7: Form a channel N-type doped layer NC by N-type epitaxial growth, wherein the formed channel width is less than 2 times the NC growth thickness, the channel is closed, and the surface is planar; Step 8, forming a channel N-type doping region NC by dry etching; Step 9: Form the source ohmic contact region N+ by N-type high-dose ion implantation, with a doping concentration greater than 1E18cm -3 ; Step 10: preparing a gate dielectric layer on the surface of the wafer, wherein the dielectric thickness is between 20 nm and 100 nm; Step 11, preparing a gate polysilicon electrode, wherein the thickness of the polysilicon electrode is between 200nm and 1000nm; Step 12: preparing a gate-source isolation dielectric, wherein the thickness of the isolation dielectric is between 100 nm and 1500 nm; Step 13: Etch the gate-source isolation dielectric and form a source OHM region, form a drain OHM region on the back of the wafer, and form a source metal region source.

7. The method for manufacturing a SiC MOSFET cell structure according to claim 6, wherein: In step 2, the Pwell concentration was 1E18 cm -3 Above, the injection depth is between 0.5um and 2.5um.

8. The method for manufacturing a SiC MOSFET cell structure according to claim 6, wherein: In step 3, the doping concentration of the N-type epitaxial layer is 1E15cm -3 To 1E18cm -3 The thickness is between 0.1um and 1.0um.

9. The method for manufacturing a SiC MOSFET cell structure according to claim 6, wherein: In step 5, the thickness of the channel P-type doping layer PC is less than 0.5um, and the doping concentration is 1E16cm -3 To 5E17cm -3 between.

10. The method for manufacturing a SiC MOSFET cell structure according to claim 6, wherein: In step 7, the doping concentration of the channel N-type doping layer NC is 1E16cm -3 Above, the thickness is greater than 0.2um.

Images