Chip packaging body, working assembly and computing device

Abstract

Provided in the embodiments of the present application are a chip packaging body, a working assembly and a computing device. The chip packaging body comprises: a substrate; and a plurality of die modules, which are arranged on one side of the substrate, wherein at least some of the plurality of die modules are connected to each other, the plurality of die modules comprise at least one memory die module, and the memory die module comprises a plurality of stacked memory dies and logic processing dies. By means of providing a chiplet-based 2.5D / 3D packaging solution, the technical solution of the embodiments of the present application can realize an ultra-large computing power and an ultra-high storage bandwidth.

Description

Chip packages, working components and computing devices

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on November 24, 2023, with application number 202311587753.2 and invention name “Chip package, working components and computing device”, the entire contents of which are incorporated by reference into this application.

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on November 24, 2023, with application number 202323192689.6 and invention name “Chip package, working components and computing device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of chip packaging technology, and in particular to a chip package, a working component and a computing device. Background Art

[0004] On the one hand, as semiconductor manufacturing technology advances, transistor density is approaching its limits, leading to problems such as heat generation, severe power consumption, and nonlinear increases in manufacturing costs. As semiconductor manufacturing technology node advancements slow and enter the "post-Moore era," advanced packaging has become a key path to continuing Moore's Law.

[0005] On the other hand, as high-performance computing applications continue to expand, higher performance requirements are being placed on computing chips. Among related technologies, the memory wall, which hinders traditional computing performance, is also a major challenge. Near-memory computing is a solution proposed to address the memory wall problem. It improves computing performance by shortening the path length between the processor and memory and increasing the path bandwidth. Furthermore, improvements in chip technology and performance are driving demand for advanced packaging and chip modules (chiplets).

[0006] Summary of the Invention

[0007] Embodiments of the present application provide a chip package, a working component, and a computing device to solve or alleviate one or more technical problems in the prior art.

[0008] As one aspect of an embodiment of the present application, an embodiment of the present application provides a chip package, comprising: a substrate; a plurality of bare chip modules arranged on one side of the substrate, at least some of the plurality of bare chip modules being interconnected; the plurality of bare chip modules including at least one memory bare chip module, the memory bare chip module including stacked memory bare chips and logic processing bare chips.

[0009] In one embodiment, the logic processing die includes a memory control unit and / or a processor unit.

[0010] In one embodiment, there are multiple memory dies.

[0011] In one embodiment, the number of logic processing dies is one or more.

[0012] In one embodiment, the top die of the memory die module is the memory die, and the bottom die of the memory die module is the logic processing die; or, the top die of the memory die module is the logic processing die, and the bottom die of the memory die module is the memory die.

[0013] In one embodiment, non-top dies of the memory die module are provided with through silicon vias (TSVs).

[0014] In one embodiment, the dies of the memory die module are connected by hybrid bonding or by micro-bumps.

[0015] In one embodiment, the connection between the bare chip modules includes: connection through the substrate.

[0016] In one embodiment, a substrate circuit is embedded in the substrate, and the bare chip modules are connected to each other via the substrate circuit.

[0017] In one embodiment, a bridge die and a redistribution RDL interposer are provided in the substrate. The RDL interposer is arranged on a side of the bridge die facing the die module. The connection between the die modules includes: connecting to each other through the RDL interposer.

[0018] In one embodiment, the bridge die is configured as a silicon dielectric.

[0019] In one embodiment, the bridge die includes a silicon dielectric and TSVs in the silicon dielectric.

[0020] In one embodiment, the connection between the bare chip modules includes: connection through an intermediary layer, wherein the intermediary layer is arranged between the substrate and the bare chip modules.

[0021] In one embodiment, the interposer includes an RDL interposer, and the RDL interposer includes an RDL medium and an RDL wiring layer in the RDL medium.

[0022] In one embodiment, the interposer includes a bridge die interposer, wherein the bridge die interposer includes a filling medium and a bridge die surrounded by the filling medium.

[0023] In one embodiment, the bridge die interposer further includes an RDL interposer, and the RDL interposer is arranged on a side of the bridge die facing the die module.

[0024] In one embodiment, the bridge die is configured as a silicon dielectric; or the bridge die includes a silicon dielectric and TSVs in the silicon dielectric.

[0025] In one embodiment, the bridge die interposer further includes a TIV located in the filling medium for connecting the die module and the substrate.

[0026] In one embodiment, the interposer includes a silicon interposer, and the silicon interposer includes a silicon dielectric and a TSV disposed in the silicon dielectric.

[0027] In one embodiment, the interposer includes a silicon interposer and an RDL interposer located between the silicon interposer and the bare die module. The silicon interposer includes a silicon dielectric and a TSV disposed in the silicon dielectric.

[0028] In one embodiment, the interposer further includes an RDL interposer located between the silicon interposer and the substrate.

[0029] In one embodiment, a plurality of memory die modules are distributed in rows and columns on one side of the substrate.

[0030] In one embodiment, there are adjacent memory die modules connected to each other among a plurality of memory die modules, wherein the adjacent memory die modules are memory die modules adjacent in a first direction, and / or the adjacent memory die modules are memory die modules adjacent in a second direction, the first direction is a row direction or a column direction, and the second direction forms an angle with the first direction in the plane where the substrate is located.

[0031] In one embodiment, the plurality of bare chip modules further include an input / output (IO) bare chip, and the IO bare chip is interconnected with at least some of the memory bare chip modules.

[0032] In one embodiment, the memory die modules and the IO die are arranged in rows and columns.

[0033] In one embodiment, the IO die is located at an edge of the array in a first direction, where the first direction is a row direction or a column direction.

[0034] In one embodiment, there are adjacent memory bare chip modules connected to each other among the multiple memory bare chip modules, wherein the adjacent memory bare chip modules are memory bare chip modules adjacent in a first direction, and / or the adjacent memory bare chip modules are memory bare chip modules adjacent in a second direction, the first direction is a row direction or a column direction, and the second direction forms an angle with the first direction in the plane where the substrate is located.

[0035] In one embodiment, at least one IO die is distributed around each of the memory die modules.

[0036] In one embodiment, four IO dies are distributed around each memory die module, and adjacent IO dies in a first direction are connected to each other, where the first direction is a row direction or a column direction.

[0037] In one embodiment, the plurality of bare chip modules further include an IO bare chip module, the IO bare chip module includes stacked IO bare chips and memory bare chips, and the IO bare chip module is interconnected with at least part of the memory bare chip modules.

[0038] In one embodiment, the top die of the IO die module is the memory die, and the bottom die of the IO die module is the IO die; or, the top die of the IO die module is the IO die, and the bottom die of the IO die module is the memory die.

[0039] In one embodiment, the memory die modules and the IO die modules are arranged in an array in rows and columns on one side of the substrate.

[0040] In one embodiment, the IO bare chip module is located at an edge of the array in a first direction, and the first direction is a row direction or a column direction.

[0041] In one embodiment, there are adjacent memory bare chip modules connected to each other among the multiple memory bare chip modules, wherein the adjacent memory bare chip modules are memory bare chip modules adjacent in a first direction, and / or the adjacent memory bare chip modules are memory bare chip modules adjacent in a second direction, the first direction is a row direction or a column direction, and the second direction forms an angle with the first direction in the plane where the substrate is located.

[0042] In one embodiment, at least one IO die module is distributed around each of the memory die modules.

[0043] In one embodiment, four IO bare chip modules are distributed around each of the memory bare chip modules, and the IO bare chip modules adjacent to each other in a first direction are connected to each other, where the first direction is a row direction or a column direction.

[0044] In one embodiment, adjacent IO die modules are connected to each other.

[0045] As one aspect of an embodiment of the present application, an embodiment of the present application provides a working component, including a chip package in any one implementation manner of the embodiment of the present application, and a PCB board, wherein the chip package is arranged on one side of the PCB board.

[0046] In one embodiment, there are multiple chip packages.

[0047] In one embodiment, at least some of the plurality of chip packages are connected to each other.

[0048] In one embodiment, a memory device is arranged on one side of the PCB board, and the bare chip module in the chip package is connected to the memory device through the PCB board.

[0049] In one embodiment, there are multiple memory devices.

[0050] In one embodiment, the memory device and the chip packaging unit are arranged on the same side of the PCB board.

[0051] As one aspect of an embodiment of the present application, an embodiment of the present application provides a computing device, including a working component and a power supply module in any implementation manner of the embodiment of the present application.

[0052] In one embodiment, there are multiple working components.

[0053] In one embodiment, at least some of the plurality of working components are connected to each other.

[0054] The technical solution of the embodiment of the present application can achieve ultra-large computing power and ultra-high storage bandwidth by providing a chiplet-based 2.5D / 3D packaging solution.

[0055] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present application will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0057] 1A and 1B are structural diagrams of a chip package according to an embodiment of the present application;

[0058] 2A, 2B and 2C are structural diagrams of a chip package according to an embodiment of the application;

[0059] 3A, 3B, 3C, 3D, and 3E illustrate structural diagrams of a chip package according to an embodiment of the present application;

[0060] FIG4 shows a topological diagram of a chip package according to an embodiment;

[0061] 5A and 5B illustrate interconnection topologies of a chip package according to an embodiment;

[0062] FIG6 shows a structural diagram of a chip package according to an embodiment of the present application;

[0063] 7A, 7B, 7C and 7D illustrate interconnection topologies of chip packages according to embodiments;

[0064] 8A and 8B illustrate interconnection topologies of a chip package according to an embodiment;

[0065] FIG9 shows a structural diagram of a chip package according to an embodiment of the present application;

[0066] FIG10 shows an interconnection topology diagram of a chip package according to an embodiment;

[0067] FIG11 shows a structural diagram of a chip package according to an embodiment of the present application;

[0068] 12A , 12B , 12C and 12D illustrate interconnection topologies of a chip package according to an embodiment;

[0069] 13A and 13B illustrate interconnection topologies of a chip package according to an embodiment;

[0070] FIG14 shows a structural diagram of a chip package according to an embodiment of the present application;

[0071] FIG15 shows an interconnection topology diagram of a chip package according to an embodiment;

[0072] FIG16 shows a structural diagram of a working component according to an embodiment of the present application;

[0073] FIG17 shows a structural diagram of a working component according to an embodiment of the present application.

[0074] Description of reference numerals:

[0075] 10: Bare die module; 20: Substrate;

[0076] 100: memory die module; 101: logic processing die; 102: memory die;

[0077] 103: substrate circuit; 104: C4 bump; 105: micro bump; 108: hole;

[0078] 110: RDL interposer; 106: RDL medium; 107: RDL wiring layer;

[0079] 210: bridge die interposer; 201: bridge die; 202: filling medium;

[0080] 203:TIV;

[0081] 310: silicon interposer; 204: TSV; 205: silicon dielectric;

[0082] 200: IO bare chip; 300: IO bare chip module;

[0083] 30: PCB board; 50: connecting wire; 109: solder ball;

[0084] 40, 60: chip package; 70: memory device. DETAILED DESCRIPTION

[0085] Hereinafter, only certain exemplary embodiments are briefly described. As will be appreciated by those skilled in the art, the described embodiments may be modified in various ways without departing from the spirit or scope of the present application. Therefore, the drawings and description are to be regarded as illustrative in nature and not restrictive.

[0086] Application Scenario

[0087] As technology advances, chips become increasingly integrated and their performance continues to improve. However, as technology further develops, integrating more functions and components on a single chip becomes increasingly challenging, increasing manufacturing costs and complexity.

[0088] To overcome these challenges, the concept of chip modules (chiplets) began to emerge in the field of semiconductor manufacturing technology. A chiplet can be understood as a small, independent chip module, which usually contains a specific functional unit or processing unit. Unlike traditional single chips, chiplets split the entire system into multiple smaller, more focused parts. These chiplets can be designed, manufactured and tested independently, and then combined together in a package to form a complete functional system or processing system to achieve a design and manufacturing method with higher flexibility, performance optimization and cost reduction. Chiplets are an innovative solution to the challenges of complexity and cost in the context of continuous improvement in chip technology and performance.

[0089] Under the technical concept of chiplet, 2.5D and 3D packaging solutions have emerged, such as chip-on-wafer-on-substrate (CoWoS) packaging technology. In an exemplary CoWoS solution, the logic processing die and high-bandwidth memory (HBM) stack are integrated together, usually by laying out multiple HBM stacks around the logic die to provide excellent computing and memory performance. Among them, the logic die is the core computing unit of the CoWoS packaged chip, which contains a large number of graphics processing units (GPUs) for high-performance computing tasks; the HBM stack uses 3D stacking technology to stack multiple memory chip components together, and communicate through silicon through-holes (TSV) to provide high-bandwidth and low-latency memory access.

[0090] The CoWoS solution allows multiple chips with different functions to be integrated into a single package, thereby providing higher performance and efficiency. However, compared with other packaging solutions with the same computing power and bandwidth, the chip packaging area of ​​the CoWoS solution will also be larger, and the power consumption and cost will be higher.

[0091] Figures 1A and 1B illustrate the architecture of a chip package provided by an embodiment of the present application. As shown in Figures 1A and 1B , the chip package includes a substrate 20 and multiple bare die modules 10 , which are arranged on one side of the substrate 20 .

[0092] The substrate 20 is used as a packaging substrate, and its material includes an organic substrate, a ceramic substrate, a sapphire substrate, etc. Different applications and requirements may select different types of materials, which are not limited in the present embodiment.

[0093] The connection method between the bare chip module 10 and the substrate 20 is not limited in the embodiment of the present application. For example, it can be connected through a controlled collapse chip connection bump (Controlled Collapse Chip Connection, referred to as C4 bump or C4 bump) or a connection method using an interposer.

[0094] C4 bumps are manufactured using a bumping process, with metal deposition as the core process. The most common metal deposition steps include the deposition of the under-bump metallization (UBM) and the deposition of the bump itself. UBM deposition is typically achieved through sputtering, electroless plating, or electroplating, while the bump itself is typically deposited through electroplating, ball placement, or printing.

[0095] Interposers can help components in the upper or lower layers to electrically interconnect and exchange information (for example, connecting two bare chips). There are many types of interposers, and you can choose one based on actual needs. The following will introduce them through specific examples.

[0096] Furthermore, the plurality of bare die modules 10 include at least one memory bare die module 100. In other words, all or some of the plurality of bare die modules 10 may be configured as memory bare die modules 100, i.e., other types of bare die modules may be present in the plurality of bare die modules 10. The embodiment of the present application does not limit the number of bare die modules 10 and memory bare die modules 100.

[0097] The memory chip module 100 includes a plurality of stacked memory dies 102 and a logic processing die 101. In the embodiment of the present application, the number, stacking method, and arrangement position of the memory dies 102 and the logic processing die 101 are not limited, and can be, for example, 1, 2, 4, 8, 12, 16, 20, 24, etc.

[0098] In one example, in the memory die module 100 shown in FIG. 1A , there are multiple memory dies 102 , the top die of the memory die module 100 is the logic processing die 101 , and the bottom die of the memory die module 100 is the memory die 102 .

[0099] In another example, in the memory die module 100 shown in FIG. 1B , there are multiple memory dies 102 , the top die of the memory die module 100 is the memory die 102 , and the bottom die of the memory die module 100 is the logic processing die 101 .

[0100] That is, the stacking position of the logic processing die 101 can be adjusted according to actual needs, for example, it can also be stacked between the memory die 102 .

[0101] The memory die 102 may be a chip die of any type of memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), non-volatile random access memory (NVRAM), flash memory, or electrically erasable programmable read-only memory (EEPROM). For example, the memory die 102 may be a customized chip die or a standardized chip die, which is not limited in the embodiments of the present application.

[0102] The logic processing die 101 may be a chip die responsible for logic processing functions. Exemplarily, the logic processing die 101 may include a memory control unit, a processor unit, or a memory control unit and a processor unit. The processor unit may be, for example, a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), a knowledge processing unit (KPU), a tensor processing unit (TPU), an intelligent processor (IPU), a reconfigurable dataflow unit (Reconfigurable Dataflow Unit), a neural network processor (NPU) or other types of processors (Any type Processing Unit, xPU), which is responsible for executing instructions and performing various calculations and data processing tasks, including simple arithmetic operations and complex logical operations, thereby realizing functions such as calculation, control, and decision-making. The memory control unit is responsible for managing and coordinating part of the memory access, such as converting the memory operation requested by the processor into the operation of the memory, and ensuring the correct transmission and storage of data to achieve efficient memory access and data transmission.

[0103] It should be noted that in the embodiment of the present application, a chip (Chip) is a small silicon wafer (or other semiconductor materials) that integrates multiple electronic components (such as transistors, capacitors, resistors, etc.) and circuit connections. These components and connections form a complex circuit that can perform various functions, thereby achieving tasks such as computing, storage, control, and signal processing. That is, the chip is a highly integrated electronic device. A die refers to an unpackaged, separate chip. During the chip manufacturing process, many identical chips are usually manufactured on a silicon wafer (or other materials). Each chip is called a die, which contains a specific circuit design and function. The die will be separated after manufacturing and can be further packaged into finished chips or used for other applications.

[0104] Furthermore, the manner in which the memory die 102 and the logic processing die 101 are interconnected (referred to as interconnection) can be configured according to actual needs, and the embodiments of the present application do not limit this.

[0105] In one embodiment, the non-top die of the memory die module 100 (which can be the memory die 102 or the logic processing die 101) is equipped with TSVs, which form vertical vias through the die to enable interconnection and communication between chips at different levels. Each TSV is a tiny metal via that passes through the thickness of the die and connects circuits at different levels, thereby achieving high-speed signal transmission, low-latency interconnection, and higher-performance, more compact packaging solutions.

[0106] As an example, the dies of the memory die module 100 (which may be the memory die 102 or the logic processing die 101) are connected by hybrid bonding. Specifically, surface chemical reactions can be used to create a very strong atomic-level connection between the two dies, so that the chip dies can be precisely aligned and connected at the micron scale on the wafer. Hybrid bonding is generally capable of transmitting electrical signals and data without the use of solder or conductive materials, so signal transmission losses can be reduced in some applications. Because the connection is very close, high-density chip stacking can be achieved through hybrid bonding, thereby achieving more functions in a smaller package size.

[0107] As another example, the dies of the memory die module 100 (which may be the memory die 102 or the logic processing die 101) are connected via microbumps. Specifically, a Ubump is a tiny raised structure, usually made of metal material, which forms interconnections and communication between the dies. Moreover, this structure is usually manufactured through a microelectronics process, and its size, position, and arrangement can be precisely controlled to achieve high-density connections.

[0108] According to the chip package provided in the embodiments of the present application, the die module is a packaging component based on the chiplet concept. By encapsulating multiple die modules on one side of a substrate, a 2.5D / 3D packaging solution is provided. The memory die module can achieve unlimited and customized stacking of memory die and logic processing die, thereby expanding storage bandwidth and improving computing power performance. Moreover, compared with the CoWoS solution, the stacking method used by the memory die module can achieve shorter interconnection distances and higher interconnection density, greatly improving interconnection efficiency and chip performance.

[0109] For example, the chip package provided in the embodiments of the present application can be used in high-performance computing chips, sensor chips, micro-electro-mechanical systems (MEMS), optical communication chips, etc. It should be noted that the above application scenarios or application examples provided in the embodiments of the present application are for ease of understanding, and the embodiments of the present application do not specifically limit the application of the chip package.

[0110] The following specific embodiments are used to describe in detail the technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems. The several specific embodiments listed can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0111] Part 1

[0112] The following describes different interconnection methods between bare die modules 10 through Examples 1 and 2. It should be noted that these interconnection methods can be applied between any type of bare die modules, and a single interconnection method can be used alone in a chip package, or multiple interconnection methods can be used simultaneously in a chip package, and the embodiments of the present application are not limited to this.

[0113] Example 1

[0114] In one interconnection mode, the die modules 10 may be connected via the substrate 20. Figures 2A, 2B, and 2C illustrate substrate-based interconnection modes between the die modules 10 and between the die modules 10 and the substrate 20.

[0115] In one example, as shown in FIG2A , the die module 10 is connected to the substrate 20 via C4 bumps 104 , and the die modules 10 are interconnected via substrate circuitry 103 within the substrate 20 . In this interconnection approach, the substrate circuitry 103 is directly embedded within the substrate 20 , meaning multiple layers of substrate circuitry 103 can be added to interconnect different components, including communication and power supply. This approach offers a simple structure and low cost.

[0116] The C4 bumps 104 are provided in the connection area between the substrate 20 and the die module 10, thereby achieving reliable interconnection between the substrate 20 and the die module 10. The C4 bumps can be arranged at a smaller pitch, thereby achieving high-density interconnection between the die modules 10 and between the substrate 20 and the die module 10.

[0117] In another example, the die modules 10 are interconnected within the substrate 20. Specifically, a bridge die 201 is provided in the substrate 20, and an RDL interposer 110 is provided above the bridge die 201 (on the side facing the die module 10). The RDL interposer 110 includes an RDL medium 106 and an RDL wiring layer 107, thereby interconnecting the die modules 10 within the substrate 20.

[0118] In this example, there are two implementations: One implementation, as shown in FIG2B , is where the bridge die 201 is configured as a silicon dielectric 205. Each die module 10 can be interconnected through vias 108 in the substrate 20 to the RDL interposer 110 on the bridge die 201, thereby achieving interconnection between the die modules 10. All other signals (including signals on the bridge die 201 or other signals on the die modules 10) can be connected to the solder balls 109 on the bottom of the substrate 20 through the substrate circuit 103 and the vias 108 in the substrate 20.

[0119] Another implementation is shown in FIG2C , where the bridge die 201 is configured to include a silicon dielectric 205 and TSVs 204 in the silicon dielectric 205. The upper surface of the RDL interposer 110 (the side facing the die module 10) is connected to the C4 bumps 104 via pads. In other words, one end of the C4 bumps 104 is connected to the die module 10, and the other end is connected to the upper surface of the RDL interposer 110, thereby achieving interconnection between the die modules 10. At the same time, the side of the bridge die 201 facing away from the die module 10 can be connected to the substrate circuit 103 via the TSVs 204.

[0120] Among them, the interconnection method based on bridge die can achieve high-density interconnection between die modules, provide higher performance, functional integration, flexibility and energy efficiency, and make complex 3D packaging systems more feasible and efficient.

[0121] Example 2

[0122] In this embodiment, the die modules 10 can be connected via an interposer, which is arranged between the substrate 20 and the die modules 10. The interposer can be used to interconnect the die modules 10 on the substrate 20, and can also be used to interconnect the substrate 20 and the die modules 10.

[0123] The interposer can include a redistribution layer (RDL), a bridge die, or a silicon interposer. It should be noted that each interposer corresponds to a specific interconnection method. Therefore, different interposers will result in different interconnection methods.

[0124] 3A , the interposer may be an RDL interposer 110 , that is, the die modules 10 may be connected via the RDL interposer 110 . Specifically, the RDL interposer 110 includes an RDL medium 106 and an RDL wiring layer 107 in the RDL medium 106 .

[0125] The RDL medium 106 is usually made of organic materials. The common material of the RDL 107 is electroplated copper (Plated Cu) supplemented with a base layer of titanium and copper sputtering. The surface of the copper layer is then covered with a corresponding protective layer ink as needed.

[0126] Exemplarily, RDL107 is used to connect the micro bumps 105 on the bare chip module 10 and the C4 bumps 104 on the other side of the RDL interposer 110, thereby realizing interconnection between the bare chip module 10 and the substrate 20 and between the bare chip modules 10, and realizing high-density and high-speed signal transmission.

[0127] The RDL interposer interconnection method is suitable for complex interconnections between bare die modules and substrates, as well as between bare die modules. Specifically, compared to substrate interconnections, which are limited by the number of substrate layers, the use of RDL interposers allows for more levels of interconnection and is more flexible in its placement, enabling more complex and higher-density interconnections. Furthermore, interconnections using RDL interposers typically have shorter and denser interconnect paths, potentially resulting in better performance and lower signal latency.

[0128] In one interconnection manner, as shown in FIG. 3B and FIG. 3C , the interposer may be a bridge die interposer 210 , which includes a filling medium 202 and a bridge die 201 surrounded and filled by the filling medium 202 .

[0129] For example, the filling medium 202 may be made of a molding material, an underfill material, or other materials used for protective filling, including organic materials or inorganic materials, as long as the filling medium 202 can protect the bridge die 201 .

[0130] In one example, as shown in FIG3B , the bridge die 201 may include a silicon dielectric 205 and TSVs 204 disposed in the silicon dielectric 205 . For example, one surface (such as the upper surface) of the bridge die 201 is disposed between two die modules 10 , and the other surface (such as the lower surface) is connected to the C4 bumps 104 through the TSVs 204 in the silicon dielectric 205 , and then connected to the substrate 20 through the C4 bumps 104 .

[0131] Exemplarily, as shown in FIG. 3B , the bridge die interposer 210 may further include an RDL interposer 110 disposed on the bridge die 201 . The RDL interposer 110 includes an RDL medium 106 and an RDL wiring layer 107 for realizing interconnection between the die modules 10 .

[0132] As an optional example, the bridging die 201 is provided with a C4 bump 104 on the side facing the substrate 20, and the bridging die 201 is connected to the C4 bump 104 through the TSV 204, and then interconnected with the substrate 20 through the C4 bump 104; the bare die module 10 is provided with a micro bump 105 on the side facing the bridging die interposer 210, and the bare die module 10 is interconnected on the RDL interposer 110 through the micro bump 105.

[0133] In another example, as shown in FIG3C , the bridge die 201 is configured as a silicon dielectric 205. It should be noted that an RDL interposer 110 can be provided on one surface (e.g., the upper surface) of the bridge die 201 as needed, and disposed between two die modules 10, so that the interconnection between the die modules 10 is achieved through the RDL interposer 110 on the upper surface of the bridge die 201, while the other surface (e.g., the lower surface) of the bridge die 201 may not be connected to the substrate 20.

[0134] Furthermore, as an example, as shown in Figures 3B and 3C, the bridging die interposer 202 may further include a Through Interposer Via (TIV) 203, which is disposed in the filling medium 202 and connected between the micro bumps 105 and the C4 bumps 104 to achieve interconnection between the die modules 10 and the substrate 20. Thus, interconnection between the die modules 10 can be achieved through the bridging die interposer 202, and other signals can be connected to the substrate 20 through the TIV 203.

[0135] For example, in an implementation in which the interposer is a bridge die interposer 210, i.e., in an implementation as shown in FIG3B and 3C , since the sparseness of the arrangement of the micro bumps 105 may be different from the sparseness of the arrangement of the TIV 203, in order to facilitate interconnection, an interconnection interposer may be provided between the bridge die interposer 210 and the micro bumps 105, such as an RDL interposer 110 (not shown in the figure).

[0136] The interconnection method based on the bridge die interposer can achieve high-density interconnection between die modules and between die modules and substrates, providing higher performance, functional integration, flexibility and energy efficiency, making complex 3D packaging systems more feasible and efficient.

[0137] In one implementation, as shown in FIG. 3D , the interposer may be a silicon interposer 310 , which includes a silicon dielectric 205 and TSVs 204 disposed in the silicon dielectric 205 .

[0138] Exemplarily, a micro-bump 105 is provided on the side of the bare chip module 10 facing the substrate, and an RDL interposer 110 is provided between the micro-bump 105 and the silicon dielectric 205. The RDL interposer 110 includes an RDL dielectric 106 and an RDL wiring layer 107. The micro-bump 105 is interconnected with the TSV 204 through the RDL 110; one end of the TSV 204 is connected to the C4 bump 104 on the substrate 20, and the other end is interconnected with the RDL 110. Thus, different bare chip modules 10 can be interconnected on the RDL interposer 110, and the remaining signals pass through the RDL interposer 110 and then through the silicon dielectric 205 and TSV 204, connected to the C4 bump 104, and finally connected to the substrate 20.

[0139] Here, the side of the silicon interposer 310 facing the substrate 20 may also have an RDL interposer 110. The RDL interposer 110 includes an RDL dielectric 106 and an RDL wiring layer 107. One end of the RDL interposer 110 is connected to the TSV 204, and the other end is connected to the C4 bump 104, and is connected to the substrate 20 through the C4 bump 104, as shown in Figure 3E.

[0140] The silicon interposer 205 can manufacture complex circuit structures in a very small size and achieve high-density interconnection. Moreover, due to the good conductivity of silicon, the signal transmission speed is fast, thereby reducing the delay of signal transmission. Furthermore, silicon has stable physical and electrical properties, which can enable the silicon interposer to maintain stable interconnection performance under different working environments.

[0141] Part 2

[0142] The following describes the interconnection topology of multiple bare die modules 10 on a substrate 20 through Examples 3 to 5. It should be noted that a single interconnection topology can be used in a chip package, or multiple interconnection topologies can be used simultaneously in a chip package, and this is not limited in the present embodiment.

[0143] As shown in FIG4 , multiple bare chip modules 10 are arranged in rows and columns on one side of a substrate 20, i.e., in an N x M topology, where N is the number of rows and M is the number of columns, such as 2x2, 3x3, 4x4, ... nxn, etc.; or 1x2, 2x4, 3x6, 4x8, ... nx2n, etc.; or 1x3, 1x4, 2x5, 3x4, 3x5, ... nxm, etc., where n, N, and M are all positive integers. In the embodiment of the present application, the first direction is the row direction X or the column direction Y, and the second direction Z forms an angle with the first direction in the plane of the substrate 20, such as a 135-degree angle.

[0144] Among the plurality of bare chip modules, there are adjacent bare chip modules that are connected to each other. For example, the bare chip modules that need to establish an interconnection relationship are configured as adjacent positions.

[0145] Example 3

[0146] This embodiment uses memory die modules 100 as an example. Multiple memory die modules 100 are arranged in rows and columns on one side of a substrate 20, for example, in arrays of 2x2, 3x3, 4x4, ... nxn, etc.; or 1x2, 2x4, 3x6, 4x8, ... nx2n, etc.; or 1x3, 1x4, 2x5, 3x4, 3x5, ... nxm, etc. Among the multiple memory die modules, adjacent memory die modules are interconnected. For example, memory die modules that need to be interconnected are arranged in adjacent positions.

[0147] In one interconnection topology, as shown in FIG5A , the memory die modules connected to each other are memory die modules 100 adjacent to each other in a first direction, where the first direction is a row direction X or a column direction Y.

[0148] In one interconnect topology, as shown in FIG5B , the interconnected memory die modules also include adjacent memory die modules 100 in a second direction. The second direction Z forms an angle with the first direction in the plane of the substrate 20, thereby forming diagonal interconnections. This allows for increased interconnections in multiple directions, expanding memory bandwidth and facilitating the implementation of high-performance, diversified chip functionality.

[0149] The technical solution of the embodiment of the present application can expand the interconnection relationship of the memory die module 100 according to actual needs, thereby achieving the expansion of storage bandwidth and the improvement of computing power performance.

[0150] Example 4

[0151] In this embodiment, the plurality of bare die modules 10 include an input and output (IO) bare die 200 and a memory bare die module 100 , as shown in FIG6 .

[0152] Exemplarily, the IO die 200 can be used to handle communications with the memory die module 100 and with the outside of the chip package system, including data input and output, communication protocol processing, etc., and can include interfaces and functions required for interaction with networks, storage, external devices, etc. For example, in the chip package of a computing accelerator card, the memory die module 100 is responsible for computing and storage, while the IO die 200 is responsible for processing input and output operations and communicating with other devices.

[0153] Among them, each IO bare chip 200 and each memory bare chip module 100 is arranged in an array distributed in rows and columns on one side of the substrate 20, and the IO bare chip 200 is interconnected with at least some of the memory bare chip modules 100, that is, the IO bare chip 200 forms an interconnected relationship with at least some of the memory bare chip modules 100.

[0154] In one embodiment, in the array formed by each memory die module 100 and each IO die 200, the IO die 200 is located at the edge of the array in a first direction, where the first direction is the row direction X or the column direction Y. That is, multiple memory die modules 100 are arranged in rows and columns on one side of the substrate 20 to form a memory die module array, for example, 2x2, 3x3, 4x4...nxn, etc.; or 1x2, 2x4, 3x6, 4x8...nx2n, etc.; or 1x3, 1x4, 2x5, 3x4, 3x5...nxm, etc., while the IO die 200 is arranged at the periphery of the memory die module array. As shown in Figures 7A, 7B, 7C, and 7D, the memory die module array is exemplified by arrays of 1x1, 1x2, 2x2, and 3x3, respectively.

[0155] As shown in FIG7A , for a 1x1 memory die module array, each memory die module 100 is interconnected with four IO dies 200. As shown in FIG7B , for a 1x2 memory die module array, each memory die module 100 is interconnected with three IO dies 200. As shown in FIG7C , for a 2x2 memory die module array, each memory die module 100 is interconnected with two IO dies 200. As shown in FIG7D , for a 3x3 memory die module array, each corner memory die module 100 is interconnected with two IO dies 200. Except for the corner memory die modules 100 in an edge row or column, the remaining memory die modules 100 are interconnected with one IO die 200. Internal memory die modules 100 (except for edge rows and columns) do not need to be interconnected with IO dies 200. The number of IO dies 200 is not limited and can be, for example, three or five.

[0156] In one embodiment, multiple memory die modules 100 are arranged in rows and columns on one side of a substrate 20 to form a memory die module array, such as 2x2, 3x3, 4x4, ... nxn, etc.; or 1x2, 2x4, 3x6, 4x8, ... nx2n, etc.; or 1x3, 1x4, 2x5, 3x4, 3x5, ... nxm, etc., and IO dies 200 are arranged on the periphery of the memory die module array. As shown in Figures 7A, 7B, 7C, and 7D, the memory die module arrays are exemplified by 1x1, 1x2, 2x2, and 3x3 arrays, respectively.

[0157] It should be noted that the interconnection relationship of the memory die module array can adopt any interconnection topology in Example 3. For example, the interconnection relationship of the diagonally oriented memory die modules can be added to the array form shown in Figures 7C and 7D, as shown in Figures 8A and 8B.

[0158] In one embodiment, at least one IO die 200 is distributed around each memory die module 100, as shown in FIG9 , wherein the number of IO die 200 can be adjusted according to bandwidth requirements, thereby achieving expansion of storage bandwidth and improvement of data transmission performance.

[0159] In one embodiment, as shown in FIG10 , four IO dies 200 are distributed around each memory die module 100 , wherein adjacent IO dies 200 in a first direction are interconnected to establish an interconnection relationship to maximize interconnection bandwidth.

[0160] The technical solution of the embodiment of the present application can expand the interconnection relationship between the memory die module 100 and the IO die 200 according to actual needs, which not only shortens the transmission distance between the memory die module 100 and the IO die 200, but also increases the interconnection density, thereby achieving the expansion of storage bandwidth and the improvement of data transmission performance.

[0161] Example 5

[0162] In this embodiment, the multiple bare chip modules 10 include an IO bare chip module 300 and a memory bare chip module 100. The IO bare chip module 300 is interconnected with at least part of the memory bare chip module 100. The IO bare chip module 300 includes stacked IO bare chips 200 and memory bare chips 102, as shown in Figure 11.

[0163] The number, stacking method, and arrangement position of the memory die 102 and the IO die 200 are not limited in the embodiments of the present application. For example, in the IO die module 300 shown in FIG11 , there are multiple memory dies 102, the top die of the IO die module 300 is the memory die 102, and the bottom die of the IO die module 300 is the IO die 200. For another example, in the IO die module 300, there are multiple memory dies 102, the top die of the IO die module 300 is the IO die 200, and the bottom die of the IO die module 300 is the memory die 102. Therefore, the stacking position of the IO die 200 can be adjusted according to actual needs, for example, it can also be stacked between the memory dies 102.

[0164] In one embodiment, the non-top die of the IO die module 300 (which can be either the memory die 102 or the IO die 200) is equipped with TSVs, which form vertical vias through the die to enable interconnection and communication between chips at different levels. Each TSV is a tiny metal via that passes through the thickness of the die and connects circuits at different levels, thereby achieving high-speed signal transmission, low-latency interconnection, and a higher-performance, more compact packaging solution.

[0165] As an example, the dies of the IO die module 300 (which can be the memory die 102 or the IO die 200) are connected by hybrid bonding. Specifically, surface chemical reactions can be used to create a very strong atomic-level connection between the two dies, so that the chip dies can be precisely aligned and connected at the micron scale on the wafer. Hybrid bonding is generally capable of transmitting electrical signals and data without the use of solder or conductive materials, so in some applications, signal transmission losses can be reduced. Because the connection is very close, high-density chip stacking can be achieved through hybrid bonding, thereby achieving more functions in a smaller package size.

[0166] As another example, the dies of the IO die module 300 (which can be the memory die 102 or the IO die 200) are connected through microbumps, thereby forming interconnection and communication between the dies, and their size, position and arrangement can be precisely controlled to achieve high-density connection.

[0167] Exemplarily, the IO die 200 can be used to handle communications with the IO die module 300 and with the outside of the IO die module 300 (such as other die modules), including data input and output, processing of communication protocols, etc., and may include interfaces and functions required for interaction with networks, storage, other die modules, etc.

[0168] The IO die modules 300 and the memory die modules 100 are arranged in rows and columns on one side of the substrate 20. Furthermore, the IO die modules 300 are interconnected with at least some of the memory die modules 100. That is, the IO die modules 300 are interconnected with at least some of the memory die modules 100. Furthermore, adjacent IO die modules 300 are interconnected.

[0169] In one embodiment, in the array formed by each memory die module 100 and each IO die module 300, the IO die module 300 is located at the edge of the array in a first direction, where the first direction is the row direction X or the column direction Y. That is, multiple memory die modules 100 are arranged in rows and columns on one side of the substrate 20 to form a memory die module array, for example, 2x2, 3x3, 4x4...nxn, etc.; or 1x2, 2x4, 3x6, 4x8...nx2n, etc.; or 1x3, 1x4, 2x5, 3x4, 3x5...nxm, etc., while the IO die modules 300 are arranged at the periphery of the memory die module array. As shown in Figures 12A, 12B, 12C, and 12D, the memory die module array is exemplified by arrays of 1x1, 1x2, 2x2, and 3x3, respectively.

[0170] As shown in FIG12A , for a 1x1 memory die module array, each memory die module 100 is interconnected with four IO die modules 300; as shown in FIG12B , for a 1x2 memory die module array, each memory die module 100 is interconnected with three IO die modules 300; as shown in FIG12C , for a 2x2 memory die module array, each memory die module 100 is interconnected with two IO die modules 300; as shown in FIG12D , for a 3x3 memory die module array, each corner memory die module 100 is interconnected with two IO die modules 300, and the remaining memory die modules 100 on the edge rows or edge columns, except for the corners, are interconnected with one IO die module 300, and the internal memory die modules 100 (except for the edge rows and edge columns) do not need to be interconnected with the IO die modules 300.

[0171] In one embodiment, multiple memory die modules 100 are arranged in rows and columns on one side of a substrate 20 to form a memory die module array, such as 2x2, 3x3, 4x4, ... nxn, etc.; or 1x2, 2x4, 3x6, 4x8, ... nx2n, etc.; or 1x3, 1x4, 2x5, 3x4, 3x5, ... nxm, etc., while IO die modules 300 are arranged on the periphery of the memory die module array. As shown in Figures 12A, 12B, 12C, and 12D, the memory die module arrays are exemplified by 1x1, 1x2, 2x2, and 3x3 arrays, respectively.

[0172] It should be noted that the interconnection relationship of the memory die module array can adopt any interconnection topology in Example 3. For example, the interconnection relationship of the diagonal memory die modules can be added to the array form shown in Figures 12C and 12D, as shown in Figures 13A and 13B.

[0173] In one embodiment, at least one IO die module 300 is distributed around each memory die module 100, as shown in FIG14 , wherein the number of IO die modules 300 can be adjusted according to bandwidth requirements, thereby achieving expansion of storage bandwidth and improvement of data transmission performance.

[0174] In one embodiment, as shown in FIG15 , four IO die modules 300 are distributed around each memory die module 100 , wherein adjacent IO die modules 300 in a first direction are interconnected to establish an interconnection relationship to maximize interconnection bandwidth.

[0175] The technical solution of the embodiment of the present application can expand the interconnection relationship between the memory bare chip module 100 and the IO bare chip module 300 according to actual needs, which not only shortens the transmission distance between the memory bare chip module 100 and the IO bare chip module 300, but also increases the interconnection density, thereby achieving the expansion of storage bandwidth and the improvement of data transmission performance.

[0176] Part 3

[0177] The following describes a working assembly including one or more chip packages through the sixth and seventh embodiments.

[0178] Example 6

[0179] As shown in FIG16 , an embodiment of the present application provides a working assembly, including a printed circuit board (PCB) 30 and a chip package 40 , wherein at least one chip package 40 is arranged on one side of the PCB 30 .

[0180] The chip package 40 may be any of the chip packages described in the aforementioned application scenarios or embodiments, i.e., the chip package 40 includes a substrate 20 and multiple bare die modules 10. It should be noted that the working assembly may include one or more chip packages, and the embodiments of the present application do not specifically limit the type, quantity, or interconnection topology of the chip package 40.

[0181] Exemplarily, the chip package 40 is connected to the PCB board 30 via the solder balls 109 , thereby interconnecting the bare die modules 10 inside different chip packages 40 on the PCB board 30 .

[0182] Among them, there can be multiple chip packages 40, and there are interconnected chip packages among the multiple chip packages 40. For example, an interconnection relationship can be established between adjacent chip packages through the PCB board 30, so that PCB board-level interconnection between the chip packages 40 can be achieved.

[0183] In one embodiment, the chip packages 40 are connected to each other on the PCB board 30 via connecting wires 50. For example, the connecting wires 50 can be any type of interconnection intellectual property (IP) component or module, such as Peripheral Component Interconnect Express (PCIE), Serializer / Deserializer (Serdes), Universal Chiplet Interconnect Express (UCIe), Compute Express Link (CXL), Remote Direct Memory Access (RDMA), Ethernet, etc.

[0184] According to the working components provided in the embodiments of the present application, the disadvantages of small storage bandwidth and low computing power of traditional packaging solutions can be avoided, and advanced packaging technology can be provided to increase storage bandwidth, thereby improving chip computing power.

[0185] Example 7

[0186] 17 , an embodiment of the present application provides a working assembly, including a PCB board 30 , a chip package 60 , and a memory device 70 . Exemplarily, the memory device 70 and the chip package 60 are arranged on the same side of the PCB board 30 .

[0187] The chip package 60 includes a substrate 20, multiple die modules 100, and multiple IO dies 200. The chip package 60 is interconnected with at least one memory device 70 via a PCB 30. The embodiment of the present application does not specifically limit the number of chip packages 60 and the interconnection topology.

[0188] The chip package 60 can be the chip package of any embodiment in the fourth embodiment, that is, the chip package 60 includes a substrate 20, an IO die 200 and a memory die module 100, and the chip package 60 is interconnected with at least one memory device 70 through a PCB board 30.

[0189] Exemplarily, the substrate 20 in the chip package 60 is connected to the PCB 30 via solder balls 109 , thereby connecting signals on the IO die 200 and the memory die module 100 to the PCB 30 .

[0190] There may be multiple chip packages 60, and some of the multiple chip packages 60 may be interconnected. For example, adjacent chip packages may be interconnected on the PCB 30. In one embodiment, the chip packages 60 are interconnected on the PCB via connecting wires 50, thereby achieving PCB-level interconnection between the chip packages 60.

[0191] The working components provided in the embodiments of the present application can further achieve the expansion of storage capacity and interconnection bandwidth.

[0192] Other components of the chip package in the above embodiment may adopt various technical solutions known to those skilled in the art now and in the future, and will not be described in detail here.

[0193] Part 4

[0194] The present application also provides a computing device including any one of the aforementioned working components and a power supply module, wherein the power supply module is configured to provide power to the working component. The number of working components may be one or more, and this embodiment of the present application is not limited thereto. For example, at least some of the multiple working components may be interconnected, which may be electrical or physical connections, and this embodiment of the present application is not limited thereto.

[0195] For example, the computing device provided in the embodiments of the present application can be used in devices and systems that require a large amount of computing power, such as supercomputers, servers in data centers, high-performance workstations, scientific research equipment, etc., and can be applied in artificial intelligence, deep learning, big data analysis and other fields.

[0196] For example, the computing device provided in the embodiments of the present application can be used in various devices that need to monitor and measure physical or chemical changes, such as smart phones, automobiles, industrial automation equipment, medical equipment, and other fields that require high-performance sensor chips.

[0197] For example, the computing device provided in the embodiments of the present application can be used in micro-electromechanical systems, such as gyroscopes and accelerometers in smartphones, airbag triggering systems in cars, micro-lens arrays in projectors, etc.

[0198] For example, the computing device provided in the embodiments of the present application can be used in fiber-optic communication systems, such as fiber-optic network equipment, optical interconnection in data centers, long-distance fiber-optic transmission systems, and other fields requiring high-speed data transmission.

[0199] When the computing device is used in different systems or fields, other components of the computing device may be different. Other components of the computing device in the above embodiment can adopt various technical solutions known to ordinary technicians in this field now and in the future, and will not be described in detail here.

[0200] In the technical solution of the embodiment of the present application, the chip package can provide 3D and 2.5D packaging structures, and combined with multi-level interconnection relationships, it can realize wireless expansion and high-density interconnection topology of the bare chip module as a packaging unit.

[0201] The first-level interconnect can be understood as the infinite stacking of memory dies and logic processing dies in the memory die module. It can be understood that the vertical stacking of memory dies and logic processing dies forms a 3D packaging structure, which can achieve shorter interconnect distances and higher interconnect density, greatly improving interconnect efficiency and chip performance, and achieving expanded storage bandwidth and improved computing performance. For details, please refer to Figures 1A and 1B of the embodiment of this application and the related introduction of memory die module 100.

[0202] The second-level interconnection can be understood as the interconnection between die modules. It is a 2.5D packaging structure between traditional 2D packaging and full 3D packaging. For example, the interconnection between memory die modules and IO die shortens the transmission distance and increases the interconnection density. For details, please refer to the relevant descriptions of Examples 1 to 5 of this application.

[0203] The third level of interconnection can be understood as PCB-level interconnection, such as connections between IO dies, between IO dies and memory devices, and between chip packages. This further expands memory bandwidth and capacity to achieve even greater performance improvements. For details, see the relevant descriptions of Examples 6 and 7 of this application.

[0204] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on this application.

[0205] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or to implicitly indicate the quantity of the technical features indicated. Thus, features defined as "first" or "second" may explicitly or implicitly include one or more of the features.

[0206] In this application, unless otherwise expressly specified or limited, terms such as "installed," "connected," "connect," and "fixed" should be understood in a broad sense. For example, they may refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection, or communication; direct connection or indirect connection through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0207] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0208] The disclosure above provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described above. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed.

[0209] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily conceive of various modifications or substitutions within the technical scope disclosed in this application, and such modifications or substitutions should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A chip package, characterized in that: include: substrate; A plurality of bare chip modules are arranged on one side of the substrate, and at least some of the plurality of bare chip modules are interconnected; the plurality of bare chip modules include at least one memory bare chip module, and the memory bare chip module includes stacked memory bare chips and logic processing bare chips.

2. The chip package according to claim 1, characterized in that: The logic processing die includes a memory control unit and / or a processor unit.

3. The chip package according to claim 1, wherein: The number of the memory dies is multiple.

4. The chip package according to claim 1, wherein: The number of the logic processing die is one or more.

5. The chip package according to claim 1, wherein: The top die of the memory die module is the memory die, and the bottom die of the memory die module is the logic processing die; or, the top die of the memory die module is the logic processing die, and the bottom die of the memory die module is the memory die.

6. The chip package according to claim 1, wherein: The non-top die of the memory die module is provided with through silicon vias (TSV).

7. The chip package according to claim 1, wherein: The bare chips of the memory bare chip module are connected by hybrid bonding or by micro bumps.

8. The chip package according to claim 1, wherein: The connection method between the bare chip modules includes: connecting through the substrate.

9. The chip package according to claim 8, characterized in that: A substrate circuit is embedded in the substrate, and the bare chip modules are connected to each other via the substrate circuit.

10. The chip package according to claim 8, wherein: The substrate is provided with a bridging die and a redistribution RDL intermediary layer, the RDL intermediary layer is arranged on a side of the bridging die facing the die module, and the connection between the die modules includes: connecting to each other through the RDL intermediary layer.

11. The chip package according to claim 10, characterized in that: The bridge die is configured as a silicon dielectric.

12. The chip package according to claim 10, characterized in that: The bridge die includes a silicon dielectric and a TSV in the silicon dielectric.

13. The chip package according to claim 1, wherein: The connection between the bare chip modules includes: connecting through an intermediate layer, and the intermediate layer is arranged between the substrate and the bare chip module.

14. The chip package according to claim 13, characterized in that: The interposer includes an RDL interposer including an RDL medium and an RDL wiring layer in the RDL medium.

15. The chip package according to claim 13, characterized in that: The interposer includes a bridge die interposer including a filling medium and a bridge die surrounded by the filling medium.

16. The chip package according to claim 15, characterized in that: The bridge die interposer further includes an RDL interposer, and the RDL interposer is arranged on a side of the bridge die facing the die module.

17. The chip package according to claim 15, characterized in that: The bridge die is configured as a silicon dielectric; or the bridge die includes a silicon dielectric and a TSV in the silicon dielectric.

18. The chip package according to claim 15, characterized in that: The bridge die interposer further includes a via TIV located in the filling medium for connecting the die module and the substrate.

19. The chip package according to claim 15, characterized in that: The interposer includes a silicon interposer, and the silicon interposer includes a silicon medium and a TSV disposed in the silicon medium.

20. The chip package according to claim 13, wherein: The interposer includes a silicon interposer and an RDL interposer located between the silicon interposer and the bare chip module. The silicon interposer includes a silicon medium and a TSV disposed in the silicon medium.

21. The chip package according to claim 20, characterized in that: The interposer also includes an RDL interposer located between the silicon interposer and the substrate.

22. The chip package according to claim 1, wherein: A plurality of memory die modules are distributed in rows and columns on one side of the substrate.

23. The chip package according to claim 22, characterized in that: There are adjacent memory bare chip modules connected to each other among the multiple memory bare chip modules, wherein the adjacent memory bare chip modules are memory bare chip modules adjacent in a first direction, and / or the adjacent memory bare chip modules are memory bare chip modules adjacent in a second direction, the first direction is a row direction or a column direction, and the second direction forms an angle with the first direction in the plane where the substrate is located.

24. The chip package according to claim 1, wherein: The plurality of bare chip modules also include an input / output IO bare chip, and the IO bare chip is interconnected with at least part of the memory bare chip modules.

25. The chip package according to claim 24, characterized in that: The memory die modules and the IO die are arranged in rows and columns.

26. The chip package according to claim 25, characterized in that: The IO die is located at an edge of the array in a first direction, and the first direction is a row direction or a column direction.

27. The chip package according to claim 25, characterized in that: There are adjacent memory bare chip modules connected to each other among the multiple memory bare chip modules, wherein the adjacent memory bare chip modules are memory bare chip modules adjacent in a first direction, and / or the adjacent memory bare chip modules are memory bare chip modules adjacent in a second direction, the first direction is a row direction or a column direction, and the second direction forms an angle with the first direction in the plane where the substrate is located.

28. The chip package according to claim 25, characterized in that: At least one IO die is distributed around each memory die module.

29. The chip package according to claim 25, characterized in that: Four IO dies are distributed around each memory die module, and adjacent IO dies in a first direction are connected to each other, where the first direction is a row direction or a column direction.

30. The chip package according to claim 1, wherein: The multiple bare chip modules also include an IO bare chip module, the IO bare chip module includes stacked IO bare chips and memory bare chips, and the IO bare chip module is interconnected with at least part of the memory bare chip modules.

31. The chip package according to claim 30, characterized in that: The top die of the IO die module is the memory die, and the bottom die of the IO die module is the IO die; or, the top die of the IO die module is the IO die, and the bottom die of the IO die module is the memory die.

32. The chip package according to claim 30, characterized in that: The memory bare chip modules and the IO bare chip modules are arranged in an array in rows and columns on one side of the substrate.

33. The chip package according to claim 32, characterized in that: The IO bare chip module is located at an edge of the array in a first direction, and the first direction is a row direction or a column direction.

34. The chip package according to claim 32, characterized in that: There are adjacent memory bare chip modules connected to each other among the multiple memory bare chip modules, wherein the adjacent memory bare chip modules are memory bare chip modules adjacent in a first direction, and / or the adjacent memory bare chip modules are memory bare chip modules adjacent in a second direction, the first direction is a row direction or a column direction, and the second direction forms an angle with the first direction in the plane where the substrate is located.

35. The chip package according to claim 32, characterized in that: At least one IO bare chip module is distributed around each of the memory bare chip modules.

36. The chip package according to claim 32, characterized in that: Four IO bare chip modules are distributed around each of the memory bare chip modules, and the adjacent IO bare chip modules in a first direction are connected to each other, and the first direction is a row direction or a column direction.

37. The chip package according to claim 30, characterized in that: Adjacent IO bare chip modules are connected to each other.

38. A working component, characterized in that: include: The chip package according to any one of claims 1 to 37; A PCB board, the chip package is arranged on one side of the PCB board.

39. The working assembly according to claim 38, characterized in that There are multiple chip packages.

40. The working assembly according to claim 39, characterized in that At least parts of the plurality of chip packages are connected to each other.

41. The working assembly according to claim 38, characterized in that A memory device is arranged on one side of the PCB board, and the bare chip module in the chip package is connected to the memory device through the PCB board.

42. The working assembly according to claim 41, characterized in that The number of the memory devices is multiple.

43. The working assembly according to claim 41, characterized in that The memory device and the chip package are arranged on the same side of the PCB board.

44. A computing device, characterized in that include: The working assembly according to any one of claims 38 to 43; Power supply module.

45. The computing device of claim 44, wherein: The number of the working components is multiple.

46. ​​The computing device of claim 44, wherein: At least some of the plurality of working components are connected to each other.

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