Signal processing method and apparatus, electronic device, and computer readable storage medium

Abstract

The present disclosure provides a signal processing method, a signal processing apparatus, an electronic device, and a computer readable storage medium. The signal processing method comprises: converting a target signal under a preset standard into symbol data, and caching the symbol data, wherein there is at least one preset standard; generating online a read address and a read enable corresponding to the symbol data; on the basis of the read address and the read enable, restoring the symbol data read from the cache into I-path and Q-path read data, and filtering the two paths of read data on the basis of channel types to obtain filtered data; optimizing the filtered data to obtain a target baseband signal; caching the target baseband signal; and reading the cache data on the basis of a set delay value, and then performing interface conversion and radio frequency (RF) processing.

Description

Signal processing method and device, electronic device and computer-readable storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to Chinese patent application No. 202311571186.1 filed on November 21, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to the field of core networks, and in particular to a signal processing method, a signal processing device, an electronic device, and a computer-readable storage medium. Background Art

[0004] With the development of mobile communication technology, NSA (non-standalone) networking using LTEA (Long-Term Evolution-Advanced) and NR (New Radio) has become a widely used 5G (fifth-generation mobile communication technology) networking method. Terminal devices using NSA networking mode must support both NR and LTEA when performing OFDM (Orthogonal Frequency Division Multiplexing) signal modulation.

[0005] For OFDM modulated signals, in order to eliminate the inter-symbol interference and inter-subcarrier interference existing in the OFDM modulation system, a cyclic prefix is ​​generally inserted into the signal after IFFT (Invert Fast Fourier Transformation) processing as a protection interval. At the same time, windowing or filtering methods are additionally required to suppress out-of-band spectrum leakage and smooth the inter-symbol phase discontinuity caused by the cyclic prefix.

[0006] Summary of the Invention

[0007] In a first aspect, the present disclosure provides a signal processing method, comprising: converting a target signal under a preset format into symbol data, and caching the symbol data; the preset format is at least one format; generating a read address and a read enable corresponding to the symbol data online in the cache; restoring the symbol data read out from the cache into two-way read data, I-way and Q-way, according to the read address and the read enable, performing corresponding filtering processing on the two-way read data according to the channel type of the I-way and Q-way read data to obtain filtered data; optimizing the filtered data to obtain a target baseband signal; caching the target baseband signal; and performing interface conversion and RF processing on the read cache data after reading the cached data according to a set delay value.

[0008] In a second aspect, the present disclosure provides a signal processing device, comprising: a first cache module, configured to convert a target signal under a preset format into symbol data and cache the symbol data; the preset format is at least one format; a generation module, configured to generate a read address and a read enable corresponding to the symbol data online in the cache; a filtering module, configured to restore the symbol data read out from the cache into two-way read data, I-way and Q-way, according to the read address and the read enable, and perform corresponding filtering processing on the two-way read data according to the channel type of the two-way read data to obtain filtered data; an optimization module, configured to optimize the filtered data to obtain a target baseband signal; a second cache module, configured to cache the target baseband signal; a processing module, configured to read the cached data according to a set delay value, and then perform interface conversion and RF processing on the read cached data.

[0009] In a third aspect, the present disclosure provides an electronic device comprising: at least one processor; and a memory storing at least one computer program, wherein when the at least one computer program is executed by the at least one processor, the at least one processor implements the signal processing method.

[0010] In a fourth aspect, the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program is executed by a processor so that the processor implements the signal processing method. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In the drawings accompanying this disclosure:

[0012] FIG1 is a block diagram of an OFDM modulation system in the related art provided by the present disclosure;

[0013] FIG2 is a flow chart of a signal processing method provided by the present disclosure;

[0014] FIG3 is a schematic diagram of a control flow of a read address and a read enable provided by the present disclosure;

[0015] FIG4 is a schematic diagram of a HBF filter including six HBF cascades provided by the present disclosure;

[0016] FIG5 is a schematic diagram of cascading 12 FIR units provided by the present disclosure;

[0017] FIG6 is a schematic diagram of timing points of a first cache module and a second cache module provided by the present disclosure;

[0018] FIG7 is a block diagram of a signal processing device provided by the present disclosure;

[0019] FIG8 is a schematic structural diagram of a signal processing device provided by the present disclosure;

[0020] FIG9 is a block diagram of the electronic device provided by the present disclosure;

[0021] FIG10 is a block diagram of the composition of a computer-readable storage medium provided by the present disclosure. DETAILED DESCRIPTION

[0022] To enable those skilled in the art to better understand the technical solutions of the present disclosure, the signal processing method, signal processing device, electronic device, and computer-readable storage medium provided by the present disclosure are described in detail below with reference to the accompanying drawings.

[0023] The present disclosure will be described more fully below with reference to the accompanying drawings, but the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. These embodiments are provided to make the present disclosure more thorough and complete and to enable those skilled in the art to fully understand the scope of the present disclosure.

[0024] The accompanying drawings provided in this disclosure are used to provide a further understanding of the implementation of the present disclosure and constitute a part of the specification. Together with the detailed embodiments, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. By describing the detailed embodiments with reference to the accompanying drawings, the above and other features and advantages will become more apparent to those skilled in the art.

[0025] The present disclosure may be described with reference to plan views and / or cross-sectional views by way of ideal schematic views of the present disclosure. Therefore, the exemplary illustrations may be modified according to manufacturing techniques and / or tolerances.

[0026] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0027] The terms used in this disclosure are only used to describe specific embodiments and do not limit this disclosure. As used in this disclosure, the term "and / or" includes any and all combinations of one or more related enumerated items. As used in this disclosure, the singular forms "a" and "the" also include plural forms, unless the context clearly indicates otherwise. As used in this disclosure, the terms "comprising" and "made of" specify the presence of specific features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of at least one other feature, whole, step, operation, element, component and / or its group.

[0028] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meanings as those commonly understood by those skilled in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined in this disclosure.

[0029] The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions of the elements, but are not restrictive.

[0030] With the development of mobile communication technology, NSA (non-standalone) networking using LTEA (Long-Term Evolution-Advanced) and NR (New Radio) has become a widely used 5G (fifth-generation mobile communication technology) networking method. Terminal devices using NSA networking mode must support both NR and LTEA when performing OFDM (Orthogonal Frequency Division Multiplexing) signal modulation.

[0031] For OFDM modulated signals, in order to eliminate the inter-symbol interference and inter-subcarrier interference existing in the OFDM modulation system, a cyclic prefix is ​​generally inserted into the signal after IFFT (Invert Fast Fourier Transformation) processing as a protection interval. At the same time, windowing or filtering methods are additionally required to suppress out-of-band spectrum leakage and smooth the inter-symbol phase discontinuity caused by the cyclic prefix.

[0032] Figure 1 shows a block diagram of an OFDM modulation system in the related art of communication systems. The OFDM modulation system transmits serial data in parallel through multiple overlapping, mutually orthogonal subcarriers and uses IFFT to modulate the OFDM signal. It has excellent fading suppression capabilities and efficient bandwidth resource utilization.

[0033] In view of the above background, the relevant technical solutions mainly have the following three problems.

[0034] 1. Implementing the OFDM signal modulation process through software. This solution is simple to implement and highly flexible. However, the OFDM signal modulation process involves a large amount of data calculation, which takes a long time and occupies more resources, which will increase the implementation cost of the product.

[0035] 2. Implementing the OFDM signal modulation process through hardware. Since different standards involve many scenarios and the process control is complex and inconvenient to unify, most of the current hardening solutions implement their own processing flows separately for each standard to meet the needs. The control is independent and convenient, but the implementation area is large, which is not conducive to reducing equipment costs.

[0036] 3. During the OFDM signal modulation process, high-order filters are used for filtering to obtain good out-of-band performance. However, the implementation complexity of high-order filters is relatively high, and it is not possible to reduce the cost for multi-standard terminal equipment. In addition, the filter has a long working time. If it is not designed properly, it will introduce high power consumption and is not conducive to energy saving of the equipment.

[0037] In order to overcome the problems of complex OFDM signal modulation process and large implementation area under multiple standards in related technologies, the present disclosure provides a signal processing method, such as an OFDM modulation signal post-processing method, which can focus on implementing the OFDM modulation signal post-processing process of current mainstream wireless communication systems at low cost and low power consumption.

[0038] In the solution provided by the present invention, the preset standard is at least one standard. By processing the target signal under the preset standard, the integrated processing of standards such as NR and LTEA is realized, thereby reducing the implementation cost and system power consumption. By generating the read address and read enable corresponding to the symbol data online in the cache, the synchronization of the uplink signal is guaranteed. By caching the target baseband signal, the uplink delay can be guaranteed to be the same (absolute time) under various sampling rates, various MCS (Modulation and Coding Scheme) scheduling and bandwidth scenarios, and it is convenient to fine-tune the delay of each channel and carrier.

[0039] The signal processing method provided in this disclosure can be executed by any electronic device requiring similar signal processing, such as a terminal device or server. Terminal devices may include, but are not limited to, in-vehicle devices, user equipment (UE), mobile devices, computing devices, wearable devices, and the like, including, but not limited to, cellular phones, cordless phones, personal digital assistants (PDAs), and portable computers. The USSD (Unstructured Supplementary Service Data) notification sending method can be implemented by a processor invoking computer-readable program instructions stored in a memory, or by a server.

[0040] The signal processing method provided by the present disclosure can be applied to but not limited to various wireless communication system-related products such as 4G (fourth-generation mobile communication technology), 5G, WiFi (wireless fidelity), NB-IoT (NR: New Radio, new wireless / new air interface; IoT: Internet of Things), and V2X (V2X: Vehicle To Everything, the exchange of all information between the vehicle and the outside world).

[0041] The solution provided in the present disclosure can be used for an OFDM modulation device that supports both NR and LTEA standards, or can be used for OFDM modulation of NR or LTEA alone, or the various processes in the device of the solution provided in the present disclosure can be split apart, and part of the implementation solution can be selected for the OFDM demodulation device.

[0042] The solution provided by the present disclosure is introduced in detail below.

[0043] The present disclosure provides a signal processing method, as shown in FIG2 , including steps S11 to S16 .

[0044] S11 . Convert a target signal under a preset standard into symbol data, and cache the symbol data; the preset standard is at least one standard.

[0045] In the present disclosure, the preset standard may include but is not limited to at least one of the following: New Radio (NR) standard and Long Term Evolution Enhanced (LTE) standard. The target signal may include but is not limited to: Orthogonal Frequency Division Multiplexing (OFDM) modulated signal.

[0046] In some embodiments of the present disclosure, converting a target signal under a preset format into symbol data and caching the symbol data (i.e., step S11) includes: subjecting the OFDM modulated signal to inverse fast Fourier transform (IFFT) processing to obtain symbol data; caching symbol data of different formats in a time-division multiplexing manner in the same first cache module, and performing ping-pong storage on the symbol data.

[0047] In the signal processing method provided herein, a first cache module can be used to store symbol data obtained by IFFT processing of an NR or LTEA OFDM modulated signal. This first cache module can be reused in multiple standards. When writing the OFDM modulated signal to the first cache module, for example, into RAM (Random Access Memory), two sets of RAM can be used for symbol-by-symbol ping-pong caching to prepare for subsequent online windowing.

[0048] S12: Generate a read address and a read enable corresponding to the symbolic data online in the cache.

[0049] In some embodiments of the present disclosure, generating a read address and a read enable corresponding to symbol data online in a cache (i.e., step S12) includes: adding a cyclic prefix CP and adjusting a time advance TA to the symbol data online in the cache; and generating a read address and a read enable corresponding to the symbol data after adding the CP and adjusting the TA based on a control scenario.

[0050] In the signal processing method provided in the present disclosure, the read address corresponding to the symbol data after NR or LTEA adds CP (Cyclic Prefix) and adjusts TA (Timing Advance) can be generated online, and the corresponding read enable is generated according to the set read start time. When adding the cyclic prefix, in order to maintain uplink synchronization, the TA adjustment value also needs to be considered. Taking into account the uplink TA adjustment, the hardware processing delay needs to be consistent under different control scenarios (or scheduling scenarios). The solution provided in the present disclosure can adjust the sending start time of the baseband signal in the second cache module (to be introduced in the subsequent content), and flexibly adjust the reading start time of the first cache module to adapt to the sending start time of the baseband signal according to different control scenarios of different standards, so as to reduce the RAM area cost of the second cache module.

[0051] In some embodiments of the present disclosure, as shown in Figure 3, generating a read address and a read enable corresponding to the symbol data after adding CP and TA adjustment based on the control scenario may include: obtaining scenario parameters of the control scenario; the scenario parameters may include but are not limited to: address parameters, time parameters and symbol length parameters; generating a read start address according to the address parameters, generating a read start time according to the time parameters, and generating a symbol length threshold according to the symbol length parameters; starting a preset symbol length counter according to the read start time and the symbol length threshold, and generating a read address according to the count of the read start address and the symbol length counter; generating a read enable according to the read start time and the symbol length threshold.

[0052] In some embodiments of the present disclosure, as shown in FIG3 , address parameters may include but are not limited to at least one of the following: standard, sampling rate, subcarrier gap, channel type, symbol position, and TA adjustment value; time parameters may include but are not limited to at least one of the following: standard, sampling rate, subcarrier gap, and channel type; symbol length parameters may include but are not limited to at least one of the following: standard, sampling rate, subcarrier gap, channel type, symbol position, and TA adjustment value.

[0053] In the signal processing method provided by the present invention, when generating a read address and a read enable, different standards, sampling rates, channel types, TA adjustment values ​​and other parameters correspond to different results, and there are many control scenarios involved. If the enumeration rule is used, the control is complex and prone to omissions or errors. Therefore, the solution provided by the present invention represents the influence of each parameter on the read address and the read enable with different variable factors, and generates the read address and the read enable by combining the variable factors, which can significantly reduce the implementation complexity.

[0054] In the signal processing method provided by the present invention, according to the control flow diagram of the read address and read enable shown in Figure 3, first, various parameters required for the calculation of the read address and read enable, such as the standard, sampling rate, subcarrier spacing, channel type, symbol position, TA adjustment value, etc., are obtained through software configuration, and then different variable factors (for example, address parameters, time parameters and symbol length parameters, etc.) are obtained based on the influence of various parameters on the read address and read enable. The variable factors are combined to obtain the corresponding read start address, read start time and symbol length threshold, and then the symbol length counter is started according to the read start time and symbol length threshold to start accumulation and generate read enable, and finally the read start address is combined with the symbol length counter to generate the corresponding read address of the symbol data online.

[0055] S13 , restoring the symbol data read from the cache into I-channel and Q-channel readout data according to the read address and the read enable, and performing corresponding filtering processing on the I-channel and Q-channel readout data according to the channel types of the I-channel and Q-channel readout data to obtain filtered data.

[0056] In some embodiments of the present disclosure, performing corresponding filtering processing on the I-channel and Q-channel readout data according to the channel type of the two-channel readout data, and obtaining the filtered data (i.e., step S13) may include: when the channel type is a PRACH (Physical Random Access Channel) channel, using a cascaded low-order filter to up-sample and filter the readout data; the low-order filter refers to a filter with a filtering order less than a preset order threshold; when the channel type is not a PRACH channel, performing at least one of windowing and finite-length unit impulse response (FIR) filtering on the readout data.

[0057] In the signal processing method provided by the present disclosure, data is read out from the first cache module in sequence according to the read address and read enable, and then restored into I / Q two-way data to obtain two-way read data, and then different subsequent processing is selected according to the channel type.

[0058] In the signal processing method provided in this disclosure, if the channel type is a PRACH channel, the data is upsampled and filtered using a cascaded low-order filter. If the channel type is not a PRACH channel, windowing or FIR (Finite Impulse Response) filtering is performed. Another equivalent implementation scheme can use a cache to store the symbol data corresponding to the cyclic prefix and TA adjustment value to be added offline, and then splice it with the valid symbol data. The disadvantage of this scheme is that it introduces multiple cache units, which increases the design area.

[0059] In some embodiments of the present disclosure, upsampling and filtering the readout data using a cascaded low-order filter includes: performing an IFFT transform on the long code of the PRACH channel according to the original number of sampling points of the PRACH sequence in the PRACH channel to obtain a transformation result; and filtering the transformation result by upsampling it to the number of sampling points corresponding to the long code using a cascaded low-order filter.

[0060] In some embodiments of the present disclosure, the low-order filter may include but is not limited to an HBF (Half Band Filter).

[0061] In some embodiments of the present disclosure, cascaded HBF upsampling filtering can be performed on some PRACH scenarios to generate PRACH preambles and suppress out-of-band leakage, while other PRACH scenarios and non-PRACH scenarios that do not require upsampling are bypassed (i.e., no longer filtered).

[0062] In the signal processing method provided by the present disclosure, for PRACH long codes, the length of its preamble SEQ (sequence) is relatively long, and theoretically the number of IFFT points required is also relatively large. For example, at a data sampling rate of 30.72 MHz (megahertz), the non-repeating SEQ length of PRACH formats 0 to 2 is 24576, and the theoretical number of IFFT points is 24576 at this time. Directly implementing such a large number of points (24576) consumes too much IFFT resources, and when the sampling rate increases, the SEQ length also becomes longer accordingly. To solve this problem, the solution provided by the present disclosure adopts a method of first performing an IFFT with a small number of points (for example, 1536), then upsampling to the corresponding number of points (24576) based on the IFFT transformation result, and then filtering.

[0063] In the present disclosure, for scenarios where a higher upsampling multiple is achieved, the solution provided by the present disclosure uses a cascade of low-order filters, which can greatly reduce the order of the filter and also reduce power consumption. The upsampling multiple used in the cascade process of the solution provided by the present disclosure is 2, so an HBF half-band filter can be used, and this structure can further save resources. Another equivalent implementation scheme can also complete upsampling once and then perform FIR filtering when reading data from the first cache module, or perform FIR filtering after multiple upsamplings, but this scheme requires a larger filter order, high implementation cost, and high power consumption.

[0064] Based on the above description, the signal processing method provided by the present disclosure can support 2 N Each HBF stage supports bypass for upsampling times. When the number of cascaded HBFs is less than N, the required number of HBF stages are enabled from the front to the back, and the remaining stages are bypassed. If upsampling is not required, all stages are bypassed. The hardware structure of each HBF stage remains consistent at different sampling rates to flexibly support different upsampling multiple requirements. Taking the cascade of six HBFs (HBF0, HBF1, HBF2, HBF3, HBF4, and HBF5) as an example, a maximum of 64x upsampling is supported. The corresponding implementation structure is shown in Figure 4.

[0065] In some embodiments of the present disclosure, the clock of the cascaded low-order filter includes two levels of gating; the two levels of gating may include: overall gating of the cascaded low-order filter and gating of each level of low-order filter; the clock of each level of low-order filter can only be turned on when the low-order filter of that level is enabled.

[0066] For example, there are two levels of clock gating to reduce power consumption in a cascaded HBF filter. The first level is gating for the entire cascaded HBF, and the second level is gating for each HBF stage. The actual working clk (clock) is only valid when the HBF stage is enabled.

[0067] In some embodiments of the present disclosure, each stage of the cascaded low-order filters uses multiple phases.

[0068] For example, to save area and power consumption, each HBF stage adopts a multi-phase implementation scheme, and the scheme provided in the present disclosure can be set to two phases.

[0069] In some embodiments of the present disclosure, before performing at least one of windowing and finite-length unit impulse response (FIR) filtering on the readout data, the signal processing method may further include: pre-setting the FIR unit based on the number of multiplications and accumulations that can be performed in one sampling period at the highest data sampling rate; cascading multiple FIR units to obtain an FIR filter with configurable order; obtaining a target FIR filter of corresponding order by controlling the number of FIR units in the enabled FIR filter; and any target FIR filter of achievable order in the FIR filter can be reused.

[0070] In some embodiments of the present disclosure, out-of-band leakage of the transmission signal may be suppressed by using any one of windowing and FIR (Finite Impulse Response) filtering, or a combination of the two.

[0071] In some embodiments of the present disclosure, adjacent OFDM symbols experience phase discontinuity and phase jumps due to the intervening CP. Windowing or filtering is required to smooth the transitions between symbols and suppress out-of-band leakage of the transmitted signal. Window lengths can vary at different data sampling rates, and windowing bypass is supported.

[0072] In some embodiments of the present disclosure, the windowing process mainly uses a section of cosine-like function (-π to 0) to achieve the "slow rise" of data, and uses another section of cosine-like function (0 to π) to achieve the "slow fall" of data, thereby achieving the filtering effect.

[0073] The signal processing method provided in this disclosure supports both windowing and filtering to reduce the order of the FIR filter. It can distinguish between different frequency ranges and different sampling rates, support configurable filter orders, and also support filter bypass.

[0074] In the signal processing method provided by the present disclosure, when the filter is implemented, the data is processed online. The solution provided by the present disclosure can adopt a fixed working clock frequency in different scenarios to reduce the implementation cost. The multiplication and accumulation operations of the filter are performed according to the number of working clocks contained in 1Ts (i.e., one sampling period, the actual sampling rate) at different sampling rates, and the data shift is performed in units of Ts. In order to have a unified hardware implementation solution at different data sampling rates, the solution provided by the present disclosure is based on the number of multiplication and accumulation that can be performed in 1Ts at the highest data sampling rate, and sets a filter particle FIR Group (i.e., the aforementioned FIR unit). Different orders call different numbers of FIR Groups for cascading to maximize the reuse of hardware resources, facilitate unified control, simplify the control logic, and reduce the overall area of ​​the filtering part.

[0075] In some embodiments of the present disclosure, the clock of the FIR filter includes two levels of gating; the two levels of gating include: gating of the FIR filter and gating of each FIR unit; the clock of the FIR unit can be turned on only when the corresponding FIR unit is enabled.

[0076] In the signal processing method provided in the present invention, in order to further reduce the system power consumption, the clock of the filtering part is gated at two levels. The first level is the gating of the entire FIR, and the second level is the gating of the FIR Group. The clock of the filtering particle is turned on only when the corresponding FIR Group is enabled, and the shift and multiplication and accumulation operations within the FIR Group are added to be executed only under the enable signal of the actual working clk (clock) being pulled high, thereby greatly reducing power consumption.

[0077] In the signal processing method provided by the present disclosure, a set of hardware structures can flexibly support different filter orders to adapt to the order requirements of different scenarios. For example, multiple FIR Groups are cascaded to implement FIR filtering, and multiple muxes (multiplexers) are used to call different numbers of FIR Groups to adapt to different orders. For example, 12 FIR Groups and 5 muxes are used as an example for explanation, that is, the FIR filter includes 12 FIR Groups and 5 muxes. The corresponding cascade implementation structure is shown in Figure 5, which includes 12 FIR Groups, namely FIR Group0, FIR Group1, FIR Group2, FIR Group3, FIR Group4, FIR Group5, FIR Group6, FIR Group7, FIR Group8, FIR Group9, FIR Group10, and FIR Group11, and 5 muxes, namely mux0, mux1, mux2, mux3, and mux4. Mux0 can be connected to a D-type trigger, and each FIR Group can be connected to an adder.

[0078] In the signal processing method provided in the present disclosure, if you want to work at the maximum order, enable 12 FIR Groups, and input data from FIR Group 0. If you want to work at a low order, enable the required number of FIR Group cascades from back to front, and use mux to feed the input data from the first FIR Group of the corresponding order.

[0079] In some embodiments of the present disclosure, performing finite-length unit impulse response (FIR) filtering on the read data may include: determining the filtering order required for the read data; and starting a target FIR filter of a corresponding order from the FIR filter according to the required filtering order to filter the read data.

[0080] In some embodiments of the present disclosure, based on the acquisition of the above-mentioned FIR filter, the order of the filter can be configured according to requirements to obtain the target FIR filter, and after determining the order, it is only necessary to input data from the first FIR Group of the mux corresponding to the corresponding order filter.

[0081] In some embodiments of the present disclosure, the above-mentioned filter order can be obtained by inputting filter order related parameters.

[0082] S14: Optimize the filtered data to obtain the target baseband signal.

[0083] In some embodiments of the present disclosure, the optimization process may include but is not limited to at least one of the following: selectively performing power ramp-up and roll-off processing on continuous filtered data; and compensating for the phase and frequency of the filtered data.

[0084] In the signal processing method provided in the present disclosure, in addition to windowing, in order to suppress out-of-band leakage of the transmitted signal, power ramp-up and roll-off processing can also be supported at the head and tail of a continuous transmission, that is, a segment of data sampling is scaled to form a process in which the amplitude of the transmitted signal gradually increases at the head and gradually decreases at the tail.

[0085] The signal processing method provided herein can also compensate for phase and frequency offsets during device operation. This solution can perform online compensation by invoking multiple CORDIC (Coordinate Rotation Digital Computer) units for parallel processing, reducing design complexity and logic area.

[0086] In some embodiments of the present disclosure, power ramp-up and roll-off processing may be performed first, followed by phase and frequency compensation.

[0087] S15. Cache the target baseband signal.

[0088] In some embodiments of the present disclosure, a second buffer module may be used to store the generated target baseband signal (eg, an OFDM baseband signal).

[0089] Based on the aforementioned first cache module, plus the second cache module, the solution provided by the present disclosure sets up two cache modules. The role of the two cache modules is mainly to take into account that when the uplink TA is adjusted, the hardware processing delay needs to be consistent under different subcarrier spacing, different sampling rates and different scheduling schemes to ensure that the receiving end can receive the corresponding signal within a fixed time window. However, when the target baseband signal is generated, the processing delay of each step is different. If the processing delay of each step is fixed, each step needs to be controlled according to the actual control scenario of different standards. The hardware control logic will be more complicated and not easy to transplant. Therefore, the solution provided by the present disclosure adopts a unified cache module to adjust the reading start time ① (adjusted by the first cache module) of the OFDM modulated signal post-processing process and the sending start time point ② (adjusted by the second cache module) of the target baseband signal.

[0090] In the signal processing method provided in the present disclosure, the second cache module, on the one hand, ensures that the uplink delay is the same (absolute time) under each sampling rate, each MCS scheduling and bandwidth scenario, and on the other hand, considers that the delay of each channel and carrier may need to be fine-tuned.

[0091] In the signal processing method provided by the present disclosure, as shown in Figure 6, there is a schematic diagram of the timing points of two cache modules (the first cache module and the second cache module). Because the read start time ① unifies the processing delay before the first cache module, the time difference corresponding to the sending time of the send start time point ② is at most the processing delay of the subsequent process after the read start time ①. On this basis, the channel delay is superimposed to obtain the depth of the second cache module without having to cache the data of the entire symbol length, thereby reducing the area of ​​the cache module. Moreover, in scenarios with small bandwidth and low sampling rate or in multi-stage HBF cascade scenarios, the processing delay of the filter is very large, but the delay of the process before the read start time ① (such as channel coding and IFFT processing, etc.) is relatively small. By adjusting the read start time ① forward, the processing delay of part of the filter can be absorbed, which can further reduce the depth of the second cache module.

[0092] S16 , after reading out the cached data according to the set delay value, performing interface conversion and radio frequency (RF) processing on the read cached data.

[0093] In the signal processing method provided by this disclosure, the target OFDM baseband signal is generated through the aforementioned processes. The data is then read out from the second buffer module at a set delay value, and after interface conversion and RF (Radio Frequency) processing, it is finally transmitted through the antenna.

[0094] The present disclosure also provides a signal processing device 100, as shown in Figure 7, including: a first cache module 101, configured to convert a target signal under a preset standard into symbol data and cache the symbol data; the preset standard is one or more standards; a generation module 102, configured to generate a read address and a read enable corresponding to the symbol data online in the cache; a filtering module 103, configured to restore the symbol data read from the cache into two-way read data, I-way and Q-way, according to the read address and the read enable, and perform corresponding filtering processing on the two-way read data according to the channel type of the I-way and Q-way read data to obtain filtered data; an optimization module 104, configured to optimize the filtered data to obtain a target baseband signal; a second cache module 105, configured to cache the target baseband signal; a processing module 106, configured to read the cached data according to a set delay value, and then perform interface conversion and RF processing on the read cached data.

[0095] In some embodiments of the present disclosure, as shown in Figure 8, the generation module 102 can implement read address logic control. The filtering module 103 can perform cascaded HBF upsampling filtering on the read data on the PRACH channel, and perform at least one of windowing and FIR filtering on non-PRACH channels or PRACH scenarios that do not require upsampling.

[0096] In the signal processing device 100 provided in the present disclosure, the optimization module 104 may include a power ramp-up and roll-off processing unit 1041 and a compensation unit 1042. The power ramp-up and roll-off processing unit 1041 may implement power ramp-up and roll-off processing, and the compensation unit 1042 may implement phase and frequency compensation for the filtered data.

[0097] In the signal processing device 100 provided in the present disclosure, the processing module 106 may include an interface conversion unit 1061 and an RF unit 1062 .

[0098] The solution provided by the present disclosure includes at least the following four advantages.

[0099] 1. The solution provided by the present invention integrates the OFDM modulation signal post-processing of NR and LTEA standards. The hardware structure of the entire signal processing device remains consistent in different scheduling scenarios, which facilitates unified control and can reduce the complexity of the control logic in each scenario after integration. In addition, some processing flows support the bypass function to maximize the reuse of OFDM modulation signal post-processing flows under different standards. As a whole, it can significantly reduce the implementation area of ​​the system and reduce the overall chip area cost.

[0100] 2. For the filtering process involved in OFDM post-processing, by using a fixed clock frequency to split the large-order filter into a cascade of small-order filters for scene-level multiplexing, it can flexibly support the different order requirements of each standard. For example, the HBF upsampling filter and FIR filtering in the solution provided by the present disclosure are both implemented by cascading small-order filters. At the same time, multi-level gating is adopted to perform refined clock gating on each filter stage to reduce power consumption, and the cascaded HBF solution is appropriately used instead of the ordinary FIR implementation solution based on the scenario.

[0101] 3. Perform operations such as adding OFDM cyclic prefix and TA adjustment in an online manner.

[0102] 4. A smaller buffer module is used to achieve the timed output of the OFDM modulated signal after out-of-band suppression processing, and two buffer modules (the first buffer module and the second buffer module) are used to control the timed reading and output of the OFDM modulated signal, ensuring the stability of the group delay of the transmission link in different scheduling scenarios under different standards, and ensuring that the receiving end can receive the corresponding signal within a fixed time window.

[0103] The present disclosure also provides an electronic device 200, as shown in Figure 9, comprising: at least one processor 201; a memory 202, on which at least one computer program is stored. When the at least one computer program is executed by the at least one processor 201, the at least one processor 201 implements the signal processing method.

[0104] In some embodiments, the electronic device 200 further includes at least one input / output I / O interface 203 connected between the processor 201 and the memory 202 and configured to implement information interaction between the processor 201 and the memory 202 .

[0105] The processor 201 is a device with data processing capabilities, including but not limited to a central processing unit (CPU); the memory 202 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically such as SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH); the I / O interface (read-write interface) 203 is connected between the processor 201 and the memory 202, and can realize information exchange between the processor 201 and the memory 202, including but not limited to a data bus (Bus), etc.

[0106] In some implementations, the processor 201 , the memory 202 , and the I / O interface 203 are connected to each other via a bus 204 , and further connected to other components of the computing device.

[0107] The present disclosure further provides a computer-readable storage medium 300, as shown in FIG10 . The computer-readable storage medium 300 stores a computer program, and the computer program is executed by a processor, so that the processor implements the signal processing method.

[0108] Those skilled in the art will appreciate that all or some of the functional modules / units disclosed above may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0109] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation.

[0110] Some or all of the physical components may be implemented as software executed by a processor (such as a central processing unit (CPU), a digital signal processor, or a microprocessor), or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or temporary media). As is well known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; compact disc (CD-ROM), digital versatile disc (DVD) or other optical disc storage; magnetic cassettes, tapes, disk storage or other magnetic storage; any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, as is well known to those skilled in the art, communication media typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0111] The present disclosure has disclosed example embodiments, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A signal processing method, comprising: Converting a target signal under a preset format into symbol data, and caching the symbol data; The preset format is at least one format; Generate a read address and a read enable corresponding to the symbol data online in a cache; The symbol data read from the cache is restored into I-channel and Q-channel read data according to the read address and the read enable, and the I-channel and Q-channel read data are subjected to corresponding filtering processing according to the channel types of the I-channel and Q-channel read data to obtain filtered data; Optimizing the filtered data to obtain a target baseband signal; Buffering the target baseband signal; After the cache data is read out according to the set delay value, interface conversion and radio frequency RF processing are performed on the read cache data.

2. The signal processing method according to claim 1, wherein: The target signal includes: an orthogonal frequency division multiplexing OFDM modulated signal; The converting the target signal under the preset format into symbol data and caching the symbol data comprises: The OFDM modulated signal is subjected to inverse fast Fourier transform (IFFT) processing to obtain the symbol data; The symbol data of different formats are cached in the same first cache module in a time-division multiplexing manner, and ping-pong storage is performed on the symbol data.

3. The signal processing method according to claim 1, wherein: Generating the read address and read enable corresponding to the symbol data online in the cache comprises: Adding a cyclic prefix CP and adjusting a time advance TA to the symbol data online in a buffer; The read address and read enable corresponding to the symbol data after adding CP and TA adjustment are generated based on the control scenario.

4. The signal processing method according to claim 3, wherein: The generating, based on the control scenario, the read address and the read enable corresponding to the symbol data after adding the CP and TA adjustment comprises: Acquire scene parameters of the control scene; the scene parameters include: address parameters, time parameters and symbol length parameters; Generate a read start address according to the address parameter, generate a read start time according to the time parameter, and generate a symbol length threshold according to the symbol length parameter; Starting a preset symbol length counter according to the read start time and the symbol length threshold, and generating the read address according to the read start address and the count of the symbol length counter; The read enable is generated according to the read start time and the symbol length threshold.

5. The signal processing method according to claim 4, wherein: The address parameters include at least one of the following: the standard, sampling rate, subcarrier spacing, channel type, symbol Number position and TA adjustment value; The time parameter includes at least one of the following: the format, the sampling rate, the subcarrier gap and the channel type; The symbol length parameter includes at least one of the following: the standard, the sampling rate, the subcarrier gap, the channel type, the symbol position and the TA adjustment value.

6. The signal processing method according to claim 1, wherein: The performing corresponding filtering processing on the I-path and Q-path readout data according to the channel types of the two-path readout data to obtain the filtered data comprises: In the case where the channel type is a physical random access PRACH channel, up-sampling and filtering the read data using a cascaded low-order filter; the low-order filter refers to a filter whose filtering order is less than a preset order threshold; In a case where the channel type is not a PRACH channel, at least one of windowing and finite-length unit impulse response (FIR) filtering is performed on the read data.

7. The signal processing method according to claim 6, wherein: The up-sampling and filtering of the read data by using a cascaded low-order filter comprises: For the long code of the PRACH channel, perform IFFT transformation according to the original sampling point number of the PRACH sequence in the PRACH channel to obtain a transformation result; The cascaded low-order filter is used to filter the transformation result upsampled to the sampling points corresponding to the long code.

8. The signal processing method according to claim 6 or 7, wherein: The low-order filter comprises: a half-band filter HBF; The cascaded low-order filter includes at least one of the following configurations: Each level of the cascaded low-order filters adopts multiple phases; The clock of the cascaded low-order filter includes two levels of gating; the two levels of gating include: overall gating of the cascaded low-order filter and gating of each level of the low-order filter; wherein the clock of each level of the low-order filter can be turned on only when each level of the low-order filter is enabled.

9. The signal processing method according to claim 6, further comprising: Before performing at least one of windowing and finite length unit impulse response (FIR) filtering on the read data, pre-setting the FIR unit based on the number of multiplication and accumulation that can be performed in one sampling cycle at the highest data sampling rate; Cascading a plurality of the FIR units to obtain a FIR filter with configurable order; A target FIR filter of a corresponding order is obtained by controlling the number of FIR units in the FIR filter; wherein any target FIR filter of an achievable order in the FIR filter can be reused.

10. The signal processing method according to claim 9, wherein: The clock of the FIR filter includes two levels of gating; The two-stage gating includes: gating of the FIR filter and gating of each of the FIR units; The clock of the FIR unit can be turned on only when the corresponding FIR unit is enabled.

11. The signal processing method according to claim 9 or 10, wherein: The performing finite length unit impulse response (FIR) filtering on the read data comprises: Determining the filtering order required for the read data; A target FIR filter of a corresponding order is started from the FIR filters according to the required filtering order to filter the read data.

12. The signal processing method according to claim 1, wherein: The optimization process includes at least one of the following: Selectively performing power ramp-up and roll-off processing on the continuous filtered data; The phase and frequency of the filtered data are compensated.

13. A signal processing device, comprising: A first buffer module, configured to convert a target signal under a preset standard into symbol data, and buffer the symbol data; The preset format is at least one format; A generating module, configured to generate a read address and a read enable corresponding to the symbol data online in a cache; a filtering module configured to restore the symbol data read from the cache into two-way read data, I-way and Q-way, according to the read address and the read enable, and perform corresponding filtering processing on the two-way read data according to the channel type of the two-way read data, to obtain filtered data; An optimization module, configured to optimize the filtered data to obtain a target baseband signal; A second cache module, configured to cache the target baseband signal; The processing module is configured to read out the cache data according to the set delay value, and then perform interface conversion and radio frequency RF processing on the read cache data.

14. An electronic device comprising: at least one processor; A memory having at least one computer program stored thereon, wherein when the at least one computer program is executed by the at least one processor, the at least one processor implements the signal processing method according to any one of claims 1 to 12.

15. A computer-readable storage medium having a computer program stored thereon, wherein the computer program is executed by a processor so that the processor implements the signal processing method according to any one of claims 1 to 12.

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