Chip package structure and chip package method

Abstract

The present invention provides a chip package structure and a chip package method. A first blocking layer is provided with a window, the window exposes the portion of a substrate at a non-filter bearing area, second pads, and the portion of the substrate at part of a via area surrounding the non-filter bearing area, a second blocking layer is formed on the first blocking layer, and the second blocking layer is located at the edge position of the first blocking layer close to the window, so that a covering film can seal a first cavity below a filter chip and is prone to break at the position of the second blocking layer close to the window to form a break; and a plastic packaging layer fills the window and a second cavity through the break, i.e., fills a space at the bottom of a non-filter chip. In this way, the operation of the filter chip is guaranteed, and the problem that the reliability of a non-filter device cannot be guaranteed due to lack of filling by a plastic packaging material is solved, thereby improving the reliability of the chip package structure.

Description

Chip packaging structure and chip packaging method Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a chip packaging structure and a chip packaging method. Background Art

[0002] Surface acoustic wave filters utilize acoustic waves transmitted across the chip surface to achieve their function. Therefore, the packaging of surface acoustic wave filters requires that the interdigital transducers within the filter be free of contact with other materials. This means that a cavity must be formed on the chip surface; otherwise, signal transmission would be affected. The chip packaging structure based on surface acoustic wave filters can also include conventional components that operate without cavities, such as antenna switches, low-noise amplifiers, capacitors, and inductors.

[0003] For example, traditional diversity receiver (DRX) modules often use a film to insulate the outer plastic encapsulation compound to ensure a cavity on the filter surface. However, due to the film's influence, other components within the module cannot be properly underfilled, which can easily lead to device shorts. Furthermore, the reliability of non-filter components cannot be guaranteed due to the lack of plastic encapsulation compound. Improving the reliability of such chip packaging structures has become a challenge for those skilled in the art.

[0004] Summary of the Invention

[0005] An object of the present invention is to provide a chip packaging structure and a chip packaging method to solve the problem of low reliability of chip packaging structures in the prior art.

[0006] In order to solve the above technical problems, the present invention provides a chip packaging structure, which includes:

[0007] A substrate comprising a filter-carrying area, a non-filter-carrying area, and an aisle area surrounding the filter-carrying area and the non-filter-carrying area, wherein a first solder pad and a second solder pad are formed on the substrate, the first solder pad is located in the filter-carrying area, and the second solder pad is located in the non-filter-carrying area;

[0008] a first barrier layer formed on the substrate, the first barrier layer having a window and an opening penetrating in a thickness direction, the window exposing the substrate and the second pad in the non-filter supporting area and a portion of the substrate in the aisle area surrounding the non-filter supporting area, and the opening exposing the first pad;

[0009] a second barrier layer formed on the first barrier layer, wherein the second barrier layer is located at an edge of the first barrier layer close to the window;

[0010] A filter chip aligned with the filter carrying area, the filter chip comprising a first substrate, an interdigital transducer formed on the first substrate, and a first bump formed on the first substrate, the interdigital transducer facing the first barrier layer, the first bump being electrically connected to the first pad, and a first cavity being formed below the filter chip;

[0011] A non-filter chip aligned with the non-filter carrying area, the non-filter chip comprising a second substrate and a second bump formed on the second substrate, the second bump being electrically connected to the second pad, a second cavity being formed below the non-filter chip, and the window being in communication with the second cavity;

[0012] a covering film covering the filter chip, the non-filter chip, the first barrier layer, and the second barrier layer, the covering film sealing the first cavity and being broken near the window in the second barrier layer to form a fracture; and

[0013] A plastic sealing layer covers the surface of the coating, and the plastic sealing layer also passes through the fracture to fill the window and the second cavity.

[0014] Optionally, in the chip packaging structure, the thickness of the coating is H1, the particle size in the plastic layer is H2, the projection of the non-filter chip on the substrate coincides with the non-filter carrying area, and the distance between at least one boundary of the window and the corresponding boundary of the non-filter carrying area is greater than or equal to H1+2H2.

[0015] Optionally, in the chip packaging structure, the projection of the non-filter chip on the substrate overlaps with the non-filter carrying area, and the distance between at least one boundary of the window and the corresponding boundary of the non-filter carrying area is greater than or equal to 10 μm.

[0016] Optionally, in the chip packaging structure, the second barrier layer is ring-shaped around the window.

[0017] Optionally, in the chip packaging structure, the second barrier layer is formed only on the first barrier layer aligned with the aisle region, and the width of the second barrier layer along the surface of the substrate is smaller than the width of the aisle region.

[0018] Optionally, in the chip packaging structure, the width of the second barrier layer along the surface of the substrate is greater than or equal to 50 μm.

[0019] Optionally, in the chip packaging structure, a boundary of the second barrier layer close to the window is flush with a boundary of the first barrier layer close to the window.

[0020] Optionally, in the chip packaging structure, a surface of the non-filter chip close to the substrate is lower than, equal to, or higher than a surface of the second barrier layer.

[0021] Optionally, in the chip packaging structure, the material of the second barrier layer is the same as or different from the material of the first barrier layer.

[0022] Optionally, in the chip packaging structure, the first barrier layer and the second barrier layer are both made of solder resist layers.

[0023] Optionally, in the chip packaging structure, the number of the filter chips and the number of the non-filter chips are one or more respectively, and the number of the filter carrying areas and the number of the non-filter carrying areas are one or more respectively.

[0024] The present invention also provides a chip packaging method, the chip packaging method comprising:

[0025] Providing a substrate, the substrate comprising a filter-carrying area, a non-filter-carrying area, and an aisle area surrounding the filter-carrying area and the non-filter-carrying area, wherein a first solder pad and a second solder pad are formed on the substrate, the first solder pad is located in the filter-carrying area, and the second solder pad is located in the non-filter-carrying area;

[0026] forming a first barrier layer on the substrate, wherein the first barrier layer has a window and an opening penetrating in a thickness direction, the window exposing the substrate and the second pad in the non-filter supporting area and a portion of the substrate in the aisle area surrounding the non-filter supporting area, and the opening exposing the first pad;

[0027] forming a second barrier layer on the first barrier layer, wherein the second barrier layer is located at an edge of the first barrier layer close to the window;

[0028] A filter chip is connected to the filter carrying area, wherein the filter chip includes a first substrate, an interdigital transducer formed on the first substrate, and a first bump formed on the first substrate, the interdigital transducer faces the first barrier layer, the first bump is electrically connected to the first pad, and a first cavity is formed below the filter chip;

[0029] A non-filter chip is connected to the non-filter carrying area, wherein the non-filter chip includes a second substrate and a second bump formed on the second substrate, the second bump is electrically connected to the second pad, a second cavity is formed below the non-filter chip, and the window is connected to the second cavity;

[0030] forming a covering film covering the filter chip, the non-filter chip, the first barrier layer, and the second barrier layer, wherein the covering film seals the first cavity and is broken near the window in the second barrier layer to form a fracture; and

[0031] A plastic sealing layer is formed to cover the surface of the coating, and the plastic sealing layer also passes through the fracture to fill the window and the second cavity.

[0032] Optionally, in the chip packaging method, the fracture is formed in the coating using a laser process.

[0033] Optionally, in the chip packaging method, the plastic packaging layer is formed by using a low-pressure plastic packaging process, and the pressure of the low-pressure plastic packaging process is less than 4T.

[0034] In the chip packaging structure and chip packaging method provided by the present invention, the first barrier layer has a window, which exposes the substrate and the second solder pad in the non-filter carrying area and the substrate in the partial aisle area surrounding the non-filter carrying area. A second barrier layer is formed on the first barrier layer and the second barrier layer is located at the edge of the first barrier layer close to the window. As a result, the coating can seal the first cavity under the filter chip and easily break at the second barrier layer close to the window to form a fracture. The plastic sealing layer will fill the window and the second cavity through the fracture, that is, fill the space at the bottom of the non-filter chip, thereby ensuring the operation of the filter chip and solving the problem that the reliability of the non-filter device cannot be guaranteed due to the lack of plastic sealing material filling, thereby improving the reliability of the chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG1 is a schematic flow chart of a chip packaging method according to an embodiment of the present invention.

[0036] FIG2 is a schematic cross-sectional view of a device in which a first barrier layer and a second barrier layer are formed according to an embodiment of the present invention.

[0037] FIG3 is a schematic top view of a device having a first barrier layer and a second barrier layer formed thereon according to an embodiment of the present invention.

[0038] FIG4 is a schematic cross-sectional view of a device connected to a filter chip and a non-filter chip according to an embodiment of the present invention.

[0039] FIG5 is a schematic cross-sectional view of a device with a coating formed thereon according to an embodiment of the present invention.

[0040] FIG6 is a schematic cross-sectional view of a chip packaging structure according to an embodiment of the present invention.

[0041] The reference numerals are as follows: 10 - chip package structure; 100 - substrate; 110 - filter-carrying area; 120 - non-filter-carrying area; 130 - aisle area; 140 - first pad; 150 - second pad; 200 - first barrier layer; 210 - window; 220 - opening; 300 - second barrier layer; 400 - filter chip; 410 - first substrate; 420 - interdigital transducer; 430 - first bump; 440 - first cavity; 500 - non-filter chip; 510 - second substrate; 520 - second bump; 530 - second cavity; 600 - cover film; 610 - fracture; 700 - plastic layer. H - distance; W - width. DETAILED DESCRIPTION

[0042] The chip packaging structure and chip packaging method proposed in the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0043] The terminology used herein is for the purpose of describing specific embodiments only and is not intended to limit the invention. Unless otherwise defined herein, technical or scientific terms used herein shall have the ordinary meaning as understood by a person of ordinary skill in the art to which the invention pertains. The terms "first," "second," and similar terms used in the specification and claims of the present invention do not denote any order, quantity, or importance, but are simply used to distinguish one component from another. Similarly, terms such as "a" or "an" do not denote a limitation of quantity, but rather denote the presence of at least one. "Multiple" or "several" refer to two or more. Unless otherwise indicated, terms such as "upper" and / or "lower" are for convenience only and are not intended to limit the invention to a specific location or spatial orientation. Terms such as "include" or "comprising" mean that the elements or structures preceding the term "include" or "comprising" encompass the elements or structures listed after the term and their equivalents, and do not exclude other elements or structures. Terms such as "connected" or "connected" are not limited to physical or mechanical connections and may include electrical connections, whether direct or indirect. As used in the present description and the appended claims, the singular forms "a," "an," "said," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0044] The core idea of ​​the present invention is to provide a chip packaging structure and a chip packaging method, wherein the first barrier layer has a window, which exposes the substrate and the second solder pad in the non-filter carrying area and the substrate in the partial aisle area surrounding the non-filter carrying area. A second barrier layer is formed on the first barrier layer and the second barrier layer is located at the edge of the first barrier layer close to the window, so that the coating can close the first cavity under the filter chip and easily break at the second barrier layer close to the window to form a fracture. The plastic sealing layer will fill the window and the second cavity through the fracture, that is, fill the space at the bottom of the non-filter chip, thereby ensuring the operation of the filter chip and solving the problem that the reliability of the non-filter device cannot be guaranteed due to the lack of plastic sealing material filling, thereby improving the reliability of the chip packaging structure.

[0045] Specifically, please refer to Figure 1, which is a schematic flow chart of a chip packaging method according to an embodiment of the present invention. As shown in Figure 1, in the embodiment of the present application, the chip packaging method specifically includes the following steps:

[0046] Step S10: providing a substrate, the substrate comprising a filter-carrying area, a non-filter-carrying area, and an aisle area surrounding the filter-carrying area and the non-filter-carrying area, a first solder pad and a second solder pad being formed on the substrate, the first solder pad being located in the filter-carrying area, and the second solder pad being located in the non-filter-carrying area;

[0047] Step S20: forming a first barrier layer on the substrate, wherein the first barrier layer has a window and an opening penetrating in a thickness direction, the window exposing the substrate and the second pad in the non-filter supporting area and a portion of the substrate in the aisle area surrounding the non-filter supporting area, and the opening exposing the first pad;

[0048] Step S30: forming a second barrier layer on the first barrier layer, wherein the second barrier layer is located at an edge of the first barrier layer close to the window;

[0049] Step S40: Connecting a filter chip to the filter supporting area, the filter chip including a first substrate, an interdigital transducer formed on the first substrate, and a first bump formed on the first substrate, the interdigital transducer facing the first barrier layer, the first bump being electrically connected to the first pad, and a first cavity being formed below the filter chip;

[0050] Step S50: connecting a non-filter chip to the non-filter supporting area, wherein the non-filter chip includes a second substrate and a second bump formed on the second substrate, the second bump is electrically connected to the second pad, a second cavity is formed below the non-filter chip, and the window is connected to the second cavity;

[0051] Step S60: forming a covering film covering the filter chip, the non-filter chip, the first barrier layer, and the second barrier layer, wherein the covering film seals the first cavity and is broken near the window in the second barrier layer to form a fracture; and

[0052] Step S70: forming a plastic encapsulation layer covering the surface of the coating film, wherein the plastic encapsulation layer also passes through the fracture and fills the window and the second cavity.

[0053] Further, please refer to Figures 2 to 6, wherein Figure 2 is a schematic cross-sectional view of a device in which a first barrier layer and a second barrier layer are formed according to an embodiment of the present invention; Figure 3 is a top-down schematic view of a device in which a first barrier layer and a second barrier layer are formed according to an embodiment of the present invention; Figure 4 is a schematic cross-sectional view of a device in which a filter chip and a non-filter chip are connected according to an embodiment of the present invention; Figure 5 is a schematic cross-sectional view of a device in which a coating is formed according to an embodiment of the present invention; and Figure 6 is a schematic cross-sectional view of a chip packaging structure in an embodiment of the present invention.

[0054] As shown in Figure 2, in an embodiment of the present application, a substrate 100 is first provided. The material of the substrate 100 can be, for example, semiconductor, resin, ceramic or glass. Here, the substrate 100 includes a filter bearing area 110 for bearing a filter chip, a non-filter bearing area 120 for bearing a non-filter chip, and an aisle area 130 surrounding the filter bearing area 110 and the non-filter bearing area 120. In an embodiment of the present application, the filter bearing area 110 and the non-filter bearing area 120 are separated by the aisle area 130. Furthermore, the filter bearing area 110 is located in the aisle area 130 and the non-filter bearing area 120 is located in the aisle area 130. In this way, it can ensure the convenience of subsequent connection of the filter chip or the non-filter chip, and at the same time improve the reliability of the connection, so that the plastic encapsulation layer formed subsequently can cover the surface of the filter chip and the non-filter chip, thereby improving the protection of the filter chip and the non-filter chip.

[0055] Furthermore, the substrate 100 may include one or more filter-carrying areas 110 to connect one or more filter chips. Similarly, the substrate 100 may include one or more non-filter-carrying areas 120 to connect one or more non-filter chips.

[0056] Among them, the filter carrying area 110 is the same as the projection of the filter chip to be connected on the substrate 100; or is larger than the projection of the filter chip to be connected on the substrate 100, that is, each boundary of the projection of the filter chip to be connected on the substrate 100 coincides with the corresponding boundary of the filter carrying area 110 or is located within the filter carrying area 110. Similarly, the non-filter carrying area 120 is the same as the projection of the non-filter chip to be connected on the substrate 100; or is larger than the projection of the non-filter chip to be connected on the substrate 100, that is, each boundary of the projection of the non-filter chip to be connected on the substrate 100 coincides with the corresponding boundary of the non-filter carrying area 120 or is located within the non-filter carrying area 120. In the embodiment of the present application, the filter carrying area 110 is the same as the projection of the filter chip to be connected on the substrate 100, that is, the two coincide; the non-filter carrying area 120 is the same as the projection of the non-filter chip to be connected on the substrate 100, that is, the two coincide.

[0057] Continuing with reference to FIG. 2 , in an embodiment of the present application, a first solder pad 140 and a second solder pad 150 are formed on the substrate 100, wherein the first solder pad 140 is located in the filter-carrying area 110, and the second solder pad 150 is located in the non-filter-carrying area 120. When the substrate 100 includes multiple filter-carrying areas 110 or multiple non-filter-carrying areas 120, each filter-carrying area 110 is formed with the first solder pad 140, and each non-filter-carrying area 120 is formed with the second solder pad 150. The first solder pad 140 and the second solder pad 150 are made of metal, for example, both the first solder pad 140 and the second solder pad 150 are made of tin. Furthermore, the number of the first solder pad 140 on each filter-carrying area 110 can be multiple and can be arranged as needed, and the number of the second solder pad 150 on each non-filter-carrying area 120 can also be multiple and can be arranged as needed, and this application does not limit this.

[0058] Please refer to Figure 3. In the embodiment of the present application, the first pad 140 and the second pad 150 are both circular in shape. In other embodiments of the present application, they may also be other shapes, such as square. Here, four first pads 140 are formed on the filter-carrying area 110, and the four first pads 140 are arranged in a rectangular shape; four second pads 150 are formed on the non-filter-carrying area 120, and the four second pads 150 are also arranged in a rectangular shape. In other embodiments of the present application, the first pads 140 and the second pads 150 may also be arranged in other forms, which is not limited by the present application.

[0059] Continuing with FIG2 , a first barrier layer 200 is then formed on the substrate 100. The first barrier layer 200 has a window 210 and an opening 220 extending through the thickness direction. The window 210 exposes the substrate 100 and the second pad 150 in the non-filter supporting area 120, as well as a portion of the substrate 100 in the aisle area 130 surrounding the non-filter supporting area 120. The opening 220 exposes the first pad 140. That is, the window 210 is larger than the non-filter supporting area 120. In this embodiment of the present application, all boundaries of the non-filter supporting area 120 are located within the window 210.

[0060] Further, referring to Figure 3 , one window 210 corresponds to one non-filter-carrying area 120. Accordingly, when the substrate 100 includes multiple non-filter-carrying areas 120, multiple windows 210 are formed in the first barrier layer 200, with each window 210 corresponding one-to-one to each non-filter-carrying area 120. Preferably, each window 210 exposes all of the second pads 150 on the corresponding non-filter-carrying area 120.

[0061] Preferably, the distance H between at least one boundary of the window 210 and the corresponding boundary of the non-filter bearing area 120 is greater than or equal to 10 μm. More preferably, the distance H between each boundary of the window 210 and the corresponding boundary of the non-filter bearing area 120 is greater than or equal to 10 μm. As shown in Figure 3, in this embodiment of the present application, the non-filter bearing area 120 and the window 210 are both rectangular. Particularly, the distances between each group of corresponding boundaries of the window 210 and the non-filter bearing area 120 may be equal or unequal. In this embodiment of the present application, the distances between each group of corresponding boundaries of the window 210 and the non-filter bearing area 120 are equal.

[0062] In other embodiments of the present application, the distance H between at least one boundary of the window 210 and the corresponding boundary of the non-filter bearing area 120 can also be determined according to the coating and plastic layer to be formed subsequently. Specifically, the thickness of the coating to be formed is H1, the particle size in the plastic layer to be formed is H2, and the distance H between at least one boundary of the window 210 and the corresponding boundary of the non-filter bearing area 120 is greater than or equal to H1+2H2. There will be particle fillers in the plastic layer, and the boundary size that allows the particles to pass through is retained here, which is conducive to the subsequent plastic layer filling the space at the bottom of the non-filter chip.

[0063] As shown in FIG2 and FIG3 , there are multiple openings 220, and each opening 220 exposes one first pad 140. The opening 220 may expose part or all of the corresponding first pad 140. In the embodiment of the present application, each opening 220 exposes only part or all of the corresponding first pad 140.

[0064] In the embodiment of the present application, specifically, a first barrier material layer (not shown) can be formed first, covering the entire upper surface of the substrate 100. Subsequently, a portion of the first barrier material layer can be removed by a semiconductor process such as etching or ashing to form the window 210 and the opening 220, thereby obtaining the first barrier layer 200. The material of the first barrier layer 200 is preferably a solder resist layer; in other embodiments of the present application, the material of the first barrier layer 200 can also be other materials, such as a dielectric material.

[0065] As shown in Figure 2 , a second barrier layer 300 is then formed on the first barrier layer 200. The second barrier layer 300 is located at the edge of the first barrier layer 200 near the window 210. In the embodiment of the present application, the second barrier layer 300 is annular and surrounds the window 210. Here, the second barrier layer 300 is in a square ring shape. In other embodiments of the present application, the second barrier layer 300 may also have other shapes, for example, the second barrier layer 300 is irregular in shape and has a window aligned with the window 210. The boundary of the second barrier layer 300 may be located on the first barrier layer 200 on the aisle area 130, or it may extend to the surface of the first barrier layer 200 on the filter supporting area 110, which is not limited in this application.

[0066] In this embodiment of the present application, the second barrier layer 300 is formed only on the first barrier layer 200 aligned with the aisle region 130, and the width of the second barrier layer 300 along the surface of the substrate 100 is smaller than the width of the aisle region 130 at the corresponding position. Specifically, the second barrier layer 300 is formed only on the first barrier layer 200 in a portion of the aisle region 130, and the second barrier layer 300 is closer to the non-filter-carrying region 120 than to the filter-carrying region 110. The width W of the second barrier layer 300 along the surface of the substrate 100 is greater than or equal to 50 μm, thereby improving the adhesion between the second barrier layer 300 and the first barrier layer 200.

[0067] 2 , in the embodiment of the present application, the boundary of the second barrier layer 300 near the window 210 is flush with the boundary of the first barrier layer 200 near the window 210. This increases the contact area between the second barrier layer 300 and the first barrier layer 200, thereby improving the adhesion between the two.

[0068] In other embodiments of the present application, a boundary of the second barrier layer 300 close to the window 210 may be concave or convex relative to a boundary of the first barrier layer 200 close to the window 210 .

[0069] When the boundary of the second barrier layer 300 near the window 210 is concave relative to the boundary of the first barrier layer 200 near the window 210, the second barrier layer 300 exposes a portion of the first barrier layer 200 near the window 210. Preferably, the cross-sectional width of the portion of the second barrier layer 300 exposing the first barrier layer 200 near the window 210 is smaller than the cross-sectional width of the second barrier layer 300.

[0070] When the boundary of the second barrier layer 300 near the window 210 is convex relative to the boundary of the first barrier layer 200 near the window 210, the second barrier layer 300 includes a first portion (not shown) protruding from the first barrier layer 200 and a second portion (not shown) covering the first barrier layer 200, wherein the cross-sectional width of the first portion is smaller than the cross-sectional width of the second portion. This ensures the contact area and adhesion between the second barrier layer 300 and the first barrier layer 200. Furthermore, the distance between the projection of the boundary of the second barrier layer 300 near the window 210 on the substrate 100 and the corresponding boundary of the non-filter bearing area 120 is also greater than or equal to 10 μm; or, greater than or equal to H1 + 2H2, to facilitate subsequent filling of the plastic encapsulation layer to the space at the bottom of the non-filter chip.

[0071] In the embodiment of the present application, the second barrier layer 300 is made of a solder mask, such as green paint. Preferably, the first barrier layer 200 is also made of a solder mask, such as green paint, so as to further improve the adhesion between the second barrier layer 300 and the first barrier layer 200, thereby improving the quality and reliability of the resulting chip package structure.

[0072] Preferably, the thickness of the second barrier layer 300 is the same as that of the first barrier layer 200, or the thickness of the second barrier layer 300 is thicker than that of the first barrier layer 200. This makes it easier to break the coating at the interface between the second barrier layer and the window when the coating is subsequently formed.

[0073] Next, please refer to FIG4 , and connect the filter chip 400 to the filter carrier area 110 and the non-filter chip 500 to the non-filter carrier area 120. Connecting the filter chip 400 to the filter carrier area 110 can be performed simultaneously with connecting the non-filter chip 500 to the non-filter carrier area 120, or connecting the filter chip 400 to the filter carrier area 110 can be performed before connecting the non-filter chip 500 to the non-filter carrier area 120, or connecting the filter chip 400 to the filter carrier area 110 can be performed after connecting the non-filter chip 500 to the non-filter carrier area 120.

[0074] Specifically, the filter chip 400 includes a first substrate 410, an IDT 420 formed on the first substrate 410, and a first bump 430 formed on the first substrate 410. The first bump 430 and the IDT 420 are located on the same surface of the first substrate 410. The IDT 420 faces the first barrier layer 200, the first bump 430 is electrically connected to the first pad 140, and a first cavity 440 is formed below the filter chip 400. The first bump 430 is made of metal, for example, a copper pillar, a gold ball, or a solder ball. The first bump 430 can be electrically connected to the first pad 140 by soldering.

[0075] Preferably, the height of the first cavity 440 is less than or equal to 20 μm, that is, the distance between the IDT 420 and the first barrier layer 200 is greater than 0 and less than or equal to 20 μm. This allows for the formation of a cavity, improves the connection reliability between the filter chip 400 and the substrate 100, and miniaturizes the resulting chip packaging structure.

[0076] The non-filter chip 500 includes a second substrate 510 and second bumps 520 formed on the second substrate 510. The second bumps 520 are electrically connected to the second pads 150. A second cavity 530 is formed below the non-filter chip 500, and the window 210 is connected to the second cavity 530. In the embodiment of the present application, the window 210 covers the second cavity 530, that is, the projection of the second cavity 530 on the substrate 100 is located within the projection of the window 210 on the substrate 100.

[0077] The second bumps 520 are made of metal, such as copper pillars, gold balls, or solder balls. The second bumps 520 can be electrically connected to the second pads 150 by soldering. The non-filter chip 500 can be, for example, an antenna switch, a low-noise amplifier, a capacitor, an inductor, or other conventional components that operate without a cavity, but this application is not limited thereto.

[0078] The surface of the non-filter chip 500 near the substrate 100 is lower than, equal to, or higher than the surface of the second barrier layer 300. Specifically, for example, the height of the second bumps 520 can be adjusted to adjust the relationship between the bottom surface of the non-filter chip 500 and the top surface of the second barrier layer 300. Alternatively, the height of the second pad 150, the thickness of the first barrier layer 200, and the thickness of the second barrier layer 300 can also be adjusted.

[0079] Next, as shown in FIG5 , a coating 600 is formed to cover the surface of the current device. Specifically, the coating 600 covers the surfaces of the filter chip 400, the non-filter chip 500, the first barrier layer 200, and the second barrier layer 300, and the coating 600 seals the first cavity 440. The coating 600 can be made of, for example, a PI-based or epoxy-based dry film material. Preferably, the thickness of the coating 600 is no less than the height of the first cavity 440. More preferably, the thickness of the coating 600 is equal to the height of the first cavity 440. This ensures the stability of the first cavity 440 while facilitating the breakage near the window 210 to form a fracture.

[0080] Please refer to FIG. 5 and FIG. 6 . In the embodiment of the present application, a fracture 610 is formed in the coating 600 . The fracture 610 is located in the second barrier layer 300 near the window 210 .

[0081] In one embodiment of the present application, the fracture 610 can be formed by utilizing the deformation of the covering film 600. Specifically, because the second barrier layer 300 is formed on the first barrier layer 200 and the second barrier layer 300 is located at the edge of the first barrier layer 200 near the window 210, the deformation of the covering film 600 at the second barrier layer 300 near the window 210 will be further increased, and the covering film 600 will become thinner at this location, so that the covering film 600 at this location will be easily broken, forming a fracture.

[0082] In this embodiment of the present application, a laser process is optionally used to form the fracture 610 in the cover film 600. The fracture 610 is aligned with the space between the second barrier layer 300 and the non-filter chip 500, that is, located in the second barrier layer 300 near the window 210. The laser process can quickly and accurately form the fracture 610. Furthermore, multiple fractures 610 can be formed around the non-filter chip 500 to facilitate subsequent filling of the plastic encapsulation layer.

[0083] Referring to Figure 6 , a plastic encapsulation layer 700 is then formed to cover the surface of the cover film 600. The plastic encapsulation layer 700 passes through the fracture 610 and fills the window 210 and the second cavity 530, that is, fills the cavity between the non-filter chip 500 and the substrate 100. This solves the problem of the reliability of the non-filter device due to the lack of plastic encapsulation material filling, thereby improving the reliability of the chip packaging structure.

[0084] Preferably, the plastic encapsulation layer 700 is formed using a low-pressure molding process, and the pressure of the low-pressure molding process is less than 4 T. Thus, the plastic encapsulation layer 700 can well fill the bottom of the non-filter chip 500 and well maintain the closed state of the first cavity 440, thereby improving the quality and reliability of the formed chip packaging structure 10.

[0085] Please continue to refer to Figure 6. Accordingly, the embodiment of the present application also provides a chip packaging structure 10, which includes: a substrate 100, the substrate 100 including a filter carrying area 110, a non-filter carrying area 120, and an aisle area 130 surrounding the filter carrying area 110 and the non-filter carrying area 120, a first solder pad 140 and a second solder pad 150 are formed on the substrate 100, the first solder pad 140 is located in the filter carrying area 110, and the second solder pad 150 is located in the non-filter carrying area 120; a first barrier layer 200 is formed on the substrate 100, the first barrier layer 200 is formed on the substrate 100, and the first barrier layer 200 is formed on the substrate 100. The barrier layer 200 has a window 210 and an opening 220 that penetrate in the thickness direction, wherein the window 210 exposes the substrate 100 and the second pad 150 in the non-filter carrying area 120 and the substrate 100 in the aisle area 130 surrounding the non-filter carrying area 120, and the opening 220 exposes the first pad 140; a second barrier layer 300 is formed on the first barrier layer 200, and the second barrier layer 300 is located at an edge position of the first barrier layer 200 close to the window 210; a filter chip 400 is aligned with the filter carrying area 110, and the filter chip 400 is aligned with the filter carrying area 110. 00 includes a first substrate 410, an interdigital transducer 420 formed on the first substrate 410, and a first bump 430 formed on the first substrate 410, wherein the interdigital transducer 420 faces the first barrier layer 200, the first bump 430 is electrically connected to the first pad 140, and a first cavity 440 is formed below the filter chip 400; a non-filter chip 500 aligned with the non-filter carrying area 120, the non-filter chip 500 includes a second substrate 510 and a second bump 520 formed on the second substrate 510, the second bump 520 and the second pad 150 Electrically connected, a second cavity 530 is formed under the non-filter chip 500, and the window 210 is connected to the second cavity 530; a coating 600 covers the surface of the filter chip 400, the non-filter chip 500, the first barrier layer 200 and the second barrier layer 300, the coating 600 closes the first cavity 440 and is broken near the window 210 in the second barrier layer 300 to form a fracture 610; and a plastic sealing layer 700 covers the surface of the coating 600, and the plastic sealing layer 700 also fills the window 210 and the second cavity 530 through the fracture 610.

[0086] Furthermore, the projection of the non-filter chip 500 on the substrate 100 overlaps with the non-filter supporting area 120, and the distance H between the boundary of the window 210 and the boundary of the non-filter supporting area 120 is greater than or equal to 10 μm. Alternatively, the thickness of the coating 600 is H1, the particle size of the plastic encapsulation layer 700 is H2, and the distance between at least one boundary of the window 210 and the corresponding boundary of the non-filter supporting area 120 is greater than or equal to H1+2H2.

[0087] Preferably, the second barrier layer 300 is annularly arranged around the window 210. The second barrier layer 300 is formed only on the first barrier layer 200 aligned with the aisle region 130, and a width W of the second barrier layer 300 along the surface of the substrate 100 is smaller than a width at a corresponding position of the aisle region 130. The width W of the second barrier layer 300 along the surface of the substrate 100 is greater than or equal to 50 μm.

[0088] The boundary of the second barrier layer 300 near the window 210 is flush with the boundary of the first barrier layer 200 near the window 210. Alternatively, the boundary of the second barrier layer 300 near the window 210 is concave or convex relative to the boundary of the first barrier layer 200 near the window 210.

[0089] In summary, it can be seen that in the chip packaging structure and chip packaging method provided in the embodiments of the present application, the first barrier layer has a window, which exposes the substrate and the second solder pad in the non-filter carrying area and the substrate in the partial aisle area surrounding the non-filter carrying area. A second barrier layer is formed on the first barrier layer and the second barrier layer is located at the edge of the first barrier layer close to the window. As a result, the coating can seal the first cavity under the filter chip and easily break at the second barrier layer close to the window to form a fracture. The plastic layer will fill the window and the second cavity through the fracture, that is, fill the space at the bottom of the non-filter chip, thereby ensuring the operation of the filter chip and solving the problem that the reliability of the non-filter device cannot be guaranteed due to the lack of plastic packaging material filling, thereby improving the reliability of the chip packaging structure.

[0090] Throughout this application, references to "one embodiment" or "some embodiments" mean that a feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment or at least some embodiments of this application. Thus, the appearance of the phrases "in one embodiment" or "in some embodiments" throughout this application does not necessarily refer to the same embodiment or embodiments. Furthermore, in one or more embodiments, features, structures, or characteristics may be combined in any suitable combinations and / or subcombinations.

[0091] Although some specific embodiments of the present application have been described in detail by way of example, it will be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present application. The various embodiments of the present application may be combined in any manner without departing from the spirit and scope of the present application. It will also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present application. The scope of the present application is defined by the appended claims.

Claims

1. A chip packaging structure, characterized in that: The chip packaging structure comprises: A substrate, the substrate comprising a filter-carrying area, a non-filter-carrying area, and an aisle area surrounding the filter-carrying area and the non-filter-carrying area, a first solder pad and a second solder pad being formed on the substrate, the first solder pad being located in the filter-carrying area, and the second solder pad being located in the non-filter-carrying area; A first barrier layer is formed on the substrate, the first barrier layer having a window and an opening penetrating in a thickness direction, the window exposing the substrate and the second pad in the non-filter carrying area and a portion of the substrate in the aisle area surrounding the non-filter carrying area, and the opening exposing the first pad; a second barrier layer formed on the first barrier layer, wherein the second barrier layer is located at an edge of the first barrier layer close to the window; A filter chip aligned with the filter bearing area, the filter chip comprising a first substrate, an IDT formed on the first substrate, and a first bump formed on the first substrate, the IDT facing the first barrier layer, the first bump and the first pad being electrically connected, and a first cavity being formed below the filter chip; A non-filter chip aligned with the non-filter bearing area, the non-filter chip comprising a second substrate and a second bump formed on the second substrate, the second bump and the second pad are electrically connected, a second cavity is formed below the non-filter chip, and the window is connected to the second cavity; a coating covering the filter chip, the non-filter chip, the first barrier layer and the second barrier layer, the coating sealing the first cavity and breaking the second barrier layer near the window to form a fracture; and, A plastic sealing layer covers the surface of the coating, and the plastic sealing layer also passes through the fracture to fill the window and the second cavity.

2. The chip packaging structure according to claim 1, characterized in that: The thickness of the coating is H1, the particle size in the plastic encapsulation layer is H2, the projection of the non-filter chip on the substrate coincides with the non-filter bearing area, and the distance between at least one boundary of the window and the corresponding boundary of the non-filter bearing area is greater than or equal to H1+2H2.

3. The chip packaging structure according to claim 1, characterized in that: The projection of the non-filter chip on the substrate overlaps with the non-filter bearing area, and the distance between at least one boundary of the window and the corresponding boundary of the non-filter bearing area is greater than or equal to 10 μm.

4. The chip packaging structure according to claim 1, characterized in that: The second barrier layer is annularly arranged around the window.

5. The chip packaging structure according to claim 1, characterized in that: The second barrier layer is formed only on the first barrier layer aligned with the aisle region, and a width of the second barrier layer along the surface of the substrate is smaller than a width of the aisle region.

6. The chip packaging structure according to claim 1, characterized in that: The width of the second barrier layer along the surface of the substrate is greater than or equal to 50 μm.

7. The chip packaging structure according to claim 1, characterized in that: A boundary of the second barrier layer close to the window is flush with a boundary of the first barrier layer close to the window.

8. The chip packaging structure according to any one of claims 1 to 7, characterized in that: The surface of the non-filter chip close to the substrate is lower than, equal to, or higher than the surface of the second barrier layer.

9. The chip packaging structure according to any one of claims 1 to 7, characterized in that: The material of the second barrier layer is the same as that of the first barrier layer.

10. The chip packaging structure according to any one of claims 1 to 7, characterized in that: The first barrier layer and the second barrier layer are both made of solder resist.

11. The chip packaging structure according to any one of claims 1 to 7, characterized in that: The material of the second barrier layer is different from that of the first barrier layer.

12. The chip packaging structure according to any one of claims 1 to 7, characterized in that: The number of the filter chips and the number of the non-filter chips are one or more respectively, and the number of the filter bearing area and the number of the non-filter bearing area are one or more respectively.

13. A chip packaging method, characterized in that: The chip packaging method comprises: A substrate is provided, the substrate comprising a filter bearing area, a non-filter bearing area, and a passage area surrounding the filter bearing area and the non-filter bearing area, and a first pad is formed on the substrate and a second pad, wherein the first pad is located in the filter bearing area, and the second pad is located in the non-filter bearing area; forming a first barrier layer on the substrate, wherein the first barrier layer has a window and an opening penetrating in a thickness direction, wherein the window exposes the substrate and the second pad in the non-filter carrying area and a portion of the substrate in the aisle area surrounding the non-filter carrying area, and the opening exposes the first pad; forming a second barrier layer on the first barrier layer, wherein the second barrier layer is located at an edge of the first barrier layer close to the window; A filter chip is connected to the filter bearing area, wherein the filter chip includes a first substrate, an interdigital transducer formed on the first substrate, and a first bump formed on the first substrate, the interdigital transducer faces the first barrier layer, the first bump is electrically connected to the first pad, and a first cavity is formed below the filter chip; A non-filter chip is connected to the non-filter bearing area, wherein the non-filter chip includes a second substrate and a second bump formed on the second substrate, the second bump is electrically connected to the second pad, a second cavity is formed below the non-filter chip, and the window is connected to the second cavity; forming a coating covering the filter chip, the non-filter chip, the first barrier layer and the second barrier layer, wherein the coating closes the first cavity and is broken at a position of the second barrier layer near the window to form a fracture; and, A plastic sealing layer is formed to cover the surface of the coating, and the plastic sealing layer also passes through the fracture to fill the window and the second cavity.

14. The chip packaging method according to claim 13, characterized in that: The fracture is formed in the coating by using a laser process.

15. The chip packaging method according to claim 13, characterized in that: The plastic sealing layer is formed by using a low-pressure plastic sealing process, and the pressure of the low-pressure plastic sealing process is less than 4T.

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