Chip etching process optimization method and system

Abstract

Disclosed are a chip etching process optimization method and a system, relating to the technical field of chip manufacturing. The method comprises: acquiring an etching condition for optimizing an etching process parameter of a target chip; constructing a wet etching process parameter adjustment domain, and constructing an etching optimization function; performing simulated wet etching of the target chip, and acquiring multiple size information sets after simulated etching; constructing multiple pieces of chip channel modeling information for simulated etching; calculating to obtain multiple guide fitnesses and multiple subordinate fitnesses; calculating to acquire multiple micro-step lengths; and, by combining multiple guide step lengths and the multiple micro-step lengths, performing iterative optimization until a preset optimization frequency is reached, obtaining an optimal etching process parameter, and taking the optimal etching process parameter as an etching process optimization result. The present invention solves the technical problems in the prior art of poor etching quality and low process optimization efficiency during chip manufacturing using wet etching, and achieves the technical effects of improving chip etching process optimization efficiency, and improving etching quality.

Description

Chip etching process optimization method and system Technical Field

[0001] The present invention relates to the technical field of chip manufacturing, and in particular to a chip etching process optimization method and system. Background Art

[0002] Controlling parameters in the wet etching process plays a crucial role in chip quality. While existing technologies utilize intelligent neural network models to learn etching process parameters during etching process optimization, the sheer volume of data required for iterative learning results in excessively long process optimization cycles and a high number of suboptimal solutions, resulting in suboptimal optimization results. Existing wet etching techniques for chip fabrication suffer from poor etching quality and low process optimization efficiency. Summary of the Invention

[0003] The present application provides a chip etching process optimization method and system for solving the technical problems of poor etching quality and low process optimization efficiency when wet etching is used to manufacture chips in the prior art.

[0004] In view of the above problems, the present application provides a chip etching process optimization method and system.

[0005] In a first aspect of the present application, a method for optimizing a chip etching process is provided, the method comprising:

[0006] Obtaining etching conditions that optimize etching process parameters of the target chip based on design information of the target chip to be wet-etched;

[0007] According to the wet etching process parameter adjustment range of the target chip, a wet etching process parameter adjustment domain is constructed, and based on the purpose of making the chip size after etching close to the design information, an etching optimization function is constructed;

[0008] Randomly generating a plurality of guided solutions within the wet etching process parameter adjustment domain, and generating a plurality of subordinate solutions within the range of the guided step lengths of the plurality of guided solutions, respectively performing simulated wet etching on the target chip, and obtaining a plurality of size information sets after the simulated etching;

[0009] Constructing multiple chip channel modeling information for simulated etching based on multiple size information sets, wherein the multiple chip channel modeling information includes multiple etching depth information, and obtaining multiple side etching amount information sets by dividing in the depth direction;

[0010] According to the plurality of etching depth information and the plurality of side etching amount information sets, combined with the design information, analyzing and calculating to obtain a plurality of etching depth compliance information and a plurality of side etching amount compliance information, and calculating and obtaining a plurality of guide fitnesses and a plurality of subordinate fitnesses based on the etching optimization function;

[0011] Calculate and obtain multiple micro-steps for updating multiple subordinate solutions according to the multiple guided fitnesses;

[0012] By adopting multiple guide step sizes and multiple micro-step sizes, multiple guide solutions and multiple subordinate solutions are updated, and iterative optimization is performed until a preset number of optimization times is reached to obtain the optimal etching process parameters as the etching process optimization result.

[0013] A second aspect of the present application provides a chip etching process optimization system, the system comprising:

[0014] An etching condition acquisition module is used to acquire etching conditions for optimizing etching process parameters of a target chip according to design information of the target chip to be wet-etched;

[0015] An optimization function construction module is used to construct a wet etching process parameter adjustment domain according to the wet etching process parameter adjustment range of the target chip, and to construct an etching optimization function based on the purpose of making the chip size after etching close to the design information;

[0016] a size information set acquisition module, configured to randomly generate a plurality of guide solutions within the wet etching process parameter adjustment domain, and respectively generate a plurality of subordinate solutions within the range of the guide step lengths of the plurality of guide solutions, respectively perform simulated wet etching on the target chip, and acquire a plurality of size information sets after the simulated etching;

[0017] A side erosion amount acquisition module is used to construct multiple chip channel modeling information for simulated etching based on multiple size information sets, wherein the multiple chip channel modeling information includes multiple etching depth information, and to obtain multiple side erosion amount information sets by dividing in the depth direction;

[0018] a fitness calculation module for analyzing and calculating, based on a plurality of etching depth information and a plurality of side etch amount information sets, in combination with design information, to obtain a plurality of etching depth compliance information and a plurality of side etch amount compliance information, and calculating a plurality of guide fitnesses and a plurality of subordinate fitnesses based on the etching optimization function;

[0019] A micro-step calculation module is used to calculate and obtain multiple micro-steps for updating multiple subordinate solutions according to multiple guided fitnesses;

[0020] The process optimization result setting module is used to adopt multiple guide step sizes and multiple micro-step sizes to update multiple guide solutions and multiple subordinate solutions, and perform iterative optimization until the preset number of optimization times is reached to obtain the optimal etching process parameters as the etching process optimization result.

[0021] One or more technical solutions provided in this application have at least the following technical effects or advantages:

[0022] The present application obtains etching conditions for optimizing etching process parameters of the target chip based on design information of the target chip to be wet-etched, and then constructs a wet etching process parameter adjustment domain based on the wet etching process parameter adjustment range of the target chip, and constructs an etching optimization function based on the purpose of making the chip size after etching close to the design information, and then randomly generates multiple guiding solutions within the wet etching process parameter adjustment domain, and generates multiple subordinate solutions within the range of guiding step lengths of the multiple guiding solutions, respectively, performs simulated wet etching of the target chip, and obtains multiple size information sets after simulated etching, and then constructs multiple chip channel modeling information of simulated etching based on the multiple size information sets. The chip channel modeling information includes multiple etching depth information, and multiple side etching amount information sets are obtained by dividing in the depth direction. Based on the multiple etching depth information and multiple side etching amount information sets, combined with the design information, multiple etching depth compliance information and multiple side etching amount compliance information are analyzed and calculated. Based on the etching optimization function, multiple guide fitness and multiple subordinate fitness are calculated. Based on the multiple guide fitness, multiple micro-steps for updating the multiple subordinate solutions are calculated. The multiple guide steps and multiple micro-steps are used to update the multiple guide solutions and multiple subordinate solutions, and iterative optimization is performed until the preset number of optimizations is reached to obtain the optimal etching process parameters as the etching process optimization result. This achieves the technical effect of efficiently and accurately optimizing the chip etching process and improving the reliability of the etching process. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] FIG1 is a schematic flow chart of a chip etching process optimization method provided in an embodiment of the present application;

[0025] FIG2 is a schematic diagram of a process for obtaining multiple sets of side etching amount information in a chip etching process optimization method provided in an embodiment of the present application;

[0026] FIG3 is a schematic diagram of a flow chart of calculating and obtaining a plurality of guide fitnesses and a plurality of slave fitnesses in a chip etching process optimization method provided in an embodiment of the present application;

[0027] FIG4 is a schematic diagram of the structure of a chip etching process optimization system provided in an embodiment of the present application.

[0028] Explanation of the accompanying symbols: etching condition acquisition module 11, optimization function construction module 12, size information set acquisition module 13, side etching amount acquisition module 14, fitness calculation module 15, micro-step length calculation module 16, process optimization result setting module 17. DETAILED DESCRIPTION

[0029] The present application provides a chip etching process optimization method and system to solve the technical problems of poor etching quality and low process optimization efficiency when using wet etching to manufacture chips in the existing technology.

[0030] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0031] It should be noted that the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or server that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or modules that are not clearly listed or are inherent to these processes, methods, products or devices.

[0032] Example 1

[0033] As shown in FIG1 , the present application provides a method for optimizing a chip etching process, wherein the method comprises:

[0034] S100: Obtaining etching conditions for optimizing etching process parameters of the target chip according to design information of the target chip to be wet-etched;

[0035] Furthermore, step S100 in the embodiment of the present application further includes:

[0036] Acquiring design information of a target chip to be wet-etched, the design information including depth information and width information of a trench after etching;

[0037] Obtain the error range of the target chip, compensate the depth information and width information, and obtain the depth information interval and width information interval;

[0038] The channel depth and width of the target chip after etching fall within the depth information interval and width information interval as etching conditions.

[0039] In one possible embodiment, the target chip is any chip to be wet-etched. Based on the design information of the target chip to be wet-etched, the etching conditions required to optimize the etching process parameters of the target chip during the wet etching are determined. By determining these etching conditions, the etching process optimization for the target chip is constrained, thereby achieving the technical effect of improving the accuracy and efficiency of etching process optimization.

[0040] In one embodiment, the design information is obtained by searching the order information of the target chip using the depth and width of the target chip's post-etch trench as an index. The design information includes the depth and width information of the post-etch trench. The design information reflects the depth and width requirements that the target chip must achieve after etching according to the design requirements. Furthermore, the quality grade of the target chip is determined based on the order information of the target chip. A person skilled in the art matches the permissible error range based on the quality grade of the target chip. Furthermore, the depth and width information of the post-etch trench in the design information are compensated to obtain the depth information interval and width information interval. The depth information interval represents the allowable depth range of the target chip after the etching process is completed. The width information interval represents the allowable width range of the target chip after the etching process is completed. Furthermore, the depth and width of the target chip's post-etch trench falling within the depth information interval and width information interval are used as etching conditions.

[0041] S200: constructing a wet etching process parameter adjustment domain according to the wet etching process parameter adjustment range of the target chip, and constructing an etching optimization function based on the goal of making the chip size after etching close to the design information;

[0042] Furthermore, step S200 in the embodiment of the present application further includes:

[0043] Obtaining the etching solution ratio range and etching time range of wet etching process parameters;

[0044] Combining the etching solution ratio range and the etching time range to obtain the process parameter adjustment range;

[0045] Based on the goal of making the chip size after etching close to the design information, an etching optimization function is constructed:

[0046] Among them, tch is the etching fitness, w1 and w2 are weights, S His the etching depth compliance of the etching depth information after etching, T is the number of locations where the channel side etching amount is tested after etching, and S Di is the compliance of the side etching amount at the i-th position in the trench after etching.

[0047] In one possible embodiment, the adjustable range for optimizing the etching process parameters, i.e., the wet etching process parameter adjustment domain, is determined based on the wet etching process parameter adjustment range for the target chip. Furthermore, an etching optimization function is constructed with the goal of ensuring that the chip size after etching is close to the design information. The etching optimization function is used to quantitatively calculate the degree of proximity between the chip size after etching according to the process parameters and the design information during the etching process optimization process for the target chip. This achieves the technical effect of improving the efficiency of etching process optimization.

[0048] In one embodiment, the wet etching process parameters of the target chip are searched using the etching solution ratio and etching time as indexes to obtain the etching solution ratio range and etching time range. Exemplarily, the etching time range is 4 to 6 minutes, or 4 to 8 minutes, etc. The process parameter adjustment domain is obtained by randomly combining the etching solution ratio range and etching time range. The process parameter adjustment domain is a parameter range that can be selected when optimizing the etching process parameters of the target chip. The etching fitness in the etching optimization function reflects the degree of closeness between the chip size after etching according to the process parameters and the target chip design information. The greater the fitness, the closer the chip size obtained after etching according to the corresponding wet etching process parameters is to the target chip design information. The etching depth compliance reflects the degree to which the etching depth in the chip channel meets the requirements after etching. The side etching amount compliance reflects the degree to which the side etching amount at any position in the chip channel meets the requirements after etching.

[0049] S300: randomly generating a plurality of guiding solutions within the wet etching process parameter adjustment domain, and generating a plurality of subordinate solutions within the range of guiding step lengths of the plurality of guiding solutions, respectively performing simulated wet etching on the target chip, and obtaining a plurality of size information sets after the simulated etching;

[0050] In one embodiment, each solution in the wet etching process parameter adjustment domain includes an etching solution ratio and an etching time. A plurality of guided solutions are obtained by randomly selecting a guided solution in the wet etching process parameter adjustment domain. The guided solution is used to provide guidance in the process of optimizing the etching process of the target chip and searching for a solution. The guided step size is the amplitude of parameter adjustment for the wet etching process parameters in the guided solution, and preferably, specifically includes the adjustment step size of the etching solution ratio and the adjustment step size of the etching time. Furthermore, a plurality of subordinate solutions are randomly generated within the range of the guided step sizes of the plurality of guided solutions. That is, the etching solution ratio range and etching time of the plurality of subordinate solutions are within the etching solution ratio range and etching time range of the plurality of guided solutions.

[0051] Furthermore, a simulated wet etching experiment was conducted on the target chip in the laboratory based on the etching solution ratio ranges and etching times in the multiple guiding solutions and the multiple subordinate solutions. After etching, the channels on the chip surface were magnified and scanned using an OLS4000 laser confocal 3D microscope and measured. The multiple sets of dimension information were obtained based on the measurement results. The multiple sets of dimension information are used to describe the channel shape after wet etching based on the multiple guiding solutions and the multiple subordinate solutions. This achieved the technical effect of providing basic analytical data for subsequent modeling and analysis.

[0052] S400: constructing multiple chip channel modeling information for simulated etching based on multiple size information sets, wherein the multiple chip channel modeling information includes multiple etching depth information, and obtaining multiple side erosion amount information sets by dividing in the depth direction;

[0053] Furthermore, as shown in FIG2 , step S400 in the embodiment of the present application further includes:

[0054] Constructing multiple chip channel modeling information for simulated etching based on multiple size information sets, performing modeling, and obtaining multiple simulated etching channel models;

[0055] Acquiring multiple etching depth information in multiple simulated etching channel models;

[0056] In the depth direction, multiple simulated etching channel models are hierarchically divided to obtain M etching layers, and the side etching amounts in the M layers are obtained to obtain multiple side etching amount information sets.

[0057] In one embodiment, a plurality of chip channel modeling information for simulating etching is constructed based on the dimensions in the plurality of size information sets. Preferably, the plurality of chip channel modeling information includes a plurality of etching depth information, and a plurality of side etching amount information sets are obtained by dividing in the depth direction. The etching depth information is used to describe the height of the chip channel relative to the chip surface. Since during the etching process, as the processing time increases, the reaction products increase, and the attachments on the side walls of the chip channel increase, resulting in different side etching amounts of the side walls in the depth direction, multiple side etching amount information sets in the corresponding depth direction are obtained according to each etching depth information.

[0058] Preferably, multiple simulated etching channel models are constructed by using 3DSMAX modeling software using the multiple size information sets. Wherein, the multiple simulated etching channel models correspond one-to-one to the multiple size information sets, reflecting the channel morphology of the corresponding size information sets. Furthermore, multiple etching depth information is obtained in the multiple simulated etching channel models. In the depth direction, the multiple simulated etching channel models are hierarchically divided according to the distribution of side etching amounts of different sizes, and the chip channel sidewalls with the same side etching amount are used as an etching layer, thereby obtaining M etching layers respectively. Wherein, M is an integer greater than or equal to 1. Furthermore, according to the multiple simulated etching channel models, the side etching amounts in the M etching layers are respectively collected to obtain multiple side etching amount information sets. The multiple side etching amount information sets correspond one-to-one to the multiple simulated etching channel models.

[0059] S500: Analyzing and calculating, based on the plurality of etching depth information and the plurality of side etch amount information sets and in combination with the design information, to obtain a plurality of etching depth compliance information and a plurality of side etch amount compliance information; and calculating and obtaining a plurality of guiding fitnesses and a plurality of subordinate fitnesses based on the etching optimization function;

[0060] Furthermore, as shown in FIG3 , step S500 in the embodiment of the present application further includes:

[0061] Training an etching compliance identifier, wherein the etching compliance identifier includes a depth compliance identification channel and multiple side etching compliance identification channels;

[0062] The etching compliance identifier is used to identify a plurality of etching depth information and a plurality of side etching amount information sets to obtain a plurality of etching depth compliance information and a plurality of side etching amount compliance information;

[0063] Based on the etching optimization function, a plurality of guide fitnesses and a plurality of slave fitnesses are calculated and obtained.

[0064] Furthermore, step S500 in the embodiment of the present application further includes:

[0065] According to the etching R&D data of the target chip, a sample etching depth information set and multiple sample side etching amount information sets are obtained;

[0066] Based on the depth information and width information of the trench in the target chip design information, evaluating and calculating the sample etching depth information set and the multiple sample side etch amount information sets to obtain a sample etching depth compliance set and multiple sample side etch amount compliance sets;

[0067] Using the sample etching depth information set and the sample etching depth compliance set, constructing and training the depth compliance recognition channel;

[0068] Constructing and training multiple side erosion compliance recognition channels by respectively using the multiple sample side erosion amount information sets and the multiple sample side erosion amount compliance sets;

[0069] By combining the depth compliance identification channel and multiple side etching compliance identification channels, an etching compliance identifier is obtained.

[0070] In one possible embodiment, compliance calculations are performed based on the multiple sets of etching depth information and the multiple sets of side etch amount information, as well as the design information, to obtain multiple etching depth compliances and multiple side etch amount compliances. Furthermore, fitness calculations are performed on the multiple etching depth compliances and multiple side etch amount compliances using an etching optimization function to obtain multiple guiding fitnesses and multiple subordinate fitnesses.

[0071] Preferably, the etching compliance identifier is a functional module for intelligently identifying the degree of conformity of chip dimensions after etching, and includes a depth compliance identification channel and multiple side etch compliance identification channels. The depth compliance identification channel is used to perform intelligent compliance identification on multiple etching depth information reflecting the chip trench after etching. The multiple side etch amount compliance identification channels are used to perform intelligent compliance identification on multiple sets of side etch amount information.

[0072] Preferably, the etching research and development data of the target chip is retrieved by taking etching depth and side etching amount as indexes, thereby obtaining a sample etching depth information set and multiple sample side etching amount information sets. Furthermore, based on the depth information and width information of the channel in the target chip design information, the sample etching depth information set and multiple sample side etching amount information sets are evaluated and calculated. Optionally, the sample etching depth compliance is obtained by taking the ratio of the sample etching depth in the sample etching depth set to the depth information of the channel in the target chip design information. Optionally, multiple sample width sets are calculated by collecting multiple sample mask width sets of the target chip and combining multiple sample side etching amount information sets. The width calculation formula is: width = mask width - 2 side etching amount. Furthermore, the ratio of the width information of the multiple sample width sets to the channel in the target chip design information is calculated, and the calculation results are used as multiple sample side etching amount compliance sets.

[0073] In one embodiment, the convolutional neural network is supervised and trained using the sample etching depth information set and the sample etching depth compliance set until the output reaches convergence, thereby obtaining the depth compliance identification channel. Furthermore, the convolutional neural network is supervised and trained using multiple sample side etching amount information sets and multiple sample side etching amount qualification sets until the output reaches convergence, thereby obtaining the multiple side etching compliance identification channels. Combining the depth compliance identification channel and the multiple side etching compliance identification channels, an etching compliance identifier is obtained. The technical effect of efficiently and accurately identifying multiple etching depth information sets and multiple side etching amount information sets is achieved.

[0074] S600: Calculate and obtain multiple micro-steps for updating multiple subordinate solutions according to multiple guided fitnesses;

[0075] Furthermore, step S600 in the embodiment of the present application further includes:

[0076] According to multiple guided fitnesses, the mean guided fitness is calculated;

[0077] The preset micro-step lengths are calculated and adjusted according to the inverse of the ratio of each guided fitness to the mean guided fitness, to obtain a plurality of adjusted micro-step lengths.

[0078] In one embodiment, multiple micro-steps for updating multiple subordinate solutions are determined based on the multiple guided fitnesses. The multiple micro-steps are amplitudes for adjusting wet etching process parameters in the multiple subordinate solutions, specifically including adjustment steps for etching solution ratio and etching time.

[0079] In one possible embodiment, the mean of the multiple guided fitnesses is calculated to obtain the guided fitness mean. The guided fitness mean reflects the average degree of proximity between the chip size and the target chip design information after the wet etching process is performed according to the multiple guided solutions. Then, the inverse of the ratio of each guided fitness to the guided fitness mean is calculated, and the preset micro-step size is calculated and adjusted according to the calculation result, thereby obtaining multiple adjusted micro-step sizes. The preset micro-step size is the amplitude of the parameter adjustment of the subordinate solution pre-set by those skilled in the art. The technical effect of performing optimization near a solution with high fitness and improving the quality of optimization is achieved.

[0080] S700: using multiple guide step sizes and multiple micro-step sizes, updating multiple guide solutions and multiple subordinate solutions, and performing iterative optimization until a preset number of optimization times is reached, to obtain optimal etching process parameters as an etching process optimization result.

[0081] In an embodiment of the present application, multiple guiding solutions and multiple subordinate solutions are updated according to the multiple guiding step sizes and multiple micro-step sizes, and after the update, iterative optimization is continued until a preset number of optimizations is reached, wherein the preset number of optimizations is the number of optimizations set by those skilled in the art. When the preset number of optimizations is reached, the etching process parameters corresponding to the solution with the greatest fitness are used as the optimal etching process parameters. Then, the optimal etching process parameters are used as the etching process optimization result. This achieves the technical effect of efficiently and accurately optimizing the etching process of the chip and improving the chip etching quality.

[0082] In summary, the embodiments of the present application have at least the following technical effects:

[0083] The present application achieves the goal of constraining the etching process optimization process by obtaining the etching conditions that need to be met during the optimization process based on the design information of the target information of the wet etching to be performed. Then, the process parameter optimization range is constructed, the wet etching process parameter adjustment domain is generated, and an etching optimization function is constructed. The etching optimization function is used to quantify the fitness of the parameters in the process optimization process. Then, multiple guiding solutions are randomly generated within the wet etching process parameter adjustment domain. Based on the multiple guiding solutions, multiple subordinate solutions are obtained. Wet etching is simulated to obtain basic analysis data for subsequent compliance analysis. Then, based on the obtained multiple etching depth information and multiple side etching amount information sets, combined with the design information, compliance calculation is performed. The calculation results are analyzed using the etching optimization function to obtain multiple guiding fitnesses and multiple subordinate fitnesses. Then, multiple micro-steps are updated for the multiple subordinate solutions based on the multiple guiding fitnesses. After multiple iterative optimizations until a preset number of optimizations is reached, the optimal etching process parameters are obtained as the etching process optimization result. The technical effect of improving the chip etching process optimization efficiency and improving the etching quality is achieved.

[0084] Example 2

[0085] Based on the same inventive concept as the etching process optimization method of a chip in the aforementioned embodiment, as shown in FIG4 , the present application provides a chip etching process optimization system. The system and method embodiments in the present application are based on the same inventive concept. The system includes:

[0086] The etching condition acquisition module 11 is used to acquire etching conditions for optimizing etching process parameters of the target chip according to design information of the target chip to be wet-etched;

[0087] An optimization function construction module 12 is used to construct a wet etching process parameter adjustment domain according to the wet etching process parameter adjustment range of the target chip, and to construct an etching optimization function based on the purpose of making the chip size after etching close to the design information;

[0088] A size information set acquisition module 13 is configured to randomly generate a plurality of guide solutions within the wet etching process parameter adjustment domain, and generate a plurality of subordinate solutions within the range of the guide step lengths of the plurality of guide solutions, perform simulated wet etching on the target chip, and acquire a plurality of size information sets after the simulated etching;

[0089] The side erosion amount acquisition module 14 is used to construct multiple chip channel modeling information for simulated etching based on multiple size information sets, wherein the multiple chip channel modeling information includes multiple etching depth information, and to obtain multiple side erosion amount information sets by dividing in the depth direction;

[0090] The fitness calculation module 15 is configured to analyze and calculate, based on the plurality of etching depth information and the plurality of side etch amount information sets, multiple etching depth compliance information and multiple side etch amount compliance information in combination with the design information, and calculate and obtain, based on the etching optimization function, multiple guiding fitnesses and multiple subordinate fitnesses;

[0091] A micro-step calculation module 16 is configured to calculate and obtain a plurality of micro-steps for updating a plurality of subordinate solutions according to a plurality of guided fitnesses;

[0092] The process optimization result setting module 17 is used to adopt multiple guide step sizes and multiple micro-step sizes to update multiple guide solutions and multiple subordinate solutions, and perform iterative optimization until a preset number of optimization times is reached to obtain the optimal etching process parameters as the etching process optimization result.

[0093] Furthermore, the etching condition acquisition module 11 is configured to perform the following steps:

[0094] Acquiring design information of a target chip to be wet-etched, the design information including depth information and width information of a channel after etching;

[0095] Obtain the error range of the target chip, compensate the depth information and width information, and obtain the depth information interval and width information interval;

[0096] The channel depth and width of the target chip after etching fall within the depth information interval and width information interval as etching conditions.

[0097] Furthermore, the optimization function construction module 12 is used to perform the following steps:

[0098] Obtaining the etching solution ratio range and etching time range of wet etching process parameters;

[0099] Combining the etching solution ratio range and the etching time range to obtain the process parameter adjustment range;

[0100] Based on the goal of making the chip size after etching close to the design information, an etching optimization function is constructed:

[0101] Among them, tch is the etching fitness, w1 and w2 are weights, S H is the etching depth compliance of the etching depth information after etching, T is the number of locations where the channel side etching amount is tested after etching, and S Di is the compliance of the side etching amount at the i-th position in the trench after etching.

[0102] Furthermore, the side erosion amount acquisition module 14 is configured to perform the following steps:

[0103] Constructing multiple chip channel modeling information for simulated etching based on multiple size information sets, performing modeling, and obtaining multiple simulated etching channel models;

[0104] Acquiring multiple etching depth information in multiple simulated etching channel models;

[0105] In the depth direction, multiple simulated etching channel models are hierarchically divided to obtain M etching layers, and the side etching amounts in the M layers are obtained to obtain multiple side etching amount information sets.

[0106] Furthermore, the fitness calculation module 15 is configured to perform the following steps:

[0107] Training an etching compliance identifier, wherein the etching compliance identifier includes a depth compliance identification channel and multiple side etching compliance identification channels;

[0108] The etching compliance identifier is used to identify a plurality of etching depth information and a plurality of side etching amount information sets to obtain a plurality of etching depth compliance information and a plurality of side etching amount compliance information;

[0109] Based on the etching optimization function, a plurality of guide fitnesses and a plurality of slave fitnesses are calculated and obtained.

[0110] Furthermore, the fitness calculation module 15 is configured to perform the following steps:

[0111] According to the etching R&D data of the target chip, a sample etching depth information set and multiple sample side etching amount information sets are obtained;

[0112] Based on the depth information and width information of the trench in the target chip design information, evaluating and calculating the sample etching depth information set and the multiple sample side etch amount information sets to obtain a sample etching depth compliance set and multiple sample side etch amount compliance sets;

[0113] Using the sample etching depth information set and the sample etching depth compliance set, constructing and training the depth compliance recognition channel;

[0114] Constructing and training multiple side erosion compliance recognition channels by respectively using the multiple sample side erosion amount information sets and the multiple sample side erosion amount compliance sets;

[0115] By combining the depth compliance identification channel and multiple side etching compliance identification channels, an etching compliance identifier is obtained.

[0116] Furthermore, the micro-step length calculation module 16 is configured to perform the following steps:

[0117] According to multiple guided fitnesses, the mean guided fitness is calculated;

[0118] The preset micro-step lengths are calculated and adjusted according to the inverse of the ratio of each guided fitness to the mean guided fitness, to obtain a plurality of adjusted micro-step lengths.

[0119] It should be noted that the above-mentioned order of the embodiments of the present application is for descriptive purposes only and does not represent the superiority or inferiority of the embodiments. The above description is of specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0120] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

[0121] This specification and drawings are merely illustrative of the present application and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Obviously, those skilled in the art may make various modifications and variations to this application without departing from the scope of this application. Thus, this application is intended to include such modifications and variations as fall within the scope of this application and its equivalents.

Claims

1. A chip etching process optimization method, characterized in that: The method comprises: According to the design information of the target chip to be wet-etched, obtaining etching conditions for optimizing etching process parameters of the target chip; According to the wet etching process parameter adjustment range of the target chip, a wet etching process parameter adjustment domain is constructed, and based on the purpose of making the chip size after etching close to the design information, an etching optimization function is constructed; Randomly generate multiple guide solutions in the wet etching process parameter adjustment domain, and generate multiple subordinate solutions within the range of the guide step lengths of the multiple guide solutions, respectively perform simulated wet etching of the target chip, and obtain multiple size information sets after the simulated etching; According to the multiple size information sets, multiple chip channel modeling information for simulated etching is constructed, wherein the multiple chip channel modeling information includes multiple etching depth information, and multiple side etching amount information sets are obtained by dividing in the depth direction; According to a plurality of etching depth information and a plurality of side etching amount information sets, combined with design information, multiple etching depth compliance information and multiple side etching amount compliance information are obtained by analysis and calculation, and based on the etching optimization function, multiple guide fitness and multiple subordinate fitness are obtained by calculation; According to the multiple guided fitnesses, multiple micro-steps for updating the multiple subordinate solutions are calculated; By adopting multiple guide step sizes and multiple micro-step sizes, multiple guide solutions and multiple subordinate solutions are updated, and iterative optimization is performed until a preset number of optimization times is reached to obtain the optimal etching process parameters as the etching process optimization result.

2. The method according to claim 1, characterized in that The method comprises: Acquiring design information of a target chip to be wet-etched, wherein the design information includes depth information and width information of a channel after etching; Obtain the error range of the target chip, compensate the depth information and the width information, and obtain the depth information interval and the width information interval; The channel depth and width of the target chip after etching fall into the depth information interval and the width information interval as etching conditions.

3. The method according to claim 1, characterized in that The method comprises: Obtaining the etching solution ratio range and etching time range of wet etching process parameters; The etching solution ratio range and the etching time range are combined to obtain the process parameter adjustment domain; Based on the purpose of making the chip size after etching close to the design information, an etching optimization function is constructed: Among them, tch is the etching fitness, w1 and w2 are weights, S H is the etching depth compliance of the etching depth information after etching, T is the number of locations of the channel side etching amount after testing etching, S Di is the side etching compliance of the side etching amount at the i-th position in the trench after etching.

4. The method according to claim 3, characterized in that The method comprises: According to the multiple size information sets, multiple chip channel modeling information of simulated etching is constructed, and modeling is performed to obtain multiple simulated etching channel models; In a plurality of simulated etching channel models, obtaining a plurality of etching depth information; In the depth direction, multiple simulated etching channel models are hierarchically divided to obtain M etching layers, and the side etching amounts in the M layers are obtained to obtain multiple side etching amount information sets.

5. The method according to claim 1, characterized in that The method comprises: Training an etching compliance identifier, wherein the etching compliance identifier includes a depth compliance identification channel and a plurality of side etching compliance identification channels; The etching compliance identifier is used to identify a plurality of etching depth information and a plurality of side etching amount information sets, and obtain a plurality of etching depth compliance information and a plurality of side etching amount compliance information; Based on the etching optimization function, a plurality of guide fitnesses and a plurality of slave fitnesses are obtained by calculation.

6. The method according to claim 5, characterized in that The method comprises: According to the etching research and development data of the target chip, a sample etching depth information set and multiple sample side etching amount information sets are obtained; Based on the depth information and width information of the trench in the target chip design information, the sample etching depth information set and the multiple sample side etching amount information sets are evaluated and calculated to obtain a sample etching depth compliance set and multiple sample side etching amount compliance sets; Using the sample etching depth information set and the sample etching depth compliance set, construct and train the depth compliance identification channel; The plurality of sample lateral erosion amount information sets and the plurality of sample lateral erosion amount compliance sets are respectively used to construct and train a plurality of lateral erosion compliance identification channels; By combining the depth compliance identification channel and multiple side etching compliance identification channels, an etching compliance identifier is obtained.

7. The method according to claim 1, characterized in that The method comprises: According to multiple guide fitnesses, the mean of the guide fitnesses is calculated and obtained; The preset micro-step lengths are calculated and adjusted according to the inverse of the ratio of each guided fitness to the mean guided fitness to obtain a plurality of adjusted micro-step lengths.

8. A chip etching process optimization system, characterized in that: The system comprises: An etching condition acquisition module, used to acquire etching conditions for optimizing etching process parameters of a target chip according to design information of the target chip to be wet-etched; An optimization function building module is used to build a wet etching process parameter adjustment domain according to the wet etching process parameter adjustment range of the target chip, and to build an etching optimization function based on the purpose of making the chip size after etching close to the design information; A size information set acquisition module, used to randomly generate a plurality of guide solutions within the wet etching process parameter adjustment domain, and respectively generate a plurality of subordinate solutions within the range of the guide step lengths of the plurality of guide solutions, respectively perform simulated wet etching of the target chip, and acquire a plurality of size information sets after the simulated etching; A side erosion amount acquisition module is used to construct multiple chip channel modeling information for simulated etching according to multiple size information sets, wherein the multiple chip channel modeling information includes multiple etching depth information, and to obtain multiple side erosion amount information sets by dividing in the depth direction; A fitness calculation module is used to analyze and calculate to obtain multiple sets of etching depth compliance information and multiple sets of side etching amount compliance information according to multiple sets of etching depth information and multiple sets of side etching amount information in combination with design information, and to calculate and obtain multiple guide fitnesses and multiple subordinate fitnesses based on the etching optimization function; A micro-step calculation module, used for calculating and obtaining a plurality of micro-steps for updating a plurality of subordinate solutions according to a plurality of guide fitnesses; The process optimization result setting module is used to adopt multiple guide step sizes and multiple micro-step sizes to update multiple guide solutions and multiple subordinate solutions, and perform iterative optimization until a preset number of optimization times is reached to obtain the optimal etching process parameters as the etching process optimization result.

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