Systems and devices for buffering and current driving

Abstract

A circuit arrangement includes a first supply voltage, a second supply voltage providing a voltage level less than the first voltage level and a voltage regulator coupled to the first supply voltage and configured to provide the second supply voltage. The circuit arrangement includes an input circuit and analog circuity coupled to the second supply voltage. The circuit arrangement includes an intermediate circuit configured to replicate input received at the input circuit using the first supply voltage.

Description

[0001] SYSTEMS AND DEVICES FOR BUFFERING AND CURRENT DRIVING

[0002] Field

[0003] This present disclosure generally relates to circuit arrangements and driver circuits.

[0004] Background

[0005] Some drivers, for example gate drivers, in certain contexts need to charge / discharge a capacitive load in a given time between different analog states. The drivers, besides a capacitive load, may need to turn on a transistor, e.g., a field-effect-transistor (FET) and as such, the gate should be moved at least of a threshold voltage away from the respective source voltage.

[0006] FIG. 1 shows a simplified example of a hard switching gate driver 100. The gate driver 100, in response to applied input voltage VINis configured to turn on the FET T1 to provide a current IGand gate voltage VGSfext to the gate of the FET Tl. The FET Tl can couple e.g., through intermediate elements therebetween not shown, to the VBAwhich may be a voltage source, in one example.

[0007] Hard switching gate drivers such as the hard switching gate driver 100 switch the control terminal / gate of external devices, e.g., a FET between two defined states, namely 0N (VDRV) and OFF (VSH) .

[0008] In some circumstances, it may be desirable for gate drivers to ensure that the power source supplying the input signal remains relatively unaffected by any external load connected to their output. However, current driers or gate drivers pose challenges as they struggle to generate an output voltage with high precision while maintaining low impedance. Description

[0009] In the drawings , like reference characters generally refer to the same parts throughout the di f ferent views . The drawings are not necessarily to scale , emphasis instead generally being placed upon illustrating the principles of the disclosure . In the following description, various aspects of the disclosure are described with reference to the following drawings , in which :

[0010] FIG . 1 shows an example of a hard switching gate driver ;

[0011] FIG . 2 shows an example of a circuit arrangement according to aspects of the present disclosure ;

[0012] FIG . 3 shows an example of an intermediate circuit according to aspects of the present disclosure .

[0013] The following detailed description refers to the accompanying drawings that show, by way of illustration, speci fic details and aspects in which the disclosure may be practiced . One or more aspects are described in suf ficient detail to enable those skilled in the art to practice the disclosure . Other aspects may be utili zed and structural , logical , and electrical changes may be made without departing from the scope of the disclosure . The various aspects described herein are not necessarily mutually exclusive , as some aspects can be combined with one or more other aspects to form new aspects . Various aspects are described in connection with methods and various aspects are described in connection with devices . However, it may be understood that aspects described in connection with methods may similarly apply to the devices , and vice versa . Throughout the drawings , it should be noted that like reference numbers are used to depict the same or similar elements , features , and structures . Throughout the drawings , it should be noted that proportions are not necessary to scale and that the si ze of features may be emphasi zed for ease of illustration .

[0014] FIG . 2 shows a circuit arrangement 200 according to at least one aspect of the present disclosure .

[0015] The circuit arrangement 200 can produce fast voltage generation, which, depending on the load, can result in fast current generation, while including both a regulated voltage supply and sensitive analog parts or components .

[0016] The circuit arrangement 200 includes a first supply voltage or first supply rail VHV . The first supply voltage VHV is configured to provide a first voltage level .

[0017] The circuit arrangement 200 further includes a second supply voltage or second supply rail VDD that is configured to provide a second voltage level . According to aspects of the present disclosure , the second voltage VDD can be a regulated voltage with the second voltage level being less than the first voltage level . For example , the first voltage level may be at least two volts ( 2V) more than the second voltage level .

[0018] In the example of FIG . 2 , the circuit arrangement 200 includes a voltage regulator 210 . The voltage regulator 210 couples to the first supply voltage VHV and is configured to provide the second supply voltage VDD . The voltage regulator 210 may be any suitable voltage regulator, including, for example , a linear regulator . Further, the linear regulator may include a low drop out ( LDO) voltage regulator circuit .

[0019] The first supply voltage VHV may provide a relatively high voltage level , such as a range of from substantially 5 to 50 volts , including for example , 25 to 50 volts . The second supply voltage VDD may provide a voltage level from substantially 3 to 5 volts , and in particular, may provide a voltage level of substantially 3 volts . In general , these ranges for the first supply voltage VHV and the second supply voltage VDD should be subject to the condition that the first supply voltage VHV should be greater than the second supply voltage VDD.

[0020] In FIG. 2, the circuit arrangement 200 includes an input circuit 215. The input circuit 215 can be coupled and powered by the second supply voltage VDD. The input circuit 215 configured to accept an input at the input node IN. In at least one instance, the input circuit 215 may be a buffer circuit, e.g., a digital buffer circuit.

[0021] The circuit arrangement 200 of FIG. 2 further includes an analog circuit or analog circuitry 220 coupled to the second supply voltage VDD. The analog circuit 200 in one example may at least include an analog-to-digital converter (ADC) circuit.

[0022] The circuit arrangement 200 includes an intermediate circuit 250. The intermediate circuit 250 by itself, is shown in FIG. 3. In at least one example, the intermediate circuit 250 is configured to replicate the input it receives. For example, in the example of FIG. 2, the input (IN) received by the input circuit 215 is to be replicated by and output by the intermediate circuit 250. In other words, the intermediate circuit 250 is configured to provide fast voltage generation that accurately reproduces the received input or input voltage.

[0023] The intermediate circuit 250 can be powered by the first voltage supply VHV, as illustrated in both FIG. 2 and FIG. 3. That is, the intermediate circuit 250 can be powered by power source different from one used to power analog circuitry. In FIG. 2, the intermediate circuit 250 is powered by VHV while the analog circuitry 220 (e.g., the ADC) is powered by VDD.

[0024] Further, the intermediate circuit 250 includes a first transistor MN1 arranged in a diode configuration. As shown, an input to the first transistor is coupled to an output of the input circuit 215. Further, an output (e.g., drain terminal) of the first transistor MN1 is coupled to an internal node N of the intermediate circuit 250 .

[0025] The intermediate circuit 250 also includes a second transistor MN2 coupled to the internal node N and further coupled to an output node OUT .

[0026] For example , as shown, the first transistor MN1 can be arranged in a diode configuration so that a control terminal CT of the first transistor MN1 is coupled to a first terminal IT o f the first transistor MN1 . Further, a second terminal 2T o f the first transistor MN1 can be coupled to the output of the input circuit . Further, the control terminal CT and the first terminal IT of the first transistor MN1 and the control terminal CT of the second transistor MN2 are coupled to the internal node N .

[0027] The intermediate circuit 250 further includes a current mirror circuit . As shown, the circuit mirror circuit includes a third transistor MP1 and a fourth transistor MP2 . The third transistor MP1 is coupled between the first supply voltage VHV and the first transistor MN1 . Similarly, the fourth transistor MP2 is coupled between the first supply voltage VHV and the second transistor MN2 . The control terminal CT ( e . g . , gate ) of the third transistor MP1 is coupled to the control terminal CT of the fourth transistor MP2 . Further, the first terminal IT of the third transistor MP1 and the first terminal IT of the fourth transistor MP2 are coupled to the first supply voltage VHV .

[0028] According to at least one example , the transistors MN1 , MN2 , MP1 , and MP2 of the intermediate circuit 250 may be fieldef fect transistors ( FET ) . For example , in the case of FIG . 2 and FIG . 3 , the first and second transistors , MN1 and MN2 , can be n-channel metal oxide semiconductor transistors and the third and fourth transistors , MP1 and MP2 , can be p-channel metal oxide semiconductor transistors . In other cases , the transistors MN1 and MN2 can be p-channel metal oxide transistors and the transistors MP1 and MP2 can be n-channel metal oxide semiconductor transistors .

[0029] Further, the transistors MN1 , MN2 , MP1 , and MP2 of the intermediate circuit 250 may be able to handle large voltage levels . For instance , the transistors MN1 , MN2 , MP1 , and MP2 may be able to handle voltage up to at least 50 volts . That is , the transistors MN1 , MN2 , MP1 , and MP2 may handle voltage levels in the range of 5 to 50 volts , 25 to 50 volts , etc .

[0030] Further, the intermediate circuit 250 includes a diode DI . The diode DI provides reverse current protection within the intermediate circuit 250 .

[0031] In addition, the intermediate circuit 250 includes a current source II . The current source II is arranged or coupled between the first supply voltage VHV and a second terminal 2T of the third transistor MP1 .

[0032] The intermediate circuit 250 also includes a current sink 12 coupled between the output node and a ground reference VSS .

[0033] The intermediate circuit 250 can also include switches . The switches can be used or configured to quickly bring the output of the intermediate circuit 250 to a desired low or ground level . In particular, the intermediate circuit 250 includes a first switch, switch SW1 which is configured to bring the internal node N to a low or ground reference VSS . That is , the first switch SW1 couples to the internal node N of the intermediate circuit 250 and is configured to pull the internal node N to a ground reference in response to an input to the input circuit being low .

[0034] Similarly, the switch SW2 coupled to the output node OUT of the intermediate circuit 250 is configured to pull the output node OUT to a ground reference in response to an input to the input circuit being low .

[0035] The switches SW1 and SW2 may receive the input signal , speci fically, each can receive the inverted input (IN) from the input node IN or from an output of the input circuit 215 and then switch or close to bring the node they are connected to a low or ground reference (VSS ) . For example , an inverter may be positioned between the input node IN and the switch input .

[0036] The transistors MN1 , MN2 , MP1 , and MP2 o f the intermediate circuit 250 form a current mirror loop . According to at least one example of the present disclosure this current mirror loop provides a current loop gain of less than one ( 1 ) . This current loop gain can help ensure stabil ity of the intermediate circuit 250 during operation . That is , i f the current loop gain were greater than one , then there is a risk that the intermediate circuit 250 would become unstable and hence no longer be able to accurately or quickly replicate or reproduce an input signal it receives at the first transistor MN1 .

[0037] The current loop gain provided by the current mirror loop formed by the transistors MN1 , MN2 , MP1 , and MP2 can be a function of the width-to-length ratios of the transistors MN1 , MN2 , MP1 , and MP2 . More precisely, the current loop gain can be achieved with a value less than one i f the transistors (MN1 , MN2 , MP1 , and MP2 ) meet the following condition :

[0038] [ (WLMN2 / WLMNI )X(WLMPI / WLMP2 ) ] < 1

[0039] - where WLMNI is the width-length ratio of the first transistor MN1

[0040] - where WLMN2 is the width-length ratio of the second transistor MN2

[0041] - where WLMPI is the width-length ratio of the third transistor MP1 - where WLMP2 is the width-length ratio of the fourth transistor MP2

[0042] In other words, the current loop gain will be less than one if a width-to-length ratio of the second transistor MN2 divided by a width-to-length ratio of the first transistor MN1, multiplied by, a width-to-length ratio of the third transistor MP1 divided by a width-to-length ratio of the fourth transistor MP2, has a value less than one. As such, when the current loop gain is less than 1, the intermediate circuit 250 is able to operate without becoming unstable.

[0043] In one or more embodiments, the circuit arrangement 200 may further include or be coupled to a load or a load circuitry 260. In other words, in some cases, the load may be a part of the circuit arrangement 200. e.g., integrated and part of the circuit arrangement 200.

[0044] In other cases, the load circuitry 260 may be external. That is, the load may be an external component not integrated but capable of being connected to the circuit arrangement 200.

[0045] In the example of FIG. 2, the intermediate circuit 250 can be configured as a light-emitting diode (LED) driver to drive at least one LED. As such, the load circuitry 260 can be LED circuitry that includes at least one LED LI, a transistor BT, and a load element R (e.g., a resistive and / or capacitive element) .

[0046] In one example, the transistor BT may be a bipolar junction transistor (BJT) . In other instances, the transistor BT may be realized as other transistors. The LED LI couples to the first supply voltage VHV and to the transistor BT (e.g., to a first terminal IT of the transistor BT) . The transistor BT is further coupled to the resistive load R. The resistive load element R is coupled between the transistor BT (e.g., a second terminal 2T of the transistor BT) and a ground reference, e.g., ground reference VSS .

[0047] In FIG. 2, the output or output node OUT of intermediate circuit 250 is input to a control terminal CT (e.g., base terminal) of the transistor BT . That is, the intermediate circuit 250 produces an output signal at the output node OUT that can be used as input to drive the load circuitry 260.

[0048] In general, circuitry such as or similar to the circuit arrangement 200 or the intermediate circuit 250 can be configured to generate voltage pulses at "OUT" within the low voltage domain with a current driving capability of several milliamps (mA) . In the example of FIG. 2, the input signal and the corresponding output signal (produced at the output node OUT) may be in a low voltage domain (e.g., 5 volts or less) . The signals can be any suitable type of voltage signals, including, for example, pulse-width-modulated signals. For example, the signals may have an amplitude of substantially or approximately VDD, e.g., 5 volts or less.

[0049] Further, such circuit arrangements such as the circuit arrangement 200 are configured so that high supply voltage is primarily response for the generated and replicated pulses. Put simply, during a pulse phase which is triggered by an input signal, the main current comes from the high-voltage supply (e.g., VHV) rather than a low-voltage supply (e.g., VDD) . In the context of the circuit arrangement 200 / intermediate circuit 250 of FIGS. 2 and 3, the high voltage supply VHV is primarily or predominantly responsible for providing the electrical power for generated pulses at the output or output node OUT. Moreover, the circuit arrangement 200 / intermediate circuit 250 is configured so that the pulse amplitude between "IN" and "OUT" remains consistent. Moreover, the circuit arrangement 200 / intermediate circuit 250 has the ability to generate fast voltage pulses (e.g., on-time ~lus, rise / fall time <100ns) .

[0050] Another benefit of the circuit arrangement 200 / intermediate circuit 250 it is low area consumption because it minimizes the number of components.

[0051] In addition, the circuit arrangement 200 / intermediate circuit 250 is configured to be stable (e.g., unconditionally stable) even in presence of a large variation of load impedance presented at the output node OUT. Also, the circuit arrangement 200 / intermediate circuit 250 is configured and able to realize no discharge of low / second supply voltage VDD during interruptions of the first / high voltage supply VHV.

[0052] In general, the circuit arrangement 200 / intermediate circuit 250 realizes a regulated voltage mirror (e.g., "IN" "VGS1" "OUT") employed to generate a precise output voltage and to draw the primary current from VHV.

[0053] Further, the specified product of ratios (WLMN2 / WLMNI)X(WLMPI / WLMP2) allows the circuit arrangement 200 / intermediate circuit 250 to achieve a desired loop gain fulfilling accuracy and stability. The loop gain ensures that the pulse amplitude between "IN" and "OUT" matches under a wide range of loading conditions .

[0054] Also, beneficially, the diode DI into the intermediate circuit 250 serves to prevent reverse current, e.g., for example in the event the first supply voltage VHV falls below the second supply voltage VDD.

[0055] One of the significant advantages of circuit arrangements such as the circuit arrangement 200 is that it allows for the analog circuitry 220 to be undisturbed by driving a load at the output node OUT. For example, the ADC of the analog circuitry 220 can remain undisturbed by the large current pulses through the LED LI , thereby also by the current flowing into the control terminal / base of the transistor / B JT BT . In other words , the circuit arrangement 200 allows the analog circuitry 220 to be decoupled from the pulse generation to drive the load circuit , e . g . , LED load circuit . In other examples , the load circuit 260 may be other types of circuitries , such as motors , actuators , transmitters , sensors , to name a few .

[0056] In the following some examples are described, which relate to what is described herein and shown in the figures .

[0057] Example 1 is a circuit arrangement including : a first supply voltage providing a first voltage level ; a second supply voltage providing a second voltage level , the second voltage level being less than the first voltage level ; a voltage regulator coupled to the first supply voltage and configured to provide the second supply voltage ; an input circuit coupled to the second supply voltage ; an analog circuit coupled to the second supply voltage ; an intermediate circuit configured to replicate input received at the input circuit using the first supply voltage , the intermediate circuit including : a first transistor arranged in a diode configuration so that an input to the first trans istor is coupled to an output of the input circuit and an output of the first transistor is coupled to an internal node of the intermediate circuit ; a second transistor coupled to the internal node and further coupled to an output node ; a current mirror circuit comprising a third transistor and fourth transistor is coupled between the first supply voltage and the first and second transistors ; a current source coupled between the first supply voltage and a second terminal of the third transistor ; and a current sink coupled between the output node and ground reference . Example 2 is the subj ect matter of Example 1 , wherein the first transistor can be arranged in a diode configuration so that a control terminal of the first transistor is coupled to a first terminal of the first transistor, wherein a second terminal of the first transistor can be coupled to an output of the input circuit , and wherein the control terminal and the first terminal of the first transistor and the control terminal of the second transistor can be coupled to the internal node .

[0058] Example 3 is the subj ect matter of Example 1 or 2 , wherein a control terminal of the third transistor can be coupled to a control terminal of the fourth transistor .

[0059] Example 4 is the subj ect matter of Example 3 , wherein the first terminal of the third transistor and a first terminal of the fourth transistor can be connected to the first supply voltage , and a second terminal of the fourth transistor can be coupled to the control terminal of the fourth transistor and to a first terminal of the second transistor .

[0060] Example 5 is the subj ect matter of Example 3 or 4 , which may further include a diode arranged coupled between a second terminal of the third transistor and the first terminal of the first transistor .

[0061] Example 6 is the subj ect matter of any of Examples 1 to 5 , which may further include a first switch circuit coupled to internal node and configured to pull the internal node to a ground reference in response to an input to the input circuit being low .

[0062] Example 7 is the subj ect matter of any of Examples 1 to 5 , which may further include a second switch circuit coupled to the output node and configured to pull the output node to a ground reference in response to an input to the input circuit being low . Example 8 is the subj ect matter of any of Example 1 to 7 , wherein the voltage regulator circuit can be a linear regulator .

[0063] Example 9 is the subj ect matter of Example 8 , wherein the linear regulator can be a low-dropout regulator circuit .

[0064] Example 10 is the subj ect matter of any of Examples 1 to 9 , wherein the analog circuit can include an analog-to-digital converter (ADC ) circuit .

[0065] Example 11 is the subj ect matter of any of Example 1 to 10 , wherein the input circuit may include a buf fer circuit .

[0066] Example 12 is the subj ect matter of any of Examples 1 to 11 , wherein the first supply voltage can be configured to supply a first voltage in a range of 5 to 50 volts .

[0067] Example 13 is the subj ect matter of any of Examples 1 to 12 , wherein the first , second, third, and fourth transistors can each be configured to handle and operate at voltage levels from 5 volts to 50 volts .

[0068] Example 14 is the subj ect matter of any of Examples 1 to 13 , wherein the second supply voltage can be configured to supply a second voltage of substantially 3 volts .

[0069] Example 15 is the subj ect matter of any of Example 1 to 14 , wherein the first , second, third, and fourth trans istors of the intermediate circuit can form a current mirror loop providing a current loop gain of less than 1 .

[0070] Example 16 is the subj ect matter of any of Examples 1 to 15 , wherein the third and fourth transistors can be p-channel metal-oxide-semiconductor transistors and the first and second transistors can be n-channel metal-oxide-semiconductor transistors . Example 17 is the subj ect matter of any of Examples 1 to 16 , wherein a width-to-length ratio of the second transistor divided by a width-to-length ratio of the first transistor multiplied by a width-to-length ratio of the third transistor divided by a width-to-length ratio of the fourth transistor can have a value less than one .

[0071] Example 18 is the subj ect matter of any of Examples 1 to 17 , which may further include a load coupled to the output node .

[0072] Example 19 is the subj ect matter of Example 20 , wherein the load may include a resistive , capacitive , and / or active load elements .

[0073] Example 20 is the subj ect matter of Example 18 or 19 , wherein the load may include a branch including at least one lightemitting diode in series with at least one transistor and a resistive load .

[0074] Example 21 is a semiconductor integrated circuit chip comprising the circuit arrangement of any of Examples 1 to 20 .

[0075] Example 1A is a method for replicating an input at output of a circuit arrangement according to any of Examples 1 to 21 .

[0076] Any of the aspects , examples , and / or embodiments described herein may be suitable or appropriately combined .

[0077] The word "exemplary" is used herein to mean " serving as an example , instance , or illustration . " Any example or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other examples or designs .

[0078] For the purposes of the present disclosure , the phrase "A and / or B" means (A) , (B ) , or (A and B ) . For the purposes of the present disclosure, the phrase "A, B, and / or C" means (A) ,

[0079] (B) , (C) , (A and B) , (A and C) , (B and C) , or (A, B, and C) .

[0080] Reference to "one embodiment" or "an embodiment" in the present disclosure means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase "in one embodiment" or "in an embodiment" are not necessarily all referring to the same embodiment. The appearances of the phrase "for example," "in an example," or "in some examples" are not necessarily all referring to the same example.

[0081] The words "plurality" and "multiple" in the description or the claims expressly refer to a quantity greater than one. The terms "group (of) ", "set [of] ", "collection (of) ", "series (of)", "sequence (of)", "grouping (of)", etc., and the like in the description or in the claims refer to a quantity equal to or greater than one, i.e. one or more. Any term expressed in plural form that does not expressly state "plurality" or "multiple" likewise refers to a quantity equal to or greater than one .

[0082] The term "connected" can be understood in the sense of a (e.g. mechanical, optical and / or electrical) , e.g. direct or indirect, connection and / or interaction. For example, several elements can be connected together mechanically such that they are physically retained (e.g., a plug connected to a socket) and electrically such that they have an electrically conductive path (e.g., signal paths exist along a communicative chain) .

[0083] As used herein, unless otherwise specified the use of the ordinal adjectives "first", "second", "third" etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

[0084] As utilized herein, terms "module", "component," "system," "circuit, " "element, " "slice, " "circuitry, " and the like are intended to refer to a set of one or more electronic components, a computer-related entity, hardware, software (e.g., in execution) , and / or firmware. For example, circuitry or a similar term can be a processor, a process running on a processor, a controller, an object, an executable program, a storage device, and / or a computer with a processing device. By way of illustration, an application running on a server and the server can also be circuitry. One or more circuits can reside within the same circuitry, and circuitry can be localized on one computer and / or distributed between two or more computers. A set of elements or a set of other circuits can be described herein, in which the term "set" can be interpreted as "one or more."

[0085] Such electric or electronic circuitry can be operated by a software application or a firmware application executed by one or more processors. The one or more processors can be internal or external to the apparatus and can execute at least a part of the software or firmware application. As yet another example, circuitry can be an apparatus that provides specific functionality through electronic components without mechanical parts; the electronic components can include one or more processors therein to execute executable instructions stored in computer readable storage medium and / or firmware that confer (s) , at least in part, the functionality of the electronic components. As another example, circuitry or similar term can be implemented in hardware such as application specific integrated circuit (ASIC) , programmable gate array (PGA) , discrete digital circuits, etc.) or in a combination of hardware and software (e.g., a software model executed by a corresponding processor) . The term "data" as used herein may be understood to include information in any suitable analog or digital form, e . g . , provided as a file , a portion of a file , a set of files , a signal or stream, a portion of a signal or stream, a set of signals or streams , and the like . Further, the term "data" may also be used to mean a reference to information, e . g . , in form of a pointer . The term data, however, is not limited to the aforementioned examples and may take various forms and represent any information as understood in the art .

[0086] As used herein, a signal that is " indicative of" a value or other information may be a digital or analog signal that encodes or otherwise communicates the value or other information in a manner that can be decoded by and / or cause a responsive action in a component receiving the signal . The signal may be stored or buf fered in computer readable storage medium prior to its receipt by the receiving component and the receiving component may retrieve the signal from the storage medium . Further, a "value" that is " indicative of" some quantity, state , or parameter may be physically embodied as a digital signal , an analog signal , or stored bits that encode or otherwise communicate the value .

[0087] As used herein, a signal may be transmitted or conducted through a signal chain in which the signal is processed to change characteristics such as phase , amplitude , frequency, and so on . The signal may be referred to as the same signal even as such characteristics are adapted . In general , so long as a signal continues to encode the same information, the signal may be considered as the same signal . For example , a transmit signal may be considered as referring to the transmit signal in baseband, intermediate , and radio frequencies .

[0088] While the above descriptions and connected figures may depict device components as separate elements , skilled persons will appreciate the various possibilities to combine or integrate discrete features , functions into a single element . Such may include combining two or more components into a single component . Conversely, skilled persons will recogni ze the possibility to separate a single element into two or more discrete elements , such as splitting a single component into two or more separate components .

[0089] It is appreciated that implementations of methods detailed herein are exemplary in nature , and are thus understood as capable of being implemented in a corresponding device . Likewise , it is appreciated that implementations of devices detailed herein are understood as capable of being implemented as a corresponding method . It is thus understood that a device corresponding to a method detailed herein may include one or more components configured to perform each aspect of the related method .

[0090] All acronyms defined in the above description additionally hold in all claims included herein .

[0091] While embodiments of the present disclosure have been described above , it is obvious that further embodiments may be implemented . For example , further embodiments may comprise any subcombination of features recited in the claims or any subcombination of elements described in the examples given above . Accordingly, this spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein .

[0092] While the disclosure has been particularly shown and described with reference to speci fic embodiments , it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims . The scope of the disclosure is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced . Reference Numeral List

[0093] 100 gate driver

[0094] 200 circuit arrangement

[0095] 210 voltage regulator

[0096] 215 input circuit

[0097] 220 analog circuitry

[0098] 250 intermediate circuit

[0099] 260 load circuit / load branch

[0100] DI diode

[0101] 11 current source

[0102] 12 current sink

[0103] MN1 first transistor

[0104] MN2 second transistor

[0105] MP1 third transistor

[0106] MP2 fourth transistor

[0107] LI light-emitting diode

[0108] BT load transistor / B JT

[0109] R load element / emitter resistance

[0110] IN input node

[0111] N internal node

[0112] OUT output node

[0113] SW1 first switch circuit

[0114] SW2 second switch circuit

[0115] VHV first supply voltage

[0116] VDD second supply voltage

[0117] VSS ground reference

[0118] ADC analog to digital converter

[0119] AIN analog circuit input

[0120] D ADC output

Claims

CLAIMSWHAT IS CLAIMED :1 . A circuit arrangement comprising : a first supply voltage providing a first voltage level ; a second supply voltage providing a second voltage level , the second voltage level being less than the first voltage level ; a voltage regulator coupled to the first supply voltage and configured to provide the second supply voltage ; an input circuit coupled to the second supply voltage ; an analog circuit coupled to the second supply voltage ; an intermediate circuit configured to replicate input received at the input circuit using the first supply voltage , the intermediate circuit comprising : a first transistor arranged in a diode configuration so that an input to the first transistor is coupled to an output of the input circuit and an output of the first transistor is coupled to an internal node of the intermediate circuit ; a second transistor coupled to the internal node and further coupled to an output node ; a current mirror circuit comprising a third transistor and fourth transistor is coupled between the first supply voltage and the first and second transistors ; a current source coupled between the first supply voltage and a second terminal of the third transistor ; and a current sink coupled between the output node and ground reference .2 . The circuit arrangement of claim 1 ,wherein the first transistor is arranged in a diode configuration so that a control terminal of the first transistor is coupled to a first terminal of the first transistor, wherein a second terminal of the first transistor is coupled to an output of the input circuit , and wherein the control terminal and the first terminal of the first transistor and the control terminal of the second transistor are coupled to the internal node .3 . The circuit arrangement of claim 1 , wherein a control terminal of the third transistor is coupled to a control terminal of the fourth transistor .4 . The circuit arrangement of claim 3 , wherein the first terminal of the third transistor and a first terminal of the fourth transistor are connected to the first supply voltage , and a second terminal of the fourth transistor is coupled to the control terminal of the fourth transistor and to a first terminal of the second transistor .

5. The circuit arrangement of claim 3 , further comprising : a diode arranged coupled between a second terminal of the third transistor and the first terminal of the first transistor .

6. The circuit arrangement of claim 1 , further comprising : a first switch circuit coupled to internal node and configured to pull the internal node to a ground reference in response to an input to the input circuit being low .7 . The circuit arrangement of claim 1 , further comprising :a second switch circuit coupled to the output node and configured to pull the output node to a ground reference in response to an input to the input circuit being low.

8. The circuit arrangement of claim 1, wherein the voltage regulator circuit is a linear regulator.

9. The circuit arrangement of claim 8, wherein the linear regulator is a low-dropout regulator circuit.

10. The circuit arrangement of claim 1, wherein the analog circuit comprises an analog-to-digital converter circuit.

11. The circuit arrangement of any of claims 1 to 10, wherein the input circuit comprises a buffer circuit.

12. The circuit arrangement of any of claims 1 to 10, wherein the first supply voltage is configured to supply a first voltage in a range of 5 to 50 volts.

13. The circuit arrangement of any of claims 1 to 10, wherein the first, second, third, and fourth transistors are configured to handle and operate at voltage levels from 5 volts to 50 volts.

14. The circuit arrangement of any of claims 1 to 10, wherein the second supply voltage is configured to supply a second voltage of substantially 3 volts.

15. The circuit arrangement of any of claims 1 to 10,wherein the first , second, third, and fourth transistors of the intermediate circuit form a current mirror loop providing a current loop gain of less than 1 .16 . The circuit arrangement of any of claims 1 to 10 , wherein the third and fourth transistors are p-channel metal- oxide-semiconductor transistors and the first and second transistors are n-channel metal-oxide-semiconductor transistors .17 . The circuit arrangement of any of claims 1 to 10 , wherein a width-to-length ratio of the second transistor divided by a width-to-length ratio of the first transistor multiplied by a width-to-length ratio of the third transistor divided by a width-to-length ratio of the fourth transistor has a value less than one .18 . The circuit arrangement of any of claims 1 to 10 , further comprising : a load coupled to the output node .19 . The circuit arrangement of claim 18 , wherein the load comprises a branch including at least one light-emitting diode in series with at least one transistor and a resistive load .20 . A semiconductor integrated circuit chip comprising the circuit arrangement of any of claims 1 to 10 .

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